java -Xmx8000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml --generate-csv --csv-dir csv -s ../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf -i ../../../trunk/examples/svcomp/loop-invgen/seq_true-unreach-call_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-dd2f093 [2018-07-24 10:54:30,444 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-07-24 10:54:30,446 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-07-24 10:54:30,458 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-07-24 10:54:30,458 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-07-24 10:54:30,459 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-07-24 10:54:30,461 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-07-24 10:54:30,462 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-07-24 10:54:30,464 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-07-24 10:54:30,465 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-07-24 10:54:30,466 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-07-24 10:54:30,466 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-07-24 10:54:30,467 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-07-24 10:54:30,468 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-07-24 10:54:30,469 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-07-24 10:54:30,470 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-07-24 10:54:30,471 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-07-24 10:54:30,473 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-07-24 10:54:30,475 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-07-24 10:54:30,476 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-07-24 10:54:30,478 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-07-24 10:54:30,479 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-07-24 10:54:30,481 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-07-24 10:54:30,482 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-07-24 10:54:30,482 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-07-24 10:54:30,483 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-07-24 10:54:30,484 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-07-24 10:54:30,485 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-07-24 10:54:30,486 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-07-24 10:54:30,487 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-07-24 10:54:30,487 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-07-24 10:54:30,488 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-07-24 10:54:30,488 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-07-24 10:54:30,488 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-07-24 10:54:30,489 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-07-24 10:54:30,490 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-07-24 10:54:30,491 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf [2018-07-24 10:54:30,512 INFO L110 SettingsManager]: Loading preferences was successful [2018-07-24 10:54:30,512 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-07-24 10:54:30,513 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-07-24 10:54:30,513 INFO L133 SettingsManager]: * User list type=DISABLED [2018-07-24 10:54:30,514 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-07-24 10:54:30,514 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-07-24 10:54:30,514 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-07-24 10:54:30,514 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-07-24 10:54:30,514 INFO L133 SettingsManager]: * Log string format=TERM [2018-07-24 10:54:30,515 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-07-24 10:54:30,515 INFO L133 SettingsManager]: * Interval Domain=false [2018-07-24 10:54:30,516 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-07-24 10:54:30,516 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-07-24 10:54:30,517 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-07-24 10:54:30,517 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-07-24 10:54:30,517 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-07-24 10:54:30,517 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-07-24 10:54:30,517 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-07-24 10:54:30,518 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-07-24 10:54:30,518 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-07-24 10:54:30,518 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-07-24 10:54:30,520 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-07-24 10:54:30,520 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-07-24 10:54:30,520 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:54:30,521 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-07-24 10:54:30,521 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-07-24 10:54:30,521 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-07-24 10:54:30,521 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-07-24 10:54:30,522 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-07-24 10:54:30,522 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-07-24 10:54:30,522 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-07-24 10:54:30,522 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-07-24 10:54:30,522 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-07-24 10:54:30,599 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-07-24 10:54:30,617 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-07-24 10:54:30,623 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-07-24 10:54:30,625 INFO L271 PluginConnector]: Initializing CDTParser... [2018-07-24 10:54:30,625 INFO L276 PluginConnector]: CDTParser initialized [2018-07-24 10:54:30,626 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-invgen/seq_true-unreach-call_true-termination.i [2018-07-24 10:54:30,984 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/21efb767e/22e85e50b8ef405a93c329afd9223802/FLAG47ba465f4 [2018-07-24 10:54:31,110 INFO L276 CDTParser]: Found 1 translation units. [2018-07-24 10:54:31,110 INFO L158 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-invgen/seq_true-unreach-call_true-termination.i [2018-07-24 10:54:31,117 INFO L324 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/21efb767e/22e85e50b8ef405a93c329afd9223802/FLAG47ba465f4 [2018-07-24 10:54:31,137 INFO L332 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/21efb767e/22e85e50b8ef405a93c329afd9223802 [2018-07-24 10:54:31,148 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-07-24 10:54:31,150 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-07-24 10:54:31,151 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-07-24 10:54:31,151 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-07-24 10:54:31,158 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-07-24 10:54:31,159 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:54:31" (1/1) ... [2018-07-24 10:54:31,162 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@f4b242b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:31, skipping insertion in model container [2018-07-24 10:54:31,162 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:54:31" (1/1) ... [2018-07-24 10:54:31,347 INFO L179 PRDispatcher]: Starting pre-run dispatcher in SV-COMP mode [2018-07-24 10:54:31,392 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:54:31,410 INFO L422 MainDispatcher]: Starting main dispatcher in SV-COMP mode [2018-07-24 10:54:31,426 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:54:31,443 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:31 WrapperNode [2018-07-24 10:54:31,443 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-07-24 10:54:31,444 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-07-24 10:54:31,444 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-07-24 10:54:31,444 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-07-24 10:54:31,455 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:31" (1/1) ... [2018-07-24 10:54:31,461 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:31" (1/1) ... [2018-07-24 10:54:31,468 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-07-24 10:54:31,469 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-07-24 10:54:31,469 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-07-24 10:54:31,469 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-07-24 10:54:31,479 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:31" (1/1) ... [2018-07-24 10:54:31,480 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:31" (1/1) ... [2018-07-24 10:54:31,481 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:31" (1/1) ... [2018-07-24 10:54:31,481 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:31" (1/1) ... [2018-07-24 10:54:31,484 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:31" (1/1) ... [2018-07-24 10:54:31,491 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:31" (1/1) ... [2018-07-24 10:54:31,493 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:31" (1/1) ... [2018-07-24 10:54:31,502 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-07-24 10:54:31,503 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-07-24 10:54:31,503 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-07-24 10:54:31,505 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-07-24 10:54:31,506 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:31" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:54:31,579 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-07-24 10:54:31,580 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-07-24 10:54:31,580 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-07-24 10:54:31,580 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-07-24 10:54:31,581 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-07-24 10:54:31,581 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-07-24 10:54:31,581 INFO L130 BoogieDeclarations]: Found specification of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assert [2018-07-24 10:54:31,582 INFO L138 BoogieDeclarations]: Found implementation of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assert [2018-07-24 10:54:32,038 INFO L261 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-07-24 10:54:32,038 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:54:32 BoogieIcfgContainer [2018-07-24 10:54:32,039 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-07-24 10:54:32,046 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-07-24 10:54:32,046 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-07-24 10:54:32,050 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-07-24 10:54:32,050 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.07 10:54:31" (1/3) ... [2018-07-24 10:54:32,050 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@15a16a15 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:54:32, skipping insertion in model container [2018-07-24 10:54:32,051 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:31" (2/3) ... [2018-07-24 10:54:32,051 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@15a16a15 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:54:32, skipping insertion in model container [2018-07-24 10:54:32,051 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:54:32" (3/3) ... [2018-07-24 10:54:32,053 INFO L112 eAbstractionObserver]: Analyzing ICFG seq_true-unreach-call_true-termination.i [2018-07-24 10:54:32,063 INFO L132 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-07-24 10:54:32,072 INFO L144 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-07-24 10:54:32,123 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-07-24 10:54:32,124 INFO L373 AbstractCegarLoop]: Interprodecural is true [2018-07-24 10:54:32,124 INFO L374 AbstractCegarLoop]: Hoare is true [2018-07-24 10:54:32,124 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-07-24 10:54:32,125 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-07-24 10:54:32,125 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-07-24 10:54:32,125 INFO L378 AbstractCegarLoop]: Difference is false [2018-07-24 10:54:32,125 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-07-24 10:54:32,125 INFO L384 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-07-24 10:54:32,142 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states. [2018-07-24 10:54:32,149 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-07-24 10:54:32,150 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:32,151 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:32,152 INFO L414 AbstractCegarLoop]: === Iteration 1 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:32,162 INFO L82 PathProgramCache]: Analyzing trace with hash 301890663, now seen corresponding path program 1 times [2018-07-24 10:54:32,167 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:32,216 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:32,216 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:32,216 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:32,216 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:32,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:32,297 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:32,299 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:54:32,299 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-07-24 10:54:32,300 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:54:32,305 INFO L450 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-07-24 10:54:32,320 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-07-24 10:54:32,321 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:54:32,324 INFO L87 Difference]: Start difference. First operand 27 states. Second operand 2 states. [2018-07-24 10:54:32,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:32,349 INFO L93 Difference]: Finished difference Result 45 states and 58 transitions. [2018-07-24 10:54:32,349 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-07-24 10:54:32,351 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 17 [2018-07-24 10:54:32,351 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:32,360 INFO L225 Difference]: With dead ends: 45 [2018-07-24 10:54:32,361 INFO L226 Difference]: Without dead ends: 23 [2018-07-24 10:54:32,367 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:54:32,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states. [2018-07-24 10:54:32,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 23. [2018-07-24 10:54:32,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23 states. [2018-07-24 10:54:32,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 25 transitions. [2018-07-24 10:54:32,423 INFO L78 Accepts]: Start accepts. Automaton has 23 states and 25 transitions. Word has length 17 [2018-07-24 10:54:32,424 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:32,424 INFO L471 AbstractCegarLoop]: Abstraction has 23 states and 25 transitions. [2018-07-24 10:54:32,424 INFO L472 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-07-24 10:54:32,425 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states and 25 transitions. [2018-07-24 10:54:32,425 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-07-24 10:54:32,426 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:32,426 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:32,426 INFO L414 AbstractCegarLoop]: === Iteration 2 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:32,427 INFO L82 PathProgramCache]: Analyzing trace with hash 1130037681, now seen corresponding path program 1 times [2018-07-24 10:54:32,427 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:32,429 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:32,430 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:32,430 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:32,430 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:32,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:32,631 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:32,632 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:54:32,632 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-07-24 10:54:32,632 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:54:32,634 INFO L450 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-07-24 10:54:32,634 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-07-24 10:54:32,635 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-07-24 10:54:32,635 INFO L87 Difference]: Start difference. First operand 23 states and 25 transitions. Second operand 7 states. [2018-07-24 10:54:33,059 WARN L169 SmtUtils]: Spent 122.00 ms on a formula simplification that was a NOOP. DAG size: 14 [2018-07-24 10:54:33,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:33,133 INFO L93 Difference]: Finished difference Result 48 states and 54 transitions. [2018-07-24 10:54:33,134 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-07-24 10:54:33,134 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 19 [2018-07-24 10:54:33,134 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:33,137 INFO L225 Difference]: With dead ends: 48 [2018-07-24 10:54:33,137 INFO L226 Difference]: Without dead ends: 35 [2018-07-24 10:54:33,138 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=39, Invalid=71, Unknown=0, NotChecked=0, Total=110 [2018-07-24 10:54:33,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states. [2018-07-24 10:54:33,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 28. [2018-07-24 10:54:33,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28 states. [2018-07-24 10:54:33,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 31 transitions. [2018-07-24 10:54:33,150 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 31 transitions. Word has length 19 [2018-07-24 10:54:33,150 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:33,150 INFO L471 AbstractCegarLoop]: Abstraction has 28 states and 31 transitions. [2018-07-24 10:54:33,151 INFO L472 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-07-24 10:54:33,151 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 31 transitions. [2018-07-24 10:54:33,152 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-07-24 10:54:33,153 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:33,153 INFO L353 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:33,153 INFO L414 AbstractCegarLoop]: === Iteration 3 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:33,154 INFO L82 PathProgramCache]: Analyzing trace with hash -1499928661, now seen corresponding path program 1 times [2018-07-24 10:54:33,154 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:33,155 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:33,156 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:33,156 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:33,157 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:33,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:33,279 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:33,279 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:54:33,280 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-07-24 10:54:33,280 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:54:33,281 INFO L450 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-07-24 10:54:33,281 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-07-24 10:54:33,281 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-07-24 10:54:33,281 INFO L87 Difference]: Start difference. First operand 28 states and 31 transitions. Second operand 6 states. [2018-07-24 10:54:33,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:33,384 INFO L93 Difference]: Finished difference Result 42 states and 46 transitions. [2018-07-24 10:54:33,384 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-07-24 10:54:33,385 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 21 [2018-07-24 10:54:33,385 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:33,386 INFO L225 Difference]: With dead ends: 42 [2018-07-24 10:54:33,386 INFO L226 Difference]: Without dead ends: 40 [2018-07-24 10:54:33,387 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-07-24 10:54:33,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-07-24 10:54:33,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 35. [2018-07-24 10:54:33,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35 states. [2018-07-24 10:54:33,394 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 38 transitions. [2018-07-24 10:54:33,394 INFO L78 Accepts]: Start accepts. Automaton has 35 states and 38 transitions. Word has length 21 [2018-07-24 10:54:33,395 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:33,395 INFO L471 AbstractCegarLoop]: Abstraction has 35 states and 38 transitions. [2018-07-24 10:54:33,395 INFO L472 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-07-24 10:54:33,395 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 38 transitions. [2018-07-24 10:54:33,396 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-07-24 10:54:33,396 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:33,396 INFO L353 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:33,397 INFO L414 AbstractCegarLoop]: === Iteration 4 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:33,397 INFO L82 PathProgramCache]: Analyzing trace with hash -1355895601, now seen corresponding path program 1 times [2018-07-24 10:54:33,397 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:33,398 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:33,398 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:33,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:33,399 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:33,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:33,666 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:33,667 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:33,667 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:33,677 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:33,677 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:33,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:33,705 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:34,125 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:34,126 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:34,408 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:34,432 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:34,432 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:34,448 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:34,449 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:34,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:34,478 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:34,488 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:34,489 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:34,566 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:34,568 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:34,568 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 14 [2018-07-24 10:54:34,568 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:34,569 INFO L450 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-07-24 10:54:34,569 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-07-24 10:54:34,570 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=137, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:54:34,573 INFO L87 Difference]: Start difference. First operand 35 states and 38 transitions. Second operand 14 states. [2018-07-24 10:54:34,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:34,919 INFO L93 Difference]: Finished difference Result 64 states and 72 transitions. [2018-07-24 10:54:34,920 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-07-24 10:54:34,920 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 29 [2018-07-24 10:54:34,920 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:34,924 INFO L225 Difference]: With dead ends: 64 [2018-07-24 10:54:34,924 INFO L226 Difference]: Without dead ends: 47 [2018-07-24 10:54:34,925 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 129 GetRequests, 99 SyntacticMatches, 12 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 122 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=105, Invalid=275, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:54:34,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2018-07-24 10:54:34,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 37. [2018-07-24 10:54:34,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2018-07-24 10:54:34,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 40 transitions. [2018-07-24 10:54:34,935 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 40 transitions. Word has length 29 [2018-07-24 10:54:34,935 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:34,935 INFO L471 AbstractCegarLoop]: Abstraction has 37 states and 40 transitions. [2018-07-24 10:54:34,935 INFO L472 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-07-24 10:54:34,935 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 40 transitions. [2018-07-24 10:54:34,936 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-07-24 10:54:34,936 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:34,937 INFO L353 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:34,937 INFO L414 AbstractCegarLoop]: === Iteration 5 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:34,937 INFO L82 PathProgramCache]: Analyzing trace with hash 95654235, now seen corresponding path program 1 times [2018-07-24 10:54:34,937 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:34,938 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:34,939 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:34,939 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:34,939 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:34,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:35,073 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:35,074 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:35,074 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:35,090 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:35,090 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:35,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:35,111 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:35,307 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:35,308 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:35,396 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:35,423 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:35,423 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:35,439 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:35,439 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:35,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:35,465 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:35,474 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:35,474 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:35,629 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:35,631 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:35,631 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 13 [2018-07-24 10:54:35,631 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:35,632 INFO L450 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-07-24 10:54:35,632 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-07-24 10:54:35,632 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=117, Unknown=0, NotChecked=0, Total=156 [2018-07-24 10:54:35,633 INFO L87 Difference]: Start difference. First operand 37 states and 40 transitions. Second operand 13 states. [2018-07-24 10:54:36,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:36,054 INFO L93 Difference]: Finished difference Result 79 states and 91 transitions. [2018-07-24 10:54:36,056 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-07-24 10:54:36,056 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 29 [2018-07-24 10:54:36,057 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:36,058 INFO L225 Difference]: With dead ends: 79 [2018-07-24 10:54:36,058 INFO L226 Difference]: Without dead ends: 62 [2018-07-24 10:54:36,059 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 130 GetRequests, 100 SyntacticMatches, 12 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 103 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=105, Invalid=275, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:54:36,059 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2018-07-24 10:54:36,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 40. [2018-07-24 10:54:36,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40 states. [2018-07-24 10:54:36,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 44 transitions. [2018-07-24 10:54:36,070 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 44 transitions. Word has length 29 [2018-07-24 10:54:36,071 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:36,071 INFO L471 AbstractCegarLoop]: Abstraction has 40 states and 44 transitions. [2018-07-24 10:54:36,071 INFO L472 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-07-24 10:54:36,071 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 44 transitions. [2018-07-24 10:54:36,072 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-07-24 10:54:36,073 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:36,073 INFO L353 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:36,073 INFO L414 AbstractCegarLoop]: === Iteration 6 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:36,074 INFO L82 PathProgramCache]: Analyzing trace with hash -446111159, now seen corresponding path program 2 times [2018-07-24 10:54:36,074 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:36,075 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:36,075 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:36,075 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:36,075 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:36,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:36,309 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 7 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:36,310 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:36,310 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:36,318 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:36,318 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:36,332 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:36,333 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:36,336 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:36,372 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:36,372 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:36,430 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:36,450 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:36,450 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:36,465 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:36,466 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:36,497 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:36,497 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:36,502 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:36,509 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:36,510 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:36,552 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:36,554 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:36,554 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7, 7, 7] total 10 [2018-07-24 10:54:36,554 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:36,554 INFO L450 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-07-24 10:54:36,555 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-07-24 10:54:36,555 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=68, Unknown=0, NotChecked=0, Total=90 [2018-07-24 10:54:36,555 INFO L87 Difference]: Start difference. First operand 40 states and 44 transitions. Second operand 10 states. [2018-07-24 10:54:36,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:36,740 INFO L93 Difference]: Finished difference Result 50 states and 54 transitions. [2018-07-24 10:54:36,740 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-07-24 10:54:36,741 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 31 [2018-07-24 10:54:36,741 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:36,743 INFO L225 Difference]: With dead ends: 50 [2018-07-24 10:54:36,743 INFO L226 Difference]: Without dead ends: 48 [2018-07-24 10:54:36,744 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 135 GetRequests, 117 SyntacticMatches, 8 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=35, Invalid=97, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:54:36,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states. [2018-07-24 10:54:36,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 48. [2018-07-24 10:54:36,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-07-24 10:54:36,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 52 transitions. [2018-07-24 10:54:36,751 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 52 transitions. Word has length 31 [2018-07-24 10:54:36,752 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:36,752 INFO L471 AbstractCegarLoop]: Abstraction has 48 states and 52 transitions. [2018-07-24 10:54:36,752 INFO L472 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-07-24 10:54:36,752 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 52 transitions. [2018-07-24 10:54:36,753 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-07-24 10:54:36,753 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:36,753 INFO L353 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:36,754 INFO L414 AbstractCegarLoop]: === Iteration 7 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:36,754 INFO L82 PathProgramCache]: Analyzing trace with hash 94447981, now seen corresponding path program 3 times [2018-07-24 10:54:36,754 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:36,755 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:36,755 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:36,755 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:36,755 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:36,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:36,894 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:36,895 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:36,895 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:36,907 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:36,907 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:36,936 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-07-24 10:54:36,937 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:36,941 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:37,125 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:37,125 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:37,258 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:37,279 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:37,279 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:37,295 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:37,295 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:37,331 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-07-24 10:54:37,331 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:37,336 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:37,348 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:37,348 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:37,502 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:37,504 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:37,505 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 18 [2018-07-24 10:54:37,505 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:37,505 INFO L450 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-07-24 10:54:37,506 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-07-24 10:54:37,506 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=71, Invalid=235, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:54:37,507 INFO L87 Difference]: Start difference. First operand 48 states and 52 transitions. Second operand 18 states. [2018-07-24 10:54:38,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:38,092 INFO L93 Difference]: Finished difference Result 87 states and 98 transitions. [2018-07-24 10:54:38,093 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-07-24 10:54:38,094 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 39 [2018-07-24 10:54:38,094 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:38,096 INFO L225 Difference]: With dead ends: 87 [2018-07-24 10:54:38,096 INFO L226 Difference]: Without dead ends: 66 [2018-07-24 10:54:38,097 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 173 GetRequests, 133 SyntacticMatches, 16 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 267 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=163, Invalid=487, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:54:38,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2018-07-24 10:54:38,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 50. [2018-07-24 10:54:38,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-07-24 10:54:38,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2018-07-24 10:54:38,106 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 39 [2018-07-24 10:54:38,107 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:38,107 INFO L471 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2018-07-24 10:54:38,107 INFO L472 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-07-24 10:54:38,107 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2018-07-24 10:54:38,108 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-07-24 10:54:38,108 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:38,108 INFO L353 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:38,109 INFO L414 AbstractCegarLoop]: === Iteration 8 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:38,109 INFO L82 PathProgramCache]: Analyzing trace with hash 594202361, now seen corresponding path program 1 times [2018-07-24 10:54:38,109 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:38,110 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:38,110 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:38,110 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:38,110 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:38,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:38,407 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 14 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:38,407 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:38,407 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:38,415 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:38,415 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:38,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:38,431 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:38,643 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 14 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:38,643 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:38,775 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 14 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:38,796 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:38,796 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:38,813 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:38,814 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:38,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:38,844 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:38,855 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 14 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:38,855 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:39,032 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 14 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:39,035 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:39,035 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 17 [2018-07-24 10:54:39,035 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:39,036 INFO L450 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-07-24 10:54:39,036 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-07-24 10:54:39,036 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=210, Unknown=0, NotChecked=0, Total=272 [2018-07-24 10:54:39,037 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 17 states. [2018-07-24 10:54:39,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:39,378 INFO L93 Difference]: Finished difference Result 103 states and 118 transitions. [2018-07-24 10:54:39,379 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-07-24 10:54:39,379 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 39 [2018-07-24 10:54:39,379 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:39,380 INFO L225 Difference]: With dead ends: 103 [2018-07-24 10:54:39,380 INFO L226 Difference]: Without dead ends: 82 [2018-07-24 10:54:39,381 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 175 GetRequests, 134 SyntacticMatches, 16 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 251 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=171, Invalid=531, Unknown=0, NotChecked=0, Total=702 [2018-07-24 10:54:39,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2018-07-24 10:54:39,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 50. [2018-07-24 10:54:39,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-07-24 10:54:39,391 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2018-07-24 10:54:39,391 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 39 [2018-07-24 10:54:39,391 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:39,392 INFO L471 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2018-07-24 10:54:39,392 INFO L472 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-07-24 10:54:39,392 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2018-07-24 10:54:39,393 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-07-24 10:54:39,393 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:39,393 INFO L353 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:39,393 INFO L414 AbstractCegarLoop]: === Iteration 9 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:39,394 INFO L82 PathProgramCache]: Analyzing trace with hash -1103599739, now seen corresponding path program 2 times [2018-07-24 10:54:39,394 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:39,394 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:39,395 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:39,395 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:39,395 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:39,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:39,534 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:39,535 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:39,535 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:39,542 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:39,543 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:39,554 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:39,554 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:39,557 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:39,764 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:39,765 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:39,820 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:39,841 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:39,841 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:39,878 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:39,878 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:39,907 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:39,908 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:39,911 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:39,923 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:39,923 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:39,999 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:40,000 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:40,000 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 16 [2018-07-24 10:54:40,001 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:40,001 INFO L450 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-07-24 10:54:40,001 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-07-24 10:54:40,002 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=183, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:54:40,002 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 16 states. [2018-07-24 10:54:40,673 WARN L169 SmtUtils]: Spent 127.00 ms on a formula simplification that was a NOOP. DAG size: 14 [2018-07-24 10:54:41,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:41,222 INFO L93 Difference]: Finished difference Result 122 states and 142 transitions. [2018-07-24 10:54:41,223 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-07-24 10:54:41,224 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 39 [2018-07-24 10:54:41,224 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:41,225 INFO L225 Difference]: With dead ends: 122 [2018-07-24 10:54:41,225 INFO L226 Difference]: Without dead ends: 101 [2018-07-24 10:54:41,228 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 175 GetRequests, 135 SyntacticMatches, 16 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 212 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=163, Invalid=487, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:54:41,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states. [2018-07-24 10:54:41,241 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 53. [2018-07-24 10:54:41,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53 states. [2018-07-24 10:54:41,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 58 transitions. [2018-07-24 10:54:41,243 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 58 transitions. Word has length 39 [2018-07-24 10:54:41,243 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:41,243 INFO L471 AbstractCegarLoop]: Abstraction has 53 states and 58 transitions. [2018-07-24 10:54:41,243 INFO L472 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-07-24 10:54:41,243 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 58 transitions. [2018-07-24 10:54:41,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-07-24 10:54:41,244 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:41,245 INFO L353 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:41,245 INFO L414 AbstractCegarLoop]: === Iteration 10 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:41,245 INFO L82 PathProgramCache]: Analyzing trace with hash -1990570393, now seen corresponding path program 4 times [2018-07-24 10:54:41,245 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:41,246 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:41,246 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:41,246 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:41,246 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:41,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:41,419 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 15 proven. 14 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-07-24 10:54:41,419 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:41,419 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:41,427 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:54:41,427 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:54:41,465 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:54:41,466 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:41,468 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:41,717 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:41,718 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:41,745 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:41,765 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:41,765 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:41,781 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:54:41,781 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:54:41,814 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:54:41,815 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:41,818 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:41,824 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:41,825 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:41,879 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:41,881 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:41,881 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 8, 8, 8] total 11 [2018-07-24 10:54:41,881 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:41,881 INFO L450 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-07-24 10:54:41,882 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-07-24 10:54:41,882 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2018-07-24 10:54:41,882 INFO L87 Difference]: Start difference. First operand 53 states and 58 transitions. Second operand 11 states. [2018-07-24 10:54:42,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:42,187 INFO L93 Difference]: Finished difference Result 63 states and 68 transitions. [2018-07-24 10:54:42,188 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-07-24 10:54:42,188 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 41 [2018-07-24 10:54:42,189 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:42,190 INFO L225 Difference]: With dead ends: 63 [2018-07-24 10:54:42,190 INFO L226 Difference]: Without dead ends: 61 [2018-07-24 10:54:42,190 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 177 GetRequests, 154 SyntacticMatches, 12 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=40, Invalid=116, Unknown=0, NotChecked=0, Total=156 [2018-07-24 10:54:42,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2018-07-24 10:54:42,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 61. [2018-07-24 10:54:42,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61 states. [2018-07-24 10:54:42,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 66 transitions. [2018-07-24 10:54:42,200 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 66 transitions. Word has length 41 [2018-07-24 10:54:42,200 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:42,201 INFO L471 AbstractCegarLoop]: Abstraction has 61 states and 66 transitions. [2018-07-24 10:54:42,201 INFO L472 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-07-24 10:54:42,201 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 66 transitions. [2018-07-24 10:54:42,202 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-07-24 10:54:42,202 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:42,202 INFO L353 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:42,202 INFO L414 AbstractCegarLoop]: === Iteration 11 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:42,203 INFO L82 PathProgramCache]: Analyzing trace with hash 1735104395, now seen corresponding path program 5 times [2018-07-24 10:54:42,203 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:42,204 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:42,204 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:42,204 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:42,204 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:42,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:42,406 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:42,406 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:42,406 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:42,415 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:54:42,415 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:42,435 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2018-07-24 10:54:42,435 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:42,438 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:42,869 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:42,870 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:43,132 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:43,153 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:43,153 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:43,168 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:54:43,168 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:43,218 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2018-07-24 10:54:43,218 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:43,221 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:43,234 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:43,234 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:43,434 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:43,436 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:43,436 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 22 [2018-07-24 10:54:43,436 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:43,437 INFO L450 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-07-24 10:54:43,437 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-07-24 10:54:43,437 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=103, Invalid=359, Unknown=0, NotChecked=0, Total=462 [2018-07-24 10:54:43,438 INFO L87 Difference]: Start difference. First operand 61 states and 66 transitions. Second operand 22 states. [2018-07-24 10:54:43,902 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:43,902 INFO L93 Difference]: Finished difference Result 110 states and 124 transitions. [2018-07-24 10:54:43,902 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-07-24 10:54:43,903 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 49 [2018-07-24 10:54:43,903 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:43,904 INFO L225 Difference]: With dead ends: 110 [2018-07-24 10:54:43,904 INFO L226 Difference]: Without dead ends: 85 [2018-07-24 10:54:43,905 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 217 GetRequests, 167 SyntacticMatches, 20 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 467 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=233, Invalid=759, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:54:43,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-07-24 10:54:43,915 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 63. [2018-07-24 10:54:43,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-07-24 10:54:43,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 68 transitions. [2018-07-24 10:54:43,917 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 68 transitions. Word has length 49 [2018-07-24 10:54:43,917 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:43,917 INFO L471 AbstractCegarLoop]: Abstraction has 63 states and 68 transitions. [2018-07-24 10:54:43,917 INFO L472 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-07-24 10:54:43,917 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 68 transitions. [2018-07-24 10:54:43,918 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-07-24 10:54:43,918 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:43,919 INFO L353 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:43,919 INFO L414 AbstractCegarLoop]: === Iteration 12 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:43,919 INFO L82 PathProgramCache]: Analyzing trace with hash 1916583447, now seen corresponding path program 2 times [2018-07-24 10:54:43,919 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:43,920 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:43,920 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:43,920 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:43,920 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:43,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:44,060 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:44,060 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:44,060 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:44,068 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:44,068 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:44,082 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:44,082 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:44,084 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:44,221 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:44,221 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:44,284 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:44,304 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:44,305 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:44,320 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:44,321 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:44,355 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:44,355 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:44,359 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:44,368 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:44,368 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:44,478 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:44,479 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:44,480 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 21 [2018-07-24 10:54:44,480 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:44,480 INFO L450 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-07-24 10:54:44,480 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-07-24 10:54:44,481 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=329, Unknown=0, NotChecked=0, Total=420 [2018-07-24 10:54:44,481 INFO L87 Difference]: Start difference. First operand 63 states and 68 transitions. Second operand 21 states. [2018-07-24 10:54:44,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:44,848 INFO L93 Difference]: Finished difference Result 132 states and 151 transitions. [2018-07-24 10:54:44,849 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-07-24 10:54:44,849 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 49 [2018-07-24 10:54:44,849 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:44,850 INFO L225 Difference]: With dead ends: 132 [2018-07-24 10:54:44,850 INFO L226 Difference]: Without dead ends: 107 [2018-07-24 10:54:44,851 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 220 GetRequests, 168 SyntacticMatches, 20 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 464 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=253, Invalid=869, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:54:44,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-07-24 10:54:44,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 63. [2018-07-24 10:54:44,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-07-24 10:54:44,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 68 transitions. [2018-07-24 10:54:44,864 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 68 transitions. Word has length 49 [2018-07-24 10:54:44,864 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:44,864 INFO L471 AbstractCegarLoop]: Abstraction has 63 states and 68 transitions. [2018-07-24 10:54:44,864 INFO L472 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-07-24 10:54:44,864 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 68 transitions. [2018-07-24 10:54:44,865 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-07-24 10:54:44,865 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:44,866 INFO L353 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:44,866 INFO L414 AbstractCegarLoop]: === Iteration 13 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:44,866 INFO L82 PathProgramCache]: Analyzing trace with hash -402778205, now seen corresponding path program 3 times [2018-07-24 10:54:44,866 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:44,867 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:44,867 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:44,867 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:44,867 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:44,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:45,004 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:45,005 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:45,005 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:45,013 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:45,013 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:45,048 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-07-24 10:54:45,048 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:45,050 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:45,211 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:45,211 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:45,265 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:45,286 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:45,286 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:45,304 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:45,304 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:45,350 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-07-24 10:54:45,350 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:45,353 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:45,363 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:45,364 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:45,449 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:45,450 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:45,451 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 20 [2018-07-24 10:54:45,451 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:45,451 INFO L450 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-07-24 10:54:45,451 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-07-24 10:54:45,452 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=297, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:54:45,452 INFO L87 Difference]: Start difference. First operand 63 states and 68 transitions. Second operand 20 states. [2018-07-24 10:54:45,889 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:45,889 INFO L93 Difference]: Finished difference Result 152 states and 176 transitions. [2018-07-24 10:54:45,889 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-07-24 10:54:45,889 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 49 [2018-07-24 10:54:45,890 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:45,891 INFO L225 Difference]: With dead ends: 152 [2018-07-24 10:54:45,891 INFO L226 Difference]: Without dead ends: 127 [2018-07-24 10:54:45,892 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 221 GetRequests, 169 SyntacticMatches, 20 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 430 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=253, Invalid=869, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:54:45,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2018-07-24 10:54:45,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 63. [2018-07-24 10:54:45,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-07-24 10:54:45,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 68 transitions. [2018-07-24 10:54:45,906 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 68 transitions. Word has length 49 [2018-07-24 10:54:45,906 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:45,906 INFO L471 AbstractCegarLoop]: Abstraction has 63 states and 68 transitions. [2018-07-24 10:54:45,907 INFO L472 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-07-24 10:54:45,907 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 68 transitions. [2018-07-24 10:54:45,908 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-07-24 10:54:45,908 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:45,908 INFO L353 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:45,908 INFO L414 AbstractCegarLoop]: === Iteration 14 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:45,908 INFO L82 PathProgramCache]: Analyzing trace with hash 488662063, now seen corresponding path program 3 times [2018-07-24 10:54:45,909 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:45,909 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:45,909 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:45,910 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:45,910 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:45,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:46,100 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:46,100 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:46,100 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:46,107 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:46,107 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:46,128 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-07-24 10:54:46,128 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:46,131 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:46,572 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:46,572 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:46,637 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:46,657 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:46,657 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:46,672 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:46,672 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:46,715 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-07-24 10:54:46,715 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:46,718 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:46,729 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:46,729 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:46,824 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:46,826 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:46,826 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 19 [2018-07-24 10:54:46,826 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:46,827 INFO L450 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-07-24 10:54:46,827 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-07-24 10:54:46,827 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=79, Invalid=263, Unknown=0, NotChecked=0, Total=342 [2018-07-24 10:54:46,827 INFO L87 Difference]: Start difference. First operand 63 states and 68 transitions. Second operand 19 states. [2018-07-24 10:54:47,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:47,363 INFO L93 Difference]: Finished difference Result 175 states and 205 transitions. [2018-07-24 10:54:47,364 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-07-24 10:54:47,364 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 49 [2018-07-24 10:54:47,364 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:47,365 INFO L225 Difference]: With dead ends: 175 [2018-07-24 10:54:47,365 INFO L226 Difference]: Without dead ends: 150 [2018-07-24 10:54:47,366 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 220 GetRequests, 170 SyntacticMatches, 20 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 359 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=233, Invalid=759, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:54:47,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-07-24 10:54:47,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 66. [2018-07-24 10:54:47,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-07-24 10:54:47,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 72 transitions. [2018-07-24 10:54:47,380 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 72 transitions. Word has length 49 [2018-07-24 10:54:47,380 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:47,380 INFO L471 AbstractCegarLoop]: Abstraction has 66 states and 72 transitions. [2018-07-24 10:54:47,381 INFO L472 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-07-24 10:54:47,381 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 72 transitions. [2018-07-24 10:54:47,381 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-07-24 10:54:47,381 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:47,382 INFO L353 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:47,382 INFO L414 AbstractCegarLoop]: === Iteration 15 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:47,382 INFO L82 PathProgramCache]: Analyzing trace with hash -396473339, now seen corresponding path program 6 times [2018-07-24 10:54:47,382 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:47,383 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:47,383 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:47,383 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:47,383 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:47,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:47,507 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 25 proven. 28 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-07-24 10:54:47,508 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:47,508 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:47,516 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:54:47,516 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:54:47,532 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2018-07-24 10:54:47,532 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:47,534 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:47,560 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 26 proven. 21 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:47,560 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:47,662 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 26 proven. 21 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:47,684 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:47,684 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:47,700 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:54:47,700 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:54:47,750 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2018-07-24 10:54:47,750 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:47,753 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:47,758 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 26 proven. 21 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:47,758 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:47,804 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 26 proven. 21 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:47,806 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:47,807 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 9, 9, 9] total 12 [2018-07-24 10:54:47,807 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:47,807 INFO L450 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-07-24 10:54:47,807 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-07-24 10:54:47,807 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=99, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:54:47,808 INFO L87 Difference]: Start difference. First operand 66 states and 72 transitions. Second operand 12 states. [2018-07-24 10:54:47,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:47,971 INFO L93 Difference]: Finished difference Result 76 states and 82 transitions. [2018-07-24 10:54:47,972 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-07-24 10:54:47,972 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 51 [2018-07-24 10:54:47,972 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:47,973 INFO L225 Difference]: With dead ends: 76 [2018-07-24 10:54:47,973 INFO L226 Difference]: Without dead ends: 74 [2018-07-24 10:54:47,974 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 219 GetRequests, 191 SyntacticMatches, 16 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 62 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=46, Invalid=136, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:54:47,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states. [2018-07-24 10:54:47,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 74. [2018-07-24 10:54:47,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-07-24 10:54:47,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 80 transitions. [2018-07-24 10:54:47,986 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 80 transitions. Word has length 51 [2018-07-24 10:54:47,987 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:47,987 INFO L471 AbstractCegarLoop]: Abstraction has 74 states and 80 transitions. [2018-07-24 10:54:47,987 INFO L472 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-07-24 10:54:47,987 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 80 transitions. [2018-07-24 10:54:47,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-07-24 10:54:47,988 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:47,988 INFO L353 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:47,988 INFO L414 AbstractCegarLoop]: === Iteration 16 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:47,989 INFO L82 PathProgramCache]: Analyzing trace with hash 928978729, now seen corresponding path program 7 times [2018-07-24 10:54:47,989 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:47,989 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:47,990 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:47,990 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:47,990 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:47,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:48,180 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:48,180 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:48,181 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:48,189 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:48,190 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:48,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:48,207 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:48,389 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:48,390 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:48,635 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:48,655 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:48,656 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:48,673 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:48,673 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:48,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:48,714 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:48,725 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:48,725 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:48,897 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:48,899 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:48,899 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 26 [2018-07-24 10:54:48,899 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:48,900 INFO L450 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-07-24 10:54:48,900 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-07-24 10:54:48,900 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=509, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:54:48,900 INFO L87 Difference]: Start difference. First operand 74 states and 80 transitions. Second operand 26 states. [2018-07-24 10:54:49,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:49,311 INFO L93 Difference]: Finished difference Result 133 states and 150 transitions. [2018-07-24 10:54:49,312 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-07-24 10:54:49,312 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 59 [2018-07-24 10:54:49,312 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:49,313 INFO L225 Difference]: With dead ends: 133 [2018-07-24 10:54:49,313 INFO L226 Difference]: Without dead ends: 104 [2018-07-24 10:54:49,314 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 261 GetRequests, 201 SyntacticMatches, 24 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 722 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=315, Invalid=1091, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:54:49,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states. [2018-07-24 10:54:49,326 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 76. [2018-07-24 10:54:49,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76 states. [2018-07-24 10:54:49,327 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 82 transitions. [2018-07-24 10:54:49,327 INFO L78 Accepts]: Start accepts. Automaton has 76 states and 82 transitions. Word has length 59 [2018-07-24 10:54:49,327 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:49,328 INFO L471 AbstractCegarLoop]: Abstraction has 76 states and 82 transitions. [2018-07-24 10:54:49,328 INFO L472 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-07-24 10:54:49,328 INFO L276 IsEmpty]: Start isEmpty. Operand 76 states and 82 transitions. [2018-07-24 10:54:49,328 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-07-24 10:54:49,329 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:49,329 INFO L353 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 4, 4, 4, 4, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:49,329 INFO L414 AbstractCegarLoop]: === Iteration 17 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:49,329 INFO L82 PathProgramCache]: Analyzing trace with hash 277511861, now seen corresponding path program 4 times [2018-07-24 10:54:49,329 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:49,330 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:49,330 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:49,330 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:49,330 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:49,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:49,493 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:49,493 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:49,493 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:49,503 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:54:49,504 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:54:49,524 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:54:49,524 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:49,526 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:49,803 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:49,803 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:49,963 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:49,983 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:49,983 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:49,998 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:54:49,998 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:54:50,045 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:54:50,045 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:50,049 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:50,059 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:50,059 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:50,178 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:50,179 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:50,179 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 25 [2018-07-24 10:54:50,179 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:50,180 INFO L450 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-07-24 10:54:50,180 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-07-24 10:54:50,180 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=126, Invalid=474, Unknown=0, NotChecked=0, Total=600 [2018-07-24 10:54:50,181 INFO L87 Difference]: Start difference. First operand 76 states and 82 transitions. Second operand 25 states. [2018-07-24 10:54:50,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:50,806 INFO L93 Difference]: Finished difference Result 161 states and 184 transitions. [2018-07-24 10:54:50,807 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-07-24 10:54:50,807 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 59 [2018-07-24 10:54:50,807 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:50,808 INFO L225 Difference]: With dead ends: 161 [2018-07-24 10:54:50,808 INFO L226 Difference]: Without dead ends: 132 [2018-07-24 10:54:50,809 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 265 GetRequests, 202 SyntacticMatches, 24 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 742 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=351, Invalid=1289, Unknown=0, NotChecked=0, Total=1640 [2018-07-24 10:54:50,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-07-24 10:54:50,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 76. [2018-07-24 10:54:50,824 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76 states. [2018-07-24 10:54:50,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 82 transitions. [2018-07-24 10:54:50,825 INFO L78 Accepts]: Start accepts. Automaton has 76 states and 82 transitions. Word has length 59 [2018-07-24 10:54:50,825 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:50,825 INFO L471 AbstractCegarLoop]: Abstraction has 76 states and 82 transitions. [2018-07-24 10:54:50,825 INFO L472 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-07-24 10:54:50,825 INFO L276 IsEmpty]: Start isEmpty. Operand 76 states and 82 transitions. [2018-07-24 10:54:50,825 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-07-24 10:54:50,825 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:50,826 INFO L353 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 4, 4, 4, 4, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:50,826 INFO L414 AbstractCegarLoop]: === Iteration 18 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:50,826 INFO L82 PathProgramCache]: Analyzing trace with hash -129869503, now seen corresponding path program 5 times [2018-07-24 10:54:50,826 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:50,827 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:50,827 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:50,827 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:50,827 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:50,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:51,008 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 44 proven. 12 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:51,009 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:51,009 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:51,016 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:54:51,016 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:51,036 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2018-07-24 10:54:51,036 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:51,038 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:51,177 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 44 proven. 12 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:51,177 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:51,310 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 44 proven. 12 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:51,330 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:51,331 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:51,346 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:54:51,346 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:51,401 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2018-07-24 10:54:51,401 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:51,405 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:51,417 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 44 proven. 12 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:51,418 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:51,598 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 44 proven. 12 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:51,600 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:51,600 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 24 [2018-07-24 10:54:51,600 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:51,600 INFO L450 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-07-24 10:54:51,600 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-07-24 10:54:51,601 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=115, Invalid=437, Unknown=0, NotChecked=0, Total=552 [2018-07-24 10:54:51,601 INFO L87 Difference]: Start difference. First operand 76 states and 82 transitions. Second operand 24 states. [2018-07-24 10:54:52,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:52,132 INFO L93 Difference]: Finished difference Result 187 states and 216 transitions. [2018-07-24 10:54:52,132 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-07-24 10:54:52,132 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 59 [2018-07-24 10:54:52,133 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:52,134 INFO L225 Difference]: With dead ends: 187 [2018-07-24 10:54:52,134 INFO L226 Difference]: Without dead ends: 158 [2018-07-24 10:54:52,135 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 267 GetRequests, 203 SyntacticMatches, 24 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 724 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=364, Invalid=1358, Unknown=0, NotChecked=0, Total=1722 [2018-07-24 10:54:52,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states. [2018-07-24 10:54:52,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 76. [2018-07-24 10:54:52,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76 states. [2018-07-24 10:54:52,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 82 transitions. [2018-07-24 10:54:52,154 INFO L78 Accepts]: Start accepts. Automaton has 76 states and 82 transitions. Word has length 59 [2018-07-24 10:54:52,154 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:52,154 INFO L471 AbstractCegarLoop]: Abstraction has 76 states and 82 transitions. [2018-07-24 10:54:52,154 INFO L472 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-07-24 10:54:52,155 INFO L276 IsEmpty]: Start isEmpty. Operand 76 states and 82 transitions. [2018-07-24 10:54:52,155 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-07-24 10:54:52,155 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:52,156 INFO L353 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 4, 4, 4, 4, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:52,156 INFO L414 AbstractCegarLoop]: === Iteration 19 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:52,156 INFO L82 PathProgramCache]: Analyzing trace with hash -49846579, now seen corresponding path program 6 times [2018-07-24 10:54:52,156 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:52,157 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:52,157 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:52,157 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:52,158 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:52,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:52,344 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:52,345 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:52,345 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:52,354 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:54:52,354 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:54:52,382 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2018-07-24 10:54:52,383 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:52,386 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:53,090 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:53,091 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:53,246 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:53,266 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:53,266 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:53,285 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:54:53,285 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:54:53,346 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2018-07-24 10:54:53,346 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:53,350 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:53,358 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:53,358 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:53,595 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:53,596 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:53,596 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 23 [2018-07-24 10:54:53,597 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:53,597 INFO L450 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-07-24 10:54:53,597 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-07-24 10:54:53,597 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=108, Invalid=398, Unknown=0, NotChecked=0, Total=506 [2018-07-24 10:54:53,598 INFO L87 Difference]: Start difference. First operand 76 states and 82 transitions. Second operand 23 states. [2018-07-24 10:54:54,270 WARN L169 SmtUtils]: Spent 145.00 ms on a formula simplification that was a NOOP. DAG size: 13 [2018-07-24 10:54:54,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:54,497 INFO L93 Difference]: Finished difference Result 211 states and 246 transitions. [2018-07-24 10:54:54,497 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-07-24 10:54:54,497 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 59 [2018-07-24 10:54:54,498 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:54,499 INFO L225 Difference]: With dead ends: 211 [2018-07-24 10:54:54,499 INFO L226 Difference]: Without dead ends: 182 [2018-07-24 10:54:54,500 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 267 GetRequests, 204 SyntacticMatches, 24 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 659 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=351, Invalid=1289, Unknown=0, NotChecked=0, Total=1640 [2018-07-24 10:54:54,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states. [2018-07-24 10:54:54,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 76. [2018-07-24 10:54:54,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76 states. [2018-07-24 10:54:54,519 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 82 transitions. [2018-07-24 10:54:54,519 INFO L78 Accepts]: Start accepts. Automaton has 76 states and 82 transitions. Word has length 59 [2018-07-24 10:54:54,520 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:54,520 INFO L471 AbstractCegarLoop]: Abstraction has 76 states and 82 transitions. [2018-07-24 10:54:54,520 INFO L472 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-07-24 10:54:54,520 INFO L276 IsEmpty]: Start isEmpty. Operand 76 states and 82 transitions. [2018-07-24 10:54:54,520 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-07-24 10:54:54,520 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:54,521 INFO L353 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:54,521 INFO L414 AbstractCegarLoop]: === Iteration 20 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:54,521 INFO L82 PathProgramCache]: Analyzing trace with hash 1451911001, now seen corresponding path program 4 times [2018-07-24 10:54:54,521 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:54,522 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:54,522 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:54,522 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:54,522 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:54,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:54,777 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:54,777 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:54,777 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:54,784 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:54:54,785 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:54:54,801 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:54:54,801 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:54,803 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:54,923 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:54,923 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:54,992 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:55,012 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:55,013 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:55,028 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:54:55,028 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:54:55,074 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:54:55,074 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:55,078 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:55,085 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:55,085 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:55,171 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:55,172 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:55,172 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 22 [2018-07-24 10:54:55,172 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:55,173 INFO L450 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-07-24 10:54:55,173 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-07-24 10:54:55,173 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=357, Unknown=0, NotChecked=0, Total=462 [2018-07-24 10:54:55,173 INFO L87 Difference]: Start difference. First operand 76 states and 82 transitions. Second operand 22 states. [2018-07-24 10:54:55,586 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:55,586 INFO L93 Difference]: Finished difference Result 238 states and 280 transitions. [2018-07-24 10:54:55,587 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-07-24 10:54:55,587 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 59 [2018-07-24 10:54:55,587 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:55,588 INFO L225 Difference]: With dead ends: 238 [2018-07-24 10:54:55,588 INFO L226 Difference]: Without dead ends: 209 [2018-07-24 10:54:55,589 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 265 GetRequests, 205 SyntacticMatches, 24 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 544 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=315, Invalid=1091, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:54:55,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 209 states. [2018-07-24 10:54:55,613 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 209 to 79. [2018-07-24 10:54:55,613 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79 states. [2018-07-24 10:54:55,614 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 86 transitions. [2018-07-24 10:54:55,614 INFO L78 Accepts]: Start accepts. Automaton has 79 states and 86 transitions. Word has length 59 [2018-07-24 10:54:55,614 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:55,614 INFO L471 AbstractCegarLoop]: Abstraction has 79 states and 86 transitions. [2018-07-24 10:54:55,614 INFO L472 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-07-24 10:54:55,614 INFO L276 IsEmpty]: Start isEmpty. Operand 79 states and 86 transitions. [2018-07-24 10:54:55,615 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-07-24 10:54:55,615 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:55,615 INFO L353 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:55,615 INFO L414 AbstractCegarLoop]: === Iteration 21 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:55,616 INFO L82 PathProgramCache]: Analyzing trace with hash 1954413347, now seen corresponding path program 8 times [2018-07-24 10:54:55,616 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:55,616 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:55,616 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:55,617 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:55,617 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:55,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:55,724 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 37 proven. 46 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-07-24 10:54:55,724 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:55,724 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:55,732 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:55,732 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:55,749 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:55,750 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:55,751 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:55,784 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 36 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:55,784 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:55,839 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 36 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:55,860 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:55,860 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:55,875 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:55,875 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:55,920 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:55,920 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:55,924 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:55,929 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 36 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:55,929 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:55,990 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 36 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:55,991 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:55,992 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 10, 10, 10] total 13 [2018-07-24 10:54:55,992 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:55,992 INFO L450 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-07-24 10:54:55,992 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-07-24 10:54:55,992 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=116, Unknown=0, NotChecked=0, Total=156 [2018-07-24 10:54:55,993 INFO L87 Difference]: Start difference. First operand 79 states and 86 transitions. Second operand 13 states. [2018-07-24 10:54:56,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:56,132 INFO L93 Difference]: Finished difference Result 89 states and 96 transitions. [2018-07-24 10:54:56,133 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-07-24 10:54:56,133 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 61 [2018-07-24 10:54:56,134 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:56,135 INFO L225 Difference]: With dead ends: 89 [2018-07-24 10:54:56,135 INFO L226 Difference]: Without dead ends: 87 [2018-07-24 10:54:56,135 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 261 GetRequests, 228 SyntacticMatches, 20 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 87 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=53, Invalid=157, Unknown=0, NotChecked=0, Total=210 [2018-07-24 10:54:56,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2018-07-24 10:54:56,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 87. [2018-07-24 10:54:56,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2018-07-24 10:54:56,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 94 transitions. [2018-07-24 10:54:56,155 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 94 transitions. Word has length 61 [2018-07-24 10:54:56,155 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:56,155 INFO L471 AbstractCegarLoop]: Abstraction has 87 states and 94 transitions. [2018-07-24 10:54:56,155 INFO L472 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-07-24 10:54:56,155 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 94 transitions. [2018-07-24 10:54:56,156 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-07-24 10:54:56,156 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:56,156 INFO L353 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:56,156 INFO L414 AbstractCegarLoop]: === Iteration 22 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:56,156 INFO L82 PathProgramCache]: Analyzing trace with hash 1550108743, now seen corresponding path program 9 times [2018-07-24 10:54:56,156 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:56,157 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:56,157 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:56,157 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:56,157 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:56,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:57,033 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:57,033 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:57,033 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:57,040 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:57,041 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:57,067 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-07-24 10:54:57,067 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:57,070 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:57,650 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:57,651 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:57,749 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:57,769 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:57,769 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:57,784 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:57,784 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:57,862 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-07-24 10:54:57,862 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:57,867 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:57,877 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:57,877 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:57,993 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:57,995 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:57,995 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 30 [2018-07-24 10:54:57,995 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:57,996 INFO L450 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-07-24 10:54:57,996 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-07-24 10:54:57,996 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=185, Invalid=685, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:54:57,996 INFO L87 Difference]: Start difference. First operand 87 states and 94 transitions. Second operand 30 states. [2018-07-24 10:54:58,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:58,434 INFO L93 Difference]: Finished difference Result 156 states and 176 transitions. [2018-07-24 10:54:58,435 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-07-24 10:54:58,435 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 69 [2018-07-24 10:54:58,435 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:58,436 INFO L225 Difference]: With dead ends: 156 [2018-07-24 10:54:58,436 INFO L226 Difference]: Without dead ends: 123 [2018-07-24 10:54:58,437 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 305 GetRequests, 235 SyntacticMatches, 28 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1032 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=409, Invalid=1483, Unknown=0, NotChecked=0, Total=1892 [2018-07-24 10:54:58,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states. [2018-07-24 10:54:58,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 89. [2018-07-24 10:54:58,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-07-24 10:54:58,460 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 96 transitions. [2018-07-24 10:54:58,460 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 96 transitions. Word has length 69 [2018-07-24 10:54:58,460 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:58,460 INFO L471 AbstractCegarLoop]: Abstraction has 89 states and 96 transitions. [2018-07-24 10:54:58,460 INFO L472 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-07-24 10:54:58,460 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 96 transitions. [2018-07-24 10:54:58,461 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-07-24 10:54:58,461 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:58,461 INFO L353 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 5, 5, 5, 5, 5, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:58,461 INFO L414 AbstractCegarLoop]: === Iteration 23 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:58,461 INFO L82 PathProgramCache]: Analyzing trace with hash 1825386707, now seen corresponding path program 7 times [2018-07-24 10:54:58,462 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:58,462 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:58,462 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:58,462 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:58,462 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:58,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:58,657 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:58,657 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:58,657 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:58,664 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:58,664 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:58,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:58,691 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:59,591 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:59,591 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:59,701 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:59,722 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:59,722 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:59,739 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:59,740 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:59,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:59,790 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:59,801 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:59,801 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:59,922 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:59,923 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:59,923 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 29 [2018-07-24 10:54:59,923 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:59,924 INFO L450 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-07-24 10:54:59,924 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-07-24 10:54:59,924 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=167, Invalid=645, Unknown=0, NotChecked=0, Total=812 [2018-07-24 10:54:59,925 INFO L87 Difference]: Start difference. First operand 89 states and 96 transitions. Second operand 29 states. [2018-07-24 10:55:00,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:00,436 INFO L93 Difference]: Finished difference Result 190 states and 217 transitions. [2018-07-24 10:55:00,436 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-07-24 10:55:00,437 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 69 [2018-07-24 10:55:00,437 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:00,438 INFO L225 Difference]: With dead ends: 190 [2018-07-24 10:55:00,438 INFO L226 Difference]: Without dead ends: 157 [2018-07-24 10:55:00,439 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 310 GetRequests, 236 SyntacticMatches, 28 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1085 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=465, Invalid=1791, Unknown=0, NotChecked=0, Total=2256 [2018-07-24 10:55:00,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-07-24 10:55:00,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 89. [2018-07-24 10:55:00,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-07-24 10:55:00,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 96 transitions. [2018-07-24 10:55:00,469 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 96 transitions. Word has length 69 [2018-07-24 10:55:00,469 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:00,469 INFO L471 AbstractCegarLoop]: Abstraction has 89 states and 96 transitions. [2018-07-24 10:55:00,469 INFO L472 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-07-24 10:55:00,469 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 96 transitions. [2018-07-24 10:55:00,470 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-07-24 10:55:00,470 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:00,470 INFO L353 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 5, 5, 5, 5, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:00,470 INFO L414 AbstractCegarLoop]: === Iteration 24 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:00,470 INFO L82 PathProgramCache]: Analyzing trace with hash -1995551649, now seen corresponding path program 8 times [2018-07-24 10:55:00,470 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:00,471 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:00,471 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:00,471 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:00,471 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:00,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:01,078 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:01,079 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:01,079 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:01,089 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:01,089 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:01,109 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:01,110 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:01,112 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:01,328 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:01,328 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:01,421 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:01,441 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:01,442 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:01,457 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:01,457 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:01,506 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:01,506 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:01,510 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:01,526 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:01,526 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:01,672 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:01,673 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:01,674 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 28 [2018-07-24 10:55:01,674 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:01,674 INFO L450 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-07-24 10:55:01,674 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-07-24 10:55:01,675 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=603, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:55:01,675 INFO L87 Difference]: Start difference. First operand 89 states and 96 transitions. Second operand 28 states. [2018-07-24 10:55:02,203 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:02,203 INFO L93 Difference]: Finished difference Result 222 states and 256 transitions. [2018-07-24 10:55:02,204 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-07-24 10:55:02,204 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 69 [2018-07-24 10:55:02,204 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:02,205 INFO L225 Difference]: With dead ends: 222 [2018-07-24 10:55:02,205 INFO L226 Difference]: Without dead ends: 189 [2018-07-24 10:55:02,206 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 313 GetRequests, 237 SyntacticMatches, 28 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1095 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=496, Invalid=1954, Unknown=0, NotChecked=0, Total=2450 [2018-07-24 10:55:02,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2018-07-24 10:55:02,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 89. [2018-07-24 10:55:02,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-07-24 10:55:02,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 96 transitions. [2018-07-24 10:55:02,233 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 96 transitions. Word has length 69 [2018-07-24 10:55:02,234 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:02,234 INFO L471 AbstractCegarLoop]: Abstraction has 89 states and 96 transitions. [2018-07-24 10:55:02,234 INFO L472 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-07-24 10:55:02,234 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 96 transitions. [2018-07-24 10:55:02,234 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-07-24 10:55:02,234 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:02,235 INFO L353 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 5, 5, 5, 5, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:02,235 INFO L414 AbstractCegarLoop]: === Iteration 25 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:02,235 INFO L82 PathProgramCache]: Analyzing trace with hash 632871659, now seen corresponding path program 9 times [2018-07-24 10:55:02,235 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:02,236 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:02,236 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:02,236 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:02,236 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:02,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:02,418 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:02,419 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:02,419 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:02,427 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:02,427 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:02,451 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-07-24 10:55:02,452 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:02,454 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:02,618 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:02,618 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:02,769 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:02,790 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:02,790 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:02,805 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:02,806 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:02,884 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-07-24 10:55:02,884 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:02,888 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:02,901 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:02,901 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:03,039 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:03,040 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:03,041 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 27 [2018-07-24 10:55:03,041 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:03,041 INFO L450 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-07-24 10:55:03,041 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-07-24 10:55:03,041 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=143, Invalid=559, Unknown=0, NotChecked=0, Total=702 [2018-07-24 10:55:03,042 INFO L87 Difference]: Start difference. First operand 89 states and 96 transitions. Second operand 27 states. [2018-07-24 10:55:03,922 WARN L169 SmtUtils]: Spent 124.00 ms on a formula simplification that was a NOOP. DAG size: 14 [2018-07-24 10:55:04,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:04,096 INFO L93 Difference]: Finished difference Result 252 states and 293 transitions. [2018-07-24 10:55:04,097 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-07-24 10:55:04,097 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 69 [2018-07-24 10:55:04,097 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:04,098 INFO L225 Difference]: With dead ends: 252 [2018-07-24 10:55:04,098 INFO L226 Difference]: Without dead ends: 219 [2018-07-24 10:55:04,099 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 314 GetRequests, 238 SyntacticMatches, 28 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1048 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=496, Invalid=1954, Unknown=0, NotChecked=0, Total=2450 [2018-07-24 10:55:04,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219 states. [2018-07-24 10:55:04,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219 to 89. [2018-07-24 10:55:04,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-07-24 10:55:04,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 96 transitions. [2018-07-24 10:55:04,136 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 96 transitions. Word has length 69 [2018-07-24 10:55:04,136 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:04,136 INFO L471 AbstractCegarLoop]: Abstraction has 89 states and 96 transitions. [2018-07-24 10:55:04,136 INFO L472 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-07-24 10:55:04,136 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 96 transitions. [2018-07-24 10:55:04,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-07-24 10:55:04,137 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:04,137 INFO L353 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 5, 5, 5, 5, 5, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:04,137 INFO L414 AbstractCegarLoop]: === Iteration 26 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:04,137 INFO L82 PathProgramCache]: Analyzing trace with hash 613260407, now seen corresponding path program 10 times [2018-07-24 10:55:04,137 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:04,138 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:04,138 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:04,138 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:04,138 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:04,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:04,287 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:04,287 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:04,287 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:04,294 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:04,294 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:04,316 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:04,316 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:04,319 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:04,579 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:04,579 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:04,669 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:04,690 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:04,690 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:04,705 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:04,705 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:04,763 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:04,763 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:04,767 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:04,785 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:04,785 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:04,928 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:04,929 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:04,930 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 26 [2018-07-24 10:55:04,930 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:04,930 INFO L450 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-07-24 10:55:04,930 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-07-24 10:55:04,931 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=137, Invalid=513, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:55:04,931 INFO L87 Difference]: Start difference. First operand 89 states and 96 transitions. Second operand 26 states. [2018-07-24 10:55:05,547 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:05,547 INFO L93 Difference]: Finished difference Result 280 states and 328 transitions. [2018-07-24 10:55:05,548 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-07-24 10:55:05,548 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 69 [2018-07-24 10:55:05,548 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:05,549 INFO L225 Difference]: With dead ends: 280 [2018-07-24 10:55:05,549 INFO L226 Difference]: Without dead ends: 247 [2018-07-24 10:55:05,550 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 313 GetRequests, 239 SyntacticMatches, 28 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 938 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=465, Invalid=1791, Unknown=0, NotChecked=0, Total=2256 [2018-07-24 10:55:05,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 247 states. [2018-07-24 10:55:05,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 247 to 89. [2018-07-24 10:55:05,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-07-24 10:55:05,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 96 transitions. [2018-07-24 10:55:05,588 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 96 transitions. Word has length 69 [2018-07-24 10:55:05,588 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:05,588 INFO L471 AbstractCegarLoop]: Abstraction has 89 states and 96 transitions. [2018-07-24 10:55:05,588 INFO L472 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-07-24 10:55:05,588 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 96 transitions. [2018-07-24 10:55:05,589 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-07-24 10:55:05,589 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:05,589 INFO L353 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:05,589 INFO L414 AbstractCegarLoop]: === Iteration 27 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:05,590 INFO L82 PathProgramCache]: Analyzing trace with hash 1618825475, now seen corresponding path program 5 times [2018-07-24 10:55:05,590 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:05,590 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:05,592 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:05,593 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:05,593 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:05,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:05,757 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:05,758 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:05,758 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:05,765 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:05,765 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:05,790 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-07-24 10:55:05,790 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:05,793 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:06,101 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:06,101 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:06,190 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:06,211 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:06,211 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:06,227 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:06,227 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:06,302 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-07-24 10:55:06,302 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:06,306 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:06,315 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:06,315 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:06,431 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:06,432 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:06,433 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 25 [2018-07-24 10:55:06,433 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:06,433 INFO L450 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-07-24 10:55:06,433 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-07-24 10:55:06,434 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=135, Invalid=465, Unknown=0, NotChecked=0, Total=600 [2018-07-24 10:55:06,434 INFO L87 Difference]: Start difference. First operand 89 states and 96 transitions. Second operand 25 states. [2018-07-24 10:55:07,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:07,046 INFO L93 Difference]: Finished difference Result 311 states and 367 transitions. [2018-07-24 10:55:07,046 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-07-24 10:55:07,047 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 69 [2018-07-24 10:55:07,047 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:07,048 INFO L225 Difference]: With dead ends: 311 [2018-07-24 10:55:07,048 INFO L226 Difference]: Without dead ends: 278 [2018-07-24 10:55:07,049 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 310 GetRequests, 240 SyntacticMatches, 28 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 767 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=409, Invalid=1483, Unknown=0, NotChecked=0, Total=1892 [2018-07-24 10:55:07,050 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 278 states. [2018-07-24 10:55:07,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 278 to 92. [2018-07-24 10:55:07,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2018-07-24 10:55:07,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 100 transitions. [2018-07-24 10:55:07,083 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 100 transitions. Word has length 69 [2018-07-24 10:55:07,083 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:07,083 INFO L471 AbstractCegarLoop]: Abstraction has 92 states and 100 transitions. [2018-07-24 10:55:07,083 INFO L472 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-07-24 10:55:07,083 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 100 transitions. [2018-07-24 10:55:07,084 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-07-24 10:55:07,084 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:07,084 INFO L353 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 6, 6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:07,084 INFO L414 AbstractCegarLoop]: === Iteration 28 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:07,084 INFO L82 PathProgramCache]: Analyzing trace with hash 2111470529, now seen corresponding path program 10 times [2018-07-24 10:55:07,085 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:07,085 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:07,085 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:07,085 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:07,086 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:07,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:08,380 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 51 proven. 68 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-07-24 10:55:08,380 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:08,380 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:08,396 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:08,396 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:08,442 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:08,443 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:08,445 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:08,691 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 52 proven. 55 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:08,691 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:08,745 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 52 proven. 55 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:08,767 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:08,767 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:08,782 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:08,782 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:08,843 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:08,843 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:08,848 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:08,857 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 52 proven. 55 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:08,857 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:09,150 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 52 proven. 55 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:55:09,151 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:09,152 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11, 11, 11, 11] total 14 [2018-07-24 10:55:09,152 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:09,152 INFO L450 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-07-24 10:55:09,152 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-07-24 10:55:09,152 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=134, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:55:09,153 INFO L87 Difference]: Start difference. First operand 92 states and 100 transitions. Second operand 14 states. [2018-07-24 10:55:09,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:09,964 INFO L93 Difference]: Finished difference Result 102 states and 110 transitions. [2018-07-24 10:55:09,964 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-07-24 10:55:09,964 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 71 [2018-07-24 10:55:09,965 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:09,965 INFO L225 Difference]: With dead ends: 102 [2018-07-24 10:55:09,966 INFO L226 Difference]: Without dead ends: 100 [2018-07-24 10:55:09,966 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 303 GetRequests, 265 SyntacticMatches, 24 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 116 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=61, Invalid=179, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:55:09,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states. [2018-07-24 10:55:10,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 100. [2018-07-24 10:55:10,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 100 states. [2018-07-24 10:55:10,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 108 transitions. [2018-07-24 10:55:10,005 INFO L78 Accepts]: Start accepts. Automaton has 100 states and 108 transitions. Word has length 71 [2018-07-24 10:55:10,005 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:10,005 INFO L471 AbstractCegarLoop]: Abstraction has 100 states and 108 transitions. [2018-07-24 10:55:10,005 INFO L472 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-07-24 10:55:10,006 INFO L276 IsEmpty]: Start isEmpty. Operand 100 states and 108 transitions. [2018-07-24 10:55:10,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-07-24 10:55:10,006 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:10,006 INFO L353 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:10,007 INFO L414 AbstractCegarLoop]: === Iteration 29 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:10,007 INFO L82 PathProgramCache]: Analyzing trace with hash 58575589, now seen corresponding path program 11 times [2018-07-24 10:55:10,007 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:10,007 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:10,007 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:10,008 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:10,008 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:10,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:10,296 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:10,297 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:10,297 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:10,306 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:10,306 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:10,333 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-07-24 10:55:10,334 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:10,336 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:11,356 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:11,357 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:11,479 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:11,499 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:11,499 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:11,516 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:11,516 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:11,607 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-07-24 10:55:11,607 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:11,611 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:11,628 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:11,629 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:11,767 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:11,768 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:11,768 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 34 [2018-07-24 10:55:11,769 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:11,769 INFO L450 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-07-24 10:55:11,769 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-07-24 10:55:11,769 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=235, Invalid=887, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:55:11,770 INFO L87 Difference]: Start difference. First operand 100 states and 108 transitions. Second operand 34 states. [2018-07-24 10:55:12,305 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:12,305 INFO L93 Difference]: Finished difference Result 179 states and 202 transitions. [2018-07-24 10:55:12,305 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-07-24 10:55:12,305 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 79 [2018-07-24 10:55:12,305 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:12,306 INFO L225 Difference]: With dead ends: 179 [2018-07-24 10:55:12,306 INFO L226 Difference]: Without dead ends: 142 [2018-07-24 10:55:12,307 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 349 GetRequests, 269 SyntacticMatches, 32 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1397 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=515, Invalid=1935, Unknown=0, NotChecked=0, Total=2450 [2018-07-24 10:55:12,308 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2018-07-24 10:55:12,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 102. [2018-07-24 10:55:12,344 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-07-24 10:55:12,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 110 transitions. [2018-07-24 10:55:12,345 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 110 transitions. Word has length 79 [2018-07-24 10:55:12,345 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:12,345 INFO L471 AbstractCegarLoop]: Abstraction has 102 states and 110 transitions. [2018-07-24 10:55:12,345 INFO L472 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-07-24 10:55:12,345 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 110 transitions. [2018-07-24 10:55:12,346 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-07-24 10:55:12,346 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:12,346 INFO L353 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 6, 6, 6, 6, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:12,346 INFO L414 AbstractCegarLoop]: === Iteration 30 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:12,346 INFO L82 PathProgramCache]: Analyzing trace with hash 127267953, now seen corresponding path program 11 times [2018-07-24 10:55:12,346 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:12,347 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:12,347 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:12,347 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:12,347 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:12,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:12,546 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:12,547 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:12,547 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:12,554 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:12,554 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:12,674 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-07-24 10:55:12,675 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:12,677 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:13,540 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:13,540 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:13,838 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:13,860 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:13,860 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:13,876 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:13,876 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:13,967 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-07-24 10:55:13,967 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:13,971 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:13,987 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:13,987 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:14,471 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:14,473 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:14,473 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 33 [2018-07-24 10:55:14,473 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:14,474 INFO L450 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-07-24 10:55:14,474 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-07-24 10:55:14,474 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=214, Invalid=842, Unknown=0, NotChecked=0, Total=1056 [2018-07-24 10:55:14,474 INFO L87 Difference]: Start difference. First operand 102 states and 110 transitions. Second operand 33 states. [2018-07-24 10:55:15,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:15,132 INFO L93 Difference]: Finished difference Result 219 states and 250 transitions. [2018-07-24 10:55:15,133 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-07-24 10:55:15,133 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 79 [2018-07-24 10:55:15,133 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:15,134 INFO L225 Difference]: With dead ends: 219 [2018-07-24 10:55:15,134 INFO L226 Difference]: Without dead ends: 182 [2018-07-24 10:55:15,135 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 355 GetRequests, 270 SyntacticMatches, 32 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1493 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=595, Invalid=2375, Unknown=0, NotChecked=0, Total=2970 [2018-07-24 10:55:15,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states. [2018-07-24 10:55:15,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 102. [2018-07-24 10:55:15,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-07-24 10:55:15,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 110 transitions. [2018-07-24 10:55:15,180 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 110 transitions. Word has length 79 [2018-07-24 10:55:15,180 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:15,180 INFO L471 AbstractCegarLoop]: Abstraction has 102 states and 110 transitions. [2018-07-24 10:55:15,180 INFO L472 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-07-24 10:55:15,181 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 110 transitions. [2018-07-24 10:55:15,181 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-07-24 10:55:15,181 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:15,181 INFO L353 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 6, 6, 6, 6, 5, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:15,181 INFO L414 AbstractCegarLoop]: === Iteration 31 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:15,181 INFO L82 PathProgramCache]: Analyzing trace with hash 310579453, now seen corresponding path program 12 times [2018-07-24 10:55:15,182 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:15,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:15,182 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:15,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:15,182 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:15,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:15,416 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:15,416 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:15,416 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:15,423 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:15,423 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:15,452 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-07-24 10:55:15,452 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:15,454 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:15,717 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:15,718 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:15,857 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:15,877 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:15,877 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:15,892 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:15,892 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:15,984 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-07-24 10:55:15,984 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:15,988 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:16,004 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:16,005 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:16,558 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:16,559 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:16,559 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 32 [2018-07-24 10:55:16,559 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:16,559 INFO L450 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-07-24 10:55:16,560 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-07-24 10:55:16,560 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=197, Invalid=795, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:55:16,560 INFO L87 Difference]: Start difference. First operand 102 states and 110 transitions. Second operand 32 states. [2018-07-24 10:55:17,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:17,458 INFO L93 Difference]: Finished difference Result 257 states and 296 transitions. [2018-07-24 10:55:17,458 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-07-24 10:55:17,459 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 79 [2018-07-24 10:55:17,459 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:17,460 INFO L225 Difference]: With dead ends: 257 [2018-07-24 10:55:17,460 INFO L226 Difference]: Without dead ends: 220 [2018-07-24 10:55:17,462 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 359 GetRequests, 271 SyntacticMatches, 32 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1543 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=649, Invalid=2657, Unknown=0, NotChecked=0, Total=3306 [2018-07-24 10:55:17,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 220 states. [2018-07-24 10:55:17,514 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 220 to 102. [2018-07-24 10:55:17,514 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-07-24 10:55:17,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 110 transitions. [2018-07-24 10:55:17,515 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 110 transitions. Word has length 79 [2018-07-24 10:55:17,515 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:17,515 INFO L471 AbstractCegarLoop]: Abstraction has 102 states and 110 transitions. [2018-07-24 10:55:17,516 INFO L472 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-07-24 10:55:17,516 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 110 transitions. [2018-07-24 10:55:17,516 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-07-24 10:55:17,516 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:17,516 INFO L353 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 6, 6, 6, 6, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:17,517 INFO L414 AbstractCegarLoop]: === Iteration 32 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:17,517 INFO L82 PathProgramCache]: Analyzing trace with hash -1427775351, now seen corresponding path program 13 times [2018-07-24 10:55:17,517 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:17,518 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:17,518 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:17,518 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:17,518 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:17,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:18,227 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 90 proven. 24 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:18,227 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:18,227 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:18,234 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:18,234 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:18,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:18,259 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:18,473 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 90 proven. 24 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:18,474 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:18,662 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 90 proven. 24 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:18,684 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:18,684 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:18,701 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:18,701 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:18,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:18,756 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:18,767 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 90 proven. 24 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:18,767 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:18,964 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 90 proven. 24 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:18,965 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:18,965 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 31 [2018-07-24 10:55:18,966 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:18,966 INFO L450 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-07-24 10:55:18,966 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-07-24 10:55:18,967 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=184, Invalid=746, Unknown=0, NotChecked=0, Total=930 [2018-07-24 10:55:18,967 INFO L87 Difference]: Start difference. First operand 102 states and 110 transitions. Second operand 31 states. [2018-07-24 10:55:20,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:20,166 INFO L93 Difference]: Finished difference Result 293 states and 340 transitions. [2018-07-24 10:55:20,167 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-07-24 10:55:20,167 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 79 [2018-07-24 10:55:20,167 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:20,168 INFO L225 Difference]: With dead ends: 293 [2018-07-24 10:55:20,168 INFO L226 Difference]: Without dead ends: 256 [2018-07-24 10:55:20,170 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 361 GetRequests, 272 SyntacticMatches, 32 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1527 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=668, Invalid=2754, Unknown=0, NotChecked=0, Total=3422 [2018-07-24 10:55:20,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states. [2018-07-24 10:55:20,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 102. [2018-07-24 10:55:20,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-07-24 10:55:20,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 110 transitions. [2018-07-24 10:55:20,219 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 110 transitions. Word has length 79 [2018-07-24 10:55:20,219 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:20,219 INFO L471 AbstractCegarLoop]: Abstraction has 102 states and 110 transitions. [2018-07-24 10:55:20,219 INFO L472 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-07-24 10:55:20,220 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 110 transitions. [2018-07-24 10:55:20,220 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-07-24 10:55:20,220 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:20,220 INFO L353 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 6, 6, 6, 6, 5, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:20,220 INFO L414 AbstractCegarLoop]: === Iteration 33 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:20,221 INFO L82 PathProgramCache]: Analyzing trace with hash 143598357, now seen corresponding path program 14 times [2018-07-24 10:55:20,221 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:20,221 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:20,221 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:20,221 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:20,221 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:20,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:20,698 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:20,699 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:20,699 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:20,705 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:20,705 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:20,728 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:20,729 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:20,731 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:20,981 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:20,982 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:21,097 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:21,117 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:21,117 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:21,133 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:21,133 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:21,184 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:21,185 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:21,188 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:21,205 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:21,205 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:21,342 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:21,344 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:21,344 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 30 [2018-07-24 10:55:21,344 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:21,344 INFO L450 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-07-24 10:55:21,344 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-07-24 10:55:21,345 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=175, Invalid=695, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:55:21,345 INFO L87 Difference]: Start difference. First operand 102 states and 110 transitions. Second operand 30 states. [2018-07-24 10:55:22,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:22,157 INFO L93 Difference]: Finished difference Result 327 states and 382 transitions. [2018-07-24 10:55:22,158 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-07-24 10:55:22,158 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 79 [2018-07-24 10:55:22,158 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:22,159 INFO L225 Difference]: With dead ends: 327 [2018-07-24 10:55:22,159 INFO L226 Difference]: Without dead ends: 290 [2018-07-24 10:55:22,160 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 361 GetRequests, 273 SyntacticMatches, 32 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1436 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=649, Invalid=2657, Unknown=0, NotChecked=0, Total=3306 [2018-07-24 10:55:22,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 290 states. [2018-07-24 10:55:22,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 290 to 102. [2018-07-24 10:55:22,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-07-24 10:55:22,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 110 transitions. [2018-07-24 10:55:22,215 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 110 transitions. Word has length 79 [2018-07-24 10:55:22,215 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:22,215 INFO L471 AbstractCegarLoop]: Abstraction has 102 states and 110 transitions. [2018-07-24 10:55:22,215 INFO L472 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-07-24 10:55:22,215 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 110 transitions. [2018-07-24 10:55:22,216 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-07-24 10:55:22,216 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:22,216 INFO L353 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 6, 6, 6, 6, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:22,216 INFO L414 AbstractCegarLoop]: === Iteration 34 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:22,216 INFO L82 PathProgramCache]: Analyzing trace with hash -1602250591, now seen corresponding path program 15 times [2018-07-24 10:55:22,216 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:22,217 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:22,217 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:22,217 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:22,217 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:22,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:22,442 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:22,443 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:22,443 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:22,449 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:22,450 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:22,474 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2018-07-24 10:55:22,474 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:22,477 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:22,927 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:22,927 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:23,035 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:23,056 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:23,057 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:23,071 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:23,072 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:23,161 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2018-07-24 10:55:23,162 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:23,166 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:23,181 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:23,181 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:23,334 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:23,336 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:23,337 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 29 [2018-07-24 10:55:23,337 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:23,337 INFO L450 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-07-24 10:55:23,337 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-07-24 10:55:23,338 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=170, Invalid=642, Unknown=0, NotChecked=0, Total=812 [2018-07-24 10:55:23,338 INFO L87 Difference]: Start difference. First operand 102 states and 110 transitions. Second operand 29 states. [2018-07-24 10:55:24,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:24,286 INFO L93 Difference]: Finished difference Result 359 states and 422 transitions. [2018-07-24 10:55:24,288 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-07-24 10:55:24,288 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 79 [2018-07-24 10:55:24,288 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:24,290 INFO L225 Difference]: With dead ends: 359 [2018-07-24 10:55:24,291 INFO L226 Difference]: Without dead ends: 322 [2018-07-24 10:55:24,292 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 359 GetRequests, 274 SyntacticMatches, 32 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1267 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=595, Invalid=2375, Unknown=0, NotChecked=0, Total=2970 [2018-07-24 10:55:24,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 322 states. [2018-07-24 10:55:24,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 322 to 102. [2018-07-24 10:55:24,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-07-24 10:55:24,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 110 transitions. [2018-07-24 10:55:24,343 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 110 transitions. Word has length 79 [2018-07-24 10:55:24,343 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:24,343 INFO L471 AbstractCegarLoop]: Abstraction has 102 states and 110 transitions. [2018-07-24 10:55:24,344 INFO L472 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-07-24 10:55:24,344 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 110 transitions. [2018-07-24 10:55:24,344 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-07-24 10:55:24,344 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:24,344 INFO L353 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:24,345 INFO L414 AbstractCegarLoop]: === Iteration 35 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:24,345 INFO L82 PathProgramCache]: Analyzing trace with hash -1326972627, now seen corresponding path program 6 times [2018-07-24 10:55:24,345 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:24,346 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:24,346 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:24,346 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:24,346 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:24,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:24,758 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:24,759 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:24,759 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:24,768 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:24,769 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:24,795 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-07-24 10:55:24,795 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:24,797 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:24,981 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:24,981 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:25,091 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:25,111 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:25,111 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:25,126 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:25,126 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:25,216 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-07-24 10:55:25,216 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:25,220 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:25,231 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:25,231 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:25,362 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:25,363 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:25,364 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 28 [2018-07-24 10:55:25,364 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:25,364 INFO L450 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-07-24 10:55:25,364 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-07-24 10:55:25,364 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=169, Invalid=587, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:55:25,365 INFO L87 Difference]: Start difference. First operand 102 states and 110 transitions. Second operand 28 states. [2018-07-24 10:55:26,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:26,168 INFO L93 Difference]: Finished difference Result 394 states and 466 transitions. [2018-07-24 10:55:26,168 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-07-24 10:55:26,169 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 79 [2018-07-24 10:55:26,169 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:26,170 INFO L225 Difference]: With dead ends: 394 [2018-07-24 10:55:26,170 INFO L226 Difference]: Without dead ends: 357 [2018-07-24 10:55:26,171 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 355 GetRequests, 275 SyntacticMatches, 32 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1028 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=515, Invalid=1935, Unknown=0, NotChecked=0, Total=2450 [2018-07-24 10:55:26,172 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 357 states. [2018-07-24 10:55:26,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 357 to 105. [2018-07-24 10:55:26,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-07-24 10:55:26,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 114 transitions. [2018-07-24 10:55:26,239 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 114 transitions. Word has length 79 [2018-07-24 10:55:26,239 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:26,239 INFO L471 AbstractCegarLoop]: Abstraction has 105 states and 114 transitions. [2018-07-24 10:55:26,240 INFO L472 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-07-24 10:55:26,240 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 114 transitions. [2018-07-24 10:55:26,240 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-07-24 10:55:26,240 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:26,240 INFO L353 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:26,241 INFO L414 AbstractCegarLoop]: === Iteration 36 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:26,241 INFO L82 PathProgramCache]: Analyzing trace with hash 1957490143, now seen corresponding path program 12 times [2018-07-24 10:55:26,241 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:26,242 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:26,242 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:26,242 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:26,242 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:26,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:26,610 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 67 proven. 94 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-07-24 10:55:26,610 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:26,610 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:26,617 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:26,617 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:26,645 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-07-24 10:55:26,646 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:26,648 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:26,691 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 68 proven. 78 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:26,691 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:26,754 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 68 proven. 78 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:26,774 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:26,774 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:26,789 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:26,789 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:26,886 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-07-24 10:55:26,886 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:26,890 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:26,899 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 68 proven. 78 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:26,899 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:26,987 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 68 proven. 78 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:55:26,988 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:26,988 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 12, 12, 12, 12] total 15 [2018-07-24 10:55:26,988 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:26,989 INFO L450 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-07-24 10:55:26,989 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-07-24 10:55:26,989 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=153, Unknown=0, NotChecked=0, Total=210 [2018-07-24 10:55:26,989 INFO L87 Difference]: Start difference. First operand 105 states and 114 transitions. Second operand 15 states. [2018-07-24 10:55:27,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:27,250 INFO L93 Difference]: Finished difference Result 115 states and 124 transitions. [2018-07-24 10:55:27,251 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-07-24 10:55:27,251 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 81 [2018-07-24 10:55:27,251 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:27,252 INFO L225 Difference]: With dead ends: 115 [2018-07-24 10:55:27,252 INFO L226 Difference]: Without dead ends: 113 [2018-07-24 10:55:27,253 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 345 GetRequests, 302 SyntacticMatches, 28 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 149 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=70, Invalid=202, Unknown=0, NotChecked=0, Total=272 [2018-07-24 10:55:27,253 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2018-07-24 10:55:27,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 113. [2018-07-24 10:55:27,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-07-24 10:55:27,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 122 transitions. [2018-07-24 10:55:27,301 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 122 transitions. Word has length 81 [2018-07-24 10:55:27,302 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:27,302 INFO L471 AbstractCegarLoop]: Abstraction has 113 states and 122 transitions. [2018-07-24 10:55:27,302 INFO L472 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-07-24 10:55:27,302 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 122 transitions. [2018-07-24 10:55:27,303 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-07-24 10:55:27,303 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:27,303 INFO L353 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:27,303 INFO L414 AbstractCegarLoop]: === Iteration 37 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:27,303 INFO L82 PathProgramCache]: Analyzing trace with hash -507298045, now seen corresponding path program 13 times [2018-07-24 10:55:27,303 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:27,304 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:27,304 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:27,304 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:27,304 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:27,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:27,612 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:27,612 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:27,612 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:27,620 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:27,620 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:27,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:27,647 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:27,955 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:27,955 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:28,104 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:28,125 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:28,125 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 69 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:28,140 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:28,140 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:28,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:28,198 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:28,215 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:28,215 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:28,375 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:28,376 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:28,377 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 38 [2018-07-24 10:55:28,377 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:28,377 INFO L450 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-07-24 10:55:28,377 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-07-24 10:55:28,378 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=291, Invalid=1115, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:55:28,378 INFO L87 Difference]: Start difference. First operand 113 states and 122 transitions. Second operand 38 states. [2018-07-24 10:55:29,029 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:29,029 INFO L93 Difference]: Finished difference Result 202 states and 228 transitions. [2018-07-24 10:55:29,029 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-07-24 10:55:29,030 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 89 [2018-07-24 10:55:29,030 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:29,031 INFO L225 Difference]: With dead ends: 202 [2018-07-24 10:55:29,031 INFO L226 Difference]: Without dead ends: 161 [2018-07-24 10:55:29,031 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 393 GetRequests, 303 SyntacticMatches, 36 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1817 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=633, Invalid=2447, Unknown=0, NotChecked=0, Total=3080 [2018-07-24 10:55:29,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161 states. [2018-07-24 10:55:29,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161 to 115. [2018-07-24 10:55:29,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-07-24 10:55:29,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 124 transitions. [2018-07-24 10:55:29,101 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 124 transitions. Word has length 89 [2018-07-24 10:55:29,101 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:29,101 INFO L471 AbstractCegarLoop]: Abstraction has 115 states and 124 transitions. [2018-07-24 10:55:29,101 INFO L472 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-07-24 10:55:29,101 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 124 transitions. [2018-07-24 10:55:29,102 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-07-24 10:55:29,102 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:29,102 INFO L353 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 7, 7, 7, 7, 7, 6, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:29,102 INFO L414 AbstractCegarLoop]: === Iteration 38 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:29,102 INFO L82 PathProgramCache]: Analyzing trace with hash -1248990833, now seen corresponding path program 16 times [2018-07-24 10:55:29,103 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:29,103 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:29,103 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:29,103 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:29,103 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:29,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:29,372 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:29,373 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:29,373 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:29,381 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:29,381 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:29,404 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:29,405 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:29,406 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:29,990 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:29,990 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:30,128 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:30,148 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:30,148 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:30,164 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:30,165 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:30,226 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:30,226 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:30,230 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:30,245 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:30,245 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:30,427 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:30,428 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:30,429 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 37 [2018-07-24 10:55:30,429 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:30,429 INFO L450 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-07-24 10:55:30,429 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-07-24 10:55:30,430 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=267, Invalid=1065, Unknown=0, NotChecked=0, Total=1332 [2018-07-24 10:55:30,430 INFO L87 Difference]: Start difference. First operand 115 states and 124 transitions. Second operand 37 states. [2018-07-24 10:55:31,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:31,151 INFO L93 Difference]: Finished difference Result 248 states and 283 transitions. [2018-07-24 10:55:31,152 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-07-24 10:55:31,152 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 89 [2018-07-24 10:55:31,152 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:31,153 INFO L225 Difference]: With dead ends: 248 [2018-07-24 10:55:31,153 INFO L226 Difference]: Without dead ends: 207 [2018-07-24 10:55:31,154 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 400 GetRequests, 304 SyntacticMatches, 36 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1966 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=741, Invalid=3041, Unknown=0, NotChecked=0, Total=3782 [2018-07-24 10:55:31,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 207 states. [2018-07-24 10:55:31,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 207 to 115. [2018-07-24 10:55:31,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-07-24 10:55:31,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 124 transitions. [2018-07-24 10:55:31,238 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 124 transitions. Word has length 89 [2018-07-24 10:55:31,238 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:31,238 INFO L471 AbstractCegarLoop]: Abstraction has 115 states and 124 transitions. [2018-07-24 10:55:31,238 INFO L472 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-07-24 10:55:31,239 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 124 transitions. [2018-07-24 10:55:31,239 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-07-24 10:55:31,239 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:31,239 INFO L353 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 7, 7, 7, 7, 6, 5, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:31,239 INFO L414 AbstractCegarLoop]: === Iteration 39 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:31,239 INFO L82 PathProgramCache]: Analyzing trace with hash 752469787, now seen corresponding path program 17 times [2018-07-24 10:55:31,240 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:31,240 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:31,240 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:31,240 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:31,240 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:31,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:31,562 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:31,563 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:31,563 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:31,571 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:31,571 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:31,708 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2018-07-24 10:55:31,709 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:31,711 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:32,357 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:32,357 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:32,498 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:32,518 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:32,518 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:32,532 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:32,533 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:32,635 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2018-07-24 10:55:32,635 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:32,639 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:32,653 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:32,654 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:32,810 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:32,811 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:32,812 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 36 [2018-07-24 10:55:32,812 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:32,812 INFO L450 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-07-24 10:55:32,812 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-07-24 10:55:32,812 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=247, Invalid=1013, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:55:32,813 INFO L87 Difference]: Start difference. First operand 115 states and 124 transitions. Second operand 36 states. [2018-07-24 10:55:33,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:33,686 INFO L93 Difference]: Finished difference Result 292 states and 336 transitions. [2018-07-24 10:55:33,687 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-07-24 10:55:33,687 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 89 [2018-07-24 10:55:33,687 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:33,688 INFO L225 Difference]: With dead ends: 292 [2018-07-24 10:55:33,688 INFO L226 Difference]: Without dead ends: 251 [2018-07-24 10:55:33,689 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 405 GetRequests, 305 SyntacticMatches, 36 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2068 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=823, Invalid=3467, Unknown=0, NotChecked=0, Total=4290 [2018-07-24 10:55:33,689 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 251 states. [2018-07-24 10:55:33,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 251 to 115. [2018-07-24 10:55:33,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-07-24 10:55:33,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 124 transitions. [2018-07-24 10:55:33,775 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 124 transitions. Word has length 89 [2018-07-24 10:55:33,775 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:33,776 INFO L471 AbstractCegarLoop]: Abstraction has 115 states and 124 transitions. [2018-07-24 10:55:33,776 INFO L472 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-07-24 10:55:33,776 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 124 transitions. [2018-07-24 10:55:33,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-07-24 10:55:33,776 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:33,777 INFO L353 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 7, 7, 7, 7, 5, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:33,777 INFO L414 AbstractCegarLoop]: === Iteration 40 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:33,777 INFO L82 PathProgramCache]: Analyzing trace with hash -1940416601, now seen corresponding path program 18 times [2018-07-24 10:55:33,777 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:33,778 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:33,778 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:33,778 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:33,778 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:33,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:34,917 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:34,917 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:34,917 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:34,927 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:34,927 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:34,964 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-07-24 10:55:34,965 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:34,967 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:35,235 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:35,235 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:35,379 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:35,399 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:35,400 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 75 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:35,415 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:35,416 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:35,522 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-07-24 10:55:35,522 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:35,526 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:35,539 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:35,540 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:35,738 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:35,739 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:35,739 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 35 [2018-07-24 10:55:35,740 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:35,740 INFO L450 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-07-24 10:55:35,740 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-07-24 10:55:35,740 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=959, Unknown=0, NotChecked=0, Total=1190 [2018-07-24 10:55:35,740 INFO L87 Difference]: Start difference. First operand 115 states and 124 transitions. Second operand 35 states. [2018-07-24 10:55:36,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:36,918 INFO L93 Difference]: Finished difference Result 334 states and 387 transitions. [2018-07-24 10:55:36,918 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-07-24 10:55:36,918 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 89 [2018-07-24 10:55:36,918 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:36,920 INFO L225 Difference]: With dead ends: 334 [2018-07-24 10:55:36,920 INFO L226 Difference]: Without dead ends: 293 [2018-07-24 10:55:36,921 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 408 GetRequests, 306 SyntacticMatches, 36 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2097 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=867, Invalid=3689, Unknown=0, NotChecked=0, Total=4556 [2018-07-24 10:55:36,921 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 293 states. [2018-07-24 10:55:37,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 293 to 115. [2018-07-24 10:55:37,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-07-24 10:55:37,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 124 transitions. [2018-07-24 10:55:37,033 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 124 transitions. Word has length 89 [2018-07-24 10:55:37,033 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:37,033 INFO L471 AbstractCegarLoop]: Abstraction has 115 states and 124 transitions. [2018-07-24 10:55:37,033 INFO L472 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-07-24 10:55:37,033 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 124 transitions. [2018-07-24 10:55:37,034 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-07-24 10:55:37,034 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:37,034 INFO L353 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 7, 7, 7, 7, 5, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:37,034 INFO L414 AbstractCegarLoop]: === Iteration 41 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:37,034 INFO L82 PathProgramCache]: Analyzing trace with hash 233315123, now seen corresponding path program 19 times [2018-07-24 10:55:37,035 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:37,035 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:37,035 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:37,036 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:37,036 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:37,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:37,842 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:37,842 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:37,842 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:37,851 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:37,852 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:37,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:37,880 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:38,122 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:38,122 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:38,253 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:38,274 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:38,274 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 77 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:38,292 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:38,292 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:38,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:38,352 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:38,370 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:38,370 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:38,528 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:38,529 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:38,530 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 34 [2018-07-24 10:55:38,530 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:38,530 INFO L450 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-07-24 10:55:38,530 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-07-24 10:55:38,531 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=219, Invalid=903, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:55:38,531 INFO L87 Difference]: Start difference. First operand 115 states and 124 transitions. Second operand 34 states. [2018-07-24 10:55:39,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:39,625 INFO L93 Difference]: Finished difference Result 374 states and 436 transitions. [2018-07-24 10:55:39,626 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-07-24 10:55:39,626 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 89 [2018-07-24 10:55:39,626 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:39,627 INFO L225 Difference]: With dead ends: 374 [2018-07-24 10:55:39,628 INFO L226 Difference]: Without dead ends: 333 [2018-07-24 10:55:39,628 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 409 GetRequests, 307 SyntacticMatches, 36 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2039 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=867, Invalid=3689, Unknown=0, NotChecked=0, Total=4556 [2018-07-24 10:55:39,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 333 states. [2018-07-24 10:55:39,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 333 to 115. [2018-07-24 10:55:39,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-07-24 10:55:39,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 124 transitions. [2018-07-24 10:55:39,730 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 124 transitions. Word has length 89 [2018-07-24 10:55:39,731 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:39,731 INFO L471 AbstractCegarLoop]: Abstraction has 115 states and 124 transitions. [2018-07-24 10:55:39,731 INFO L472 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-07-24 10:55:39,731 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 124 transitions. [2018-07-24 10:55:39,732 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-07-24 10:55:39,732 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:39,732 INFO L353 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 7, 7, 7, 7, 6, 5, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:39,732 INFO L414 AbstractCegarLoop]: === Iteration 42 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:39,732 INFO L82 PathProgramCache]: Analyzing trace with hash 1822167487, now seen corresponding path program 20 times [2018-07-24 10:55:39,732 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:39,733 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:39,733 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:39,733 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:39,733 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:39,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:40,217 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:40,217 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:40,217 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:40,224 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:40,225 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:40,252 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:40,252 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:40,253 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:40,493 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:40,493 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:40,625 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:40,645 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:40,645 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 79 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:40,661 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:40,661 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:40,719 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:40,719 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:40,723 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:40,742 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:40,742 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:41,976 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:41,977 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:41,977 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 33 [2018-07-24 10:55:41,977 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:41,978 INFO L450 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-07-24 10:55:41,978 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-07-24 10:55:41,978 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=211, Invalid=845, Unknown=0, NotChecked=0, Total=1056 [2018-07-24 10:55:41,978 INFO L87 Difference]: Start difference. First operand 115 states and 124 transitions. Second operand 33 states. [2018-07-24 10:55:43,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:43,099 INFO L93 Difference]: Finished difference Result 412 states and 483 transitions. [2018-07-24 10:55:43,099 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-07-24 10:55:43,099 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 89 [2018-07-24 10:55:43,100 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:43,101 INFO L225 Difference]: With dead ends: 412 [2018-07-24 10:55:43,101 INFO L226 Difference]: Without dead ends: 371 [2018-07-24 10:55:43,102 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 408 GetRequests, 308 SyntacticMatches, 36 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1888 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=823, Invalid=3467, Unknown=0, NotChecked=0, Total=4290 [2018-07-24 10:55:43,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 371 states. [2018-07-24 10:55:43,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 371 to 115. [2018-07-24 10:55:43,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-07-24 10:55:43,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 124 transitions. [2018-07-24 10:55:43,171 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 124 transitions. Word has length 89 [2018-07-24 10:55:43,171 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:43,171 INFO L471 AbstractCegarLoop]: Abstraction has 115 states and 124 transitions. [2018-07-24 10:55:43,171 INFO L472 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-07-24 10:55:43,171 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 124 transitions. [2018-07-24 10:55:43,172 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-07-24 10:55:43,172 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:43,172 INFO L353 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 7, 7, 7, 7, 7, 6, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:43,172 INFO L414 AbstractCegarLoop]: === Iteration 43 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:43,172 INFO L82 PathProgramCache]: Analyzing trace with hash 1890859851, now seen corresponding path program 21 times [2018-07-24 10:55:43,172 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:43,173 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:43,173 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:43,173 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:43,173 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:43,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:44,422 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:44,422 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:44,422 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:44,452 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:44,452 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:44,480 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2018-07-24 10:55:44,481 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:44,483 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:44,707 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:44,707 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:45,038 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:45,058 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:45,058 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 81 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:45,074 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:45,075 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:45,179 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2018-07-24 10:55:45,179 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:45,183 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:45,200 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:45,200 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:45,357 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:45,358 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:45,359 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 32 [2018-07-24 10:55:45,359 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:45,359 INFO L450 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-07-24 10:55:45,359 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-07-24 10:55:45,359 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=207, Invalid=785, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:55:45,360 INFO L87 Difference]: Start difference. First operand 115 states and 124 transitions. Second operand 32 states. [2018-07-24 10:55:46,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:46,853 INFO L93 Difference]: Finished difference Result 448 states and 528 transitions. [2018-07-24 10:55:46,853 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-07-24 10:55:46,853 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 89 [2018-07-24 10:55:46,854 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:46,856 INFO L225 Difference]: With dead ends: 448 [2018-07-24 10:55:46,856 INFO L226 Difference]: Without dead ends: 407 [2018-07-24 10:55:46,857 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 405 GetRequests, 309 SyntacticMatches, 36 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1646 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=741, Invalid=3041, Unknown=0, NotChecked=0, Total=3782 [2018-07-24 10:55:46,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 407 states. [2018-07-24 10:55:46,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 407 to 115. [2018-07-24 10:55:46,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-07-24 10:55:46,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 124 transitions. [2018-07-24 10:55:46,937 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 124 transitions. Word has length 89 [2018-07-24 10:55:46,937 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:46,937 INFO L471 AbstractCegarLoop]: Abstraction has 115 states and 124 transitions. [2018-07-24 10:55:46,937 INFO L472 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-07-24 10:55:46,937 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 124 transitions. [2018-07-24 10:55:46,938 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-07-24 10:55:46,938 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:46,938 INFO L353 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:46,938 INFO L414 AbstractCegarLoop]: === Iteration 44 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:46,938 INFO L82 PathProgramCache]: Analyzing trace with hash 2074171351, now seen corresponding path program 7 times [2018-07-24 10:55:46,938 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:46,939 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:46,939 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:46,939 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:46,939 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:46,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:47,137 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:47,137 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:47,138 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:47,145 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:47,145 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:47,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:47,172 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:47,408 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:47,408 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:47,539 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:47,558 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:47,558 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 83 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 83 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:47,574 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:47,574 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:47,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:47,634 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:47,647 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:47,647 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:47,805 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:47,806 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:47,807 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 31 [2018-07-24 10:55:47,807 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:47,807 INFO L450 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-07-24 10:55:47,807 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-07-24 10:55:47,808 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=207, Invalid=723, Unknown=0, NotChecked=0, Total=930 [2018-07-24 10:55:47,808 INFO L87 Difference]: Start difference. First operand 115 states and 124 transitions. Second operand 31 states. [2018-07-24 10:55:48,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:48,949 INFO L93 Difference]: Finished difference Result 487 states and 577 transitions. [2018-07-24 10:55:48,949 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-07-24 10:55:48,949 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 89 [2018-07-24 10:55:48,949 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:48,952 INFO L225 Difference]: With dead ends: 487 [2018-07-24 10:55:48,952 INFO L226 Difference]: Without dead ends: 446 [2018-07-24 10:55:48,953 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 400 GetRequests, 310 SyntacticMatches, 36 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1327 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=633, Invalid=2447, Unknown=0, NotChecked=0, Total=3080 [2018-07-24 10:55:48,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 446 states. [2018-07-24 10:55:49,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 446 to 118. [2018-07-24 10:55:49,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-07-24 10:55:49,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 128 transitions. [2018-07-24 10:55:49,078 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 128 transitions. Word has length 89 [2018-07-24 10:55:49,079 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:49,079 INFO L471 AbstractCegarLoop]: Abstraction has 118 states and 128 transitions. [2018-07-24 10:55:49,079 INFO L472 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-07-24 10:55:49,079 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 128 transitions. [2018-07-24 10:55:49,079 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-07-24 10:55:49,080 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:49,080 INFO L353 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:49,080 INFO L414 AbstractCegarLoop]: === Iteration 45 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:49,080 INFO L82 PathProgramCache]: Analyzing trace with hash -1421446787, now seen corresponding path program 14 times [2018-07-24 10:55:49,080 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:49,081 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:49,081 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:49,081 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:49,081 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:49,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:49,366 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 85 proven. 124 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2018-07-24 10:55:49,367 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:49,367 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:49,373 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:49,374 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:49,398 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:49,398 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:49,400 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:49,443 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 86 proven. 105 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:49,443 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:49,577 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 86 proven. 105 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:49,596 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:49,597 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 85 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 85 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:49,612 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:49,612 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:49,674 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:49,674 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:49,678 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:49,690 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 86 proven. 105 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:49,691 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:50,151 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 86 proven. 105 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:50,152 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:50,152 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13, 13, 13, 13] total 16 [2018-07-24 10:55:50,152 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:50,153 INFO L450 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-07-24 10:55:50,153 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-07-24 10:55:50,153 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=173, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:55:50,153 INFO L87 Difference]: Start difference. First operand 118 states and 128 transitions. Second operand 16 states. [2018-07-24 10:55:50,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:50,482 INFO L93 Difference]: Finished difference Result 128 states and 138 transitions. [2018-07-24 10:55:50,482 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-07-24 10:55:50,482 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 91 [2018-07-24 10:55:50,483 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:50,483 INFO L225 Difference]: With dead ends: 128 [2018-07-24 10:55:50,484 INFO L226 Difference]: Without dead ends: 126 [2018-07-24 10:55:50,484 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 387 GetRequests, 339 SyntacticMatches, 32 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 186 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=80, Invalid=226, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:55:50,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-07-24 10:55:50,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 126. [2018-07-24 10:55:50,562 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 126 states. [2018-07-24 10:55:50,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 136 transitions. [2018-07-24 10:55:50,563 INFO L78 Accepts]: Start accepts. Automaton has 126 states and 136 transitions. Word has length 91 [2018-07-24 10:55:50,563 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:50,563 INFO L471 AbstractCegarLoop]: Abstraction has 126 states and 136 transitions. [2018-07-24 10:55:50,563 INFO L472 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-07-24 10:55:50,563 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 136 transitions. [2018-07-24 10:55:50,564 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-07-24 10:55:50,564 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:50,564 INFO L353 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:50,564 INFO L414 AbstractCegarLoop]: === Iteration 46 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:50,564 INFO L82 PathProgramCache]: Analyzing trace with hash -161069919, now seen corresponding path program 15 times [2018-07-24 10:55:50,564 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:50,565 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:50,565 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:50,565 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:50,565 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:50,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:50,878 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:50,879 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:50,879 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:50,886 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:50,886 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:50,918 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-07-24 10:55:50,918 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:50,920 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:51,283 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:51,283 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:51,778 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:51,798 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:51,798 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 87 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 87 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:51,813 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:51,813 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:51,937 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-07-24 10:55:51,937 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:51,941 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:51,964 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:51,965 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:52,787 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:52,789 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:52,789 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 42 [2018-07-24 10:55:52,789 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:52,790 INFO L450 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-07-24 10:55:52,790 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-07-24 10:55:52,791 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=353, Invalid=1369, Unknown=0, NotChecked=0, Total=1722 [2018-07-24 10:55:52,791 INFO L87 Difference]: Start difference. First operand 126 states and 136 transitions. Second operand 42 states. [2018-07-24 10:55:53,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:53,559 INFO L93 Difference]: Finished difference Result 225 states and 254 transitions. [2018-07-24 10:55:53,559 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-07-24 10:55:53,559 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 99 [2018-07-24 10:55:53,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:53,561 INFO L225 Difference]: With dead ends: 225 [2018-07-24 10:55:53,561 INFO L226 Difference]: Without dead ends: 180 [2018-07-24 10:55:53,562 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 437 GetRequests, 337 SyntacticMatches, 40 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2292 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=763, Invalid=3019, Unknown=0, NotChecked=0, Total=3782 [2018-07-24 10:55:53,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180 states. [2018-07-24 10:55:53,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180 to 128. [2018-07-24 10:55:53,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-07-24 10:55:53,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-07-24 10:55:53,660 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-07-24 10:55:53,660 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:53,660 INFO L471 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-07-24 10:55:53,660 INFO L472 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-07-24 10:55:53,660 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-07-24 10:55:53,661 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-07-24 10:55:53,661 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:53,661 INFO L353 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 8, 8, 8, 8, 8, 7, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:53,661 INFO L414 AbstractCegarLoop]: === Iteration 47 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:53,662 INFO L82 PathProgramCache]: Analyzing trace with hash 1635135533, now seen corresponding path program 22 times [2018-07-24 10:55:53,662 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:53,662 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:53,662 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:53,663 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:53,663 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:53,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:54,237 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:54,237 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:54,237 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:54,244 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:54,245 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:54,271 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:54,271 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:54,273 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:54,649 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:54,650 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:54,923 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:54,944 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:54,944 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 89 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 89 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:54,959 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:54,959 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:55,033 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:55,033 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:55,037 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:55,053 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:55,054 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:55,498 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:55,499 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:55,499 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 41 [2018-07-24 10:55:55,499 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:55,500 INFO L450 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-07-24 10:55:55,500 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-07-24 10:55:55,500 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=326, Invalid=1314, Unknown=0, NotChecked=0, Total=1640 [2018-07-24 10:55:55,500 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 41 states. [2018-07-24 10:55:56,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:56,612 INFO L93 Difference]: Finished difference Result 277 states and 316 transitions. [2018-07-24 10:55:56,612 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-07-24 10:55:56,612 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 99 [2018-07-24 10:55:56,612 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:56,613 INFO L225 Difference]: With dead ends: 277 [2018-07-24 10:55:56,613 INFO L226 Difference]: Without dead ends: 232 [2018-07-24 10:55:56,614 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 445 GetRequests, 338 SyntacticMatches, 40 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2504 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=903, Invalid=3789, Unknown=0, NotChecked=0, Total=4692 [2018-07-24 10:55:56,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 232 states. [2018-07-24 10:55:56,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 232 to 128. [2018-07-24 10:55:56,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-07-24 10:55:56,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-07-24 10:55:56,702 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-07-24 10:55:56,703 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:56,703 INFO L471 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-07-24 10:55:56,703 INFO L472 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-07-24 10:55:56,703 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-07-24 10:55:56,703 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-07-24 10:55:56,703 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:56,704 INFO L353 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 8, 8, 8, 8, 7, 6, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:56,704 INFO L414 AbstractCegarLoop]: === Iteration 48 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:56,704 INFO L82 PathProgramCache]: Analyzing trace with hash 1382256313, now seen corresponding path program 23 times [2018-07-24 10:55:56,704 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:56,704 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:56,704 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:56,704 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:56,705 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:56,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:56,978 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:56,978 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:56,978 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:56,985 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:56,985 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:57,020 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 9 check-sat command(s) [2018-07-24 10:55:57,020 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:57,022 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:57,362 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:57,362 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:57,525 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:57,546 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:57,546 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 91 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 91 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:57,561 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:57,561 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:57,677 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 9 check-sat command(s) [2018-07-24 10:55:57,677 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:57,681 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:57,698 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:57,698 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:57,930 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:57,931 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:57,931 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 40 [2018-07-24 10:55:57,931 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:57,932 INFO L450 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-07-24 10:55:57,932 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-07-24 10:55:57,932 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=303, Invalid=1257, Unknown=0, NotChecked=0, Total=1560 [2018-07-24 10:55:57,933 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 40 states. [2018-07-24 10:55:59,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:59,150 INFO L93 Difference]: Finished difference Result 327 states and 376 transitions. [2018-07-24 10:55:59,150 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-07-24 10:55:59,150 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 99 [2018-07-24 10:55:59,151 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:59,152 INFO L225 Difference]: With dead ends: 327 [2018-07-24 10:55:59,152 INFO L226 Difference]: Without dead ends: 282 [2018-07-24 10:55:59,153 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 451 GetRequests, 339 SyntacticMatches, 40 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2670 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1018, Invalid=4384, Unknown=0, NotChecked=0, Total=5402 [2018-07-24 10:55:59,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282 states. [2018-07-24 10:55:59,254 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282 to 128. [2018-07-24 10:55:59,254 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-07-24 10:55:59,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-07-24 10:55:59,254 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-07-24 10:55:59,255 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:59,255 INFO L471 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-07-24 10:55:59,255 INFO L472 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-07-24 10:55:59,255 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-07-24 10:55:59,255 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-07-24 10:55:59,255 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:59,255 INFO L353 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 8, 8, 8, 8, 6, 5, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:59,256 INFO L414 AbstractCegarLoop]: === Iteration 49 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:59,256 INFO L82 PathProgramCache]: Analyzing trace with hash 2012160069, now seen corresponding path program 24 times [2018-07-24 10:55:59,256 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:59,256 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:59,256 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:59,256 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:59,257 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:59,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:59,533 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:59,533 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:59,534 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:59,541 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:59,542 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:59,571 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2018-07-24 10:55:59,571 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:59,574 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:59,893 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:59,893 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:00,056 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:00,077 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:00,077 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 93 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 93 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:00,092 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:56:00,092 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:00,214 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2018-07-24 10:56:00,214 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:00,218 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:00,236 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:00,236 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:01,175 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:01,176 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:01,176 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 39 [2018-07-24 10:56:01,176 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:01,177 INFO L450 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-07-24 10:56:01,177 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-07-24 10:56:01,177 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=284, Invalid=1198, Unknown=0, NotChecked=0, Total=1482 [2018-07-24 10:56:01,178 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 39 states. [2018-07-24 10:56:02,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:02,732 INFO L93 Difference]: Finished difference Result 375 states and 434 transitions. [2018-07-24 10:56:02,733 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-07-24 10:56:02,733 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 99 [2018-07-24 10:56:02,733 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:02,734 INFO L225 Difference]: With dead ends: 375 [2018-07-24 10:56:02,734 INFO L226 Difference]: Without dead ends: 330 [2018-07-24 10:56:02,735 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 455 GetRequests, 340 SyntacticMatches, 40 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2758 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1093, Invalid=4759, Unknown=0, NotChecked=0, Total=5852 [2018-07-24 10:56:02,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 330 states. [2018-07-24 10:56:02,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 330 to 128. [2018-07-24 10:56:02,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-07-24 10:56:02,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-07-24 10:56:02,847 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-07-24 10:56:02,847 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:02,847 INFO L471 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-07-24 10:56:02,847 INFO L472 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-07-24 10:56:02,847 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-07-24 10:56:02,848 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-07-24 10:56:02,848 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:02,848 INFO L353 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 8, 8, 8, 8, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:02,848 INFO L414 AbstractCegarLoop]: === Iteration 50 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:02,848 INFO L82 PathProgramCache]: Analyzing trace with hash -1173773103, now seen corresponding path program 25 times [2018-07-24 10:56:02,848 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:02,849 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:02,849 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:02,849 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:02,849 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:02,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:03,098 INFO L134 CoverageAnalysis]: Checked inductivity of 304 backedges. 152 proven. 40 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:03,098 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:03,098 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:03,105 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:03,106 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:56:03,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:03,136 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:03,469 INFO L134 CoverageAnalysis]: Checked inductivity of 304 backedges. 152 proven. 40 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:03,469 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:03,625 INFO L134 CoverageAnalysis]: Checked inductivity of 304 backedges. 152 proven. 40 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:03,655 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:03,655 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 95 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 95 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:03,678 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:03,678 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:56:03,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:03,741 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:03,761 INFO L134 CoverageAnalysis]: Checked inductivity of 304 backedges. 152 proven. 40 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:03,761 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:03,955 INFO L134 CoverageAnalysis]: Checked inductivity of 304 backedges. 152 proven. 40 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:03,957 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:03,957 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 38 [2018-07-24 10:56:03,957 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:03,957 INFO L450 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-07-24 10:56:03,958 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-07-24 10:56:03,958 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=269, Invalid=1137, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:56:03,958 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 38 states. [2018-07-24 10:56:05,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:05,963 INFO L93 Difference]: Finished difference Result 421 states and 490 transitions. [2018-07-24 10:56:05,964 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-07-24 10:56:05,964 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 99 [2018-07-24 10:56:05,964 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:05,966 INFO L225 Difference]: With dead ends: 421 [2018-07-24 10:56:05,966 INFO L226 Difference]: Without dead ends: 376 [2018-07-24 10:56:05,967 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 457 GetRequests, 341 SyntacticMatches, 40 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2748 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1119, Invalid=4887, Unknown=0, NotChecked=0, Total=6006 [2018-07-24 10:56:05,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 376 states. [2018-07-24 10:56:06,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 376 to 128. [2018-07-24 10:56:06,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-07-24 10:56:06,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-07-24 10:56:06,132 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-07-24 10:56:06,133 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:06,133 INFO L471 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-07-24 10:56:06,133 INFO L472 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-07-24 10:56:06,133 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-07-24 10:56:06,134 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-07-24 10:56:06,134 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:06,134 INFO L353 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 8, 8, 8, 8, 6, 5, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:06,134 INFO L414 AbstractCegarLoop]: === Iteration 51 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:06,134 INFO L82 PathProgramCache]: Analyzing trace with hash -975971235, now seen corresponding path program 26 times [2018-07-24 10:56:06,134 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:06,135 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:06,135 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:06,135 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:06,135 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:06,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:06,605 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:06,605 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:06,606 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 96 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 96 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:06,612 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:06,612 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:06,641 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:06,641 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:06,643 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:06,966 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:06,966 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:07,119 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:07,140 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:07,140 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 97 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 97 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:07,155 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:07,155 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:07,219 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:07,219 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:07,223 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:07,239 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:07,239 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:07,500 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:07,502 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:07,502 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 37 [2018-07-24 10:56:07,502 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:07,503 INFO L450 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-07-24 10:56:07,504 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-07-24 10:56:07,504 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=258, Invalid=1074, Unknown=0, NotChecked=0, Total=1332 [2018-07-24 10:56:07,504 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 37 states. [2018-07-24 10:56:09,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:09,195 INFO L93 Difference]: Finished difference Result 465 states and 544 transitions. [2018-07-24 10:56:09,196 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-07-24 10:56:09,196 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 99 [2018-07-24 10:56:09,196 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:09,198 INFO L225 Difference]: With dead ends: 465 [2018-07-24 10:56:09,198 INFO L226 Difference]: Without dead ends: 420 [2018-07-24 10:56:09,199 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 457 GetRequests, 342 SyntacticMatches, 40 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2631 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1093, Invalid=4759, Unknown=0, NotChecked=0, Total=5852 [2018-07-24 10:56:09,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 420 states. [2018-07-24 10:56:09,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 420 to 128. [2018-07-24 10:56:09,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-07-24 10:56:09,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-07-24 10:56:09,317 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-07-24 10:56:09,317 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:09,317 INFO L471 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-07-24 10:56:09,317 INFO L472 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-07-24 10:56:09,317 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-07-24 10:56:09,318 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-07-24 10:56:09,318 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:09,318 INFO L353 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 8, 8, 8, 8, 7, 6, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:09,318 INFO L414 AbstractCegarLoop]: === Iteration 52 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:09,319 INFO L82 PathProgramCache]: Analyzing trace with hash -1717664023, now seen corresponding path program 27 times [2018-07-24 10:56:09,319 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:09,319 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:09,319 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:09,320 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:09,320 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:09,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:10,076 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:10,076 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:10,077 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 98 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 98 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:10,083 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:56:10,083 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:56:10,116 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-07-24 10:56:10,116 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:10,119 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:10,431 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:10,431 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:10,784 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:10,803 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:10,803 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 99 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 99 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:10,818 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:56:10,818 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:56:10,952 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-07-24 10:56:10,952 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:10,956 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:10,970 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:10,970 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:11,148 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:11,149 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:11,149 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 36 [2018-07-24 10:56:11,149 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:11,150 INFO L450 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-07-24 10:56:11,150 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-07-24 10:56:11,150 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=251, Invalid=1009, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:56:11,150 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 36 states. [2018-07-24 10:56:12,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:12,909 INFO L93 Difference]: Finished difference Result 507 states and 596 transitions. [2018-07-24 10:56:12,909 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-07-24 10:56:12,909 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 99 [2018-07-24 10:56:12,909 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:12,911 INFO L225 Difference]: With dead ends: 507 [2018-07-24 10:56:12,911 INFO L226 Difference]: Without dead ends: 462 [2018-07-24 10:56:12,912 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 455 GetRequests, 343 SyntacticMatches, 40 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2404 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1018, Invalid=4384, Unknown=0, NotChecked=0, Total=5402 [2018-07-24 10:56:12,912 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 462 states. [2018-07-24 10:56:13,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 462 to 128. [2018-07-24 10:56:13,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-07-24 10:56:13,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-07-24 10:56:13,053 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-07-24 10:56:13,053 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:13,053 INFO L471 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-07-24 10:56:13,053 INFO L472 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-07-24 10:56:13,053 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-07-24 10:56:13,053 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-07-24 10:56:13,053 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:13,054 INFO L353 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 8, 8, 8, 8, 8, 7, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:13,054 INFO L414 AbstractCegarLoop]: === Iteration 53 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:13,054 INFO L82 PathProgramCache]: Analyzing trace with hash 283796597, now seen corresponding path program 28 times [2018-07-24 10:56:13,054 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:13,055 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:13,055 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:13,055 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:13,055 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:13,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:13,343 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:13,343 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:13,343 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 100 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 100 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:13,351 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:56:13,351 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:56:13,380 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:56:13,380 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:13,382 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:13,639 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:13,639 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:13,792 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:13,812 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:13,812 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 101 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 101 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:13,828 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:56:13,828 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:56:13,903 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:56:13,903 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:13,907 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:13,926 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:13,926 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:14,233 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:14,234 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:14,234 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 35 [2018-07-24 10:56:14,234 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:14,234 INFO L450 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-07-24 10:56:14,235 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-07-24 10:56:14,235 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=248, Invalid=942, Unknown=0, NotChecked=0, Total=1190 [2018-07-24 10:56:14,235 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 35 states. [2018-07-24 10:56:15,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:15,968 INFO L93 Difference]: Finished difference Result 547 states and 646 transitions. [2018-07-24 10:56:15,969 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-07-24 10:56:15,969 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 99 [2018-07-24 10:56:15,969 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:15,971 INFO L225 Difference]: With dead ends: 547 [2018-07-24 10:56:15,971 INFO L226 Difference]: Without dead ends: 502 [2018-07-24 10:56:15,972 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 451 GetRequests, 344 SyntacticMatches, 40 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2075 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=903, Invalid=3789, Unknown=0, NotChecked=0, Total=4692 [2018-07-24 10:56:15,972 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 502 states. [2018-07-24 10:56:16,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 502 to 128. [2018-07-24 10:56:16,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-07-24 10:56:16,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-07-24 10:56:16,109 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-07-24 10:56:16,109 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:16,109 INFO L471 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-07-24 10:56:16,109 INFO L472 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-07-24 10:56:16,109 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-07-24 10:56:16,109 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-07-24 10:56:16,110 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:16,110 INFO L353 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:16,110 INFO L414 AbstractCegarLoop]: === Iteration 54 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:16,110 INFO L82 PathProgramCache]: Analyzing trace with hash 1885877505, now seen corresponding path program 8 times [2018-07-24 10:56:16,110 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:16,110 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:16,111 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:16,111 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:16,111 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:16,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:17,507 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:17,507 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:17,507 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 102 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 102 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:17,514 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:17,514 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:17,542 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:17,542 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:17,545 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:17,781 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:17,781 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:17,940 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:17,960 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:17,960 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 103 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 103 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:17,975 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:17,975 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:18,039 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:18,039 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:18,044 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:18,060 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:18,060 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:18,250 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:18,252 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:18,252 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 34 [2018-07-24 10:56:18,252 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:18,252 INFO L450 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-07-24 10:56:18,253 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-07-24 10:56:18,253 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=249, Invalid=873, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:56:18,253 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 34 states. [2018-07-24 10:56:19,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:19,995 INFO L93 Difference]: Finished difference Result 590 states and 700 transitions. [2018-07-24 10:56:19,995 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-07-24 10:56:19,996 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 99 [2018-07-24 10:56:19,996 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:19,998 INFO L225 Difference]: With dead ends: 590 [2018-07-24 10:56:19,998 INFO L226 Difference]: Without dead ends: 545 [2018-07-24 10:56:19,998 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 445 GetRequests, 345 SyntacticMatches, 40 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1664 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=763, Invalid=3019, Unknown=0, NotChecked=0, Total=3782 [2018-07-24 10:56:19,999 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 545 states. [2018-07-24 10:56:20,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 545 to 131. [2018-07-24 10:56:20,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2018-07-24 10:56:20,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 142 transitions. [2018-07-24 10:56:20,137 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 142 transitions. Word has length 99 [2018-07-24 10:56:20,137 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:20,137 INFO L471 AbstractCegarLoop]: Abstraction has 131 states and 142 transitions. [2018-07-24 10:56:20,137 INFO L472 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-07-24 10:56:20,137 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 142 transitions. [2018-07-24 10:56:20,138 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2018-07-24 10:56:20,138 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:20,138 INFO L353 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 9, 9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:20,139 INFO L414 AbstractCegarLoop]: === Iteration 55 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:20,139 INFO L82 PathProgramCache]: Analyzing trace with hash -1743772005, now seen corresponding path program 16 times [2018-07-24 10:56:20,139 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:20,139 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:20,140 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:20,140 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:20,140 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:20,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:20,296 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 105 proven. 158 refuted. 0 times theorem prover too weak. 91 trivial. 0 not checked. [2018-07-24 10:56:20,296 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:20,296 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 104 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 104 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:20,303 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:56:20,304 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:56:20,336 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:56:20,336 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:20,338 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:20,379 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 106 proven. 136 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:20,379 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:20,481 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 106 proven. 136 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:20,502 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:20,502 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 105 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 105 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:20,517 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:56:20,517 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:56:20,596 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:56:20,596 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:20,600 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:20,610 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 106 proven. 136 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:20,610 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:20,843 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 106 proven. 136 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:56:20,844 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:20,844 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 14, 14, 14, 14] total 17 [2018-07-24 10:56:20,845 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:20,845 INFO L450 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-07-24 10:56:20,845 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-07-24 10:56:20,845 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=194, Unknown=0, NotChecked=0, Total=272 [2018-07-24 10:56:20,846 INFO L87 Difference]: Start difference. First operand 131 states and 142 transitions. Second operand 17 states. [2018-07-24 10:56:21,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:21,193 INFO L93 Difference]: Finished difference Result 141 states and 152 transitions. [2018-07-24 10:56:21,194 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-07-24 10:56:21,194 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 101 [2018-07-24 10:56:21,194 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:21,195 INFO L225 Difference]: With dead ends: 141 [2018-07-24 10:56:21,195 INFO L226 Difference]: Without dead ends: 139 [2018-07-24 10:56:21,196 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 429 GetRequests, 376 SyntacticMatches, 36 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 227 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=91, Invalid=251, Unknown=0, NotChecked=0, Total=342 [2018-07-24 10:56:21,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2018-07-24 10:56:21,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 139. [2018-07-24 10:56:21,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-07-24 10:56:21,319 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 150 transitions. [2018-07-24 10:56:21,319 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 150 transitions. Word has length 101 [2018-07-24 10:56:21,320 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:21,320 INFO L471 AbstractCegarLoop]: Abstraction has 139 states and 150 transitions. [2018-07-24 10:56:21,320 INFO L472 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-07-24 10:56:21,320 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 150 transitions. [2018-07-24 10:56:21,320 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-07-24 10:56:21,320 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:21,320 INFO L353 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:21,321 INFO L414 AbstractCegarLoop]: === Iteration 56 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:21,321 INFO L82 PathProgramCache]: Analyzing trace with hash -860881985, now seen corresponding path program 17 times [2018-07-24 10:56:21,321 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:21,321 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:21,321 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:21,322 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:21,322 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:21,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:23,017 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:23,017 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:23,017 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 106 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 106 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:23,024 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:56:23,024 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:23,064 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-07-24 10:56:23,065 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:23,067 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:23,517 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:23,517 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:23,716 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:23,736 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:23,736 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 107 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 107 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:23,751 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:56:23,751 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:23,896 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-07-24 10:56:23,896 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:23,901 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:23,920 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:23,920 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:24,157 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:24,158 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:24,159 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 46 [2018-07-24 10:56:24,159 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:24,159 INFO L450 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-07-24 10:56:24,160 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-07-24 10:56:24,160 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=421, Invalid=1649, Unknown=0, NotChecked=0, Total=2070 [2018-07-24 10:56:24,160 INFO L87 Difference]: Start difference. First operand 139 states and 150 transitions. Second operand 46 states. [2018-07-24 10:56:25,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:25,116 INFO L93 Difference]: Finished difference Result 248 states and 280 transitions. [2018-07-24 10:56:25,116 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-07-24 10:56:25,116 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 109 [2018-07-24 10:56:25,116 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:25,117 INFO L225 Difference]: With dead ends: 248 [2018-07-24 10:56:25,117 INFO L226 Difference]: Without dead ends: 199 [2018-07-24 10:56:25,118 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 481 GetRequests, 371 SyntacticMatches, 44 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2822 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=905, Invalid=3651, Unknown=0, NotChecked=0, Total=4556 [2018-07-24 10:56:25,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 199 states. [2018-07-24 10:56:25,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 199 to 141. [2018-07-24 10:56:25,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-07-24 10:56:25,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-07-24 10:56:25,262 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-07-24 10:56:25,262 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:25,262 INFO L471 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-07-24 10:56:25,262 INFO L472 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-07-24 10:56:25,262 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-07-24 10:56:25,263 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-07-24 10:56:25,263 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:25,263 INFO L353 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 9, 8, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:25,263 INFO L414 AbstractCegarLoop]: === Iteration 57 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:25,263 INFO L82 PathProgramCache]: Analyzing trace with hash 1311238219, now seen corresponding path program 29 times [2018-07-24 10:56:25,263 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:25,264 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:25,264 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:25,264 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:25,264 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:25,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:25,538 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:25,538 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:25,538 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 108 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 108 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:25,545 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:56:25,545 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:25,582 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-07-24 10:56:25,582 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:25,584 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:26,291 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:26,292 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:26,506 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:26,525 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:26,526 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 109 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 109 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:26,540 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:56:26,541 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:26,678 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-07-24 10:56:26,678 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:26,682 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:26,703 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:26,703 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:26,986 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (109)] Exception during sending of exit command (exit): Broken pipe [2018-07-24 10:56:26,987 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:26,987 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 45 [2018-07-24 10:56:26,988 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:26,988 INFO L450 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-07-24 10:56:26,988 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-07-24 10:56:26,989 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=391, Invalid=1589, Unknown=0, NotChecked=0, Total=1980 [2018-07-24 10:56:26,989 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 45 states. [2018-07-24 10:56:28,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:28,331 INFO L93 Difference]: Finished difference Result 306 states and 349 transitions. [2018-07-24 10:56:28,331 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-07-24 10:56:28,331 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 109 [2018-07-24 10:56:28,331 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:28,332 INFO L225 Difference]: With dead ends: 306 [2018-07-24 10:56:28,332 INFO L226 Difference]: Without dead ends: 257 [2018-07-24 10:56:28,333 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 490 GetRequests, 372 SyntacticMatches, 44 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3107 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1081, Invalid=4619, Unknown=0, NotChecked=0, Total=5700 [2018-07-24 10:56:28,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 257 states. [2018-07-24 10:56:28,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 257 to 141. [2018-07-24 10:56:28,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-07-24 10:56:28,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-07-24 10:56:28,468 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-07-24 10:56:28,468 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:28,468 INFO L471 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-07-24 10:56:28,469 INFO L472 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-07-24 10:56:28,469 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-07-24 10:56:28,469 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-07-24 10:56:28,469 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:28,469 INFO L353 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 8, 7, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:28,469 INFO L414 AbstractCegarLoop]: === Iteration 58 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:28,470 INFO L82 PathProgramCache]: Analyzing trace with hash 562661335, now seen corresponding path program 30 times [2018-07-24 10:56:28,470 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:28,470 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:28,470 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:28,470 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:28,471 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:28,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:29,940 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:29,941 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:29,941 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 110 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 110 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:29,949 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:56:29,949 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:29,984 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2018-07-24 10:56:29,985 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:29,987 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:30,419 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:30,419 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:30,613 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:30,633 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:30,633 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 111 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 111 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:30,648 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:56:30,648 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:30,793 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2018-07-24 10:56:30,793 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:30,798 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:30,817 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:30,817 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:31,347 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:31,349 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:31,349 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 44 [2018-07-24 10:56:31,349 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:31,349 INFO L450 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-07-24 10:56:31,350 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-07-24 10:56:31,350 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=365, Invalid=1527, Unknown=0, NotChecked=0, Total=1892 [2018-07-24 10:56:31,350 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 44 states. [2018-07-24 10:56:33,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:33,021 INFO L93 Difference]: Finished difference Result 362 states and 416 transitions. [2018-07-24 10:56:33,021 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-07-24 10:56:33,022 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 109 [2018-07-24 10:56:33,022 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:33,023 INFO L225 Difference]: With dead ends: 362 [2018-07-24 10:56:33,023 INFO L226 Difference]: Without dead ends: 313 [2018-07-24 10:56:33,024 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 497 GetRequests, 373 SyntacticMatches, 44 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3349 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=1234, Invalid=5408, Unknown=0, NotChecked=0, Total=6642 [2018-07-24 10:56:33,024 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 313 states. [2018-07-24 10:56:33,230 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 313 to 141. [2018-07-24 10:56:33,231 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-07-24 10:56:33,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-07-24 10:56:33,231 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-07-24 10:56:33,231 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:33,231 INFO L471 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-07-24 10:56:33,231 INFO L472 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-07-24 10:56:33,232 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-07-24 10:56:33,232 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-07-24 10:56:33,232 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:33,232 INFO L353 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 7, 6, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:33,233 INFO L414 AbstractCegarLoop]: === Iteration 59 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:33,233 INFO L82 PathProgramCache]: Analyzing trace with hash 195402339, now seen corresponding path program 31 times [2018-07-24 10:56:33,233 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:33,233 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:33,234 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:33,234 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:33,234 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:33,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:34,062 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:34,063 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:34,063 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 112 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 112 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:34,070 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:34,070 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:56:34,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:34,102 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:34,485 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:34,485 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:34,679 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:34,700 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:34,700 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 113 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 113 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:34,715 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:34,715 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:56:34,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:34,787 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:34,806 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:34,807 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:35,010 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:35,011 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:35,011 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 43 [2018-07-24 10:56:35,011 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:35,011 INFO L450 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-07-24 10:56:35,012 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-07-24 10:56:35,012 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=343, Invalid=1463, Unknown=0, NotChecked=0, Total=1806 [2018-07-24 10:56:35,012 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 43 states. [2018-07-24 10:56:37,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:37,021 INFO L93 Difference]: Finished difference Result 416 states and 481 transitions. [2018-07-24 10:56:37,021 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-07-24 10:56:37,021 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 109 [2018-07-24 10:56:37,021 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:37,023 INFO L225 Difference]: With dead ends: 416 [2018-07-24 10:56:37,023 INFO L226 Difference]: Without dead ends: 367 [2018-07-24 10:56:37,024 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 502 GetRequests, 374 SyntacticMatches, 44 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3510 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1346, Invalid=5964, Unknown=0, NotChecked=0, Total=7310 [2018-07-24 10:56:37,024 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 367 states. [2018-07-24 10:56:37,252 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 367 to 141. [2018-07-24 10:56:37,252 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-07-24 10:56:37,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-07-24 10:56:37,253 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-07-24 10:56:37,253 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:37,253 INFO L471 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-07-24 10:56:37,253 INFO L472 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-07-24 10:56:37,253 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-07-24 10:56:37,254 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-07-24 10:56:37,254 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:37,254 INFO L353 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 6, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:37,254 INFO L414 AbstractCegarLoop]: === Iteration 60 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:37,255 INFO L82 PathProgramCache]: Analyzing trace with hash 1316806639, now seen corresponding path program 32 times [2018-07-24 10:56:37,255 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:37,255 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:37,256 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:37,256 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:37,256 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:37,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:38,800 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:38,800 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:38,800 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 114 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 114 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:38,808 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:38,808 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:38,851 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:38,852 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:38,854 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:39,221 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:39,221 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:39,408 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:39,428 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:39,428 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 115 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 115 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:39,443 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:39,443 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:39,517 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:39,517 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:39,521 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:39,539 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:39,540 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:39,853 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:39,855 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:39,855 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 42 [2018-07-24 10:56:39,855 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:39,855 INFO L450 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-07-24 10:56:39,856 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-07-24 10:56:39,856 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=1397, Unknown=0, NotChecked=0, Total=1722 [2018-07-24 10:56:39,856 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 42 states. [2018-07-24 10:56:41,894 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:41,894 INFO L93 Difference]: Finished difference Result 468 states and 544 transitions. [2018-07-24 10:56:41,895 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-07-24 10:56:41,895 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 109 [2018-07-24 10:56:41,895 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:41,896 INFO L225 Difference]: With dead ends: 468 [2018-07-24 10:56:41,897 INFO L226 Difference]: Without dead ends: 419 [2018-07-24 10:56:41,897 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 505 GetRequests, 375 SyntacticMatches, 44 SemanticMatches, 86 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3564 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=1405, Invalid=6251, Unknown=0, NotChecked=0, Total=7656 [2018-07-24 10:56:41,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 419 states. [2018-07-24 10:56:42,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 419 to 141. [2018-07-24 10:56:42,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-07-24 10:56:42,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-07-24 10:56:42,052 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-07-24 10:56:42,052 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:42,052 INFO L471 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-07-24 10:56:42,052 INFO L472 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-07-24 10:56:42,052 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-07-24 10:56:42,053 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-07-24 10:56:42,053 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:42,053 INFO L353 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 6, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:42,053 INFO L414 AbstractCegarLoop]: === Iteration 61 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:42,053 INFO L82 PathProgramCache]: Analyzing trace with hash 893393019, now seen corresponding path program 33 times [2018-07-24 10:56:42,054 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:42,054 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:42,054 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:42,054 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:42,055 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:42,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:42,401 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:42,401 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:42,401 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 116 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 116 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:42,409 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:56:42,409 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:56:42,444 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-07-24 10:56:42,444 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:42,446 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:42,793 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:42,793 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:43,279 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:43,298 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:43,299 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 117 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 117 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:43,313 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:56:43,314 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:56:43,467 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-07-24 10:56:43,468 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:43,472 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:43,491 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:43,491 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:43,713 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:43,714 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:43,715 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 41 [2018-07-24 10:56:43,715 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:43,715 INFO L450 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-07-24 10:56:43,715 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-07-24 10:56:43,715 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=311, Invalid=1329, Unknown=0, NotChecked=0, Total=1640 [2018-07-24 10:56:43,716 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 41 states. [2018-07-24 10:56:45,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:45,850 INFO L93 Difference]: Finished difference Result 518 states and 605 transitions. [2018-07-24 10:56:45,850 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-07-24 10:56:45,850 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 109 [2018-07-24 10:56:45,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:45,852 INFO L225 Difference]: With dead ends: 518 [2018-07-24 10:56:45,852 INFO L226 Difference]: Without dead ends: 469 [2018-07-24 10:56:45,853 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 506 GetRequests, 376 SyntacticMatches, 44 SemanticMatches, 86 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3497 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1405, Invalid=6251, Unknown=0, NotChecked=0, Total=7656 [2018-07-24 10:56:45,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 469 states. [2018-07-24 10:56:46,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 469 to 141. [2018-07-24 10:56:46,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-07-24 10:56:46,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-07-24 10:56:46,016 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-07-24 10:56:46,016 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:46,016 INFO L471 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-07-24 10:56:46,016 INFO L472 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-07-24 10:56:46,016 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-07-24 10:56:46,017 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-07-24 10:56:46,017 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:46,018 INFO L353 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 7, 6, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:46,018 INFO L414 AbstractCegarLoop]: === Iteration 62 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:46,018 INFO L82 PathProgramCache]: Analyzing trace with hash -1605368825, now seen corresponding path program 34 times [2018-07-24 10:56:46,018 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:46,019 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:46,019 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:46,019 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:46,019 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:46,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:46,829 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:46,830 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:46,830 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 118 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 118 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:46,839 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:56:46,839 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:56:46,870 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:56:46,870 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:46,872 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:47,263 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:47,263 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:47,451 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:47,470 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:47,471 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 119 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 119 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:47,485 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:56:47,485 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:56:47,566 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:56:47,566 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:47,570 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:47,588 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:47,588 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:47,841 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:47,842 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:47,842 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 40 [2018-07-24 10:56:47,842 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:47,843 INFO L450 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-07-24 10:56:47,843 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-07-24 10:56:47,843 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=301, Invalid=1259, Unknown=0, NotChecked=0, Total=1560 [2018-07-24 10:56:47,843 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 40 states. [2018-07-24 10:56:50,219 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:50,220 INFO L93 Difference]: Finished difference Result 566 states and 664 transitions. [2018-07-24 10:56:50,220 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-07-24 10:56:50,220 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 109 [2018-07-24 10:56:50,220 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:50,222 INFO L225 Difference]: With dead ends: 566 [2018-07-24 10:56:50,222 INFO L226 Difference]: Without dead ends: 517 [2018-07-24 10:56:50,223 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 505 GetRequests, 377 SyntacticMatches, 44 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3303 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=1346, Invalid=5964, Unknown=0, NotChecked=0, Total=7310 [2018-07-24 10:56:50,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 517 states. [2018-07-24 10:56:50,389 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 517 to 141. [2018-07-24 10:56:50,389 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-07-24 10:56:50,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-07-24 10:56:50,390 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-07-24 10:56:50,390 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:50,390 INFO L471 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-07-24 10:56:50,390 INFO L472 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-07-24 10:56:50,390 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-07-24 10:56:50,391 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-07-24 10:56:50,391 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:50,391 INFO L353 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 8, 7, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:50,391 INFO L414 AbstractCegarLoop]: === Iteration 63 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:50,391 INFO L82 PathProgramCache]: Analyzing trace with hash -1858248045, now seen corresponding path program 35 times [2018-07-24 10:56:50,391 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:50,392 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:50,392 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:50,392 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:50,392 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:50,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:50,788 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:50,789 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:50,789 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 120 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 120 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:50,798 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:56:50,799 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:50,838 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-07-24 10:56:50,838 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:50,841 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:51,165 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:51,166 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:51,486 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:51,505 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:51,505 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 121 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 121 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:51,521 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:56:51,521 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:51,657 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-07-24 10:56:51,657 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:51,661 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:51,680 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:51,680 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:51,921 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:51,922 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:51,923 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 39 [2018-07-24 10:56:51,923 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:51,923 INFO L450 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-07-24 10:56:51,923 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-07-24 10:56:51,923 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=295, Invalid=1187, Unknown=0, NotChecked=0, Total=1482 [2018-07-24 10:56:51,924 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 39 states. [2018-07-24 10:56:54,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:54,198 INFO L93 Difference]: Finished difference Result 612 states and 721 transitions. [2018-07-24 10:56:54,198 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-07-24 10:56:54,198 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 109 [2018-07-24 10:56:54,199 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:54,201 INFO L225 Difference]: With dead ends: 612 [2018-07-24 10:56:54,201 INFO L226 Difference]: Without dead ends: 563 [2018-07-24 10:56:54,202 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 502 GetRequests, 378 SyntacticMatches, 44 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2984 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1234, Invalid=5408, Unknown=0, NotChecked=0, Total=6642 [2018-07-24 10:56:54,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 563 states. [2018-07-24 10:56:54,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 563 to 141. [2018-07-24 10:56:54,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-07-24 10:56:54,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-07-24 10:56:54,363 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-07-24 10:56:54,363 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:54,363 INFO L471 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-07-24 10:56:54,363 INFO L472 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-07-24 10:56:54,364 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-07-24 10:56:54,364 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-07-24 10:56:54,364 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:54,364 INFO L353 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 9, 8, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:54,364 INFO L414 AbstractCegarLoop]: === Iteration 64 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:54,365 INFO L82 PathProgramCache]: Analyzing trace with hash -1228344289, now seen corresponding path program 36 times [2018-07-24 10:56:54,365 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:54,365 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:54,365 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:54,365 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:54,366 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:54,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:54,825 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:54,825 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:54,826 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 122 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 122 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:54,833 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:56:54,833 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:54,874 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2018-07-24 10:56:54,874 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:54,877 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:55,184 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:55,184 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:55,371 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:55,392 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:55,392 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 123 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 123 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:55,407 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:56:55,407 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:55,547 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2018-07-24 10:56:55,547 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:55,551 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:55,568 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:55,569 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:55,782 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:55,783 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:55,783 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 38 [2018-07-24 10:56:55,783 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:55,783 INFO L450 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-07-24 10:56:55,784 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-07-24 10:56:55,784 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=293, Invalid=1113, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:56:55,784 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 38 states. [2018-07-24 10:56:58,216 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:58,217 INFO L93 Difference]: Finished difference Result 656 states and 776 transitions. [2018-07-24 10:56:58,217 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-07-24 10:56:58,217 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 109 [2018-07-24 10:56:58,217 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:58,219 INFO L225 Difference]: With dead ends: 656 [2018-07-24 10:56:58,219 INFO L226 Difference]: Without dead ends: 607 [2018-07-24 10:56:58,220 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 497 GetRequests, 379 SyntacticMatches, 44 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2554 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1081, Invalid=4619, Unknown=0, NotChecked=0, Total=5700 [2018-07-24 10:56:58,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 607 states. [2018-07-24 10:56:58,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 607 to 141. [2018-07-24 10:56:58,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-07-24 10:56:58,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-07-24 10:56:58,393 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-07-24 10:56:58,393 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:58,393 INFO L471 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-07-24 10:56:58,394 INFO L472 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-07-24 10:56:58,394 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-07-24 10:56:58,394 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-07-24 10:56:58,394 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:58,395 INFO L353 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:58,395 INFO L414 AbstractCegarLoop]: === Iteration 65 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:58,395 INFO L82 PathProgramCache]: Analyzing trace with hash -119310165, now seen corresponding path program 9 times [2018-07-24 10:56:58,395 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:58,395 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:58,396 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:58,396 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:58,396 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:58,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:59,182 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:59,183 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:59,183 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 124 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 124 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:59,190 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:56:59,190 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:56:59,226 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-07-24 10:56:59,226 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:59,229 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:59,516 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:59,516 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:59,733 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:59,753 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:59,753 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 125 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 125 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:59,768 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:56:59,768 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:56:59,912 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-07-24 10:56:59,913 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:59,917 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:59,935 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:56:59,935 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:00,146 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:57:00,148 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:00,148 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 37 [2018-07-24 10:57:00,148 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:00,148 INFO L450 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-07-24 10:57:00,148 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-07-24 10:57:00,149 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=295, Invalid=1037, Unknown=0, NotChecked=0, Total=1332 [2018-07-24 10:57:00,149 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 37 states. [2018-07-24 10:57:02,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:02,652 INFO L93 Difference]: Finished difference Result 703 states and 835 transitions. [2018-07-24 10:57:02,653 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-07-24 10:57:02,653 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 109 [2018-07-24 10:57:02,653 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:02,656 INFO L225 Difference]: With dead ends: 703 [2018-07-24 10:57:02,656 INFO L226 Difference]: Without dead ends: 654 [2018-07-24 10:57:02,657 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 490 GetRequests, 380 SyntacticMatches, 44 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2039 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=905, Invalid=3651, Unknown=0, NotChecked=0, Total=4556 [2018-07-24 10:57:02,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 654 states. [2018-07-24 10:57:02,826 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 654 to 144. [2018-07-24 10:57:02,826 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-07-24 10:57:02,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 156 transitions. [2018-07-24 10:57:02,827 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 156 transitions. Word has length 109 [2018-07-24 10:57:02,827 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:02,827 INFO L471 AbstractCegarLoop]: Abstraction has 144 states and 156 transitions. [2018-07-24 10:57:02,827 INFO L472 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-07-24 10:57:02,827 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 156 transitions. [2018-07-24 10:57:02,827 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-07-24 10:57:02,828 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:02,828 INFO L353 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:02,828 INFO L414 AbstractCegarLoop]: === Iteration 66 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:02,828 INFO L82 PathProgramCache]: Analyzing trace with hash -1752486599, now seen corresponding path program 18 times [2018-07-24 10:57:02,828 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:02,828 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:02,829 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:02,829 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:02,829 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:02,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:02,989 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 127 proven. 196 refuted. 0 times theorem prover too weak. 120 trivial. 0 not checked. [2018-07-24 10:57:02,989 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:02,990 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 126 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 126 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:02,997 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:57:02,997 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:57:03,032 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2018-07-24 10:57:03,033 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:03,035 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:03,094 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 128 proven. 171 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:57:03,094 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:03,207 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 128 proven. 171 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:57:03,227 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:03,227 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 127 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 127 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:03,242 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:57:03,242 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:57:03,400 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2018-07-24 10:57:03,401 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:03,405 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:03,415 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 128 proven. 171 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:57:03,416 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:03,544 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 128 proven. 171 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:57:03,546 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:03,546 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 15, 15, 15, 15] total 18 [2018-07-24 10:57:03,546 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:03,546 INFO L450 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-07-24 10:57:03,547 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-07-24 10:57:03,547 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=90, Invalid=216, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:57:03,547 INFO L87 Difference]: Start difference. First operand 144 states and 156 transitions. Second operand 18 states. [2018-07-24 10:57:04,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:04,001 INFO L93 Difference]: Finished difference Result 154 states and 166 transitions. [2018-07-24 10:57:04,001 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-07-24 10:57:04,001 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 111 [2018-07-24 10:57:04,002 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:04,003 INFO L225 Difference]: With dead ends: 154 [2018-07-24 10:57:04,003 INFO L226 Difference]: Without dead ends: 152 [2018-07-24 10:57:04,003 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 471 GetRequests, 413 SyntacticMatches, 40 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 272 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=103, Invalid=277, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:57:04,003 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-07-24 10:57:04,182 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 152. [2018-07-24 10:57:04,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 152 states. [2018-07-24 10:57:04,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152 states to 152 states and 164 transitions. [2018-07-24 10:57:04,183 INFO L78 Accepts]: Start accepts. Automaton has 152 states and 164 transitions. Word has length 111 [2018-07-24 10:57:04,183 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:04,184 INFO L471 AbstractCegarLoop]: Abstraction has 152 states and 164 transitions. [2018-07-24 10:57:04,184 INFO L472 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-07-24 10:57:04,184 INFO L276 IsEmpty]: Start isEmpty. Operand 152 states and 164 transitions. [2018-07-24 10:57:04,184 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-07-24 10:57:04,185 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:04,185 INFO L353 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 11, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:04,185 INFO L414 AbstractCegarLoop]: === Iteration 67 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:04,185 INFO L82 PathProgramCache]: Analyzing trace with hash 1040286813, now seen corresponding path program 19 times [2018-07-24 10:57:04,185 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:04,186 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:04,186 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:04,186 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:04,186 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:04,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:05,314 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:05,314 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:05,314 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 128 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 128 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:05,323 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:05,323 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:57:05,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:05,356 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:05,857 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:05,857 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:06,115 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:06,136 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:06,136 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 129 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 129 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:06,152 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:06,152 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:57:06,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:06,226 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:06,248 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:06,249 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:06,492 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:06,494 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:06,494 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 50 [2018-07-24 10:57:06,494 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:06,495 INFO L450 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-07-24 10:57:06,496 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-07-24 10:57:06,496 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=495, Invalid=1955, Unknown=0, NotChecked=0, Total=2450 [2018-07-24 10:57:06,496 INFO L87 Difference]: Start difference. First operand 152 states and 164 transitions. Second operand 50 states. [2018-07-24 10:57:07,821 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:07,821 INFO L93 Difference]: Finished difference Result 271 states and 306 transitions. [2018-07-24 10:57:07,821 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-07-24 10:57:07,821 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 119 [2018-07-24 10:57:07,822 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:07,822 INFO L225 Difference]: With dead ends: 271 [2018-07-24 10:57:07,823 INFO L226 Difference]: Without dead ends: 218 [2018-07-24 10:57:07,823 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 525 GetRequests, 405 SyntacticMatches, 48 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3407 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=1059, Invalid=4343, Unknown=0, NotChecked=0, Total=5402 [2018-07-24 10:57:07,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 218 states. [2018-07-24 10:57:08,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 218 to 154. [2018-07-24 10:57:08,009 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-07-24 10:57:08,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-07-24 10:57:08,009 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-07-24 10:57:08,009 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:08,010 INFO L471 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-07-24 10:57:08,010 INFO L472 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-07-24 10:57:08,010 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-07-24 10:57:08,010 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-07-24 10:57:08,010 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:08,011 INFO L353 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 10, 9, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:08,011 INFO L414 AbstractCegarLoop]: === Iteration 68 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:08,011 INFO L82 PathProgramCache]: Analyzing trace with hash -661376535, now seen corresponding path program 37 times [2018-07-24 10:57:08,011 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:08,012 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:08,012 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:08,012 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:08,012 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:08,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:08,310 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:08,310 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:08,311 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 130 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 130 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:08,318 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:08,318 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:57:08,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:08,356 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:08,835 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:08,835 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:09,088 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:09,108 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:09,108 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 131 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 131 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:09,123 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:09,124 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:57:09,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:09,201 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:09,223 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:09,223 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:09,476 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:09,477 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:09,477 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 49 [2018-07-24 10:57:09,477 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:09,478 INFO L450 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-07-24 10:57:09,478 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-07-24 10:57:09,478 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=462, Invalid=1890, Unknown=0, NotChecked=0, Total=2352 [2018-07-24 10:57:09,478 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 49 states. [2018-07-24 10:57:11,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:11,338 INFO L93 Difference]: Finished difference Result 335 states and 382 transitions. [2018-07-24 10:57:11,338 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-07-24 10:57:11,338 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 119 [2018-07-24 10:57:11,338 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:11,340 INFO L225 Difference]: With dead ends: 335 [2018-07-24 10:57:11,340 INFO L226 Difference]: Without dead ends: 282 [2018-07-24 10:57:11,340 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 535 GetRequests, 406 SyntacticMatches, 48 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3775 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1275, Invalid=5531, Unknown=0, NotChecked=0, Total=6806 [2018-07-24 10:57:11,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282 states. [2018-07-24 10:57:11,543 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282 to 154. [2018-07-24 10:57:11,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-07-24 10:57:11,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-07-24 10:57:11,544 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-07-24 10:57:11,544 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:11,544 INFO L471 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-07-24 10:57:11,544 INFO L472 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-07-24 10:57:11,544 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-07-24 10:57:11,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-07-24 10:57:11,545 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:11,545 INFO L353 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 9, 8, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:11,545 INFO L414 AbstractCegarLoop]: === Iteration 69 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:11,545 INFO L82 PathProgramCache]: Analyzing trace with hash 516739701, now seen corresponding path program 38 times [2018-07-24 10:57:11,545 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:11,546 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:11,546 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:11,546 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:11,546 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:11,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:12,003 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:12,004 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:12,004 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 132 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 132 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:12,010 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:57:12,011 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:12,046 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:57:12,046 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:12,048 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:12,594 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:12,594 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:12,889 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:12,910 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:12,911 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 133 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 133 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:12,925 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:57:12,925 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:13,001 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:57:13,002 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:13,007 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:13,035 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:13,035 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:13,293 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:13,295 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:13,295 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 48 [2018-07-24 10:57:13,295 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:13,295 INFO L450 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-07-24 10:57:13,296 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-07-24 10:57:13,296 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=433, Invalid=1823, Unknown=0, NotChecked=0, Total=2256 [2018-07-24 10:57:13,296 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 48 states. [2018-07-24 10:57:15,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:15,533 INFO L93 Difference]: Finished difference Result 397 states and 456 transitions. [2018-07-24 10:57:15,533 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-07-24 10:57:15,533 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 119 [2018-07-24 10:57:15,534 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:15,535 INFO L225 Difference]: With dead ends: 397 [2018-07-24 10:57:15,535 INFO L226 Difference]: Without dead ends: 344 [2018-07-24 10:57:15,536 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 543 GetRequests, 407 SyntacticMatches, 48 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4105 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1471, Invalid=6539, Unknown=0, NotChecked=0, Total=8010 [2018-07-24 10:57:15,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 344 states. [2018-07-24 10:57:15,742 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 344 to 154. [2018-07-24 10:57:15,742 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-07-24 10:57:15,743 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-07-24 10:57:15,743 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-07-24 10:57:15,743 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:15,743 INFO L471 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-07-24 10:57:15,743 INFO L472 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-07-24 10:57:15,743 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-07-24 10:57:15,744 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-07-24 10:57:15,744 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:15,744 INFO L353 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 8, 7, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:15,744 INFO L414 AbstractCegarLoop]: === Iteration 70 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:15,744 INFO L82 PathProgramCache]: Analyzing trace with hash -1752422911, now seen corresponding path program 39 times [2018-07-24 10:57:15,744 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:15,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:15,745 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:15,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:15,745 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:15,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:16,019 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:16,019 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:16,020 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 134 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 134 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:16,027 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:57:16,027 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:57:16,066 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-07-24 10:57:16,066 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:16,068 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:16,552 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:16,552 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:16,777 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:16,796 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:16,797 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 135 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 135 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:16,812 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:57:16,812 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:57:16,990 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-07-24 10:57:16,991 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:16,994 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:17,015 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:17,016 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:17,405 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:17,406 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:17,406 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 47 [2018-07-24 10:57:17,406 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:17,407 INFO L450 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-07-24 10:57:17,407 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-07-24 10:57:17,407 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=408, Invalid=1754, Unknown=0, NotChecked=0, Total=2162 [2018-07-24 10:57:17,407 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 47 states. [2018-07-24 10:57:19,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:19,836 INFO L93 Difference]: Finished difference Result 457 states and 528 transitions. [2018-07-24 10:57:19,836 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-07-24 10:57:19,836 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 119 [2018-07-24 10:57:19,836 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:19,838 INFO L225 Difference]: With dead ends: 457 [2018-07-24 10:57:19,838 INFO L226 Difference]: Without dead ends: 404 [2018-07-24 10:57:19,839 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 549 GetRequests, 408 SyntacticMatches, 48 SemanticMatches, 93 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4353 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1626, Invalid=7304, Unknown=0, NotChecked=0, Total=8930 [2018-07-24 10:57:19,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 404 states. [2018-07-24 10:57:20,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 404 to 154. [2018-07-24 10:57:20,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-07-24 10:57:20,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-07-24 10:57:20,090 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-07-24 10:57:20,090 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:20,090 INFO L471 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-07-24 10:57:20,090 INFO L472 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-07-24 10:57:20,090 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-07-24 10:57:20,091 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-07-24 10:57:20,091 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:20,091 INFO L353 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 7, 6, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:20,091 INFO L414 AbstractCegarLoop]: === Iteration 71 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:20,091 INFO L82 PathProgramCache]: Analyzing trace with hash -1964839795, now seen corresponding path program 40 times [2018-07-24 10:57:20,092 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:20,092 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:20,092 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:20,092 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:20,092 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:20,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:20,390 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:20,390 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:20,390 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 136 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 136 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:20,398 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:57:20,398 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:57:20,434 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:57:20,434 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:20,437 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:20,878 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:20,879 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:21,108 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:21,128 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:21,128 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 137 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 137 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:21,143 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:57:21,143 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:57:21,235 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:57:21,235 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:21,239 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:21,260 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:21,261 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:21,527 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:21,528 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:21,529 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 46 [2018-07-24 10:57:21,529 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:21,529 INFO L450 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-07-24 10:57:21,529 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-07-24 10:57:21,530 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=387, Invalid=1683, Unknown=0, NotChecked=0, Total=2070 [2018-07-24 10:57:21,530 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 46 states. [2018-07-24 10:57:24,370 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:24,370 INFO L93 Difference]: Finished difference Result 515 states and 598 transitions. [2018-07-24 10:57:24,371 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-07-24 10:57:24,371 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 119 [2018-07-24 10:57:24,371 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:24,373 INFO L225 Difference]: With dead ends: 515 [2018-07-24 10:57:24,373 INFO L226 Difference]: Without dead ends: 462 [2018-07-24 10:57:24,374 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 553 GetRequests, 409 SyntacticMatches, 48 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4487 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1725, Invalid=7781, Unknown=0, NotChecked=0, Total=9506 [2018-07-24 10:57:24,375 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 462 states. [2018-07-24 10:57:24,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 462 to 154. [2018-07-24 10:57:24,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-07-24 10:57:24,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-07-24 10:57:24,600 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-07-24 10:57:24,600 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:24,600 INFO L471 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-07-24 10:57:24,600 INFO L472 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-07-24 10:57:24,600 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-07-24 10:57:24,600 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-07-24 10:57:24,600 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:24,601 INFO L353 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 6, 6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:24,601 INFO L414 AbstractCegarLoop]: === Iteration 72 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:24,601 INFO L82 PathProgramCache]: Analyzing trace with hash -1911429607, now seen corresponding path program 41 times [2018-07-24 10:57:24,601 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:24,602 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:24,602 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:24,602 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:24,602 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:24,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:24,895 INFO L134 CoverageAnalysis]: Checked inductivity of 470 backedges. 230 proven. 60 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:24,895 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:24,895 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 138 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 138 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:24,903 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:57:24,903 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:24,941 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 11 check-sat command(s) [2018-07-24 10:57:24,941 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:24,944 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:25,365 INFO L134 CoverageAnalysis]: Checked inductivity of 470 backedges. 230 proven. 60 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:25,365 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:25,598 INFO L134 CoverageAnalysis]: Checked inductivity of 470 backedges. 230 proven. 60 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:25,617 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:25,617 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 139 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 139 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:25,633 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:57:25,633 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:25,781 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 11 check-sat command(s) [2018-07-24 10:57:25,782 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:25,786 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:25,808 INFO L134 CoverageAnalysis]: Checked inductivity of 470 backedges. 230 proven. 60 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:25,808 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:26,057 INFO L134 CoverageAnalysis]: Checked inductivity of 470 backedges. 230 proven. 60 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:26,058 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:26,058 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 45 [2018-07-24 10:57:26,059 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:26,059 INFO L450 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-07-24 10:57:26,059 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-07-24 10:57:26,059 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=370, Invalid=1610, Unknown=0, NotChecked=0, Total=1980 [2018-07-24 10:57:26,060 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 45 states. [2018-07-24 10:57:29,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:29,052 INFO L93 Difference]: Finished difference Result 571 states and 666 transitions. [2018-07-24 10:57:29,052 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-07-24 10:57:29,052 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 119 [2018-07-24 10:57:29,052 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:29,055 INFO L225 Difference]: With dead ends: 571 [2018-07-24 10:57:29,055 INFO L226 Difference]: Without dead ends: 518 [2018-07-24 10:57:29,056 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 555 GetRequests, 410 SyntacticMatches, 48 SemanticMatches, 97 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4487 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1759, Invalid=7943, Unknown=0, NotChecked=0, Total=9702 [2018-07-24 10:57:29,057 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518 states. [2018-07-24 10:57:29,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518 to 154. [2018-07-24 10:57:29,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-07-24 10:57:29,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-07-24 10:57:29,291 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-07-24 10:57:29,291 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:29,291 INFO L471 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-07-24 10:57:29,291 INFO L472 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-07-24 10:57:29,291 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-07-24 10:57:29,292 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-07-24 10:57:29,292 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:29,292 INFO L353 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 7, 6, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:29,292 INFO L414 AbstractCegarLoop]: === Iteration 73 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:29,292 INFO L82 PathProgramCache]: Analyzing trace with hash 260690597, now seen corresponding path program 42 times [2018-07-24 10:57:29,292 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:29,293 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:29,293 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:29,293 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:29,293 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:29,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:29,711 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:29,711 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:29,712 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 140 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 140 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:29,718 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:57:29,718 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:57:29,758 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2018-07-24 10:57:29,758 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:29,774 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:30,219 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:30,219 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:30,442 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:30,462 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:30,462 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 141 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 141 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:30,478 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:57:30,478 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:57:30,644 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2018-07-24 10:57:30,644 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:30,649 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:30,671 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:30,671 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:30,914 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:30,916 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:30,916 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 44 [2018-07-24 10:57:30,916 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:30,916 INFO L450 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-07-24 10:57:30,916 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-07-24 10:57:30,917 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=357, Invalid=1535, Unknown=0, NotChecked=0, Total=1892 [2018-07-24 10:57:30,917 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 44 states. [2018-07-24 10:57:34,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:34,126 INFO L93 Difference]: Finished difference Result 625 states and 732 transitions. [2018-07-24 10:57:34,127 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-07-24 10:57:34,127 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 119 [2018-07-24 10:57:34,127 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:34,129 INFO L225 Difference]: With dead ends: 625 [2018-07-24 10:57:34,129 INFO L226 Difference]: Without dead ends: 572 [2018-07-24 10:57:34,130 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 555 GetRequests, 411 SyntacticMatches, 48 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4344 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=1725, Invalid=7781, Unknown=0, NotChecked=0, Total=9506 [2018-07-24 10:57:34,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 572 states. [2018-07-24 10:57:34,363 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 572 to 154. [2018-07-24 10:57:34,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-07-24 10:57:34,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-07-24 10:57:34,364 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-07-24 10:57:34,364 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:34,364 INFO L471 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-07-24 10:57:34,365 INFO L472 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-07-24 10:57:34,365 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-07-24 10:57:34,365 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-07-24 10:57:34,365 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:34,366 INFO L353 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 8, 7, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:34,366 INFO L414 AbstractCegarLoop]: === Iteration 74 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:34,366 INFO L82 PathProgramCache]: Analyzing trace with hash -487886287, now seen corresponding path program 43 times [2018-07-24 10:57:34,366 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:34,367 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:34,367 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:34,367 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:34,367 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:34,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:34,643 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:34,644 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:34,644 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 142 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 142 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:34,651 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:34,651 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:57:34,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:34,688 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:35,067 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:35,067 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:35,285 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:35,305 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:35,305 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 143 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 143 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:35,320 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:35,320 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:57:35,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:35,397 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:35,418 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:35,418 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:35,688 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:35,689 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:35,689 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 43 [2018-07-24 10:57:35,689 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:35,690 INFO L450 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-07-24 10:57:35,690 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-07-24 10:57:35,691 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=348, Invalid=1458, Unknown=0, NotChecked=0, Total=1806 [2018-07-24 10:57:35,691 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 43 states. [2018-07-24 10:57:39,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:39,065 INFO L93 Difference]: Finished difference Result 677 states and 796 transitions. [2018-07-24 10:57:39,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-07-24 10:57:39,066 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 119 [2018-07-24 10:57:39,066 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:39,068 INFO L225 Difference]: With dead ends: 677 [2018-07-24 10:57:39,068 INFO L226 Difference]: Without dead ends: 624 [2018-07-24 10:57:39,069 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 553 GetRequests, 412 SyntacticMatches, 48 SemanticMatches, 93 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4055 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1626, Invalid=7304, Unknown=0, NotChecked=0, Total=8930 [2018-07-24 10:57:39,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 624 states. [2018-07-24 10:57:39,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 624 to 154. [2018-07-24 10:57:39,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-07-24 10:57:39,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-07-24 10:57:39,299 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-07-24 10:57:39,299 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:39,299 INFO L471 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-07-24 10:57:39,299 INFO L472 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-07-24 10:57:39,299 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-07-24 10:57:39,300 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-07-24 10:57:39,300 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:39,300 INFO L353 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 9, 8, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:39,300 INFO L414 AbstractCegarLoop]: === Iteration 75 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:39,300 INFO L82 PathProgramCache]: Analyzing trace with hash -855145283, now seen corresponding path program 44 times [2018-07-24 10:57:39,300 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:39,301 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:39,301 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:39,301 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:39,301 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:39,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:39,675 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:39,676 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:39,676 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 144 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 144 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:39,683 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:57:39,683 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:39,718 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:57:39,719 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:39,720 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:40,113 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:40,113 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:40,326 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:40,346 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:40,346 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 145 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 145 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:40,361 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:57:40,361 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:40,439 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:57:40,439 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:40,444 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:40,465 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:40,465 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:40,708 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:40,709 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:40,709 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 42 [2018-07-24 10:57:40,709 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:40,709 INFO L450 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-07-24 10:57:40,710 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-07-24 10:57:40,710 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=343, Invalid=1379, Unknown=0, NotChecked=0, Total=1722 [2018-07-24 10:57:40,710 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 42 states. [2018-07-24 10:57:43,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:43,975 INFO L93 Difference]: Finished difference Result 727 states and 858 transitions. [2018-07-24 10:57:43,975 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-07-24 10:57:43,975 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 119 [2018-07-24 10:57:43,975 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:43,978 INFO L225 Difference]: With dead ends: 727 [2018-07-24 10:57:43,978 INFO L226 Difference]: Without dead ends: 674 [2018-07-24 10:57:43,979 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 549 GetRequests, 413 SyntacticMatches, 48 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3628 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1471, Invalid=6539, Unknown=0, NotChecked=0, Total=8010 [2018-07-24 10:57:43,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 674 states. [2018-07-24 10:57:44,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 674 to 154. [2018-07-24 10:57:44,225 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-07-24 10:57:44,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-07-24 10:57:44,225 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-07-24 10:57:44,225 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:44,225 INFO L471 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-07-24 10:57:44,225 INFO L472 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-07-24 10:57:44,225 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-07-24 10:57:44,226 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-07-24 10:57:44,226 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:44,226 INFO L353 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 10, 9, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:44,226 INFO L414 AbstractCegarLoop]: === Iteration 76 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:44,226 INFO L82 PathProgramCache]: Analyzing trace with hash 266259017, now seen corresponding path program 45 times [2018-07-24 10:57:44,227 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:44,227 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:44,227 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:44,227 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:44,227 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:44,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:44,690 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:44,690 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:44,690 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 146 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 146 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:44,708 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:57:44,708 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:57:44,747 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-07-24 10:57:44,747 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:44,749 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:45,110 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:45,110 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:45,326 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:45,347 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:45,347 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 147 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 147 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:45,361 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:57:45,362 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:57:45,536 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-07-24 10:57:45,536 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:45,540 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:45,560 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:45,560 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:45,806 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:45,808 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:45,809 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 41 [2018-07-24 10:57:45,809 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:45,809 INFO L450 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-07-24 10:57:45,809 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-07-24 10:57:45,810 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=342, Invalid=1298, Unknown=0, NotChecked=0, Total=1640 [2018-07-24 10:57:45,810 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 41 states. [2018-07-24 10:57:49,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:49,256 INFO L93 Difference]: Finished difference Result 775 states and 918 transitions. [2018-07-24 10:57:49,257 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-07-24 10:57:49,257 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 119 [2018-07-24 10:57:49,257 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:49,260 INFO L225 Difference]: With dead ends: 775 [2018-07-24 10:57:49,260 INFO L226 Difference]: Without dead ends: 722 [2018-07-24 10:57:49,260 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 543 GetRequests, 414 SyntacticMatches, 48 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3083 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1275, Invalid=5531, Unknown=0, NotChecked=0, Total=6806 [2018-07-24 10:57:49,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 722 states. [2018-07-24 10:57:49,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 722 to 154. [2018-07-24 10:57:49,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-07-24 10:57:49,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-07-24 10:57:49,498 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-07-24 10:57:49,498 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:49,498 INFO L471 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-07-24 10:57:49,498 INFO L472 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-07-24 10:57:49,498 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-07-24 10:57:49,499 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-07-24 10:57:49,499 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:49,499 INFO L353 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 11, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:49,499 INFO L414 AbstractCegarLoop]: === Iteration 77 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:49,499 INFO L82 PathProgramCache]: Analyzing trace with hash -157154603, now seen corresponding path program 10 times [2018-07-24 10:57:49,499 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:49,499 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:49,500 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:49,500 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:49,500 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:49,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:49,841 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:49,842 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:49,842 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 148 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 148 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:49,848 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:57:49,849 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:57:49,884 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:57:49,884 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:49,886 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:50,242 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:50,242 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:50,475 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:50,495 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:50,495 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 149 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 149 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:50,510 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:57:50,510 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:57:50,601 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:57:50,601 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:50,606 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:50,626 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:50,626 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:50,867 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:50,869 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:50,869 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 40 [2018-07-24 10:57:50,869 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:50,869 INFO L450 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-07-24 10:57:50,869 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-07-24 10:57:50,870 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=345, Invalid=1215, Unknown=0, NotChecked=0, Total=1560 [2018-07-24 10:57:50,870 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 40 states. [2018-07-24 10:57:54,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:54,142 INFO L93 Difference]: Finished difference Result 826 states and 982 transitions. [2018-07-24 10:57:54,143 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-07-24 10:57:54,143 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 119 [2018-07-24 10:57:54,143 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:54,145 INFO L225 Difference]: With dead ends: 826 [2018-07-24 10:57:54,146 INFO L226 Difference]: Without dead ends: 773 [2018-07-24 10:57:54,146 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 535 GetRequests, 415 SyntacticMatches, 48 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2452 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1059, Invalid=4343, Unknown=0, NotChecked=0, Total=5402 [2018-07-24 10:57:54,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 773 states. [2018-07-24 10:57:54,389 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 773 to 157. [2018-07-24 10:57:54,389 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 157 states. [2018-07-24 10:57:54,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 170 transitions. [2018-07-24 10:57:54,390 INFO L78 Accepts]: Start accepts. Automaton has 157 states and 170 transitions. Word has length 119 [2018-07-24 10:57:54,390 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:54,390 INFO L471 AbstractCegarLoop]: Abstraction has 157 states and 170 transitions. [2018-07-24 10:57:54,390 INFO L472 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-07-24 10:57:54,390 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 170 transitions. [2018-07-24 10:57:54,390 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 122 [2018-07-24 10:57:54,391 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:54,391 INFO L353 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 11, 11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:54,391 INFO L414 AbstractCegarLoop]: === Iteration 78 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:54,391 INFO L82 PathProgramCache]: Analyzing trace with hash 777037143, now seen corresponding path program 20 times [2018-07-24 10:57:54,391 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:54,391 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:54,391 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:54,392 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:54,392 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:54,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:54,824 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 151 proven. 238 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-07-24 10:57:54,824 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:54,824 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 150 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 150 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:54,835 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:57:54,835 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:54,871 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:57:54,871 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:54,873 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:54,909 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 152 proven. 210 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:54,909 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:55,048 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 152 proven. 210 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:55,068 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:55,069 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 151 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 151 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:55,084 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:57:55,084 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:55,163 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:57:55,164 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:55,168 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:55,180 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 152 proven. 210 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:55,180 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:55,357 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 152 proven. 210 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:57:55,359 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:55,359 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 16, 16, 16, 16] total 19 [2018-07-24 10:57:55,359 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:55,359 INFO L450 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-07-24 10:57:55,359 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-07-24 10:57:55,360 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=103, Invalid=239, Unknown=0, NotChecked=0, Total=342 [2018-07-24 10:57:55,360 INFO L87 Difference]: Start difference. First operand 157 states and 170 transitions. Second operand 19 states. [2018-07-24 10:57:55,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:55,934 INFO L93 Difference]: Finished difference Result 167 states and 180 transitions. [2018-07-24 10:57:55,935 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-07-24 10:57:55,935 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 121 [2018-07-24 10:57:55,935 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:55,936 INFO L225 Difference]: With dead ends: 167 [2018-07-24 10:57:55,937 INFO L226 Difference]: Without dead ends: 165 [2018-07-24 10:57:55,937 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 513 GetRequests, 450 SyntacticMatches, 44 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 321 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=116, Invalid=304, Unknown=0, NotChecked=0, Total=420 [2018-07-24 10:57:55,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165 states. [2018-07-24 10:57:56,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165 to 165. [2018-07-24 10:57:56,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-07-24 10:57:56,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 178 transitions. [2018-07-24 10:57:56,199 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 178 transitions. Word has length 121 [2018-07-24 10:57:56,200 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:56,200 INFO L471 AbstractCegarLoop]: Abstraction has 165 states and 178 transitions. [2018-07-24 10:57:56,200 INFO L472 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-07-24 10:57:56,200 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 178 transitions. [2018-07-24 10:57:56,200 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-07-24 10:57:56,200 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:56,200 INFO L353 BasicCegarLoop]: trace histogram [12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:56,201 INFO L414 AbstractCegarLoop]: === Iteration 79 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:56,201 INFO L82 PathProgramCache]: Analyzing trace with hash -1277952389, now seen corresponding path program 21 times [2018-07-24 10:57:56,201 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:56,201 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:56,201 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:56,202 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:56,202 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:56,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:56,559 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:57:56,559 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:56,559 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 152 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 152 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:56,566 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:57:56,566 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:57:56,613 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-07-24 10:57:56,613 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:56,615 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:57,195 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:57:57,196 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:57,465 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:57:57,486 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:57,486 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 153 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 153 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:57,501 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:57:57,501 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:57:57,703 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-07-24 10:57:57,703 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:57,708 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:57,734 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:57:57,734 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:58,352 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:57:58,353 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:58,353 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 54 [2018-07-24 10:57:58,353 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:58,354 INFO L450 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-07-24 10:57:58,354 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-07-24 10:57:58,354 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=575, Invalid=2287, Unknown=0, NotChecked=0, Total=2862 [2018-07-24 10:57:58,354 INFO L87 Difference]: Start difference. First operand 165 states and 178 transitions. Second operand 54 states. [2018-07-24 10:58:00,229 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:00,230 INFO L93 Difference]: Finished difference Result 294 states and 332 transitions. [2018-07-24 10:58:00,230 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-07-24 10:58:00,230 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 129 [2018-07-24 10:58:00,230 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:00,231 INFO L225 Difference]: With dead ends: 294 [2018-07-24 10:58:00,231 INFO L226 Difference]: Without dead ends: 237 [2018-07-24 10:58:00,232 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 569 GetRequests, 439 SyntacticMatches, 52 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4047 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1225, Invalid=5095, Unknown=0, NotChecked=0, Total=6320 [2018-07-24 10:58:00,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 237 states. [2018-07-24 10:58:00,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 237 to 167. [2018-07-24 10:58:00,514 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-07-24 10:58:00,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 180 transitions. [2018-07-24 10:58:00,514 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 180 transitions. Word has length 129 [2018-07-24 10:58:00,514 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:00,514 INFO L471 AbstractCegarLoop]: Abstraction has 167 states and 180 transitions. [2018-07-24 10:58:00,514 INFO L472 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-07-24 10:58:00,514 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 180 transitions. [2018-07-24 10:58:00,515 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-07-24 10:58:00,515 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:00,515 INFO L353 BasicCegarLoop]: trace histogram [12, 12, 12, 12, 11, 11, 11, 11, 11, 10, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:00,515 INFO L414 AbstractCegarLoop]: === Iteration 80 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:00,516 INFO L82 PathProgramCache]: Analyzing trace with hash -1178325753, now seen corresponding path program 46 times [2018-07-24 10:58:00,516 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:00,516 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:00,516 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:00,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:00,517 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:00,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:00,883 INFO L134 CoverageAnalysis]: Checked inductivity of 607 backedges. 275 proven. 112 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:00,883 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:00,883 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 154 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 154 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:00,891 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:58:00,891 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:58:00,929 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:58:00,929 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:00,932 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:01,521 INFO L134 CoverageAnalysis]: Checked inductivity of 607 backedges. 275 proven. 112 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:01,522 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:01,795 INFO L134 CoverageAnalysis]: Checked inductivity of 607 backedges. 275 proven. 112 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:01,816 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:01,816 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 155 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 155 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:01,831 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:58:01,831 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:58:01,932 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:58:01,932 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:01,936 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:01,962 INFO L134 CoverageAnalysis]: Checked inductivity of 607 backedges. 275 proven. 112 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:01,962 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:02,249 INFO L134 CoverageAnalysis]: Checked inductivity of 607 backedges. 275 proven. 112 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:02,251 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:02,251 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 53 [2018-07-24 10:58:02,251 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:02,252 INFO L450 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-07-24 10:58:02,252 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-07-24 10:58:02,253 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=539, Invalid=2217, Unknown=0, NotChecked=0, Total=2756 [2018-07-24 10:58:02,253 INFO L87 Difference]: Start difference. First operand 167 states and 180 transitions. Second operand 53 states. [2018-07-24 10:58:04,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:04,815 INFO L93 Difference]: Finished difference Result 364 states and 415 transitions. [2018-07-24 10:58:04,816 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-07-24 10:58:04,816 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 129 [2018-07-24 10:58:04,816 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:04,817 INFO L225 Difference]: With dead ends: 364 [2018-07-24 10:58:04,817 INFO L226 Difference]: Without dead ends: 307 [2018-07-24 10:58:04,818 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 580 GetRequests, 440 SyntacticMatches, 52 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4508 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1485, Invalid=6525, Unknown=0, NotChecked=0, Total=8010 [2018-07-24 10:58:04,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 307 states. [2018-07-24 10:58:05,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 307 to 167. [2018-07-24 10:58:05,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-07-24 10:58:05,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 180 transitions. [2018-07-24 10:58:05,106 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 180 transitions. Word has length 129 [2018-07-24 10:58:05,106 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:05,106 INFO L471 AbstractCegarLoop]: Abstraction has 167 states and 180 transitions. [2018-07-24 10:58:05,106 INFO L472 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-07-24 10:58:05,106 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 180 transitions. [2018-07-24 10:58:05,107 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-07-24 10:58:05,107 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:05,107 INFO L353 BasicCegarLoop]: trace histogram [12, 12, 12, 12, 11, 11, 11, 11, 10, 9, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:05,107 INFO L414 AbstractCegarLoop]: === Iteration 81 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:05,107 INFO L82 PathProgramCache]: Analyzing trace with hash -154759533, now seen corresponding path program 47 times [2018-07-24 10:58:05,108 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:05,108 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:05,108 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:05,108 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:05,109 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:05,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:05,547 INFO L134 CoverageAnalysis]: Checked inductivity of 591 backedges. 275 proven. 96 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:05,548 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:05,548 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 156 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 156 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:05,555 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:58:05,555 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:05,598 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2018-07-24 10:58:05,599 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:05,601 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:06,149 INFO L134 CoverageAnalysis]: Checked inductivity of 591 backedges. 275 proven. 96 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:06,149 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:06,441 INFO L134 CoverageAnalysis]: Checked inductivity of 591 backedges. 275 proven. 96 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:06,463 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:06,463 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 157 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 157 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:06,477 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:58:06,478 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:06,665 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2018-07-24 10:58:06,666 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:06,671 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:06,696 INFO L134 CoverageAnalysis]: Checked inductivity of 591 backedges. 275 proven. 96 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:06,696 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:06,975 INFO L134 CoverageAnalysis]: Checked inductivity of 591 backedges. 275 proven. 96 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:06,976 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:06,976 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 52 [2018-07-24 10:58:06,976 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:06,977 INFO L450 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-07-24 10:58:06,977 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-07-24 10:58:06,977 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=507, Invalid=2145, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:58:06,977 INFO L87 Difference]: Start difference. First operand 167 states and 180 transitions. Second operand 52 states. [2018-07-24 10:58:10,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:10,016 INFO L93 Difference]: Finished difference Result 432 states and 496 transitions. [2018-07-24 10:58:10,017 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-07-24 10:58:10,017 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 129 [2018-07-24 10:58:10,017 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:10,018 INFO L225 Difference]: With dead ends: 432 [2018-07-24 10:58:10,018 INFO L226 Difference]: Without dead ends: 375 [2018-07-24 10:58:10,019 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 589 GetRequests, 441 SyntacticMatches, 52 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4938 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1729, Invalid=7777, Unknown=0, NotChecked=0, Total=9506 [2018-07-24 10:58:10,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 375 states. [2018-07-24 10:58:10,310 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 375 to 167. [2018-07-24 10:58:10,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-07-24 10:58:10,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 180 transitions. [2018-07-24 10:58:10,311 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 180 transitions. Word has length 129 [2018-07-24 10:58:10,311 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:10,311 INFO L471 AbstractCegarLoop]: Abstraction has 167 states and 180 transitions. [2018-07-24 10:58:10,311 INFO L472 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-07-24 10:58:10,311 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 180 transitions. [2018-07-24 10:58:10,311 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-07-24 10:58:10,311 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:10,312 INFO L353 BasicCegarLoop]: trace histogram [12, 12, 12, 12, 11, 11, 11, 11, 9, 8, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:10,312 INFO L414 AbstractCegarLoop]: === Iteration 82 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:10,312 INFO L82 PathProgramCache]: Analyzing trace with hash 1607197471, now seen corresponding path program 48 times [2018-07-24 10:58:10,312 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:10,312 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:10,313 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:10,313 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:10,313 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:10,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:10,624 INFO L134 CoverageAnalysis]: Checked inductivity of 579 backedges. 275 proven. 84 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:10,624 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:10,624 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 158 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 158 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:10,631 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:58:10,631 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:58:10,691 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 12 check-sat command(s) [2018-07-24 10:58:10,691 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:10,693 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:11,220 INFO L134 CoverageAnalysis]: Checked inductivity of 579 backedges. 275 proven. 84 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:11,220 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:11,478 INFO L134 CoverageAnalysis]: Checked inductivity of 579 backedges. 275 proven. 84 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:11,497 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:11,497 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 159 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 159 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:11,512 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:58:11,512 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:58:11,719 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 12 check-sat command(s) [2018-07-24 10:58:11,719 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:11,723 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:11,748 INFO L134 CoverageAnalysis]: Checked inductivity of 579 backedges. 275 proven. 84 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:11,748 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:12,030 INFO L134 CoverageAnalysis]: Checked inductivity of 579 backedges. 275 proven. 84 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:12,031 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:12,032 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 51 [2018-07-24 10:58:12,032 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:12,032 INFO L450 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-07-24 10:58:12,032 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-07-24 10:58:12,032 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=479, Invalid=2071, Unknown=0, NotChecked=0, Total=2550 [2018-07-24 10:58:12,033 INFO L87 Difference]: Start difference. First operand 167 states and 180 transitions. Second operand 51 states. [2018-07-24 10:58:15,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:15,454 INFO L93 Difference]: Finished difference Result 498 states and 575 transitions. [2018-07-24 10:58:15,454 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-07-24 10:58:15,454 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 129 [2018-07-24 10:58:15,454 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:15,456 INFO L225 Difference]: With dead ends: 498 [2018-07-24 10:58:15,456 INFO L226 Difference]: Without dead ends: 441 [2018-07-24 10:58:15,457 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 596 GetRequests, 442 SyntacticMatches, 52 SemanticMatches, 102 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5287 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1933, Invalid=8779, Unknown=0, NotChecked=0, Total=10712 [2018-07-24 10:58:15,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 441 states. [2018-07-24 10:58:15,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 441 to 167. [2018-07-24 10:58:15,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-07-24 10:58:15,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 180 transitions. [2018-07-24 10:58:15,773 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 180 transitions. Word has length 129 [2018-07-24 10:58:15,773 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:15,773 INFO L471 AbstractCegarLoop]: Abstraction has 167 states and 180 transitions. [2018-07-24 10:58:15,773 INFO L472 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-07-24 10:58:15,773 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 180 transitions. [2018-07-24 10:58:15,773 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-07-24 10:58:15,774 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:15,774 INFO L353 BasicCegarLoop]: trace histogram [12, 12, 12, 12, 11, 11, 11, 11, 8, 7, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:15,774 INFO L414 AbstractCegarLoop]: === Iteration 83 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:15,774 INFO L82 PathProgramCache]: Analyzing trace with hash -285939029, now seen corresponding path program 49 times [2018-07-24 10:58:15,774 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:15,774 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:15,775 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:15,775 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:15,775 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:15,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:16,167 INFO L134 CoverageAnalysis]: Checked inductivity of 571 backedges. 275 proven. 76 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:16,167 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:16,167 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 160 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 160 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:16,175 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:58:16,176 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:58:16,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:16,215 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:16,720 INFO L134 CoverageAnalysis]: Checked inductivity of 571 backedges. 275 proven. 76 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:16,720 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:16,981 INFO L134 CoverageAnalysis]: Checked inductivity of 571 backedges. 275 proven. 76 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:17,001 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:17,002 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 161 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 161 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:17,016 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:58:17,016 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:58:17,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:17,102 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:17,126 INFO L134 CoverageAnalysis]: Checked inductivity of 571 backedges. 275 proven. 76 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:17,127 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:17,407 INFO L134 CoverageAnalysis]: Checked inductivity of 571 backedges. 275 proven. 76 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:17,408 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:17,408 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 50 [2018-07-24 10:58:17,408 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:17,409 INFO L450 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-07-24 10:58:17,409 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-07-24 10:58:17,409 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=455, Invalid=1995, Unknown=0, NotChecked=0, Total=2450 [2018-07-24 10:58:17,409 INFO L87 Difference]: Start difference. First operand 167 states and 180 transitions. Second operand 50 states. [2018-07-24 10:58:21,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:21,250 INFO L93 Difference]: Finished difference Result 562 states and 652 transitions. [2018-07-24 10:58:21,250 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-07-24 10:58:21,250 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 129 [2018-07-24 10:58:21,250 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:21,252 INFO L225 Difference]: With dead ends: 562 [2018-07-24 10:58:21,252 INFO L226 Difference]: Without dead ends: 505 [2018-07-24 10:58:21,253 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 601 GetRequests, 443 SyntacticMatches, 52 SemanticMatches, 106 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5517 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=2079, Invalid=9477, Unknown=0, NotChecked=0, Total=11556 [2018-07-24 10:58:21,253 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 505 states. [2018-07-24 10:58:21,589 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 505 to 167. [2018-07-24 10:58:21,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-07-24 10:58:21,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 180 transitions. [2018-07-24 10:58:21,589 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 180 transitions. Word has length 129 [2018-07-24 10:58:21,590 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:21,590 INFO L471 AbstractCegarLoop]: Abstraction has 167 states and 180 transitions. [2018-07-24 10:58:21,590 INFO L472 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-07-24 10:58:21,590 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 180 transitions. [2018-07-24 10:58:21,590 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-07-24 10:58:21,591 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:21,591 INFO L353 BasicCegarLoop]: trace histogram [12, 12, 12, 12, 11, 11, 11, 11, 7, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:21,591 INFO L414 AbstractCegarLoop]: === Iteration 84 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:21,591 INFO L82 PathProgramCache]: Analyzing trace with hash 798123319, now seen corresponding path program 50 times [2018-07-24 10:58:21,591 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:21,592 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:21,592 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:58:21,592 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:21,592 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:21,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:21,911 INFO L134 CoverageAnalysis]: Checked inductivity of 567 backedges. 275 proven. 72 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:21,912 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:21,912 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 162 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 162 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:21,919 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:58:21,919 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:21,957 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:58:21,957 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:21,959 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:22,434 INFO L134 CoverageAnalysis]: Checked inductivity of 567 backedges. 275 proven. 72 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:22,434 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:22,706 INFO L134 CoverageAnalysis]: Checked inductivity of 567 backedges. 275 proven. 72 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:22,726 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:22,726 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 163 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 163 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:22,741 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:58:22,741 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:22,826 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:58:22,826 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:22,831 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:22,855 INFO L134 CoverageAnalysis]: Checked inductivity of 567 backedges. 275 proven. 72 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:22,855 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:23,127 INFO L134 CoverageAnalysis]: Checked inductivity of 567 backedges. 275 proven. 72 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:58:23,128 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:23,128 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 49 [2018-07-24 10:58:23,128 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:23,129 INFO L450 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-07-24 10:58:23,129 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-07-24 10:58:23,129 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=1917, Unknown=0, NotChecked=0, Total=2352 [2018-07-24 10:58:23,129 INFO L87 Difference]: Start difference. First operand 167 states and 180 transitions. Second operand 49 states. Received shutdown request... [2018-07-24 10:58:23,210 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-07-24 10:58:23,211 WARN L540 AbstractCegarLoop]: Verification canceled [2018-07-24 10:58:23,214 WARN L202 ceAbstractionStarter]: Timeout [2018-07-24 10:58:23,214 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.07 10:58:23 BoogieIcfgContainer [2018-07-24 10:58:23,214 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-07-24 10:58:23,215 INFO L168 Benchmark]: Toolchain (without parser) took 232066.76 ms. Allocated memory was 1.5 GB in the beginning and 2.2 GB in the end (delta: 698.4 MB). Free memory was 1.4 GB in the beginning and 1.7 GB in the end (delta: -238.9 MB). Peak memory consumption was 459.4 MB. Max. memory is 7.1 GB. [2018-07-24 10:58:23,216 INFO L168 Benchmark]: CDTParser took 0.21 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-24 10:58:23,216 INFO L168 Benchmark]: CACSL2BoogieTranslator took 292.58 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. [2018-07-24 10:58:23,216 INFO L168 Benchmark]: Boogie Procedure Inliner took 24.25 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-24 10:58:23,216 INFO L168 Benchmark]: Boogie Preprocessor took 33.91 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-24 10:58:23,217 INFO L168 Benchmark]: RCFGBuilder took 535.96 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 750.3 MB). Free memory was 1.4 GB in the beginning and 2.2 GB in the end (delta: -803.8 MB). Peak memory consumption was 27.1 MB. Max. memory is 7.1 GB. [2018-07-24 10:58:23,217 INFO L168 Benchmark]: TraceAbstraction took 231168.79 ms. Allocated memory was 2.3 GB in the beginning and 2.2 GB in the end (delta: -51.9 MB). Free memory was 2.2 GB in the beginning and 1.7 GB in the end (delta: 551.0 MB). Peak memory consumption was 499.1 MB. Max. memory is 7.1 GB. [2018-07-24 10:58:23,219 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 292.58 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 24.25 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Preprocessor took 33.91 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * RCFGBuilder took 535.96 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 750.3 MB). Free memory was 1.4 GB in the beginning and 2.2 GB in the end (delta: -803.8 MB). Peak memory consumption was 27.1 MB. Max. memory is 7.1 GB. * TraceAbstraction took 231168.79 ms. Allocated memory was 2.3 GB in the beginning and 2.2 GB in the end (delta: -51.9 MB). Free memory was 2.2 GB in the beginning and 1.7 GB in the end (delta: 551.0 MB). Peak memory consumption was 499.1 MB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 5]: Timeout (TraceAbstraction) Unable to prove that call of __VERIFIER_error() unreachable (line 5). Cancelled while BasicCegarLoop was constructing difference of abstraction (167states) and interpolant automaton (currently 8 states, 49 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 27 locations, 1 error locations. TIMEOUT Result, 231.1s OverallTime, 84 OverallIterations, 12 TraceHistogramMax, 108.3s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 3904 SDtfs, 9936 SDslu, 33895 SDs, 0 SdLazy, 30622 SolverSat, 6448 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 28.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 32342 GetRequests, 24895 SyntacticMatches, 2852 SemanticMatches, 4594 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 159436 ImplicationChecksByTransitivity, 123.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=167occurred in iteration=79, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 9.1s AutomataMinimizationTime, 83 MinimizatonAttempts, 14082 StatesRemovedByMinimization, 72 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.8s SsaConstructionTime, 9.2s SatisfiabilityAnalysisTime, 98.5s InterpolantComputationTime, 21564 NumberOfCodeBlocks, 21564 NumberOfCodeBlocksAsserted, 850 NumberOfCheckSat, 35494 ConstructedInterpolants, 0 QuantifiedInterpolants, 14039772 SizeOfPredicates, 1034 NumberOfNonLiveVariables, 30972 ConjunctsInSsa, 3256 ConjunctsInUnsatCore, 408 InterpolantComputations, 3 PerfectInterpolantSequences, 91807/113237 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/seq_true-unreach-call_true-termination.i_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-Benchmark-0-2018-07-24_10-58-23-227.csv Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/seq_true-unreach-call_true-termination.i_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-TraceAbstractionBenchmarks-0-2018-07-24_10-58-23-227.csv Completed graceful shutdown