java -Xmx8000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml --generate-csv --csv-dir csv -s ../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf -i ../../../trunk/examples/svcomp/loop-crafted/simple_array_index_value_true-unreach-call3_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-dd2f093 [2018-07-24 10:53:21,054 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-07-24 10:53:21,056 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-07-24 10:53:21,073 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-07-24 10:53:21,074 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-07-24 10:53:21,075 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-07-24 10:53:21,076 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-07-24 10:53:21,078 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-07-24 10:53:21,080 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-07-24 10:53:21,080 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-07-24 10:53:21,081 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-07-24 10:53:21,082 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-07-24 10:53:21,082 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-07-24 10:53:21,083 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-07-24 10:53:21,085 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-07-24 10:53:21,085 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-07-24 10:53:21,086 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-07-24 10:53:21,088 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-07-24 10:53:21,092 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-07-24 10:53:21,097 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-07-24 10:53:21,098 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-07-24 10:53:21,100 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-07-24 10:53:21,103 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-07-24 10:53:21,104 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-07-24 10:53:21,104 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-07-24 10:53:21,105 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-07-24 10:53:21,110 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-07-24 10:53:21,111 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-07-24 10:53:21,111 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-07-24 10:53:21,116 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-07-24 10:53:21,116 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-07-24 10:53:21,117 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... 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[2018-07-24 10:53:21,121 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf [2018-07-24 10:53:21,136 INFO L110 SettingsManager]: Loading preferences was successful [2018-07-24 10:53:21,137 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-07-24 10:53:21,137 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-07-24 10:53:21,138 INFO L133 SettingsManager]: * User list type=DISABLED [2018-07-24 10:53:21,138 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-07-24 10:53:21,138 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-07-24 10:53:21,138 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-07-24 10:53:21,138 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-07-24 10:53:21,139 INFO L133 SettingsManager]: * Log string format=TERM [2018-07-24 10:53:21,139 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-07-24 10:53:21,139 INFO L133 SettingsManager]: * Interval Domain=false [2018-07-24 10:53:21,140 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-07-24 10:53:21,140 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-07-24 10:53:21,140 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-07-24 10:53:21,140 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-07-24 10:53:21,140 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-07-24 10:53:21,141 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-07-24 10:53:21,141 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-07-24 10:53:21,141 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-07-24 10:53:21,141 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-07-24 10:53:21,141 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-07-24 10:53:21,142 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-07-24 10:53:21,142 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-07-24 10:53:21,142 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:53:21,142 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-07-24 10:53:21,142 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-07-24 10:53:21,142 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-07-24 10:53:21,143 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-07-24 10:53:21,143 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-07-24 10:53:21,143 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-07-24 10:53:21,143 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-07-24 10:53:21,143 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-07-24 10:53:21,144 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-07-24 10:53:21,192 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-07-24 10:53:21,206 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-07-24 10:53:21,211 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-07-24 10:53:21,213 INFO L271 PluginConnector]: Initializing CDTParser... [2018-07-24 10:53:21,213 INFO L276 PluginConnector]: CDTParser initialized [2018-07-24 10:53:21,214 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-crafted/simple_array_index_value_true-unreach-call3_true-termination.i [2018-07-24 10:53:21,601 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/65d6f6349/fc8508332a904606a727f262c34b2989/FLAG5da2a879a [2018-07-24 10:53:21,766 INFO L276 CDTParser]: Found 1 translation units. [2018-07-24 10:53:21,766 INFO L158 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-crafted/simple_array_index_value_true-unreach-call3_true-termination.i [2018-07-24 10:53:21,772 INFO L324 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/65d6f6349/fc8508332a904606a727f262c34b2989/FLAG5da2a879a [2018-07-24 10:53:21,788 INFO L332 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/65d6f6349/fc8508332a904606a727f262c34b2989 [2018-07-24 10:53:21,802 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-07-24 10:53:21,803 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-07-24 10:53:21,804 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-07-24 10:53:21,804 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-07-24 10:53:21,812 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-07-24 10:53:21,813 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:53:21" (1/1) ... [2018-07-24 10:53:21,817 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@40a20aca and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:21, skipping insertion in model container [2018-07-24 10:53:21,817 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:53:21" (1/1) ... [2018-07-24 10:53:21,970 INFO L179 PRDispatcher]: Starting pre-run dispatcher in SV-COMP mode [2018-07-24 10:53:22,011 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:53:22,027 INFO L422 MainDispatcher]: Starting main dispatcher in SV-COMP mode [2018-07-24 10:53:22,033 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:53:22,045 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:22 WrapperNode [2018-07-24 10:53:22,046 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-07-24 10:53:22,047 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-07-24 10:53:22,047 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-07-24 10:53:22,047 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-07-24 10:53:22,057 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:22" (1/1) ... [2018-07-24 10:53:22,064 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:22" (1/1) ... [2018-07-24 10:53:22,070 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-07-24 10:53:22,071 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-07-24 10:53:22,071 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-07-24 10:53:22,071 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-07-24 10:53:22,083 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:22" (1/1) ... [2018-07-24 10:53:22,083 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:22" (1/1) ... [2018-07-24 10:53:22,084 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:22" (1/1) ... [2018-07-24 10:53:22,084 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:22" (1/1) ... [2018-07-24 10:53:22,086 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:22" (1/1) ... [2018-07-24 10:53:22,095 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:22" (1/1) ... [2018-07-24 10:53:22,096 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:22" (1/1) ... [2018-07-24 10:53:22,097 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-07-24 10:53:22,098 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-07-24 10:53:22,098 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-07-24 10:53:22,098 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-07-24 10:53:22,099 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:22" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:53:22,159 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-07-24 10:53:22,159 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-07-24 10:53:22,159 INFO L130 BoogieDeclarations]: Found specification of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assert [2018-07-24 10:53:22,159 INFO L138 BoogieDeclarations]: Found implementation of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assert [2018-07-24 10:53:22,160 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-07-24 10:53:22,160 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-07-24 10:53:22,160 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-07-24 10:53:22,160 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-07-24 10:53:22,459 INFO L261 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-07-24 10:53:22,460 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:53:22 BoogieIcfgContainer [2018-07-24 10:53:22,461 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-07-24 10:53:22,463 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-07-24 10:53:22,463 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-07-24 10:53:22,467 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-07-24 10:53:22,467 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.07 10:53:21" (1/3) ... [2018-07-24 10:53:22,468 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@70d72950 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:53:22, skipping insertion in model container [2018-07-24 10:53:22,468 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:22" (2/3) ... [2018-07-24 10:53:22,469 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@70d72950 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:53:22, skipping insertion in model container [2018-07-24 10:53:22,469 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:53:22" (3/3) ... [2018-07-24 10:53:22,470 INFO L112 eAbstractionObserver]: Analyzing ICFG simple_array_index_value_true-unreach-call3_true-termination.i [2018-07-24 10:53:22,482 INFO L132 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-07-24 10:53:22,491 INFO L144 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-07-24 10:53:22,549 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-07-24 10:53:22,550 INFO L373 AbstractCegarLoop]: Interprodecural is true [2018-07-24 10:53:22,550 INFO L374 AbstractCegarLoop]: Hoare is true [2018-07-24 10:53:22,551 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-07-24 10:53:22,551 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-07-24 10:53:22,551 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-07-24 10:53:22,551 INFO L378 AbstractCegarLoop]: Difference is false [2018-07-24 10:53:22,551 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-07-24 10:53:22,551 INFO L384 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-07-24 10:53:22,571 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states. [2018-07-24 10:53:22,578 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-07-24 10:53:22,578 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:22,579 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:22,579 INFO L414 AbstractCegarLoop]: === Iteration 1 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:22,585 INFO L82 PathProgramCache]: Analyzing trace with hash -1098901645, now seen corresponding path program 1 times [2018-07-24 10:53:22,587 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:22,644 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:22,644 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:53:22,644 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:22,645 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:22,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:22,701 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:22,704 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:53:22,704 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-07-24 10:53:22,704 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:53:22,708 INFO L450 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-07-24 10:53:22,721 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-07-24 10:53:22,721 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:53:22,724 INFO L87 Difference]: Start difference. First operand 22 states. Second operand 2 states. [2018-07-24 10:53:22,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:22,745 INFO L93 Difference]: Finished difference Result 37 states and 44 transitions. [2018-07-24 10:53:22,745 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-07-24 10:53:22,747 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 13 [2018-07-24 10:53:22,747 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:22,755 INFO L225 Difference]: With dead ends: 37 [2018-07-24 10:53:22,756 INFO L226 Difference]: Without dead ends: 18 [2018-07-24 10:53:22,759 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:53:22,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states. [2018-07-24 10:53:22,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 18. [2018-07-24 10:53:22,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2018-07-24 10:53:22,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 19 transitions. [2018-07-24 10:53:22,796 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 19 transitions. Word has length 13 [2018-07-24 10:53:22,797 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:22,797 INFO L471 AbstractCegarLoop]: Abstraction has 18 states and 19 transitions. [2018-07-24 10:53:22,797 INFO L472 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-07-24 10:53:22,797 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 19 transitions. [2018-07-24 10:53:22,798 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-07-24 10:53:22,798 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:22,798 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:22,799 INFO L414 AbstractCegarLoop]: === Iteration 2 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:22,799 INFO L82 PathProgramCache]: Analyzing trace with hash 593775156, now seen corresponding path program 1 times [2018-07-24 10:53:22,799 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:22,801 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:22,801 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:53:22,801 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:22,801 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:22,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:22,875 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:22,875 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:53:22,875 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-07-24 10:53:22,875 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:53:22,877 INFO L450 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-07-24 10:53:22,878 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-07-24 10:53:22,878 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 10:53:22,878 INFO L87 Difference]: Start difference. First operand 18 states and 19 transitions. Second operand 3 states. [2018-07-24 10:53:22,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:22,958 INFO L93 Difference]: Finished difference Result 35 states and 38 transitions. [2018-07-24 10:53:22,960 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-07-24 10:53:22,960 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 14 [2018-07-24 10:53:22,960 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:22,963 INFO L225 Difference]: With dead ends: 35 [2018-07-24 10:53:22,963 INFO L226 Difference]: Without dead ends: 24 [2018-07-24 10:53:22,964 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 10:53:22,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states. [2018-07-24 10:53:22,975 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 20. [2018-07-24 10:53:22,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2018-07-24 10:53:22,976 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 21 transitions. [2018-07-24 10:53:22,976 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 21 transitions. Word has length 14 [2018-07-24 10:53:22,977 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:22,977 INFO L471 AbstractCegarLoop]: Abstraction has 20 states and 21 transitions. [2018-07-24 10:53:22,977 INFO L472 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-07-24 10:53:22,977 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 21 transitions. [2018-07-24 10:53:22,978 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-07-24 10:53:22,978 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:22,978 INFO L353 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:22,978 INFO L414 AbstractCegarLoop]: === Iteration 3 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:22,979 INFO L82 PathProgramCache]: Analyzing trace with hash -208069298, now seen corresponding path program 1 times [2018-07-24 10:53:22,979 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:22,980 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:22,980 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:53:22,980 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:22,980 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:22,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:23,103 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:23,104 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:23,104 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:23,120 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:53:23,121 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:53:23,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:23,158 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:23,250 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-07-24 10:53:23,252 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-07-24 10:53:23,268 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-07-24 10:53:23,268 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-07-24 10:53:23,487 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:23,487 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:23,895 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 5 [2018-07-24 10:53:23,896 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-07-24 10:53:23,904 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-07-24 10:53:23,905 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-07-24 10:53:23,950 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:23,972 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:23,972 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:53:23,991 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:53:23,991 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:53:24,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:24,013 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:24,035 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:24,035 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:24,260 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:24,262 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:53:24,262 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 7, 7, 4, 4] total 16 [2018-07-24 10:53:24,262 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:53:24,263 INFO L450 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-07-24 10:53:24,263 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-07-24 10:53:24,264 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=192, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:53:24,264 INFO L87 Difference]: Start difference. First operand 20 states and 21 transitions. Second operand 9 states. [2018-07-24 10:53:24,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:24,514 INFO L93 Difference]: Finished difference Result 60 states and 68 transitions. [2018-07-24 10:53:24,515 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-07-24 10:53:24,516 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 16 [2018-07-24 10:53:24,516 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:24,517 INFO L225 Difference]: With dead ends: 60 [2018-07-24 10:53:24,518 INFO L226 Difference]: Without dead ends: 49 [2018-07-24 10:53:24,519 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 51 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 46 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=61, Invalid=245, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:53:24,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-07-24 10:53:24,528 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 32. [2018-07-24 10:53:24,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32 states. [2018-07-24 10:53:24,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 34 transitions. [2018-07-24 10:53:24,529 INFO L78 Accepts]: Start accepts. Automaton has 32 states and 34 transitions. Word has length 16 [2018-07-24 10:53:24,529 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:24,530 INFO L471 AbstractCegarLoop]: Abstraction has 32 states and 34 transitions. [2018-07-24 10:53:24,530 INFO L472 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-07-24 10:53:24,530 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 34 transitions. [2018-07-24 10:53:24,531 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-07-24 10:53:24,531 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:24,531 INFO L353 BasicCegarLoop]: trace histogram [4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:24,531 INFO L414 AbstractCegarLoop]: === Iteration 4 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:24,532 INFO L82 PathProgramCache]: Analyzing trace with hash -1092139006, now seen corresponding path program 2 times [2018-07-24 10:53:24,532 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:24,533 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:24,533 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:53:24,533 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:24,533 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:24,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:25,005 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:25,006 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:25,006 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:25,025 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:53:25,025 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:53:25,041 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:53:25,041 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:25,043 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:25,073 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:25,074 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:25,195 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:25,216 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:25,216 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:53:25,233 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:53:25,233 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:53:25,263 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:53:25,263 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:25,267 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:25,284 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:25,284 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:25,298 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:25,300 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:53:25,300 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 10 [2018-07-24 10:53:25,300 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:53:25,301 INFO L450 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-07-24 10:53:25,301 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-07-24 10:53:25,301 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-07-24 10:53:25,302 INFO L87 Difference]: Start difference. First operand 32 states and 34 transitions. Second operand 6 states. [2018-07-24 10:53:25,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:25,479 INFO L93 Difference]: Finished difference Result 61 states and 68 transitions. [2018-07-24 10:53:25,480 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-07-24 10:53:25,480 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 20 [2018-07-24 10:53:25,481 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:25,482 INFO L225 Difference]: With dead ends: 61 [2018-07-24 10:53:25,482 INFO L226 Difference]: Without dead ends: 42 [2018-07-24 10:53:25,483 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 74 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-07-24 10:53:25,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states. [2018-07-24 10:53:25,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 26. [2018-07-24 10:53:25,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2018-07-24 10:53:25,489 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 27 transitions. [2018-07-24 10:53:25,489 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 27 transitions. Word has length 20 [2018-07-24 10:53:25,489 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:25,489 INFO L471 AbstractCegarLoop]: Abstraction has 26 states and 27 transitions. [2018-07-24 10:53:25,489 INFO L472 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-07-24 10:53:25,490 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 27 transitions. [2018-07-24 10:53:25,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-07-24 10:53:25,491 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:25,491 INFO L353 BasicCegarLoop]: trace histogram [5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:25,491 INFO L414 AbstractCegarLoop]: === Iteration 5 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:25,491 INFO L82 PathProgramCache]: Analyzing trace with hash -1168908388, now seen corresponding path program 3 times [2018-07-24 10:53:25,491 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:25,492 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:25,493 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:53:25,493 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:25,493 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:25,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:25,629 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:25,629 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:25,629 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:25,639 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:53:25,639 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:53:25,660 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2018-07-24 10:53:25,660 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:25,663 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:25,693 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:25,693 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:25,813 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:25,833 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:25,833 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:53:25,852 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:53:25,852 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:53:25,927 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2018-07-24 10:53:25,927 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:25,931 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:25,944 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:25,944 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:25,959 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:25,968 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:53:25,969 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 12 [2018-07-24 10:53:25,969 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:53:25,970 INFO L450 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-07-24 10:53:25,970 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-07-24 10:53:25,970 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:53:25,971 INFO L87 Difference]: Start difference. First operand 26 states and 27 transitions. Second operand 7 states. [2018-07-24 10:53:26,219 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:26,220 INFO L93 Difference]: Finished difference Result 59 states and 66 transitions. [2018-07-24 10:53:26,220 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-07-24 10:53:26,221 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 22 [2018-07-24 10:53:26,221 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:26,222 INFO L225 Difference]: With dead ends: 59 [2018-07-24 10:53:26,222 INFO L226 Difference]: Without dead ends: 48 [2018-07-24 10:53:26,223 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 81 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:53:26,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states. [2018-07-24 10:53:26,228 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 28. [2018-07-24 10:53:26,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28 states. [2018-07-24 10:53:26,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 29 transitions. [2018-07-24 10:53:26,229 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 29 transitions. Word has length 22 [2018-07-24 10:53:26,230 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:26,230 INFO L471 AbstractCegarLoop]: Abstraction has 28 states and 29 transitions. [2018-07-24 10:53:26,230 INFO L472 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-07-24 10:53:26,230 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 29 transitions. [2018-07-24 10:53:26,231 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-07-24 10:53:26,231 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:26,231 INFO L353 BasicCegarLoop]: trace histogram [6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:26,231 INFO L414 AbstractCegarLoop]: === Iteration 6 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:26,231 INFO L82 PathProgramCache]: Analyzing trace with hash -1929840458, now seen corresponding path program 4 times [2018-07-24 10:53:26,232 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:26,232 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:26,233 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:53:26,233 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:26,233 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:26,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:26,396 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:26,397 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:26,397 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:26,407 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:53:26,408 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:53:26,437 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:53:26,437 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:26,439 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:26,453 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:26,453 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:26,628 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:26,651 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:26,651 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:53:26,667 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:53:26,667 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:53:26,704 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:53:26,705 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:26,708 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:26,737 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:26,737 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:26,787 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:26,792 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:53:26,792 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 14 [2018-07-24 10:53:26,792 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:53:26,793 INFO L450 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-07-24 10:53:26,793 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-07-24 10:53:26,793 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:53:26,793 INFO L87 Difference]: Start difference. First operand 28 states and 29 transitions. Second operand 8 states. [2018-07-24 10:53:27,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:27,141 INFO L93 Difference]: Finished difference Result 65 states and 73 transitions. [2018-07-24 10:53:27,142 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-07-24 10:53:27,142 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 24 [2018-07-24 10:53:27,143 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:27,144 INFO L225 Difference]: With dead ends: 65 [2018-07-24 10:53:27,144 INFO L226 Difference]: Without dead ends: 54 [2018-07-24 10:53:27,145 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 102 GetRequests, 88 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:53:27,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-07-24 10:53:27,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 30. [2018-07-24 10:53:27,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-07-24 10:53:27,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 31 transitions. [2018-07-24 10:53:27,153 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 31 transitions. Word has length 24 [2018-07-24 10:53:27,153 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:27,153 INFO L471 AbstractCegarLoop]: Abstraction has 30 states and 31 transitions. [2018-07-24 10:53:27,154 INFO L472 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-07-24 10:53:27,154 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 31 transitions. [2018-07-24 10:53:27,154 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-07-24 10:53:27,155 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:27,155 INFO L353 BasicCegarLoop]: trace histogram [7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:27,155 INFO L414 AbstractCegarLoop]: === Iteration 7 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:27,155 INFO L82 PathProgramCache]: Analyzing trace with hash 1253847888, now seen corresponding path program 5 times [2018-07-24 10:53:27,155 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:27,156 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:27,157 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:53:27,157 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:27,157 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:27,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:27,327 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:27,327 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:27,327 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:27,339 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:53:27,339 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:53:27,370 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-07-24 10:53:27,370 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:27,372 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:27,389 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:27,389 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:27,736 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:27,757 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:27,757 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:53:27,773 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:53:27,773 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:53:27,889 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-07-24 10:53:27,889 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:27,894 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:27,918 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:27,918 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:27,933 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:27,934 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:53:27,935 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 16 [2018-07-24 10:53:27,935 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:53:27,936 INFO L450 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-07-24 10:53:27,937 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-07-24 10:53:27,937 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:53:27,938 INFO L87 Difference]: Start difference. First operand 30 states and 31 transitions. Second operand 9 states. [2018-07-24 10:53:28,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:28,166 INFO L93 Difference]: Finished difference Result 71 states and 80 transitions. [2018-07-24 10:53:28,167 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-07-24 10:53:28,168 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 26 [2018-07-24 10:53:28,168 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:28,169 INFO L225 Difference]: With dead ends: 71 [2018-07-24 10:53:28,169 INFO L226 Difference]: Without dead ends: 60 [2018-07-24 10:53:28,170 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 111 GetRequests, 95 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:53:28,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2018-07-24 10:53:28,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 32. [2018-07-24 10:53:28,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32 states. [2018-07-24 10:53:28,176 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 33 transitions. [2018-07-24 10:53:28,177 INFO L78 Accepts]: Start accepts. Automaton has 32 states and 33 transitions. Word has length 26 [2018-07-24 10:53:28,177 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:28,177 INFO L471 AbstractCegarLoop]: Abstraction has 32 states and 33 transitions. [2018-07-24 10:53:28,177 INFO L472 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-07-24 10:53:28,177 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 33 transitions. [2018-07-24 10:53:28,178 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-07-24 10:53:28,178 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:28,178 INFO L353 BasicCegarLoop]: trace histogram [8, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:28,179 INFO L414 AbstractCegarLoop]: === Iteration 8 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:28,179 INFO L82 PathProgramCache]: Analyzing trace with hash -1533333654, now seen corresponding path program 6 times [2018-07-24 10:53:28,179 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:28,180 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:28,180 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:53:28,180 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:28,181 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:28,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:28,406 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:28,407 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:28,407 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:28,415 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:53:28,415 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:53:28,476 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-07-24 10:53:28,476 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:28,478 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:28,502 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:28,503 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:28,699 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:28,722 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:28,722 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:53:28,737 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:53:28,737 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:53:28,938 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-07-24 10:53:28,939 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:28,945 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:28,964 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:28,965 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:29,022 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:29,025 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:53:29,025 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 18 [2018-07-24 10:53:29,025 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:53:29,026 INFO L450 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-07-24 10:53:29,028 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-07-24 10:53:29,029 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:53:29,029 INFO L87 Difference]: Start difference. First operand 32 states and 33 transitions. Second operand 10 states. [2018-07-24 10:53:29,476 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:29,477 INFO L93 Difference]: Finished difference Result 77 states and 87 transitions. [2018-07-24 10:53:29,478 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-07-24 10:53:29,478 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 28 [2018-07-24 10:53:29,478 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:29,479 INFO L225 Difference]: With dead ends: 77 [2018-07-24 10:53:29,480 INFO L226 Difference]: Without dead ends: 66 [2018-07-24 10:53:29,480 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 120 GetRequests, 102 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:53:29,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2018-07-24 10:53:29,485 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 34. [2018-07-24 10:53:29,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34 states. [2018-07-24 10:53:29,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 35 transitions. [2018-07-24 10:53:29,487 INFO L78 Accepts]: Start accepts. Automaton has 34 states and 35 transitions. Word has length 28 [2018-07-24 10:53:29,487 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:29,487 INFO L471 AbstractCegarLoop]: Abstraction has 34 states and 35 transitions. [2018-07-24 10:53:29,487 INFO L472 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-07-24 10:53:29,487 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 35 transitions. [2018-07-24 10:53:29,488 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-07-24 10:53:29,488 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:29,488 INFO L353 BasicCegarLoop]: trace histogram [9, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:29,489 INFO L414 AbstractCegarLoop]: === Iteration 9 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:29,489 INFO L82 PathProgramCache]: Analyzing trace with hash 44797188, now seen corresponding path program 7 times [2018-07-24 10:53:29,489 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:29,490 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:29,490 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:53:29,490 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:29,490 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:29,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:29,686 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:29,687 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:29,687 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:29,695 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:53:29,695 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:53:29,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:29,719 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:29,773 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:29,773 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:30,397 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:30,418 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:30,419 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:53:30,434 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:53:30,434 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:53:30,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:30,487 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:30,519 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:30,520 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:30,565 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:30,567 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:53:30,568 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 20 [2018-07-24 10:53:30,568 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:53:30,569 INFO L450 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-07-24 10:53:30,569 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-07-24 10:53:30,569 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:53:30,570 INFO L87 Difference]: Start difference. First operand 34 states and 35 transitions. Second operand 11 states. [2018-07-24 10:53:31,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:31,059 INFO L93 Difference]: Finished difference Result 83 states and 94 transitions. [2018-07-24 10:53:31,062 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-07-24 10:53:31,063 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 30 [2018-07-24 10:53:31,063 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:31,064 INFO L225 Difference]: With dead ends: 83 [2018-07-24 10:53:31,064 INFO L226 Difference]: Without dead ends: 72 [2018-07-24 10:53:31,065 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 129 GetRequests, 109 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:53:31,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states. [2018-07-24 10:53:31,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 36. [2018-07-24 10:53:31,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2018-07-24 10:53:31,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 37 transitions. [2018-07-24 10:53:31,072 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 37 transitions. Word has length 30 [2018-07-24 10:53:31,072 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:31,072 INFO L471 AbstractCegarLoop]: Abstraction has 36 states and 37 transitions. [2018-07-24 10:53:31,073 INFO L472 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-07-24 10:53:31,073 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 37 transitions. [2018-07-24 10:53:31,073 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-07-24 10:53:31,074 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:31,074 INFO L353 BasicCegarLoop]: trace histogram [10, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:31,074 INFO L414 AbstractCegarLoop]: === Iteration 10 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:31,074 INFO L82 PathProgramCache]: Analyzing trace with hash 505080862, now seen corresponding path program 8 times [2018-07-24 10:53:31,074 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:31,075 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:31,075 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:53:31,076 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:31,076 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:31,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:31,325 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:31,326 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:31,326 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:31,334 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:53:31,335 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:53:31,380 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:53:31,381 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:31,383 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:31,454 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:31,455 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:32,004 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:32,025 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:32,025 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:53:32,041 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:53:32,041 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:53:32,099 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:53:32,099 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:32,103 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:32,119 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:32,119 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:32,126 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:32,127 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:53:32,128 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 22 [2018-07-24 10:53:32,128 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:53:32,128 INFO L450 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-07-24 10:53:32,129 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-07-24 10:53:32,129 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-07-24 10:53:32,130 INFO L87 Difference]: Start difference. First operand 36 states and 37 transitions. Second operand 12 states. [2018-07-24 10:53:32,706 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:32,707 INFO L93 Difference]: Finished difference Result 89 states and 101 transitions. [2018-07-24 10:53:32,707 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-07-24 10:53:32,707 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 32 [2018-07-24 10:53:32,708 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:32,709 INFO L225 Difference]: With dead ends: 89 [2018-07-24 10:53:32,709 INFO L226 Difference]: Without dead ends: 78 [2018-07-24 10:53:32,710 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 138 GetRequests, 116 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-07-24 10:53:32,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states. [2018-07-24 10:53:32,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 38. [2018-07-24 10:53:32,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2018-07-24 10:53:32,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 39 transitions. [2018-07-24 10:53:32,718 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 39 transitions. Word has length 32 [2018-07-24 10:53:32,719 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:32,719 INFO L471 AbstractCegarLoop]: Abstraction has 38 states and 39 transitions. [2018-07-24 10:53:32,719 INFO L472 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-07-24 10:53:32,719 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 39 transitions. [2018-07-24 10:53:32,720 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-07-24 10:53:32,720 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:32,720 INFO L353 BasicCegarLoop]: trace histogram [11, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:32,720 INFO L414 AbstractCegarLoop]: === Iteration 11 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:32,720 INFO L82 PathProgramCache]: Analyzing trace with hash 456060088, now seen corresponding path program 9 times [2018-07-24 10:53:32,720 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:32,721 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:32,721 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:53:32,721 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:32,722 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:32,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:33,123 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:33,123 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:33,123 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:33,132 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:53:33,132 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:53:33,241 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-07-24 10:53:33,241 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:33,244 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:33,273 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:33,275 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:33,766 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:33,786 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:33,787 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:53:33,801 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:53:33,802 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:53:47,198 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-07-24 10:53:47,198 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:47,202 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:47,213 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:47,213 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:47,229 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:47,231 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:53:47,231 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 24 [2018-07-24 10:53:47,231 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:53:47,232 INFO L450 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-07-24 10:53:47,232 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-07-24 10:53:47,233 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-07-24 10:53:47,234 INFO L87 Difference]: Start difference. First operand 38 states and 39 transitions. Second operand 13 states. [2018-07-24 10:53:47,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:47,973 INFO L93 Difference]: Finished difference Result 95 states and 108 transitions. [2018-07-24 10:53:47,973 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-07-24 10:53:47,973 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 34 [2018-07-24 10:53:47,974 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:47,975 INFO L225 Difference]: With dead ends: 95 [2018-07-24 10:53:47,975 INFO L226 Difference]: Without dead ends: 84 [2018-07-24 10:53:47,976 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 147 GetRequests, 123 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-07-24 10:53:47,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2018-07-24 10:53:47,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 40. [2018-07-24 10:53:47,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40 states. [2018-07-24 10:53:47,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 41 transitions. [2018-07-24 10:53:47,986 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 41 transitions. Word has length 34 [2018-07-24 10:53:47,987 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:47,987 INFO L471 AbstractCegarLoop]: Abstraction has 40 states and 41 transitions. [2018-07-24 10:53:47,987 INFO L472 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-07-24 10:53:47,987 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 41 transitions. [2018-07-24 10:53:47,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-07-24 10:53:47,988 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:47,988 INFO L353 BasicCegarLoop]: trace histogram [12, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:47,989 INFO L414 AbstractCegarLoop]: === Iteration 12 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:47,989 INFO L82 PathProgramCache]: Analyzing trace with hash 591736530, now seen corresponding path program 10 times [2018-07-24 10:53:47,989 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:47,990 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:47,990 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:53:47,990 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:47,990 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:48,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:48,228 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:48,229 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:48,229 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:48,248 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:53:48,248 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:53:48,275 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:53:48,275 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:48,277 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:48,303 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:48,303 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:48,672 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:48,693 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:48,693 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:53:48,708 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:53:48,708 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:53:48,828 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:53:48,828 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:48,833 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:48,852 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:48,853 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:48,905 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:48,908 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:53:48,909 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 26 [2018-07-24 10:53:48,909 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:53:48,909 INFO L450 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-07-24 10:53:48,910 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-07-24 10:53:48,910 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:53:48,910 INFO L87 Difference]: Start difference. First operand 40 states and 41 transitions. Second operand 14 states. [2018-07-24 10:53:49,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:49,527 INFO L93 Difference]: Finished difference Result 101 states and 115 transitions. [2018-07-24 10:53:49,529 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-07-24 10:53:49,529 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 36 [2018-07-24 10:53:49,530 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:49,530 INFO L225 Difference]: With dead ends: 101 [2018-07-24 10:53:49,530 INFO L226 Difference]: Without dead ends: 90 [2018-07-24 10:53:49,531 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 130 SyntacticMatches, 2 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:53:49,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states. [2018-07-24 10:53:49,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 42. [2018-07-24 10:53:49,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2018-07-24 10:53:49,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 43 transitions. [2018-07-24 10:53:49,538 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 43 transitions. Word has length 36 [2018-07-24 10:53:49,538 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:49,538 INFO L471 AbstractCegarLoop]: Abstraction has 42 states and 43 transitions. [2018-07-24 10:53:49,538 INFO L472 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-07-24 10:53:49,538 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 43 transitions. [2018-07-24 10:53:49,539 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-07-24 10:53:49,539 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:49,539 INFO L353 BasicCegarLoop]: trace histogram [13, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:49,539 INFO L414 AbstractCegarLoop]: === Iteration 13 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:49,539 INFO L82 PathProgramCache]: Analyzing trace with hash 2127778412, now seen corresponding path program 11 times [2018-07-24 10:53:49,539 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:49,540 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:49,540 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:53:49,540 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:49,541 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:49,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:49,858 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:49,859 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:49,859 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:49,867 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:53:49,867 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:53:49,965 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2018-07-24 10:53:49,965 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:49,967 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:49,978 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:49,978 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:50,430 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:50,450 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:50,450 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:53:50,464 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:53:50,464 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:53:51,548 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2018-07-24 10:53:51,548 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:51,561 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:51,568 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:51,569 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:51,582 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:51,583 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:53:51,584 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 28 [2018-07-24 10:53:51,584 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:53:51,584 INFO L450 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-07-24 10:53:51,584 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-07-24 10:53:51,585 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:53:51,585 INFO L87 Difference]: Start difference. First operand 42 states and 43 transitions. Second operand 15 states. [2018-07-24 10:53:52,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:52,555 INFO L93 Difference]: Finished difference Result 107 states and 122 transitions. [2018-07-24 10:53:52,556 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-07-24 10:53:52,556 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 38 [2018-07-24 10:53:52,557 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:52,558 INFO L225 Difference]: With dead ends: 107 [2018-07-24 10:53:52,558 INFO L226 Difference]: Without dead ends: 96 [2018-07-24 10:53:52,560 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 165 GetRequests, 137 SyntacticMatches, 2 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:53:52,560 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-07-24 10:53:52,565 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 44. [2018-07-24 10:53:52,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2018-07-24 10:53:52,566 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 45 transitions. [2018-07-24 10:53:52,566 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 45 transitions. Word has length 38 [2018-07-24 10:53:52,567 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:52,567 INFO L471 AbstractCegarLoop]: Abstraction has 44 states and 45 transitions. [2018-07-24 10:53:52,567 INFO L472 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-07-24 10:53:52,567 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 45 transitions. [2018-07-24 10:53:52,568 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-07-24 10:53:52,568 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:52,568 INFO L353 BasicCegarLoop]: trace histogram [14, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:52,568 INFO L414 AbstractCegarLoop]: === Iteration 14 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:52,568 INFO L82 PathProgramCache]: Analyzing trace with hash 795277190, now seen corresponding path program 12 times [2018-07-24 10:53:52,569 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:52,569 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:52,570 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:53:52,570 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:52,570 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:52,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:53,293 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:53,293 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:53,293 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:53,300 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:53:53,300 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:53:53,733 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 14 check-sat command(s) [2018-07-24 10:53:53,734 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:53,736 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:53,750 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:53,750 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:54,334 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:54,354 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:54,355 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:53:54,369 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:53:54,370 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:54:09,198 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 14 check-sat command(s) [2018-07-24 10:54:09,198 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:09,215 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:09,228 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:09,228 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:09,237 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:09,239 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:09,239 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 30 [2018-07-24 10:54:09,239 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:09,240 INFO L450 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-07-24 10:54:09,240 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-07-24 10:54:09,241 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:54:09,241 INFO L87 Difference]: Start difference. First operand 44 states and 45 transitions. Second operand 16 states. [2018-07-24 10:54:09,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:09,914 INFO L93 Difference]: Finished difference Result 113 states and 129 transitions. [2018-07-24 10:54:09,917 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-07-24 10:54:09,917 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 40 [2018-07-24 10:54:09,917 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:09,918 INFO L225 Difference]: With dead ends: 113 [2018-07-24 10:54:09,918 INFO L226 Difference]: Without dead ends: 102 [2018-07-24 10:54:09,919 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 174 GetRequests, 144 SyntacticMatches, 2 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:54:09,919 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states. [2018-07-24 10:54:09,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 46. [2018-07-24 10:54:09,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-07-24 10:54:09,925 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 47 transitions. [2018-07-24 10:54:09,925 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 47 transitions. Word has length 40 [2018-07-24 10:54:09,926 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:09,926 INFO L471 AbstractCegarLoop]: Abstraction has 46 states and 47 transitions. [2018-07-24 10:54:09,926 INFO L472 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-07-24 10:54:09,926 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 47 transitions. [2018-07-24 10:54:09,927 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-07-24 10:54:09,927 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:09,927 INFO L353 BasicCegarLoop]: trace histogram [15, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:09,927 INFO L414 AbstractCegarLoop]: === Iteration 15 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:09,927 INFO L82 PathProgramCache]: Analyzing trace with hash 161857056, now seen corresponding path program 13 times [2018-07-24 10:54:09,928 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:09,928 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:09,928 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:09,929 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:09,929 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:09,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:10,250 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:10,250 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:10,250 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:10,259 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:10,259 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:10,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:10,279 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:10,306 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:10,306 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:11,001 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:11,020 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:11,021 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:11,035 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:11,035 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:11,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:11,137 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:11,154 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:11,155 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:11,166 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (27)] Exception during sending of exit command (exit): Broken pipe [2018-07-24 10:54:11,172 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:11,173 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 32 [2018-07-24 10:54:11,173 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:11,173 INFO L450 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-07-24 10:54:11,174 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-07-24 10:54:11,174 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:54:11,174 INFO L87 Difference]: Start difference. First operand 46 states and 47 transitions. Second operand 17 states. [2018-07-24 10:54:12,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:12,072 INFO L93 Difference]: Finished difference Result 119 states and 136 transitions. [2018-07-24 10:54:12,073 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-07-24 10:54:12,073 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 42 [2018-07-24 10:54:12,073 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:12,074 INFO L225 Difference]: With dead ends: 119 [2018-07-24 10:54:12,074 INFO L226 Difference]: Without dead ends: 108 [2018-07-24 10:54:12,075 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 183 GetRequests, 151 SyntacticMatches, 2 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:54:12,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108 states. [2018-07-24 10:54:12,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108 to 48. [2018-07-24 10:54:12,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-07-24 10:54:12,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 49 transitions. [2018-07-24 10:54:12,081 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 49 transitions. Word has length 42 [2018-07-24 10:54:12,082 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:12,082 INFO L471 AbstractCegarLoop]: Abstraction has 48 states and 49 transitions. [2018-07-24 10:54:12,082 INFO L472 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-07-24 10:54:12,082 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 49 transitions. [2018-07-24 10:54:12,083 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-07-24 10:54:12,083 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:12,083 INFO L353 BasicCegarLoop]: trace histogram [16, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:12,083 INFO L414 AbstractCegarLoop]: === Iteration 16 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:12,083 INFO L82 PathProgramCache]: Analyzing trace with hash 1330464314, now seen corresponding path program 14 times [2018-07-24 10:54:12,083 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:12,084 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:12,084 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:12,084 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:12,084 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:12,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:12,479 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:12,480 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:12,480 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:12,489 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:12,489 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:12,510 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:12,510 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:12,512 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:12,542 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:12,543 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:13,433 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:13,453 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:13,453 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:13,468 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:13,468 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:13,561 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:13,561 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:13,565 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:13,614 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:13,614 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:13,671 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:13,673 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:13,673 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 34 [2018-07-24 10:54:13,673 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:13,674 INFO L450 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-07-24 10:54:13,674 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-07-24 10:54:13,675 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:54:13,675 INFO L87 Difference]: Start difference. First operand 48 states and 49 transitions. Second operand 18 states. [2018-07-24 10:54:14,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:14,532 INFO L93 Difference]: Finished difference Result 125 states and 143 transitions. [2018-07-24 10:54:14,532 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-07-24 10:54:14,533 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 44 [2018-07-24 10:54:14,533 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:14,534 INFO L225 Difference]: With dead ends: 125 [2018-07-24 10:54:14,534 INFO L226 Difference]: Without dead ends: 114 [2018-07-24 10:54:14,535 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 192 GetRequests, 158 SyntacticMatches, 2 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:54:14,535 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-07-24 10:54:14,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 50. [2018-07-24 10:54:14,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-07-24 10:54:14,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 51 transitions. [2018-07-24 10:54:14,542 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 51 transitions. Word has length 44 [2018-07-24 10:54:14,542 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:14,542 INFO L471 AbstractCegarLoop]: Abstraction has 50 states and 51 transitions. [2018-07-24 10:54:14,542 INFO L472 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-07-24 10:54:14,542 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 51 transitions. [2018-07-24 10:54:14,542 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-07-24 10:54:14,543 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:14,543 INFO L353 BasicCegarLoop]: trace histogram [17, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:14,543 INFO L414 AbstractCegarLoop]: === Iteration 17 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:14,543 INFO L82 PathProgramCache]: Analyzing trace with hash -919392300, now seen corresponding path program 15 times [2018-07-24 10:54:14,543 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:14,544 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:14,544 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:14,544 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:14,544 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:14,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:15,212 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:15,212 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:15,212 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:15,219 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:15,220 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:17,183 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 17 check-sat command(s) [2018-07-24 10:54:17,184 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:17,187 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:17,198 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:17,198 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:18,112 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:18,133 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:18,134 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:18,148 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:18,148 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:37,173 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 17 check-sat command(s) [2018-07-24 10:55:37,173 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:37,179 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:37,206 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:37,207 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:37,213 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:37,217 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:37,217 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 36 [2018-07-24 10:55:37,217 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:37,217 INFO L450 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-07-24 10:55:37,218 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-07-24 10:55:37,218 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:55:37,219 INFO L87 Difference]: Start difference. First operand 50 states and 51 transitions. Second operand 19 states. [2018-07-24 10:55:38,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:38,181 INFO L93 Difference]: Finished difference Result 131 states and 150 transitions. [2018-07-24 10:55:38,182 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-07-24 10:55:38,182 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 46 [2018-07-24 10:55:38,182 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:38,184 INFO L225 Difference]: With dead ends: 131 [2018-07-24 10:55:38,184 INFO L226 Difference]: Without dead ends: 120 [2018-07-24 10:55:38,185 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 201 GetRequests, 165 SyntacticMatches, 2 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:55:38,185 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states. [2018-07-24 10:55:38,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 52. [2018-07-24 10:55:38,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. [2018-07-24 10:55:38,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 53 transitions. [2018-07-24 10:55:38,191 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 53 transitions. Word has length 46 [2018-07-24 10:55:38,191 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:38,191 INFO L471 AbstractCegarLoop]: Abstraction has 52 states and 53 transitions. [2018-07-24 10:55:38,191 INFO L472 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-07-24 10:55:38,191 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 53 transitions. [2018-07-24 10:55:38,191 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-07-24 10:55:38,192 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:38,192 INFO L353 BasicCegarLoop]: trace histogram [18, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:38,192 INFO L414 AbstractCegarLoop]: === Iteration 18 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:38,192 INFO L82 PathProgramCache]: Analyzing trace with hash 1631918830, now seen corresponding path program 16 times [2018-07-24 10:55:38,192 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:38,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:38,193 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:38,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:38,193 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:38,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:38,566 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:38,566 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:38,566 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:38,574 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:38,575 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:38,600 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:38,600 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:38,602 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:38,620 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:38,621 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:39,578 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:39,598 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:39,599 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:39,613 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:39,613 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:39,766 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:39,766 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:39,771 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:39,780 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:39,781 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:39,807 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:39,808 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:39,808 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 38 [2018-07-24 10:55:39,808 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:39,809 INFO L450 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-07-24 10:55:39,809 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-07-24 10:55:39,809 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:55:39,810 INFO L87 Difference]: Start difference. First operand 52 states and 53 transitions. Second operand 20 states. [2018-07-24 10:55:41,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:41,575 INFO L93 Difference]: Finished difference Result 137 states and 157 transitions. [2018-07-24 10:55:41,575 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-07-24 10:55:41,575 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 48 [2018-07-24 10:55:41,575 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:41,576 INFO L225 Difference]: With dead ends: 137 [2018-07-24 10:55:41,576 INFO L226 Difference]: Without dead ends: 126 [2018-07-24 10:55:41,577 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 210 GetRequests, 172 SyntacticMatches, 2 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:55:41,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-07-24 10:55:41,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 54. [2018-07-24 10:55:41,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-07-24 10:55:41,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 55 transitions. [2018-07-24 10:55:41,585 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 55 transitions. Word has length 48 [2018-07-24 10:55:41,585 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:41,585 INFO L471 AbstractCegarLoop]: Abstraction has 54 states and 55 transitions. [2018-07-24 10:55:41,585 INFO L472 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-07-24 10:55:41,585 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 55 transitions. [2018-07-24 10:55:41,586 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-07-24 10:55:41,586 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:41,586 INFO L353 BasicCegarLoop]: trace histogram [19, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:41,586 INFO L414 AbstractCegarLoop]: === Iteration 19 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:41,586 INFO L82 PathProgramCache]: Analyzing trace with hash 1015588744, now seen corresponding path program 17 times [2018-07-24 10:55:41,586 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:41,587 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:41,587 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:41,587 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:41,588 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:41,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:42,495 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:42,496 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:42,496 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:42,503 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:42,504 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:48,703 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2018-07-24 10:55:48,703 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:48,710 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:48,723 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:48,723 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:49,943 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:49,964 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:49,964 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:49,981 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:49,981 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:56,625 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2018-07-24 10:55:56,626 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:56,632 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:56,647 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:56,647 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:56,654 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:56,655 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:56,656 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 40 [2018-07-24 10:55:56,656 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:56,656 INFO L450 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-07-24 10:55:56,656 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-07-24 10:55:56,657 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-07-24 10:55:56,657 INFO L87 Difference]: Start difference. First operand 54 states and 55 transitions. Second operand 21 states. [2018-07-24 10:55:57,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:57,751 INFO L93 Difference]: Finished difference Result 143 states and 164 transitions. [2018-07-24 10:55:57,751 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-07-24 10:55:57,751 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 50 [2018-07-24 10:55:57,752 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:57,753 INFO L225 Difference]: With dead ends: 143 [2018-07-24 10:55:57,753 INFO L226 Difference]: Without dead ends: 132 [2018-07-24 10:55:57,754 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 219 GetRequests, 179 SyntacticMatches, 2 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-07-24 10:55:57,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-07-24 10:55:57,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 56. [2018-07-24 10:55:57,758 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56 states. [2018-07-24 10:55:57,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 57 transitions. [2018-07-24 10:55:57,759 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 57 transitions. Word has length 50 [2018-07-24 10:55:57,759 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:57,759 INFO L471 AbstractCegarLoop]: Abstraction has 56 states and 57 transitions. [2018-07-24 10:55:57,759 INFO L472 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-07-24 10:55:57,759 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 57 transitions. [2018-07-24 10:55:57,760 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-07-24 10:55:57,760 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:57,760 INFO L353 BasicCegarLoop]: trace histogram [20, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:57,760 INFO L414 AbstractCegarLoop]: === Iteration 20 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:57,760 INFO L82 PathProgramCache]: Analyzing trace with hash 1427862946, now seen corresponding path program 18 times [2018-07-24 10:55:57,761 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:57,761 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:57,761 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:57,761 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:57,761 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:57,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:58,144 INFO L134 CoverageAnalysis]: Checked inductivity of 380 backedges. 0 proven. 380 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:58,144 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:58,144 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:58,151 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:58,151 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:01,920 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 20 check-sat command(s) [2018-07-24 10:56:01,920 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:01,923 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:01,965 INFO L134 CoverageAnalysis]: Checked inductivity of 380 backedges. 0 proven. 380 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:01,966 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:03,374 INFO L134 CoverageAnalysis]: Checked inductivity of 380 backedges. 0 proven. 380 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:03,395 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:03,395 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:03,411 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:56:03,411 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:57:21,017 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 20 check-sat command(s) [2018-07-24 10:57:21,017 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:21,024 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:21,052 INFO L134 CoverageAnalysis]: Checked inductivity of 380 backedges. 0 proven. 380 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:21,052 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:21,063 INFO L134 CoverageAnalysis]: Checked inductivity of 380 backedges. 0 proven. 380 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:21,066 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:21,067 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22, 22, 22] total 42 [2018-07-24 10:57:21,067 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:21,067 INFO L450 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-07-24 10:57:21,068 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-07-24 10:57:21,069 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-07-24 10:57:21,069 INFO L87 Difference]: Start difference. First operand 56 states and 57 transitions. Second operand 22 states. [2018-07-24 10:57:22,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:22,439 INFO L93 Difference]: Finished difference Result 149 states and 171 transitions. [2018-07-24 10:57:22,439 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-07-24 10:57:22,439 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 52 [2018-07-24 10:57:22,440 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:22,441 INFO L225 Difference]: With dead ends: 149 [2018-07-24 10:57:22,441 INFO L226 Difference]: Without dead ends: 138 [2018-07-24 10:57:22,443 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 228 GetRequests, 186 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-07-24 10:57:22,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2018-07-24 10:57:22,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 58. [2018-07-24 10:57:22,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2018-07-24 10:57:22,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 59 transitions. [2018-07-24 10:57:22,448 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 59 transitions. Word has length 52 [2018-07-24 10:57:22,449 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:22,449 INFO L471 AbstractCegarLoop]: Abstraction has 58 states and 59 transitions. [2018-07-24 10:57:22,449 INFO L472 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-07-24 10:57:22,449 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 59 transitions. [2018-07-24 10:57:22,449 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-07-24 10:57:22,450 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:22,450 INFO L353 BasicCegarLoop]: trace histogram [21, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:22,450 INFO L414 AbstractCegarLoop]: === Iteration 21 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:22,450 INFO L82 PathProgramCache]: Analyzing trace with hash -1808587460, now seen corresponding path program 19 times [2018-07-24 10:57:22,450 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:22,451 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:22,451 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:22,451 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:22,451 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:22,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:23,571 INFO L134 CoverageAnalysis]: Checked inductivity of 420 backedges. 0 proven. 420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:23,572 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:23,572 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:23,581 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:23,581 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:57:23,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:23,611 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:23,633 INFO L134 CoverageAnalysis]: Checked inductivity of 420 backedges. 0 proven. 420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:23,633 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:24,852 INFO L134 CoverageAnalysis]: Checked inductivity of 420 backedges. 0 proven. 420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:24,872 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:24,872 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:24,888 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:24,889 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:57:25,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:25,057 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:25,074 INFO L134 CoverageAnalysis]: Checked inductivity of 420 backedges. 0 proven. 420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:25,074 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:25,085 INFO L134 CoverageAnalysis]: Checked inductivity of 420 backedges. 0 proven. 420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:25,086 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:25,086 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 44 [2018-07-24 10:57:25,086 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:25,086 INFO L450 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-07-24 10:57:25,087 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-07-24 10:57:25,087 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-07-24 10:57:25,088 INFO L87 Difference]: Start difference. First operand 58 states and 59 transitions. Second operand 23 states. [2018-07-24 10:57:29,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:29,215 INFO L93 Difference]: Finished difference Result 155 states and 178 transitions. [2018-07-24 10:57:29,215 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-07-24 10:57:29,215 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 54 [2018-07-24 10:57:29,216 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:29,217 INFO L225 Difference]: With dead ends: 155 [2018-07-24 10:57:29,217 INFO L226 Difference]: Without dead ends: 144 [2018-07-24 10:57:29,218 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 237 GetRequests, 193 SyntacticMatches, 2 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-07-24 10:57:29,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-07-24 10:57:29,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 60. [2018-07-24 10:57:29,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-07-24 10:57:29,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 61 transitions. [2018-07-24 10:57:29,224 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 61 transitions. Word has length 54 [2018-07-24 10:57:29,224 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:29,225 INFO L471 AbstractCegarLoop]: Abstraction has 60 states and 61 transitions. [2018-07-24 10:57:29,225 INFO L472 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-07-24 10:57:29,225 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 61 transitions. [2018-07-24 10:57:29,225 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-07-24 10:57:29,225 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:29,226 INFO L353 BasicCegarLoop]: trace histogram [22, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:29,226 INFO L414 AbstractCegarLoop]: === Iteration 22 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:29,226 INFO L82 PathProgramCache]: Analyzing trace with hash 1813861974, now seen corresponding path program 20 times [2018-07-24 10:57:29,226 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:29,227 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:29,227 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:29,227 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:29,227 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:29,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:29,610 INFO L134 CoverageAnalysis]: Checked inductivity of 462 backedges. 0 proven. 462 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:29,611 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:29,611 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:29,619 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:57:29,619 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:29,648 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:57:29,648 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:29,650 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:29,679 INFO L134 CoverageAnalysis]: Checked inductivity of 462 backedges. 0 proven. 462 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:29,679 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:31,036 INFO L134 CoverageAnalysis]: Checked inductivity of 462 backedges. 0 proven. 462 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:31,056 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:31,056 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:31,071 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:57:31,071 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:31,212 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:57:31,213 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:31,220 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:31,251 INFO L134 CoverageAnalysis]: Checked inductivity of 462 backedges. 0 proven. 462 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:31,251 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:31,292 INFO L134 CoverageAnalysis]: Checked inductivity of 462 backedges. 0 proven. 462 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:31,293 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:31,293 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 46 [2018-07-24 10:57:31,293 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:31,294 INFO L450 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-07-24 10:57:31,294 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-07-24 10:57:31,295 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-07-24 10:57:31,295 INFO L87 Difference]: Start difference. First operand 60 states and 61 transitions. Second operand 24 states. [2018-07-24 10:57:32,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:32,881 INFO L93 Difference]: Finished difference Result 161 states and 185 transitions. [2018-07-24 10:57:32,883 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-07-24 10:57:32,884 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 56 [2018-07-24 10:57:32,884 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:32,885 INFO L225 Difference]: With dead ends: 161 [2018-07-24 10:57:32,885 INFO L226 Difference]: Without dead ends: 150 [2018-07-24 10:57:32,886 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 246 GetRequests, 200 SyntacticMatches, 2 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-07-24 10:57:32,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-07-24 10:57:32,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 62. [2018-07-24 10:57:32,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 62 states. [2018-07-24 10:57:32,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 63 transitions. [2018-07-24 10:57:32,893 INFO L78 Accepts]: Start accepts. Automaton has 62 states and 63 transitions. Word has length 56 [2018-07-24 10:57:32,893 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:32,893 INFO L471 AbstractCegarLoop]: Abstraction has 62 states and 63 transitions. [2018-07-24 10:57:32,893 INFO L472 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-07-24 10:57:32,893 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 63 transitions. [2018-07-24 10:57:32,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-07-24 10:57:32,894 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:32,894 INFO L353 BasicCegarLoop]: trace histogram [23, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:32,894 INFO L414 AbstractCegarLoop]: === Iteration 23 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_crafted_simple_array_index_value_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:32,894 INFO L82 PathProgramCache]: Analyzing trace with hash -230709008, now seen corresponding path program 21 times [2018-07-24 10:57:32,894 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:32,895 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:32,895 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:32,895 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:32,895 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:32,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:33,550 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:33,551 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:33,551 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:33,558 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:57:33,558 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:57:48,989 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 23 check-sat command(s) [2018-07-24 10:57:48,989 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:48,994 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:49,007 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:49,007 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:50,671 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:50,692 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:50,692 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:50,709 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:57:50,709 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) Received shutdown request... Cannot interrupt operation gracefully because timeout expired. Forcing shutdown