java -Xmx8000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml --generate-csv --csv-dir csv -s ../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf -i ../../../trunk/examples/svcomp/loop-acceleration/simple_true-unreach-call1.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-dd2f093 [2018-07-24 10:52:46,919 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-07-24 10:52:46,921 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-07-24 10:52:46,932 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-07-24 10:52:46,933 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-07-24 10:52:46,934 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-07-24 10:52:46,937 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-07-24 10:52:46,941 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-07-24 10:52:46,945 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-07-24 10:52:46,945 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-07-24 10:52:46,947 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-07-24 10:52:46,947 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-07-24 10:52:46,948 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-07-24 10:52:46,949 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-07-24 10:52:46,951 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-07-24 10:52:46,954 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-07-24 10:52:46,955 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-07-24 10:52:46,957 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-07-24 10:52:46,968 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-07-24 10:52:46,971 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-07-24 10:52:46,973 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-07-24 10:52:46,974 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-07-24 10:52:46,978 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-07-24 10:52:46,978 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-07-24 10:52:46,978 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-07-24 10:52:46,979 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-07-24 10:52:46,982 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-07-24 10:52:46,982 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-07-24 10:52:46,983 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-07-24 10:52:46,984 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-07-24 10:52:46,984 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-07-24 10:52:46,985 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-07-24 10:52:46,985 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-07-24 10:52:46,985 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-07-24 10:52:46,989 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-07-24 10:52:46,990 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-07-24 10:52:46,990 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf [2018-07-24 10:52:47,017 INFO L110 SettingsManager]: Loading preferences was successful [2018-07-24 10:52:47,018 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-07-24 10:52:47,019 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-07-24 10:52:47,019 INFO L133 SettingsManager]: * User list type=DISABLED [2018-07-24 10:52:47,019 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-07-24 10:52:47,019 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-07-24 10:52:47,020 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-07-24 10:52:47,020 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-07-24 10:52:47,020 INFO L133 SettingsManager]: * Log string format=TERM [2018-07-24 10:52:47,020 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-07-24 10:52:47,020 INFO L133 SettingsManager]: * Interval Domain=false [2018-07-24 10:52:47,021 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-07-24 10:52:47,021 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-07-24 10:52:47,021 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-07-24 10:52:47,022 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-07-24 10:52:47,022 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-07-24 10:52:47,022 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-07-24 10:52:47,022 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-07-24 10:52:47,022 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-07-24 10:52:47,023 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-07-24 10:52:47,023 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-07-24 10:52:47,023 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-07-24 10:52:47,023 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-07-24 10:52:47,023 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:52:47,024 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-07-24 10:52:47,024 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-07-24 10:52:47,024 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-07-24 10:52:47,024 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-07-24 10:52:47,024 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-07-24 10:52:47,024 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-07-24 10:52:47,025 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-07-24 10:52:47,025 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-07-24 10:52:47,025 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-07-24 10:52:47,076 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-07-24 10:52:47,090 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-07-24 10:52:47,097 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-07-24 10:52:47,099 INFO L271 PluginConnector]: Initializing CDTParser... [2018-07-24 10:52:47,099 INFO L276 PluginConnector]: CDTParser initialized [2018-07-24 10:52:47,100 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-acceleration/simple_true-unreach-call1.i [2018-07-24 10:52:47,446 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f3a20ac8c/a2e24c4e30bd4674b660916197ade6a4/FLAG47e88c69d [2018-07-24 10:52:47,558 INFO L276 CDTParser]: Found 1 translation units. [2018-07-24 10:52:47,558 INFO L158 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-acceleration/simple_true-unreach-call1.i [2018-07-24 10:52:47,565 INFO L324 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f3a20ac8c/a2e24c4e30bd4674b660916197ade6a4/FLAG47e88c69d [2018-07-24 10:52:47,579 INFO L332 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f3a20ac8c/a2e24c4e30bd4674b660916197ade6a4 [2018-07-24 10:52:47,588 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-07-24 10:52:47,589 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-07-24 10:52:47,590 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-07-24 10:52:47,590 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-07-24 10:52:47,597 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-07-24 10:52:47,598 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:52:47" (1/1) ... [2018-07-24 10:52:47,600 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@47d47768 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:47, skipping insertion in model container [2018-07-24 10:52:47,601 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:52:47" (1/1) ... [2018-07-24 10:52:47,747 INFO L179 PRDispatcher]: Starting pre-run dispatcher in SV-COMP mode [2018-07-24 10:52:47,778 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:52:47,792 INFO L422 MainDispatcher]: Starting main dispatcher in SV-COMP mode [2018-07-24 10:52:47,796 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:52:47,811 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:47 WrapperNode [2018-07-24 10:52:47,811 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-07-24 10:52:47,812 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-07-24 10:52:47,812 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-07-24 10:52:47,812 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-07-24 10:52:47,821 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:47" (1/1) ... [2018-07-24 10:52:47,827 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:47" (1/1) ... [2018-07-24 10:52:47,832 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-07-24 10:52:47,833 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-07-24 10:52:47,833 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-07-24 10:52:47,833 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-07-24 10:52:47,843 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:47" (1/1) ... [2018-07-24 10:52:47,843 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:47" (1/1) ... [2018-07-24 10:52:47,844 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:47" (1/1) ... [2018-07-24 10:52:47,844 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:47" (1/1) ... [2018-07-24 10:52:47,845 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:47" (1/1) ... [2018-07-24 10:52:47,851 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:47" (1/1) ... [2018-07-24 10:52:47,852 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:47" (1/1) ... [2018-07-24 10:52:47,854 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-07-24 10:52:47,859 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-07-24 10:52:47,860 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-07-24 10:52:47,860 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-07-24 10:52:47,861 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:47" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:52:47,920 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-07-24 10:52:47,921 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-07-24 10:52:47,921 INFO L130 BoogieDeclarations]: Found specification of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_simple_true_unreach_call__i____VERIFIER_assert [2018-07-24 10:52:47,921 INFO L138 BoogieDeclarations]: Found implementation of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_simple_true_unreach_call__i____VERIFIER_assert [2018-07-24 10:52:47,921 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-07-24 10:52:47,922 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-07-24 10:52:47,922 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-07-24 10:52:47,922 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-07-24 10:52:48,304 INFO L261 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-07-24 10:52:48,304 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:52:48 BoogieIcfgContainer [2018-07-24 10:52:48,305 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-07-24 10:52:48,306 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-07-24 10:52:48,306 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-07-24 10:52:48,309 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-07-24 10:52:48,310 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.07 10:52:47" (1/3) ... [2018-07-24 10:52:48,311 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@51058be1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:52:48, skipping insertion in model container [2018-07-24 10:52:48,311 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:47" (2/3) ... [2018-07-24 10:52:48,311 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@51058be1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:52:48, skipping insertion in model container [2018-07-24 10:52:48,312 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:52:48" (3/3) ... [2018-07-24 10:52:48,313 INFO L112 eAbstractionObserver]: Analyzing ICFG simple_true-unreach-call1.i [2018-07-24 10:52:48,323 INFO L132 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-07-24 10:52:48,331 INFO L144 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-07-24 10:52:48,382 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-07-24 10:52:48,382 INFO L373 AbstractCegarLoop]: Interprodecural is true [2018-07-24 10:52:48,383 INFO L374 AbstractCegarLoop]: Hoare is true [2018-07-24 10:52:48,383 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-07-24 10:52:48,383 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-07-24 10:52:48,383 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-07-24 10:52:48,383 INFO L378 AbstractCegarLoop]: Difference is false [2018-07-24 10:52:48,383 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-07-24 10:52:48,384 INFO L384 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-07-24 10:52:48,402 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states. [2018-07-24 10:52:48,408 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2018-07-24 10:52:48,408 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:48,409 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:48,409 INFO L414 AbstractCegarLoop]: === Iteration 1 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_simple_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:48,414 INFO L82 PathProgramCache]: Analyzing trace with hash 314686959, now seen corresponding path program 1 times [2018-07-24 10:52:48,417 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:48,474 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:48,474 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:48,474 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:48,474 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:48,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:48,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:48,539 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:52:48,539 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-07-24 10:52:48,540 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:52:48,545 INFO L450 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-07-24 10:52:48,560 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-07-24 10:52:48,561 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:52:48,563 INFO L87 Difference]: Start difference. First operand 18 states. Second operand 2 states. [2018-07-24 10:52:48,586 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:48,586 INFO L93 Difference]: Finished difference Result 29 states and 32 transitions. [2018-07-24 10:52:48,586 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-07-24 10:52:48,588 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 10 [2018-07-24 10:52:48,588 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:48,597 INFO L225 Difference]: With dead ends: 29 [2018-07-24 10:52:48,597 INFO L226 Difference]: Without dead ends: 12 [2018-07-24 10:52:48,600 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:52:48,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states. [2018-07-24 10:52:48,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 12. [2018-07-24 10:52:48,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2018-07-24 10:52:48,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 12 transitions. [2018-07-24 10:52:48,641 INFO L78 Accepts]: Start accepts. Automaton has 12 states and 12 transitions. Word has length 10 [2018-07-24 10:52:48,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:48,641 INFO L471 AbstractCegarLoop]: Abstraction has 12 states and 12 transitions. [2018-07-24 10:52:48,641 INFO L472 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-07-24 10:52:48,642 INFO L276 IsEmpty]: Start isEmpty. Operand 12 states and 12 transitions. [2018-07-24 10:52:48,642 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-07-24 10:52:48,642 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:48,643 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:48,643 INFO L414 AbstractCegarLoop]: === Iteration 2 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_simple_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:48,643 INFO L82 PathProgramCache]: Analyzing trace with hash 926255632, now seen corresponding path program 1 times [2018-07-24 10:52:48,644 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:48,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:48,645 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:48,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:48,645 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:48,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:48,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:48,780 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:52:48,780 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-07-24 10:52:48,780 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:52:48,782 INFO L450 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-07-24 10:52:48,783 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-07-24 10:52:48,783 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 10:52:48,783 INFO L87 Difference]: Start difference. First operand 12 states and 12 transitions. Second operand 3 states. [2018-07-24 10:52:48,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:48,816 INFO L93 Difference]: Finished difference Result 19 states and 19 transitions. [2018-07-24 10:52:48,818 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-07-24 10:52:48,818 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-07-24 10:52:48,818 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:48,820 INFO L225 Difference]: With dead ends: 19 [2018-07-24 10:52:48,820 INFO L226 Difference]: Without dead ends: 14 [2018-07-24 10:52:48,822 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 10:52:48,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states. [2018-07-24 10:52:48,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 14. [2018-07-24 10:52:48,827 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2018-07-24 10:52:48,828 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 14 transitions. [2018-07-24 10:52:48,828 INFO L78 Accepts]: Start accepts. Automaton has 14 states and 14 transitions. Word has length 11 [2018-07-24 10:52:48,828 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:48,829 INFO L471 AbstractCegarLoop]: Abstraction has 14 states and 14 transitions. [2018-07-24 10:52:48,829 INFO L472 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-07-24 10:52:48,829 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 14 transitions. [2018-07-24 10:52:48,830 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-07-24 10:52:48,830 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:48,830 INFO L353 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:48,831 INFO L414 AbstractCegarLoop]: === Iteration 3 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_simple_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:48,831 INFO L82 PathProgramCache]: Analyzing trace with hash -1883357962, now seen corresponding path program 1 times [2018-07-24 10:52:48,831 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:48,832 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:48,833 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:48,833 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:48,833 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:48,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:49,069 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:49,070 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:49,070 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:49,089 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:49,089 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:52:49,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:49,124 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:49,168 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:49,168 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:49,253 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:49,274 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:49,274 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:49,292 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:49,293 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:52:49,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:49,310 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:49,346 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:49,347 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:49,368 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:49,372 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:49,372 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 6 [2018-07-24 10:52:49,372 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:49,373 INFO L450 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-07-24 10:52:49,373 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-07-24 10:52:49,373 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-07-24 10:52:49,374 INFO L87 Difference]: Start difference. First operand 14 states and 14 transitions. Second operand 4 states. [2018-07-24 10:52:49,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:49,445 INFO L93 Difference]: Finished difference Result 21 states and 21 transitions. [2018-07-24 10:52:49,445 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-07-24 10:52:49,446 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2018-07-24 10:52:49,447 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:49,447 INFO L225 Difference]: With dead ends: 21 [2018-07-24 10:52:49,448 INFO L226 Difference]: Without dead ends: 16 [2018-07-24 10:52:49,450 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 48 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-07-24 10:52:49,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2018-07-24 10:52:49,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 16. [2018-07-24 10:52:49,455 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2018-07-24 10:52:49,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 16 transitions. [2018-07-24 10:52:49,456 INFO L78 Accepts]: Start accepts. Automaton has 16 states and 16 transitions. Word has length 13 [2018-07-24 10:52:49,456 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:49,456 INFO L471 AbstractCegarLoop]: Abstraction has 16 states and 16 transitions. [2018-07-24 10:52:49,456 INFO L472 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-07-24 10:52:49,457 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 16 transitions. [2018-07-24 10:52:49,457 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-07-24 10:52:49,460 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:49,460 INFO L353 BasicCegarLoop]: trace histogram [3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:49,460 INFO L414 AbstractCegarLoop]: === Iteration 4 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_simple_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:49,460 INFO L82 PathProgramCache]: Analyzing trace with hash -387592612, now seen corresponding path program 2 times [2018-07-24 10:52:49,461 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:49,462 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:49,462 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:49,462 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:49,462 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:49,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:49,675 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:49,676 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:49,676 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-07-24 10:52:49,695 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:52:49,696 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:49,710 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:52:49,710 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:49,712 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:49,733 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:49,733 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:49,981 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:50,002 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:50,003 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:50,019 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:52:50,019 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:52:50,038 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:52:50,039 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:50,042 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:50,059 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:50,059 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:50,087 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:50,089 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:50,089 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 8 [2018-07-24 10:52:50,090 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:50,090 INFO L450 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-07-24 10:52:50,090 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-07-24 10:52:50,091 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-07-24 10:52:50,091 INFO L87 Difference]: Start difference. First operand 16 states and 16 transitions. Second operand 5 states. [2018-07-24 10:52:50,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:50,134 INFO L93 Difference]: Finished difference Result 23 states and 23 transitions. [2018-07-24 10:52:50,135 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-07-24 10:52:50,135 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 15 [2018-07-24 10:52:50,136 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:50,136 INFO L225 Difference]: With dead ends: 23 [2018-07-24 10:52:50,136 INFO L226 Difference]: Without dead ends: 18 [2018-07-24 10:52:50,137 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 55 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-07-24 10:52:50,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states. [2018-07-24 10:52:50,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 18. [2018-07-24 10:52:50,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2018-07-24 10:52:50,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 18 transitions. [2018-07-24 10:52:50,142 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 18 transitions. Word has length 15 [2018-07-24 10:52:50,142 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:50,143 INFO L471 AbstractCegarLoop]: Abstraction has 18 states and 18 transitions. [2018-07-24 10:52:50,143 INFO L472 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-07-24 10:52:50,143 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 18 transitions. [2018-07-24 10:52:50,143 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-07-24 10:52:50,144 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:50,144 INFO L353 BasicCegarLoop]: trace histogram [4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:50,144 INFO L414 AbstractCegarLoop]: === Iteration 5 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_simple_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:50,144 INFO L82 PathProgramCache]: Analyzing trace with hash -1771135422, now seen corresponding path program 3 times [2018-07-24 10:52:50,144 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:50,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:50,145 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:50,146 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:50,146 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:50,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:50,263 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:50,263 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:50,264 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:50,277 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:52:50,277 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:52:50,288 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-07-24 10:52:50,288 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:50,290 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:50,337 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:50,338 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:50,512 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:50,533 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:50,533 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:50,549 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:52:50,550 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:52:50,580 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-07-24 10:52:50,581 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:50,584 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:50,596 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:50,596 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:50,614 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:50,617 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:50,617 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 10 [2018-07-24 10:52:50,617 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:50,618 INFO L450 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-07-24 10:52:50,618 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-07-24 10:52:50,618 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-07-24 10:52:50,619 INFO L87 Difference]: Start difference. First operand 18 states and 18 transitions. Second operand 6 states. [2018-07-24 10:52:50,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:50,695 INFO L93 Difference]: Finished difference Result 25 states and 25 transitions. [2018-07-24 10:52:50,696 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-07-24 10:52:50,696 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 17 [2018-07-24 10:52:50,696 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:50,697 INFO L225 Difference]: With dead ends: 25 [2018-07-24 10:52:50,697 INFO L226 Difference]: Without dead ends: 20 [2018-07-24 10:52:50,698 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 62 SyntacticMatches, 3 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-07-24 10:52:50,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2018-07-24 10:52:50,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2018-07-24 10:52:50,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2018-07-24 10:52:50,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 20 transitions. [2018-07-24 10:52:50,702 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 20 transitions. Word has length 17 [2018-07-24 10:52:50,703 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:50,703 INFO L471 AbstractCegarLoop]: Abstraction has 20 states and 20 transitions. [2018-07-24 10:52:50,703 INFO L472 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-07-24 10:52:50,703 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 20 transitions. [2018-07-24 10:52:50,704 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-07-24 10:52:50,704 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:50,704 INFO L353 BasicCegarLoop]: trace histogram [5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:50,704 INFO L414 AbstractCegarLoop]: === Iteration 6 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_simple_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:50,704 INFO L82 PathProgramCache]: Analyzing trace with hash 84085928, now seen corresponding path program 4 times [2018-07-24 10:52:50,705 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:50,705 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:50,706 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:50,706 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:50,706 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:50,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:50,915 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:50,916 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:50,916 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:50,928 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:52:50,929 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:52:50,959 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:52:50,959 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:50,961 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:51,034 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:51,034 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:51,388 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:51,410 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:51,410 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:51,425 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:52:51,426 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:52:51,446 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:52:51,447 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:51,451 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:51,459 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:51,460 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:51,466 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (9)] Exception during sending of exit command (exit): Broken pipe [2018-07-24 10:52:51,469 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:51,470 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 12 [2018-07-24 10:52:51,470 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:51,470 INFO L450 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-07-24 10:52:51,470 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-07-24 10:52:51,471 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:52:51,472 INFO L87 Difference]: Start difference. First operand 20 states and 20 transitions. Second operand 7 states. [2018-07-24 10:52:51,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:51,541 INFO L93 Difference]: Finished difference Result 27 states and 27 transitions. [2018-07-24 10:52:51,541 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-07-24 10:52:51,542 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 19 [2018-07-24 10:52:51,542 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:51,542 INFO L225 Difference]: With dead ends: 27 [2018-07-24 10:52:51,543 INFO L226 Difference]: Without dead ends: 22 [2018-07-24 10:52:51,543 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 82 GetRequests, 69 SyntacticMatches, 3 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:52:51,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2018-07-24 10:52:51,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2018-07-24 10:52:51,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2018-07-24 10:52:51,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 22 transitions. [2018-07-24 10:52:51,548 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 22 transitions. Word has length 19 [2018-07-24 10:52:51,548 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:51,548 INFO L471 AbstractCegarLoop]: Abstraction has 22 states and 22 transitions. [2018-07-24 10:52:51,548 INFO L472 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-07-24 10:52:51,549 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 22 transitions. [2018-07-24 10:52:51,549 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-07-24 10:52:51,549 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:51,549 INFO L353 BasicCegarLoop]: trace histogram [6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:51,550 INFO L414 AbstractCegarLoop]: === Iteration 7 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_simple_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:51,550 INFO L82 PathProgramCache]: Analyzing trace with hash 540375438, now seen corresponding path program 5 times [2018-07-24 10:52:51,550 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:51,551 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:51,551 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:51,551 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:51,551 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:51,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:51,939 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:51,940 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:51,940 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:51,948 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:52:51,948 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:52:51,985 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-07-24 10:52:51,986 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:51,989 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:52,007 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:52,007 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:52,204 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:52,226 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:52,226 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:52,242 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:52:52,242 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:52:52,279 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-07-24 10:52:52,279 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:52,282 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:52,302 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:52,302 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:52,311 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (11)] Exception during sending of exit command (exit): Broken pipe [2018-07-24 10:52:52,313 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:52,314 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 14 [2018-07-24 10:52:52,314 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:52,314 INFO L450 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-07-24 10:52:52,315 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-07-24 10:52:52,315 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:52:52,315 INFO L87 Difference]: Start difference. First operand 22 states and 22 transitions. Second operand 8 states. [2018-07-24 10:52:52,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:52,441 INFO L93 Difference]: Finished difference Result 29 states and 29 transitions. [2018-07-24 10:52:52,443 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-07-24 10:52:52,444 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 21 [2018-07-24 10:52:52,444 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:52,444 INFO L225 Difference]: With dead ends: 29 [2018-07-24 10:52:52,444 INFO L226 Difference]: Without dead ends: 24 [2018-07-24 10:52:52,445 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 76 SyntacticMatches, 3 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:52:52,445 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states. [2018-07-24 10:52:52,448 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 24. [2018-07-24 10:52:52,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-07-24 10:52:52,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 24 transitions. [2018-07-24 10:52:52,449 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 24 transitions. Word has length 21 [2018-07-24 10:52:52,450 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:52,450 INFO L471 AbstractCegarLoop]: Abstraction has 24 states and 24 transitions. [2018-07-24 10:52:52,450 INFO L472 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-07-24 10:52:52,450 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 24 transitions. [2018-07-24 10:52:52,451 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-07-24 10:52:52,451 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:52,451 INFO L353 BasicCegarLoop]: trace histogram [7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:52,451 INFO L414 AbstractCegarLoop]: === Iteration 8 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_simple_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:52,451 INFO L82 PathProgramCache]: Analyzing trace with hash 947930356, now seen corresponding path program 6 times [2018-07-24 10:52:52,451 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:52,452 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:52,452 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:52,452 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:52,453 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:52,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:52,664 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:52,665 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:52,665 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:52,679 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:52:52,679 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:52:52,700 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-07-24 10:52:52,701 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:52,702 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:52,720 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:52,720 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:52,873 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:52,895 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:52,895 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:52,911 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:52:52,911 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:52:52,973 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-07-24 10:52:52,973 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:52,977 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:52,992 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:52,992 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:53,011 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:53,013 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:53,013 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 16 [2018-07-24 10:52:53,013 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:53,014 INFO L450 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-07-24 10:52:53,014 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-07-24 10:52:53,014 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:52:53,015 INFO L87 Difference]: Start difference. First operand 24 states and 24 transitions. Second operand 9 states. [2018-07-24 10:52:53,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:53,083 INFO L93 Difference]: Finished difference Result 31 states and 31 transitions. [2018-07-24 10:52:53,084 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-07-24 10:52:53,084 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 23 [2018-07-24 10:52:53,085 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:53,086 INFO L225 Difference]: With dead ends: 31 [2018-07-24 10:52:53,086 INFO L226 Difference]: Without dead ends: 26 [2018-07-24 10:52:53,086 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 83 SyntacticMatches, 3 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:52:53,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2018-07-24 10:52:53,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 26. [2018-07-24 10:52:53,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2018-07-24 10:52:53,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 26 transitions. [2018-07-24 10:52:53,091 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 26 transitions. Word has length 23 [2018-07-24 10:52:53,091 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:53,091 INFO L471 AbstractCegarLoop]: Abstraction has 26 states and 26 transitions. [2018-07-24 10:52:53,091 INFO L472 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-07-24 10:52:53,091 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 26 transitions. [2018-07-24 10:52:53,092 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-07-24 10:52:53,092 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:53,092 INFO L353 BasicCegarLoop]: trace histogram [8, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:53,092 INFO L414 AbstractCegarLoop]: === Iteration 9 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_simple_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:53,092 INFO L82 PathProgramCache]: Analyzing trace with hash 1766182618, now seen corresponding path program 7 times [2018-07-24 10:52:53,093 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:53,093 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:53,094 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:53,094 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:53,094 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:53,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:53,278 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:53,278 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:53,278 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:53,286 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:53,286 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:52:53,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:53,296 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:53,309 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:53,309 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:53,733 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:53,753 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:53,753 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:53,768 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:53,769 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:52:53,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:53,789 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:53,814 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:53,814 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:53,832 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:53,833 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:53,834 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 18 [2018-07-24 10:52:53,834 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:53,834 INFO L450 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-07-24 10:52:53,835 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-07-24 10:52:53,835 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:52:53,836 INFO L87 Difference]: Start difference. First operand 26 states and 26 transitions. Second operand 10 states. [2018-07-24 10:52:53,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:53,923 INFO L93 Difference]: Finished difference Result 33 states and 33 transitions. [2018-07-24 10:52:53,933 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-07-24 10:52:53,933 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 25 [2018-07-24 10:52:53,934 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:53,934 INFO L225 Difference]: With dead ends: 33 [2018-07-24 10:52:53,934 INFO L226 Difference]: Without dead ends: 28 [2018-07-24 10:52:53,935 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 109 GetRequests, 90 SyntacticMatches, 3 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:52:53,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2018-07-24 10:52:53,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 28. [2018-07-24 10:52:53,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28 states. [2018-07-24 10:52:53,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 28 transitions. [2018-07-24 10:52:53,939 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 28 transitions. Word has length 25 [2018-07-24 10:52:53,939 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:53,939 INFO L471 AbstractCegarLoop]: Abstraction has 28 states and 28 transitions. [2018-07-24 10:52:53,940 INFO L472 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-07-24 10:52:53,940 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 28 transitions. [2018-07-24 10:52:53,940 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-07-24 10:52:53,940 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:53,941 INFO L353 BasicCegarLoop]: trace histogram [9, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:53,941 INFO L414 AbstractCegarLoop]: === Iteration 10 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_simple_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:53,941 INFO L82 PathProgramCache]: Analyzing trace with hash 2127591232, now seen corresponding path program 8 times [2018-07-24 10:52:53,941 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:53,942 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:53,942 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:53,942 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:53,942 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:53,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:54,238 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:54,238 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:54,238 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:54,246 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:52:54,246 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:52:54,258 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:52:54,258 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:54,260 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:54,283 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:54,283 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:54,541 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:54,560 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:54,561 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:54,576 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:52:54,576 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:52:54,601 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:52:54,601 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:54,604 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:54,639 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:54,639 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:54,695 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:54,701 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:54,701 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 20 [2018-07-24 10:52:54,701 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:54,702 INFO L450 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-07-24 10:52:54,702 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-07-24 10:52:54,703 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:52:54,703 INFO L87 Difference]: Start difference. First operand 28 states and 28 transitions. Second operand 11 states. [2018-07-24 10:52:55,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:55,107 INFO L93 Difference]: Finished difference Result 35 states and 35 transitions. [2018-07-24 10:52:55,107 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-07-24 10:52:55,107 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 27 [2018-07-24 10:52:55,108 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:55,108 INFO L225 Difference]: With dead ends: 35 [2018-07-24 10:52:55,109 INFO L226 Difference]: Without dead ends: 30 [2018-07-24 10:52:55,110 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 97 SyntacticMatches, 3 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:52:55,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states. [2018-07-24 10:52:55,114 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 30. [2018-07-24 10:52:55,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-07-24 10:52:55,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 30 transitions. [2018-07-24 10:52:55,115 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 30 transitions. Word has length 27 [2018-07-24 10:52:55,115 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:55,115 INFO L471 AbstractCegarLoop]: Abstraction has 30 states and 30 transitions. [2018-07-24 10:52:55,115 INFO L472 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-07-24 10:52:55,115 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 30 transitions. [2018-07-24 10:52:55,116 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-07-24 10:52:55,116 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:55,116 INFO L353 BasicCegarLoop]: trace histogram [10, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:55,117 INFO L414 AbstractCegarLoop]: === Iteration 11 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_simple_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:55,117 INFO L82 PathProgramCache]: Analyzing trace with hash 1548918310, now seen corresponding path program 9 times [2018-07-24 10:52:55,117 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:55,118 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:55,118 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:55,118 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:55,118 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:55,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:55,291 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:55,291 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:55,291 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:55,299 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:52:55,299 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:52:55,392 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-07-24 10:52:55,393 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:55,395 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:55,426 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:55,426 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:55,933 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:55,954 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:55,954 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:55,969 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:52:55,969 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:52:56,072 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-07-24 10:52:56,072 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:56,075 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:56,093 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:56,093 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:56,112 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (19)] Exception during sending of exit command (exit): Broken pipe [2018-07-24 10:52:56,114 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:56,114 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 22 [2018-07-24 10:52:56,114 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:56,115 INFO L450 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-07-24 10:52:56,115 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-07-24 10:52:56,115 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-07-24 10:52:56,116 INFO L87 Difference]: Start difference. First operand 30 states and 30 transitions. Second operand 12 states. [2018-07-24 10:52:56,309 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:56,310 INFO L93 Difference]: Finished difference Result 37 states and 37 transitions. [2018-07-24 10:52:56,311 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-07-24 10:52:56,311 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 29 [2018-07-24 10:52:56,312 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:56,312 INFO L225 Difference]: With dead ends: 37 [2018-07-24 10:52:56,312 INFO L226 Difference]: Without dead ends: 32 [2018-07-24 10:52:56,313 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 127 GetRequests, 104 SyntacticMatches, 3 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-07-24 10:52:56,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states. [2018-07-24 10:52:56,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 32. [2018-07-24 10:52:56,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32 states. [2018-07-24 10:52:56,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 32 transitions. [2018-07-24 10:52:56,318 INFO L78 Accepts]: Start accepts. Automaton has 32 states and 32 transitions. Word has length 29 [2018-07-24 10:52:56,318 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:56,318 INFO L471 AbstractCegarLoop]: Abstraction has 32 states and 32 transitions. [2018-07-24 10:52:56,318 INFO L472 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-07-24 10:52:56,318 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 32 transitions. [2018-07-24 10:52:56,319 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-07-24 10:52:56,319 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:56,319 INFO L353 BasicCegarLoop]: trace histogram [11, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:56,320 INFO L414 AbstractCegarLoop]: === Iteration 12 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_simple_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:56,320 INFO L82 PathProgramCache]: Analyzing trace with hash -504978548, now seen corresponding path program 10 times [2018-07-24 10:52:56,320 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:56,320 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:56,321 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:56,321 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:56,321 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:56,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:56,506 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:56,507 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:56,507 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:56,517 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:52:56,518 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:52:56,529 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:52:56,529 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:56,531 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:56,545 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:56,545 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:57,003 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:57,024 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:57,025 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:57,040 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:52:57,040 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:52:57,065 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:52:57,065 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:57,068 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:57,097 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:57,097 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:57,129 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:57,130 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:57,130 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 24 [2018-07-24 10:52:57,130 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:57,131 INFO L450 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-07-24 10:52:57,131 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-07-24 10:52:57,131 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-07-24 10:52:57,132 INFO L87 Difference]: Start difference. First operand 32 states and 32 transitions. Second operand 13 states. [2018-07-24 10:52:57,292 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:57,293 INFO L93 Difference]: Finished difference Result 39 states and 39 transitions. [2018-07-24 10:52:57,293 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-07-24 10:52:57,293 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 31 [2018-07-24 10:52:57,294 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:57,294 INFO L225 Difference]: With dead ends: 39 [2018-07-24 10:52:57,295 INFO L226 Difference]: Without dead ends: 34 [2018-07-24 10:52:57,295 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 111 SyntacticMatches, 3 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-07-24 10:52:57,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-07-24 10:52:57,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 34. [2018-07-24 10:52:57,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34 states. [2018-07-24 10:52:57,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 34 transitions. [2018-07-24 10:52:57,300 INFO L78 Accepts]: Start accepts. Automaton has 34 states and 34 transitions. Word has length 31 [2018-07-24 10:52:57,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:57,300 INFO L471 AbstractCegarLoop]: Abstraction has 34 states and 34 transitions. [2018-07-24 10:52:57,300 INFO L472 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-07-24 10:52:57,300 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 34 transitions. [2018-07-24 10:52:57,301 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-07-24 10:52:57,301 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:57,301 INFO L353 BasicCegarLoop]: trace histogram [12, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:57,301 INFO L414 AbstractCegarLoop]: === Iteration 13 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_simple_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:57,301 INFO L82 PathProgramCache]: Analyzing trace with hash 1385097074, now seen corresponding path program 11 times [2018-07-24 10:52:57,302 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:57,302 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:57,302 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:57,303 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:57,303 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:57,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:57,680 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:57,680 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:57,680 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:57,688 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:52:57,688 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:20,478 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2018-07-24 10:54:20,478 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:23,460 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:23,491 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:23,491 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:23,993 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:23,996 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:23,997 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:24,012 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:54:24,013 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:24,158 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2018-07-24 10:54:24,159 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:24,163 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:24,226 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:24,227 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:24,283 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:24,285 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:24,286 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 26 [2018-07-24 10:54:24,286 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:24,287 INFO L450 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-07-24 10:54:24,287 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-07-24 10:54:24,287 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:54:24,288 INFO L87 Difference]: Start difference. First operand 34 states and 34 transitions. Second operand 14 states. [2018-07-24 10:54:24,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:24,562 INFO L93 Difference]: Finished difference Result 41 states and 41 transitions. [2018-07-24 10:54:24,566 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-07-24 10:54:24,567 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 33 [2018-07-24 10:54:24,567 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:24,567 INFO L225 Difference]: With dead ends: 41 [2018-07-24 10:54:24,567 INFO L226 Difference]: Without dead ends: 36 [2018-07-24 10:54:24,568 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 145 GetRequests, 118 SyntacticMatches, 3 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:54:24,568 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2018-07-24 10:54:24,571 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2018-07-24 10:54:24,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2018-07-24 10:54:24,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 36 transitions. [2018-07-24 10:54:24,573 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 36 transitions. Word has length 33 [2018-07-24 10:54:24,573 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:24,573 INFO L471 AbstractCegarLoop]: Abstraction has 36 states and 36 transitions. [2018-07-24 10:54:24,573 INFO L472 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-07-24 10:54:24,573 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 36 transitions. [2018-07-24 10:54:24,574 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-07-24 10:54:24,574 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:24,574 INFO L353 BasicCegarLoop]: trace histogram [13, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:24,574 INFO L414 AbstractCegarLoop]: === Iteration 14 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_simple_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:24,574 INFO L82 PathProgramCache]: Analyzing trace with hash 976603608, now seen corresponding path program 12 times [2018-07-24 10:54:24,575 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:24,575 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:24,575 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:24,576 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:24,576 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:24,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:24,954 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:24,955 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:24,955 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:24,963 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:54:24,963 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:04,622 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2018-07-24 10:56:04,622 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:07,401 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:07,441 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:07,441 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:08,040 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:08,044 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:08,044 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:08,061 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:56:08,062 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:08,235 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2018-07-24 10:56:08,235 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:08,239 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:08,257 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:08,257 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:08,273 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:08,275 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:08,275 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 28 [2018-07-24 10:56:08,275 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:08,275 INFO L450 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-07-24 10:56:08,276 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-07-24 10:56:08,277 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:56:08,277 INFO L87 Difference]: Start difference. First operand 36 states and 36 transitions. Second operand 15 states. [2018-07-24 10:56:08,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:08,416 INFO L93 Difference]: Finished difference Result 43 states and 43 transitions. [2018-07-24 10:56:08,417 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-07-24 10:56:08,417 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 35 [2018-07-24 10:56:08,418 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:08,419 INFO L225 Difference]: With dead ends: 43 [2018-07-24 10:56:08,419 INFO L226 Difference]: Without dead ends: 38 [2018-07-24 10:56:08,420 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 154 GetRequests, 125 SyntacticMatches, 3 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:56:08,420 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states. [2018-07-24 10:56:08,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 38. [2018-07-24 10:56:08,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2018-07-24 10:56:08,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 38 transitions. [2018-07-24 10:56:08,424 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 38 transitions. Word has length 35 [2018-07-24 10:56:08,424 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:08,424 INFO L471 AbstractCegarLoop]: Abstraction has 38 states and 38 transitions. [2018-07-24 10:56:08,425 INFO L472 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-07-24 10:56:08,425 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 38 transitions. [2018-07-24 10:56:08,425 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-07-24 10:56:08,425 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:08,425 INFO L353 BasicCegarLoop]: trace histogram [14, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:08,426 INFO L414 AbstractCegarLoop]: === Iteration 15 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_simple_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:08,426 INFO L82 PathProgramCache]: Analyzing trace with hash -743593282, now seen corresponding path program 13 times [2018-07-24 10:56:08,426 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:08,427 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:08,427 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:08,427 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:08,427 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:08,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:09,183 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:09,184 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:09,184 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:09,192 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:09,192 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:56:09,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:09,205 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:09,224 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:09,224 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:09,839 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:09,861 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:09,861 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:09,882 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:09,882 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:56:09,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:09,911 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:09,938 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:09,938 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:09,991 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:09,993 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:09,994 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 30 [2018-07-24 10:56:09,994 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:09,994 INFO L450 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-07-24 10:56:09,994 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-07-24 10:56:09,995 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:56:09,995 INFO L87 Difference]: Start difference. First operand 38 states and 38 transitions. Second operand 16 states. [2018-07-24 10:56:10,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:10,231 INFO L93 Difference]: Finished difference Result 45 states and 45 transitions. [2018-07-24 10:56:10,231 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-07-24 10:56:10,231 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 37 [2018-07-24 10:56:10,232 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:10,233 INFO L225 Difference]: With dead ends: 45 [2018-07-24 10:56:10,233 INFO L226 Difference]: Without dead ends: 40 [2018-07-24 10:56:10,234 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 163 GetRequests, 132 SyntacticMatches, 3 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:56:10,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-07-24 10:56:10,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 40. [2018-07-24 10:56:10,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40 states. [2018-07-24 10:56:10,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 40 transitions. [2018-07-24 10:56:10,239 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 40 transitions. Word has length 37 [2018-07-24 10:56:10,239 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:10,239 INFO L471 AbstractCegarLoop]: Abstraction has 40 states and 40 transitions. [2018-07-24 10:56:10,239 INFO L472 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-07-24 10:56:10,240 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 40 transitions. [2018-07-24 10:56:10,240 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-07-24 10:56:10,240 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:10,240 INFO L353 BasicCegarLoop]: trace histogram [15, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:10,241 INFO L414 AbstractCegarLoop]: === Iteration 16 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_simple_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:10,241 INFO L82 PathProgramCache]: Analyzing trace with hash -290395612, now seen corresponding path program 14 times [2018-07-24 10:56:10,241 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:10,242 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:10,242 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:10,242 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:10,242 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:10,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:10,752 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:10,753 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:10,753 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:10,761 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:10,761 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:10,775 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:10,775 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:10,777 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:10,789 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:10,789 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:11,469 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:11,489 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:11,489 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:11,504 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:11,505 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:11,535 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:11,535 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:11,539 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:11,564 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:11,564 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:11,576 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:11,579 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:11,579 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 32 [2018-07-24 10:56:11,579 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:11,580 INFO L450 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-07-24 10:56:11,580 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-07-24 10:56:11,580 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:56:11,581 INFO L87 Difference]: Start difference. First operand 40 states and 40 transitions. Second operand 17 states. [2018-07-24 10:56:11,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:11,801 INFO L93 Difference]: Finished difference Result 47 states and 47 transitions. [2018-07-24 10:56:11,802 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-07-24 10:56:11,803 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 39 [2018-07-24 10:56:11,803 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:11,803 INFO L225 Difference]: With dead ends: 47 [2018-07-24 10:56:11,803 INFO L226 Difference]: Without dead ends: 42 [2018-07-24 10:56:11,804 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 172 GetRequests, 139 SyntacticMatches, 3 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:56:11,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states. [2018-07-24 10:56:11,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 42. [2018-07-24 10:56:11,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2018-07-24 10:56:11,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 42 transitions. [2018-07-24 10:56:11,809 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 42 transitions. Word has length 39 [2018-07-24 10:56:11,809 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:11,809 INFO L471 AbstractCegarLoop]: Abstraction has 42 states and 42 transitions. [2018-07-24 10:56:11,809 INFO L472 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-07-24 10:56:11,809 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 42 transitions. [2018-07-24 10:56:11,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-07-24 10:56:11,810 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:11,810 INFO L353 BasicCegarLoop]: trace histogram [16, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:11,810 INFO L414 AbstractCegarLoop]: === Iteration 17 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_simple_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:11,811 INFO L82 PathProgramCache]: Analyzing trace with hash 1440868362, now seen corresponding path program 15 times [2018-07-24 10:56:11,811 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:11,811 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:11,812 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:11,812 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:11,812 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:11,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:12,086 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:12,086 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:12,086 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:12,097 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:56:12,097 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:57:25,226 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-07-24 10:57:25,226 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:25,583 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:25,598 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:25,599 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:26,428 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:26,448 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:26,449 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:26,464 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:57:26,464 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:57:26,694 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-07-24 10:57:26,694 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:26,698 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:26,731 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:26,732 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:26,745 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:26,747 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:26,747 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 34 [2018-07-24 10:57:26,747 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:26,747 INFO L450 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-07-24 10:57:26,748 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-07-24 10:57:26,748 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:57:26,748 INFO L87 Difference]: Start difference. First operand 42 states and 42 transitions. Second operand 18 states. [2018-07-24 10:57:26,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:26,978 INFO L93 Difference]: Finished difference Result 49 states and 49 transitions. [2018-07-24 10:57:26,979 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-07-24 10:57:26,979 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 41 [2018-07-24 10:57:26,979 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:26,980 INFO L225 Difference]: With dead ends: 49 [2018-07-24 10:57:26,980 INFO L226 Difference]: Without dead ends: 44 [2018-07-24 10:57:26,981 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 181 GetRequests, 146 SyntacticMatches, 3 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:57:26,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2018-07-24 10:57:26,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 44. [2018-07-24 10:57:26,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2018-07-24 10:57:26,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 44 transitions. [2018-07-24 10:57:26,987 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 44 transitions. Word has length 41 [2018-07-24 10:57:26,987 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:26,987 INFO L471 AbstractCegarLoop]: Abstraction has 44 states and 44 transitions. [2018-07-24 10:57:26,987 INFO L472 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-07-24 10:57:26,988 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 44 transitions. [2018-07-24 10:57:26,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-07-24 10:57:26,988 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:26,989 INFO L353 BasicCegarLoop]: trace histogram [17, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:26,989 INFO L414 AbstractCegarLoop]: === Iteration 18 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_simple_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:26,989 INFO L82 PathProgramCache]: Analyzing trace with hash -1261763472, now seen corresponding path program 16 times [2018-07-24 10:57:26,989 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:26,990 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:26,990 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:26,990 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:26,990 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:26,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:27,613 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:27,614 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:27,614 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:27,621 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:57:27,622 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:57:27,636 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:57:27,636 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:27,638 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:27,673 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:27,673 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:28,619 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:28,641 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:28,641 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:28,657 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:57:28,657 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:57:28,688 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:57:28,689 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:28,693 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:28,770 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:28,771 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:28,777 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:28,778 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:28,779 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 36 [2018-07-24 10:57:28,779 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:28,779 INFO L450 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-07-24 10:57:28,779 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-07-24 10:57:28,780 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:57:28,780 INFO L87 Difference]: Start difference. First operand 44 states and 44 transitions. Second operand 19 states. [2018-07-24 10:57:29,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:29,074 INFO L93 Difference]: Finished difference Result 51 states and 51 transitions. [2018-07-24 10:57:29,075 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-07-24 10:57:29,075 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 43 [2018-07-24 10:57:29,075 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:29,076 INFO L225 Difference]: With dead ends: 51 [2018-07-24 10:57:29,076 INFO L226 Difference]: Without dead ends: 46 [2018-07-24 10:57:29,077 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 190 GetRequests, 153 SyntacticMatches, 3 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:57:29,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states. [2018-07-24 10:57:29,081 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 46. [2018-07-24 10:57:29,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-07-24 10:57:29,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 46 transitions. [2018-07-24 10:57:29,082 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 46 transitions. Word has length 43 [2018-07-24 10:57:29,083 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:29,083 INFO L471 AbstractCegarLoop]: Abstraction has 46 states and 46 transitions. [2018-07-24 10:57:29,083 INFO L472 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-07-24 10:57:29,083 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 46 transitions. [2018-07-24 10:57:29,084 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-07-24 10:57:29,084 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:29,084 INFO L353 BasicCegarLoop]: trace histogram [18, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:29,084 INFO L414 AbstractCegarLoop]: === Iteration 19 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_simple_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:29,084 INFO L82 PathProgramCache]: Analyzing trace with hash -35741866, now seen corresponding path program 17 times [2018-07-24 10:57:29,084 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:29,085 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:29,085 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:29,085 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:29,085 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:29,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:29,485 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:29,486 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:29,486 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:29,494 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:57:29,495 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) Received shutdown request... Cannot interrupt operation gracefully because timeout expired. Forcing shutdown