java -Xmx8000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml --generate-csv --csv-dir csv -s ../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf -i ../../../trunk/examples/svcomp/loop-invgen/up_true-unreach-call_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-dd2f093 [2018-07-24 10:54:43,021 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-07-24 10:54:43,023 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-07-24 10:54:43,035 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-07-24 10:54:43,036 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-07-24 10:54:43,037 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-07-24 10:54:43,038 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-07-24 10:54:43,040 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-07-24 10:54:43,042 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-07-24 10:54:43,043 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-07-24 10:54:43,044 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-07-24 10:54:43,044 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-07-24 10:54:43,045 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-07-24 10:54:43,046 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-07-24 10:54:43,047 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-07-24 10:54:43,048 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-07-24 10:54:43,048 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-07-24 10:54:43,053 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-07-24 10:54:43,056 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-07-24 10:54:43,058 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-07-24 10:54:43,059 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-07-24 10:54:43,063 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-07-24 10:54:43,066 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-07-24 10:54:43,067 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-07-24 10:54:43,067 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-07-24 10:54:43,068 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-07-24 10:54:43,069 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-07-24 10:54:43,070 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-07-24 10:54:43,074 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-07-24 10:54:43,075 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-07-24 10:54:43,075 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-07-24 10:54:43,077 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-07-24 10:54:43,077 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-07-24 10:54:43,077 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-07-24 10:54:43,078 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-07-24 10:54:43,080 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-07-24 10:54:43,080 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf [2018-07-24 10:54:43,102 INFO L110 SettingsManager]: Loading preferences was successful [2018-07-24 10:54:43,102 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-07-24 10:54:43,103 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-07-24 10:54:43,103 INFO L133 SettingsManager]: * User list type=DISABLED [2018-07-24 10:54:43,103 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-07-24 10:54:43,103 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-07-24 10:54:43,103 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-07-24 10:54:43,104 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-07-24 10:54:43,104 INFO L133 SettingsManager]: * Log string format=TERM [2018-07-24 10:54:43,104 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-07-24 10:54:43,104 INFO L133 SettingsManager]: * Interval Domain=false [2018-07-24 10:54:43,105 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-07-24 10:54:43,105 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-07-24 10:54:43,105 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-07-24 10:54:43,106 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-07-24 10:54:43,106 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-07-24 10:54:43,106 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-07-24 10:54:43,106 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-07-24 10:54:43,107 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-07-24 10:54:43,107 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-07-24 10:54:43,107 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-07-24 10:54:43,107 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-07-24 10:54:43,107 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-07-24 10:54:43,108 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:54:43,108 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-07-24 10:54:43,108 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-07-24 10:54:43,108 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-07-24 10:54:43,108 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-07-24 10:54:43,109 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-07-24 10:54:43,109 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-07-24 10:54:43,109 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-07-24 10:54:43,109 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-07-24 10:54:43,109 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-07-24 10:54:43,177 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-07-24 10:54:43,193 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-07-24 10:54:43,200 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-07-24 10:54:43,202 INFO L271 PluginConnector]: Initializing CDTParser... [2018-07-24 10:54:43,202 INFO L276 PluginConnector]: CDTParser initialized [2018-07-24 10:54:43,203 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-invgen/up_true-unreach-call_true-termination.i [2018-07-24 10:54:43,551 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/38ae5d81c/3223d33575aa40ca93cc20aef61d197c/FLAG659837f28 [2018-07-24 10:54:43,700 INFO L276 CDTParser]: Found 1 translation units. [2018-07-24 10:54:43,701 INFO L158 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-invgen/up_true-unreach-call_true-termination.i [2018-07-24 10:54:43,706 INFO L324 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/38ae5d81c/3223d33575aa40ca93cc20aef61d197c/FLAG659837f28 [2018-07-24 10:54:43,721 INFO L332 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/38ae5d81c/3223d33575aa40ca93cc20aef61d197c [2018-07-24 10:54:43,734 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-07-24 10:54:43,735 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-07-24 10:54:43,737 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-07-24 10:54:43,737 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-07-24 10:54:43,743 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-07-24 10:54:43,744 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:54:43" (1/1) ... [2018-07-24 10:54:43,747 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3cd04cac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:43, skipping insertion in model container [2018-07-24 10:54:43,748 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:54:43" (1/1) ... [2018-07-24 10:54:43,929 INFO L179 PRDispatcher]: Starting pre-run dispatcher in SV-COMP mode [2018-07-24 10:54:43,974 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:54:43,991 INFO L422 MainDispatcher]: Starting main dispatcher in SV-COMP mode [2018-07-24 10:54:43,999 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:54:44,023 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:44 WrapperNode [2018-07-24 10:54:44,023 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-07-24 10:54:44,027 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-07-24 10:54:44,027 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-07-24 10:54:44,027 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-07-24 10:54:44,037 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:44" (1/1) ... [2018-07-24 10:54:44,044 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:44" (1/1) ... [2018-07-24 10:54:44,051 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-07-24 10:54:44,051 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-07-24 10:54:44,051 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-07-24 10:54:44,051 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-07-24 10:54:44,062 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:44" (1/1) ... [2018-07-24 10:54:44,062 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:44" (1/1) ... [2018-07-24 10:54:44,063 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:44" (1/1) ... [2018-07-24 10:54:44,063 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:44" (1/1) ... [2018-07-24 10:54:44,068 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:44" (1/1) ... [2018-07-24 10:54:44,074 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:44" (1/1) ... [2018-07-24 10:54:44,075 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:44" (1/1) ... [2018-07-24 10:54:44,077 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-07-24 10:54:44,078 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-07-24 10:54:44,083 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-07-24 10:54:44,084 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-07-24 10:54:44,085 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:44" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:54:44,160 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-07-24 10:54:44,160 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-07-24 10:54:44,160 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-07-24 10:54:44,161 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-07-24 10:54:44,161 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-07-24 10:54:44,161 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-07-24 10:54:44,161 INFO L130 BoogieDeclarations]: Found specification of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assert [2018-07-24 10:54:44,162 INFO L138 BoogieDeclarations]: Found implementation of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assert [2018-07-24 10:54:44,521 INFO L261 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-07-24 10:54:44,522 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:54:44 BoogieIcfgContainer [2018-07-24 10:54:44,522 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-07-24 10:54:44,523 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-07-24 10:54:44,523 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-07-24 10:54:44,526 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-07-24 10:54:44,527 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.07 10:54:43" (1/3) ... [2018-07-24 10:54:44,527 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@f1c763c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:54:44, skipping insertion in model container [2018-07-24 10:54:44,528 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:54:44" (2/3) ... [2018-07-24 10:54:44,528 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@f1c763c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:54:44, skipping insertion in model container [2018-07-24 10:54:44,529 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:54:44" (3/3) ... [2018-07-24 10:54:44,531 INFO L112 eAbstractionObserver]: Analyzing ICFG up_true-unreach-call_true-termination.i [2018-07-24 10:54:44,541 INFO L132 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-07-24 10:54:44,550 INFO L144 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-07-24 10:54:44,601 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-07-24 10:54:44,602 INFO L373 AbstractCegarLoop]: Interprodecural is true [2018-07-24 10:54:44,602 INFO L374 AbstractCegarLoop]: Hoare is true [2018-07-24 10:54:44,602 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-07-24 10:54:44,602 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-07-24 10:54:44,602 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-07-24 10:54:44,603 INFO L378 AbstractCegarLoop]: Difference is false [2018-07-24 10:54:44,603 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-07-24 10:54:44,603 INFO L384 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-07-24 10:54:44,621 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states. [2018-07-24 10:54:44,628 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-07-24 10:54:44,628 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:44,630 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:44,630 INFO L414 AbstractCegarLoop]: === Iteration 1 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:44,642 INFO L82 PathProgramCache]: Analyzing trace with hash -1884544245, now seen corresponding path program 1 times [2018-07-24 10:54:44,649 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:44,711 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:44,712 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:44,712 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:44,712 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:44,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:44,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:44,783 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:54:44,783 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-07-24 10:54:44,784 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:54:44,788 INFO L450 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-07-24 10:54:44,803 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-07-24 10:54:44,804 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:54:44,807 INFO L87 Difference]: Start difference. First operand 22 states. Second operand 2 states. [2018-07-24 10:54:44,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:44,836 INFO L93 Difference]: Finished difference Result 37 states and 44 transitions. [2018-07-24 10:54:44,837 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-07-24 10:54:44,840 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 13 [2018-07-24 10:54:44,840 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:44,850 INFO L225 Difference]: With dead ends: 37 [2018-07-24 10:54:44,856 INFO L226 Difference]: Without dead ends: 18 [2018-07-24 10:54:44,860 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:54:44,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states. [2018-07-24 10:54:44,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 18. [2018-07-24 10:54:44,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2018-07-24 10:54:44,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 19 transitions. [2018-07-24 10:54:44,898 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 19 transitions. Word has length 13 [2018-07-24 10:54:44,898 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:44,899 INFO L471 AbstractCegarLoop]: Abstraction has 18 states and 19 transitions. [2018-07-24 10:54:44,899 INFO L472 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-07-24 10:54:44,899 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 19 transitions. [2018-07-24 10:54:44,900 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-07-24 10:54:44,900 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:44,900 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:44,900 INFO L414 AbstractCegarLoop]: === Iteration 2 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:44,901 INFO L82 PathProgramCache]: Analyzing trace with hash 1969781111, now seen corresponding path program 1 times [2018-07-24 10:54:44,901 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:44,902 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:44,902 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:44,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:44,903 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:44,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:45,005 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:45,006 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:54:45,006 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-07-24 10:54:45,006 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:54:45,008 INFO L450 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-07-24 10:54:45,009 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-07-24 10:54:45,009 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-07-24 10:54:45,009 INFO L87 Difference]: Start difference. First operand 18 states and 19 transitions. Second operand 5 states. [2018-07-24 10:54:45,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:45,138 INFO L93 Difference]: Finished difference Result 33 states and 35 transitions. [2018-07-24 10:54:45,138 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-07-24 10:54:45,138 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 14 [2018-07-24 10:54:45,139 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:45,139 INFO L225 Difference]: With dead ends: 33 [2018-07-24 10:54:45,140 INFO L226 Difference]: Without dead ends: 20 [2018-07-24 10:54:45,141 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-07-24 10:54:45,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2018-07-24 10:54:45,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2018-07-24 10:54:45,145 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2018-07-24 10:54:45,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 21 transitions. [2018-07-24 10:54:45,147 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 21 transitions. Word has length 14 [2018-07-24 10:54:45,147 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:45,147 INFO L471 AbstractCegarLoop]: Abstraction has 20 states and 21 transitions. [2018-07-24 10:54:45,147 INFO L472 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-07-24 10:54:45,148 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 21 transitions. [2018-07-24 10:54:45,148 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-07-24 10:54:45,148 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:45,149 INFO L353 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:45,150 INFO L414 AbstractCegarLoop]: === Iteration 3 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:45,151 INFO L82 PathProgramCache]: Analyzing trace with hash -1960344783, now seen corresponding path program 1 times [2018-07-24 10:54:45,151 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:45,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:45,152 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:45,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:45,152 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:45,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:45,269 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:45,270 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:54:45,270 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-07-24 10:54:45,270 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:54:45,271 INFO L450 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-07-24 10:54:45,271 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-07-24 10:54:45,271 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-07-24 10:54:45,272 INFO L87 Difference]: Start difference. First operand 20 states and 21 transitions. Second operand 6 states. [2018-07-24 10:54:45,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:45,440 INFO L93 Difference]: Finished difference Result 34 states and 36 transitions. [2018-07-24 10:54:45,441 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-07-24 10:54:45,441 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 16 [2018-07-24 10:54:45,445 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:45,449 INFO L225 Difference]: With dead ends: 34 [2018-07-24 10:54:45,449 INFO L226 Difference]: Without dead ends: 32 [2018-07-24 10:54:45,450 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-07-24 10:54:45,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states. [2018-07-24 10:54:45,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 27. [2018-07-24 10:54:45,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27 states. [2018-07-24 10:54:45,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 28 transitions. [2018-07-24 10:54:45,471 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 28 transitions. Word has length 16 [2018-07-24 10:54:45,471 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:45,472 INFO L471 AbstractCegarLoop]: Abstraction has 27 states and 28 transitions. [2018-07-24 10:54:45,472 INFO L472 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-07-24 10:54:45,472 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 28 transitions. [2018-07-24 10:54:45,473 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-07-24 10:54:45,473 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:45,474 INFO L353 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:45,474 INFO L414 AbstractCegarLoop]: === Iteration 4 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:45,474 INFO L82 PathProgramCache]: Analyzing trace with hash -1864992939, now seen corresponding path program 1 times [2018-07-24 10:54:45,475 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:45,476 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:45,477 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:45,477 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:45,477 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:45,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:45,738 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:45,739 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:45,739 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:45,758 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:45,758 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:45,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:45,798 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:45,899 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:45,900 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:45,975 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:46,005 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:46,005 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:46,024 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:46,024 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:46,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:46,046 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:46,054 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:46,055 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:46,221 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:46,223 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:46,226 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 9 [2018-07-24 10:54:46,227 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:46,227 INFO L450 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-07-24 10:54:46,227 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-07-24 10:54:46,228 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-07-24 10:54:46,228 INFO L87 Difference]: Start difference. First operand 27 states and 28 transitions. Second operand 9 states. [2018-07-24 10:54:46,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:46,348 INFO L93 Difference]: Finished difference Result 46 states and 49 transitions. [2018-07-24 10:54:46,349 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-07-24 10:54:46,349 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 24 [2018-07-24 10:54:46,349 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:46,352 INFO L225 Difference]: With dead ends: 46 [2018-07-24 10:54:46,352 INFO L226 Difference]: Without dead ends: 29 [2018-07-24 10:54:46,353 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 104 GetRequests, 86 SyntacticMatches, 8 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=44, Invalid=88, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:54:46,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2018-07-24 10:54:46,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2018-07-24 10:54:46,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2018-07-24 10:54:46,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 30 transitions. [2018-07-24 10:54:46,359 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 30 transitions. Word has length 24 [2018-07-24 10:54:46,360 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:46,360 INFO L471 AbstractCegarLoop]: Abstraction has 29 states and 30 transitions. [2018-07-24 10:54:46,360 INFO L472 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-07-24 10:54:46,360 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 30 transitions. [2018-07-24 10:54:46,361 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-07-24 10:54:46,361 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:46,361 INFO L353 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:46,361 INFO L414 AbstractCegarLoop]: === Iteration 5 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:46,362 INFO L82 PathProgramCache]: Analyzing trace with hash -62381937, now seen corresponding path program 2 times [2018-07-24 10:54:46,362 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:46,363 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:46,363 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:46,363 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:46,363 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:46,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:46,540 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 7 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:46,541 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:46,541 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:46,549 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:46,550 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:46,586 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:46,586 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:46,590 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:46,884 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:46,884 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:46,928 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:46,949 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:46,950 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:46,965 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:46,965 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:46,988 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:46,988 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:46,993 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:47,001 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:47,001 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:47,116 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:47,118 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:47,118 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7, 7, 7] total 10 [2018-07-24 10:54:47,118 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:47,118 INFO L450 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-07-24 10:54:47,119 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-07-24 10:54:47,119 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=68, Unknown=0, NotChecked=0, Total=90 [2018-07-24 10:54:47,119 INFO L87 Difference]: Start difference. First operand 29 states and 30 transitions. Second operand 10 states. [2018-07-24 10:54:47,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:47,322 INFO L93 Difference]: Finished difference Result 39 states and 40 transitions. [2018-07-24 10:54:47,323 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-07-24 10:54:47,323 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 26 [2018-07-24 10:54:47,324 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:47,325 INFO L225 Difference]: With dead ends: 39 [2018-07-24 10:54:47,325 INFO L226 Difference]: Without dead ends: 37 [2018-07-24 10:54:47,326 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 95 SyntacticMatches, 10 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 30 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=35, Invalid=97, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:54:47,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2018-07-24 10:54:47,331 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 37. [2018-07-24 10:54:47,331 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2018-07-24 10:54:47,332 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 38 transitions. [2018-07-24 10:54:47,332 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 38 transitions. Word has length 26 [2018-07-24 10:54:47,333 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:47,333 INFO L471 AbstractCegarLoop]: Abstraction has 37 states and 38 transitions. [2018-07-24 10:54:47,333 INFO L472 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-07-24 10:54:47,333 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 38 transitions. [2018-07-24 10:54:47,334 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-07-24 10:54:47,334 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:47,335 INFO L353 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:47,335 INFO L414 AbstractCegarLoop]: === Iteration 6 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:47,335 INFO L82 PathProgramCache]: Analyzing trace with hash 1261098675, now seen corresponding path program 3 times [2018-07-24 10:54:47,335 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:47,336 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:47,337 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:47,337 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:47,337 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:47,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:47,458 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:47,458 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:47,458 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:47,476 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:47,477 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:47,509 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-07-24 10:54:47,510 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:47,513 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:47,654 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:47,655 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:47,757 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:47,777 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:47,778 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:47,798 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:47,798 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:47,830 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-07-24 10:54:47,831 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:47,835 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:47,845 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:47,845 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:47,952 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:47,953 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:47,954 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 12 [2018-07-24 10:54:47,954 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:47,954 INFO L450 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-07-24 10:54:47,955 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-07-24 10:54:47,955 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=93, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:54:47,956 INFO L87 Difference]: Start difference. First operand 37 states and 38 transitions. Second operand 12 states. [2018-07-24 10:54:48,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:48,119 INFO L93 Difference]: Finished difference Result 60 states and 64 transitions. [2018-07-24 10:54:48,121 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-07-24 10:54:48,122 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 34 [2018-07-24 10:54:48,122 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:48,123 INFO L225 Difference]: With dead ends: 60 [2018-07-24 10:54:48,123 INFO L226 Difference]: Without dead ends: 39 [2018-07-24 10:54:48,124 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 147 GetRequests, 121 SyntacticMatches, 12 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 76 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=73, Invalid=167, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:54:48,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states. [2018-07-24 10:54:48,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 39. [2018-07-24 10:54:48,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2018-07-24 10:54:48,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 40 transitions. [2018-07-24 10:54:48,132 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 40 transitions. Word has length 34 [2018-07-24 10:54:48,132 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:48,133 INFO L471 AbstractCegarLoop]: Abstraction has 39 states and 40 transitions. [2018-07-24 10:54:48,133 INFO L472 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-07-24 10:54:48,133 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 40 transitions. [2018-07-24 10:54:48,134 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-07-24 10:54:48,134 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:48,134 INFO L353 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:48,134 INFO L414 AbstractCegarLoop]: === Iteration 7 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:48,135 INFO L82 PathProgramCache]: Analyzing trace with hash -1825718419, now seen corresponding path program 4 times [2018-07-24 10:54:48,135 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:48,136 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:48,136 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:48,136 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:48,136 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:48,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:48,269 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 15 proven. 14 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-07-24 10:54:48,270 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:48,270 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:48,277 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:54:48,278 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:54:48,323 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:54:48,324 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:48,326 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:48,538 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:48,539 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:48,669 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:48,690 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:48,690 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:48,707 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:54:48,708 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:54:48,737 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:54:48,737 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:48,742 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:48,751 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:48,751 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:48,830 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:54:48,833 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:48,833 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 8, 8, 8] total 11 [2018-07-24 10:54:48,833 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:48,834 INFO L450 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-07-24 10:54:48,834 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-07-24 10:54:48,834 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2018-07-24 10:54:48,835 INFO L87 Difference]: Start difference. First operand 39 states and 40 transitions. Second operand 11 states. [2018-07-24 10:54:48,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:48,994 INFO L93 Difference]: Finished difference Result 49 states and 50 transitions. [2018-07-24 10:54:48,994 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-07-24 10:54:48,994 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 36 [2018-07-24 10:54:48,995 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:48,996 INFO L225 Difference]: With dead ends: 49 [2018-07-24 10:54:48,996 INFO L226 Difference]: Without dead ends: 47 [2018-07-24 10:54:48,997 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 157 GetRequests, 132 SyntacticMatches, 14 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 49 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=40, Invalid=116, Unknown=0, NotChecked=0, Total=156 [2018-07-24 10:54:48,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2018-07-24 10:54:49,003 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 47. [2018-07-24 10:54:49,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47 states. [2018-07-24 10:54:49,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 48 transitions. [2018-07-24 10:54:49,004 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 48 transitions. Word has length 36 [2018-07-24 10:54:49,005 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:49,005 INFO L471 AbstractCegarLoop]: Abstraction has 47 states and 48 transitions. [2018-07-24 10:54:49,005 INFO L472 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-07-24 10:54:49,005 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 48 transitions. [2018-07-24 10:54:49,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-07-24 10:54:49,007 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:49,007 INFO L353 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:49,007 INFO L414 AbstractCegarLoop]: === Iteration 8 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:49,007 INFO L82 PathProgramCache]: Analyzing trace with hash -51726447, now seen corresponding path program 5 times [2018-07-24 10:54:49,008 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:49,009 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:49,009 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:49,009 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:49,009 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:49,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:49,148 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:49,148 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:49,149 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:49,157 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:54:49,157 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:49,196 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2018-07-24 10:54:49,196 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:49,200 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:49,322 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:49,322 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:49,413 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:49,434 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:49,434 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:49,452 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:54:49,452 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:49,503 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2018-07-24 10:54:49,504 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:49,508 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:49,520 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:49,520 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:49,961 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:49,970 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:49,970 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 15 [2018-07-24 10:54:49,970 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:49,972 INFO L450 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-07-24 10:54:49,972 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-07-24 10:54:49,973 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=151, Unknown=0, NotChecked=0, Total=210 [2018-07-24 10:54:49,973 INFO L87 Difference]: Start difference. First operand 47 states and 48 transitions. Second operand 15 states. [2018-07-24 10:54:50,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:50,260 INFO L93 Difference]: Finished difference Result 74 states and 79 transitions. [2018-07-24 10:54:50,262 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-07-24 10:54:50,262 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 44 [2018-07-24 10:54:50,262 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:50,263 INFO L225 Difference]: With dead ends: 74 [2018-07-24 10:54:50,263 INFO L226 Difference]: Without dead ends: 49 [2018-07-24 10:54:50,264 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 190 GetRequests, 156 SyntacticMatches, 16 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 144 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=109, Invalid=271, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:54:50,264 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-07-24 10:54:50,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 49. [2018-07-24 10:54:50,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2018-07-24 10:54:50,272 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 50 transitions. [2018-07-24 10:54:50,272 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 50 transitions. Word has length 44 [2018-07-24 10:54:50,272 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:50,272 INFO L471 AbstractCegarLoop]: Abstraction has 49 states and 50 transitions. [2018-07-24 10:54:50,273 INFO L472 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-07-24 10:54:50,273 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 50 transitions. [2018-07-24 10:54:50,274 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-07-24 10:54:50,274 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:50,274 INFO L353 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:50,275 INFO L414 AbstractCegarLoop]: === Iteration 9 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:50,275 INFO L82 PathProgramCache]: Analyzing trace with hash 446005195, now seen corresponding path program 6 times [2018-07-24 10:54:50,275 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:50,276 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:50,276 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:50,276 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:50,276 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:50,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:50,400 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 25 proven. 28 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-07-24 10:54:50,400 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:50,401 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:50,408 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:54:50,408 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:54:50,438 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2018-07-24 10:54:50,438 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:50,442 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:50,482 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 26 proven. 21 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:50,482 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:50,548 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 26 proven. 21 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:50,569 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:50,569 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:50,585 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:54:50,585 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:54:50,633 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2018-07-24 10:54:50,634 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:50,637 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:50,648 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 26 proven. 21 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:50,648 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:50,765 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 26 proven. 21 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:50,767 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:50,767 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 9, 9, 9] total 12 [2018-07-24 10:54:50,767 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:50,768 INFO L450 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-07-24 10:54:50,768 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-07-24 10:54:50,768 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=99, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:54:50,769 INFO L87 Difference]: Start difference. First operand 49 states and 50 transitions. Second operand 12 states. [2018-07-24 10:54:50,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:50,958 INFO L93 Difference]: Finished difference Result 59 states and 60 transitions. [2018-07-24 10:54:50,959 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-07-24 10:54:50,959 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 46 [2018-07-24 10:54:50,960 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:50,960 INFO L225 Difference]: With dead ends: 59 [2018-07-24 10:54:50,961 INFO L226 Difference]: Without dead ends: 57 [2018-07-24 10:54:50,961 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 199 GetRequests, 169 SyntacticMatches, 18 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 72 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=46, Invalid=136, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:54:50,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states. [2018-07-24 10:54:50,967 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 57. [2018-07-24 10:54:50,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 57 states. [2018-07-24 10:54:50,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 58 transitions. [2018-07-24 10:54:50,968 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 58 transitions. Word has length 46 [2018-07-24 10:54:50,968 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:50,969 INFO L471 AbstractCegarLoop]: Abstraction has 57 states and 58 transitions. [2018-07-24 10:54:50,969 INFO L472 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-07-24 10:54:50,969 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 58 transitions. [2018-07-24 10:54:50,970 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-07-24 10:54:50,970 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:50,970 INFO L353 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:50,970 INFO L414 AbstractCegarLoop]: === Iteration 10 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:50,970 INFO L82 PathProgramCache]: Analyzing trace with hash -239912465, now seen corresponding path program 7 times [2018-07-24 10:54:50,971 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:50,971 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:50,972 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:50,972 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:50,972 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:50,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:51,136 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:51,137 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:51,137 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:51,150 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:51,150 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:51,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:51,188 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:51,717 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:51,717 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:51,835 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:51,856 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:51,856 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:51,871 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:51,871 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:51,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:51,914 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:51,927 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:51,928 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:52,230 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:52,235 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:52,236 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 18 [2018-07-24 10:54:52,236 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:52,237 INFO L450 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-07-24 10:54:52,237 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-07-24 10:54:52,237 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=223, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:54:52,238 INFO L87 Difference]: Start difference. First operand 57 states and 58 transitions. Second operand 18 states. [2018-07-24 10:54:52,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:52,550 INFO L93 Difference]: Finished difference Result 88 states and 94 transitions. [2018-07-24 10:54:52,551 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-07-24 10:54:52,551 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 54 [2018-07-24 10:54:52,551 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:52,552 INFO L225 Difference]: With dead ends: 88 [2018-07-24 10:54:52,552 INFO L226 Difference]: Without dead ends: 59 [2018-07-24 10:54:52,553 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 233 GetRequests, 191 SyntacticMatches, 20 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 233 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=152, Invalid=400, Unknown=0, NotChecked=0, Total=552 [2018-07-24 10:54:52,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-07-24 10:54:52,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 59. [2018-07-24 10:54:52,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 59 states. [2018-07-24 10:54:52,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 60 transitions. [2018-07-24 10:54:52,560 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 60 transitions. Word has length 54 [2018-07-24 10:54:52,561 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:52,561 INFO L471 AbstractCegarLoop]: Abstraction has 59 states and 60 transitions. [2018-07-24 10:54:52,561 INFO L472 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-07-24 10:54:52,561 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 60 transitions. [2018-07-24 10:54:52,562 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-07-24 10:54:52,562 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:52,562 INFO L353 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:52,562 INFO L414 AbstractCegarLoop]: === Iteration 11 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:52,563 INFO L82 PathProgramCache]: Analyzing trace with hash -363560535, now seen corresponding path program 8 times [2018-07-24 10:54:52,563 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:52,563 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:52,564 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:52,564 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:52,564 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:52,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:52,760 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 37 proven. 46 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-07-24 10:54:52,760 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:52,760 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:52,773 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:52,773 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:52,805 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:52,806 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:52,808 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:52,972 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 36 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:52,972 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:53,067 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 36 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:53,087 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:53,088 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:53,105 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:53,105 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:53,147 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:53,147 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:53,150 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:53,158 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 36 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:53,158 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:53,255 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 36 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:53,257 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:53,257 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 10, 10, 10] total 13 [2018-07-24 10:54:53,257 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:53,258 INFO L450 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-07-24 10:54:53,258 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-07-24 10:54:53,258 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=116, Unknown=0, NotChecked=0, Total=156 [2018-07-24 10:54:53,258 INFO L87 Difference]: Start difference. First operand 59 states and 60 transitions. Second operand 13 states. [2018-07-24 10:54:53,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:53,396 INFO L93 Difference]: Finished difference Result 69 states and 70 transitions. [2018-07-24 10:54:53,397 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-07-24 10:54:53,397 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 56 [2018-07-24 10:54:53,397 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:53,399 INFO L225 Difference]: With dead ends: 69 [2018-07-24 10:54:53,399 INFO L226 Difference]: Without dead ends: 67 [2018-07-24 10:54:53,399 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 241 GetRequests, 206 SyntacticMatches, 22 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 99 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=53, Invalid=157, Unknown=0, NotChecked=0, Total=210 [2018-07-24 10:54:53,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2018-07-24 10:54:53,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 67. [2018-07-24 10:54:53,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67 states. [2018-07-24 10:54:53,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 68 transitions. [2018-07-24 10:54:53,406 INFO L78 Accepts]: Start accepts. Automaton has 67 states and 68 transitions. Word has length 56 [2018-07-24 10:54:53,406 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:53,407 INFO L471 AbstractCegarLoop]: Abstraction has 67 states and 68 transitions. [2018-07-24 10:54:53,407 INFO L472 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-07-24 10:54:53,407 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 68 transitions. [2018-07-24 10:54:53,408 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-07-24 10:54:53,408 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:53,408 INFO L353 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:53,408 INFO L414 AbstractCegarLoop]: === Iteration 12 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:53,408 INFO L82 PathProgramCache]: Analyzing trace with hash 1782152653, now seen corresponding path program 9 times [2018-07-24 10:54:53,408 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:53,409 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:53,409 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:53,409 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:53,410 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:53,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:53,603 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:53,604 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:53,604 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:53,618 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:53,618 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:53,657 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-07-24 10:54:53,658 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:53,659 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:53,921 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:53,921 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:54,026 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:54,046 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:54,046 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:54,062 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:54,062 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:54,131 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-07-24 10:54:54,132 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:54,135 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:54,146 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:54,147 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:54,282 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:54,283 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:54,283 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 21 [2018-07-24 10:54:54,283 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:54,284 INFO L450 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-07-24 10:54:54,284 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-07-24 10:54:54,285 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=111, Invalid=309, Unknown=0, NotChecked=0, Total=420 [2018-07-24 10:54:54,285 INFO L87 Difference]: Start difference. First operand 67 states and 68 transitions. Second operand 21 states. [2018-07-24 10:54:54,702 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:54,702 INFO L93 Difference]: Finished difference Result 102 states and 109 transitions. [2018-07-24 10:54:54,702 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-07-24 10:54:54,702 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 64 [2018-07-24 10:54:54,703 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:54,703 INFO L225 Difference]: With dead ends: 102 [2018-07-24 10:54:54,703 INFO L226 Difference]: Without dead ends: 69 [2018-07-24 10:54:54,704 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 276 GetRequests, 226 SyntacticMatches, 24 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 343 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=202, Invalid=554, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:54:54,705 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2018-07-24 10:54:54,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 69. [2018-07-24 10:54:54,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2018-07-24 10:54:54,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 70 transitions. [2018-07-24 10:54:54,713 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 70 transitions. Word has length 64 [2018-07-24 10:54:54,713 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:54,713 INFO L471 AbstractCegarLoop]: Abstraction has 69 states and 70 transitions. [2018-07-24 10:54:54,713 INFO L472 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-07-24 10:54:54,713 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 70 transitions. [2018-07-24 10:54:54,714 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-07-24 10:54:54,715 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:54,715 INFO L353 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 6, 6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:54,715 INFO L414 AbstractCegarLoop]: === Iteration 13 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:54,715 INFO L82 PathProgramCache]: Analyzing trace with hash 1767367943, now seen corresponding path program 10 times [2018-07-24 10:54:54,715 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:54,716 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:54,716 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:54,716 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:54,716 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:54,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:54,874 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 51 proven. 68 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-07-24 10:54:54,875 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:54,875 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:54,882 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:54:54,882 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:54:54,927 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:54:54,928 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:54,930 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:55,096 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 52 proven. 55 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:55,097 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:55,159 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 52 proven. 55 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:55,180 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:55,180 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:55,196 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:54:55,196 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:54:55,252 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:54:55,253 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:55,257 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:55,267 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 52 proven. 55 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:55,267 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:55,350 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 52 proven. 55 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:55,352 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:55,352 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11, 11, 11, 11] total 14 [2018-07-24 10:54:55,352 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:55,352 INFO L450 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-07-24 10:54:55,353 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-07-24 10:54:55,353 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=134, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:54:55,354 INFO L87 Difference]: Start difference. First operand 69 states and 70 transitions. Second operand 14 states. [2018-07-24 10:54:55,587 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:55,587 INFO L93 Difference]: Finished difference Result 79 states and 80 transitions. [2018-07-24 10:54:55,588 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-07-24 10:54:55,588 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 66 [2018-07-24 10:54:55,588 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:55,589 INFO L225 Difference]: With dead ends: 79 [2018-07-24 10:54:55,590 INFO L226 Difference]: Without dead ends: 77 [2018-07-24 10:54:55,590 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 283 GetRequests, 243 SyntacticMatches, 26 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 130 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=61, Invalid=179, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:54:55,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states. [2018-07-24 10:54:55,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 77. [2018-07-24 10:54:55,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-07-24 10:54:55,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 78 transitions. [2018-07-24 10:54:55,597 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 78 transitions. Word has length 66 [2018-07-24 10:54:55,597 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:55,597 INFO L471 AbstractCegarLoop]: Abstraction has 77 states and 78 transitions. [2018-07-24 10:54:55,598 INFO L472 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-07-24 10:54:55,598 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 78 transitions. [2018-07-24 10:54:55,599 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-07-24 10:54:55,599 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:55,599 INFO L353 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:55,599 INFO L414 AbstractCegarLoop]: === Iteration 14 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:55,599 INFO L82 PathProgramCache]: Analyzing trace with hash 508207915, now seen corresponding path program 11 times [2018-07-24 10:54:55,599 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:55,600 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:55,600 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:55,600 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:55,601 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:55,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:55,764 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:54:55,765 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:55,765 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:55,772 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:54:55,772 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:55,799 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-07-24 10:54:55,800 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:55,803 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:55,987 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:54:55,988 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:56,074 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:54:56,093 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:56,094 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:56,108 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:54:56,108 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:56,195 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-07-24 10:54:56,195 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:56,198 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:56,211 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:54:56,212 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:56,534 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:54:56,535 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:56,535 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 24 [2018-07-24 10:54:56,536 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:56,536 INFO L450 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-07-24 10:54:56,536 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-07-24 10:54:56,537 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=143, Invalid=409, Unknown=0, NotChecked=0, Total=552 [2018-07-24 10:54:56,537 INFO L87 Difference]: Start difference. First operand 77 states and 78 transitions. Second operand 24 states. [2018-07-24 10:54:56,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:56,842 INFO L93 Difference]: Finished difference Result 116 states and 124 transitions. [2018-07-24 10:54:56,842 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-07-24 10:54:56,842 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 74 [2018-07-24 10:54:56,843 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:56,843 INFO L225 Difference]: With dead ends: 116 [2018-07-24 10:54:56,844 INFO L226 Difference]: Without dead ends: 79 [2018-07-24 10:54:56,845 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 319 GetRequests, 261 SyntacticMatches, 28 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 474 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=259, Invalid=733, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:54:56,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states. [2018-07-24 10:54:56,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 79. [2018-07-24 10:54:56,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79 states. [2018-07-24 10:54:56,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 80 transitions. [2018-07-24 10:54:56,852 INFO L78 Accepts]: Start accepts. Automaton has 79 states and 80 transitions. Word has length 74 [2018-07-24 10:54:56,852 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:56,852 INFO L471 AbstractCegarLoop]: Abstraction has 79 states and 80 transitions. [2018-07-24 10:54:56,852 INFO L472 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-07-24 10:54:56,853 INFO L276 IsEmpty]: Start isEmpty. Operand 79 states and 80 transitions. [2018-07-24 10:54:56,853 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-07-24 10:54:56,853 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:56,854 INFO L353 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:56,854 INFO L414 AbstractCegarLoop]: === Iteration 15 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:56,854 INFO L82 PathProgramCache]: Analyzing trace with hash 262457829, now seen corresponding path program 12 times [2018-07-24 10:54:56,854 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:56,855 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:56,855 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:56,855 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:56,855 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:56,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:57,901 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 67 proven. 94 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-07-24 10:54:57,901 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:57,901 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:57,908 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:54:57,908 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:54:57,942 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-07-24 10:54:57,943 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:57,945 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:58,004 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 68 proven. 78 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:54:58,004 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:58,109 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 68 proven. 78 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:54:58,130 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:58,130 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:58,145 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:54:58,145 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:54:58,235 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-07-24 10:54:58,236 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:58,240 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:58,252 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 68 proven. 78 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:54:58,252 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:58,441 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 68 proven. 78 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:54:58,442 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:58,442 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 12, 12, 12, 12] total 15 [2018-07-24 10:54:58,442 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:58,443 INFO L450 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-07-24 10:54:58,443 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-07-24 10:54:58,443 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=153, Unknown=0, NotChecked=0, Total=210 [2018-07-24 10:54:58,444 INFO L87 Difference]: Start difference. First operand 79 states and 80 transitions. Second operand 15 states. [2018-07-24 10:54:58,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:58,692 INFO L93 Difference]: Finished difference Result 89 states and 90 transitions. [2018-07-24 10:54:58,692 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-07-24 10:54:58,692 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 76 [2018-07-24 10:54:58,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:58,693 INFO L225 Difference]: With dead ends: 89 [2018-07-24 10:54:58,693 INFO L226 Difference]: Without dead ends: 87 [2018-07-24 10:54:58,694 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 325 GetRequests, 280 SyntacticMatches, 30 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 165 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=70, Invalid=202, Unknown=0, NotChecked=0, Total=272 [2018-07-24 10:54:58,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2018-07-24 10:54:58,700 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 87. [2018-07-24 10:54:58,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2018-07-24 10:54:58,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 88 transitions. [2018-07-24 10:54:58,701 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 88 transitions. Word has length 76 [2018-07-24 10:54:58,701 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:58,701 INFO L471 AbstractCegarLoop]: Abstraction has 87 states and 88 transitions. [2018-07-24 10:54:58,701 INFO L472 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-07-24 10:54:58,701 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 88 transitions. [2018-07-24 10:54:58,702 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-07-24 10:54:58,702 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:58,703 INFO L353 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:58,703 INFO L414 AbstractCegarLoop]: === Iteration 16 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:58,703 INFO L82 PathProgramCache]: Analyzing trace with hash 1053542921, now seen corresponding path program 13 times [2018-07-24 10:54:58,703 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:58,704 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:58,704 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:58,704 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:58,704 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:58,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:59,457 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:54:59,457 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:59,458 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:59,465 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:59,465 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:59,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:59,489 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:59,682 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:54:59,682 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:59,808 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:54:59,828 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:59,828 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:59,847 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:59,847 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:59,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:59,903 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:59,918 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:54:59,919 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:00,127 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:00,128 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:00,128 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 27 [2018-07-24 10:55:00,129 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:00,129 INFO L450 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-07-24 10:55:00,129 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-07-24 10:55:00,129 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=179, Invalid=523, Unknown=0, NotChecked=0, Total=702 [2018-07-24 10:55:00,130 INFO L87 Difference]: Start difference. First operand 87 states and 88 transitions. Second operand 27 states. [2018-07-24 10:55:00,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:00,434 INFO L93 Difference]: Finished difference Result 130 states and 139 transitions. [2018-07-24 10:55:00,434 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-07-24 10:55:00,435 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 84 [2018-07-24 10:55:00,435 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:00,436 INFO L225 Difference]: With dead ends: 130 [2018-07-24 10:55:00,437 INFO L226 Difference]: Without dead ends: 89 [2018-07-24 10:55:00,438 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 362 GetRequests, 296 SyntacticMatches, 32 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 626 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=323, Invalid=937, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:55:00,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states. [2018-07-24 10:55:00,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 89. [2018-07-24 10:55:00,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-07-24 10:55:00,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 90 transitions. [2018-07-24 10:55:00,447 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 90 transitions. Word has length 84 [2018-07-24 10:55:00,447 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:00,447 INFO L471 AbstractCegarLoop]: Abstraction has 89 states and 90 transitions. [2018-07-24 10:55:00,447 INFO L472 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-07-24 10:55:00,447 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 90 transitions. [2018-07-24 10:55:00,448 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-07-24 10:55:00,448 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:00,449 INFO L353 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:00,449 INFO L414 AbstractCegarLoop]: === Iteration 17 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:00,449 INFO L82 PathProgramCache]: Analyzing trace with hash -396865469, now seen corresponding path program 14 times [2018-07-24 10:55:00,449 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:00,450 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:00,450 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:00,450 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:00,450 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:00,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:00,687 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 85 proven. 124 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2018-07-24 10:55:00,687 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:00,687 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:00,695 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:00,696 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:00,722 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:00,722 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:00,724 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:00,758 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 86 proven. 105 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:00,758 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:00,892 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 86 proven. 105 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:00,913 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:00,913 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:00,929 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:00,930 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:00,990 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:00,990 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:00,995 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:01,003 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 86 proven. 105 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:01,004 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:01,102 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 86 proven. 105 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:55:01,104 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:01,104 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13, 13, 13, 13] total 16 [2018-07-24 10:55:01,104 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:01,104 INFO L450 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-07-24 10:55:01,104 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-07-24 10:55:01,105 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=173, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:55:01,105 INFO L87 Difference]: Start difference. First operand 89 states and 90 transitions. Second operand 16 states. [2018-07-24 10:55:01,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:01,351 INFO L93 Difference]: Finished difference Result 99 states and 100 transitions. [2018-07-24 10:55:01,352 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-07-24 10:55:01,352 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 86 [2018-07-24 10:55:01,352 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:01,353 INFO L225 Difference]: With dead ends: 99 [2018-07-24 10:55:01,353 INFO L226 Difference]: Without dead ends: 97 [2018-07-24 10:55:01,354 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 367 GetRequests, 317 SyntacticMatches, 34 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 204 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=80, Invalid=226, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:55:01,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states. [2018-07-24 10:55:01,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 97. [2018-07-24 10:55:01,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-07-24 10:55:01,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 98 transitions. [2018-07-24 10:55:01,360 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 98 transitions. Word has length 86 [2018-07-24 10:55:01,360 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:01,360 INFO L471 AbstractCegarLoop]: Abstraction has 97 states and 98 transitions. [2018-07-24 10:55:01,360 INFO L472 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-07-24 10:55:01,361 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 98 transitions. [2018-07-24 10:55:01,361 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-07-24 10:55:01,362 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:01,362 INFO L353 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:01,362 INFO L414 AbstractCegarLoop]: === Iteration 18 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:01,362 INFO L82 PathProgramCache]: Analyzing trace with hash -138800537, now seen corresponding path program 15 times [2018-07-24 10:55:01,362 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:01,363 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:01,363 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:01,363 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:01,363 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:01,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:01,714 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:01,714 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:01,714 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:01,721 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:01,722 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:01,756 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-07-24 10:55:01,756 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:01,759 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:02,511 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:02,511 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:02,659 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:02,679 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:02,679 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:02,693 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:02,693 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:02,812 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-07-24 10:55:02,812 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:02,816 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:02,835 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:02,836 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:03,067 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:03,068 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:03,068 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 30 [2018-07-24 10:55:03,068 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:03,069 INFO L450 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-07-24 10:55:03,069 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-07-24 10:55:03,069 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=219, Invalid=651, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:55:03,070 INFO L87 Difference]: Start difference. First operand 97 states and 98 transitions. Second operand 30 states. [2018-07-24 10:55:03,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:03,436 INFO L93 Difference]: Finished difference Result 144 states and 154 transitions. [2018-07-24 10:55:03,437 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-07-24 10:55:03,437 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 94 [2018-07-24 10:55:03,437 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:03,438 INFO L225 Difference]: With dead ends: 144 [2018-07-24 10:55:03,438 INFO L226 Difference]: Without dead ends: 99 [2018-07-24 10:55:03,439 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 405 GetRequests, 331 SyntacticMatches, 36 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 799 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=394, Invalid=1166, Unknown=0, NotChecked=0, Total=1560 [2018-07-24 10:55:03,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states. [2018-07-24 10:55:03,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 99. [2018-07-24 10:55:03,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2018-07-24 10:55:03,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 100 transitions. [2018-07-24 10:55:03,446 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 100 transitions. Word has length 94 [2018-07-24 10:55:03,446 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:03,446 INFO L471 AbstractCegarLoop]: Abstraction has 99 states and 100 transitions. [2018-07-24 10:55:03,446 INFO L472 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-07-24 10:55:03,446 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 100 transitions. [2018-07-24 10:55:03,447 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-07-24 10:55:03,447 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:03,448 INFO L353 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 9, 9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:03,448 INFO L414 AbstractCegarLoop]: === Iteration 19 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:03,448 INFO L82 PathProgramCache]: Analyzing trace with hash -1817733087, now seen corresponding path program 16 times [2018-07-24 10:55:03,448 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:03,449 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:03,449 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:03,449 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:03,449 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:03,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:04,171 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 105 proven. 158 refuted. 0 times theorem prover too weak. 91 trivial. 0 not checked. [2018-07-24 10:55:04,171 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:04,171 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:04,179 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:04,179 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:04,211 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:04,211 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:04,214 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:04,258 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 106 proven. 136 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:04,258 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:04,414 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 106 proven. 136 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:04,435 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:04,435 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:04,454 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:04,454 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:04,533 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:04,533 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:04,538 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:04,573 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 106 proven. 136 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:04,573 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:04,890 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 106 proven. 136 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:55:04,892 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:04,892 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 14, 14, 14, 14] total 17 [2018-07-24 10:55:04,892 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:04,893 INFO L450 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-07-24 10:55:04,893 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-07-24 10:55:04,893 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=194, Unknown=0, NotChecked=0, Total=272 [2018-07-24 10:55:04,893 INFO L87 Difference]: Start difference. First operand 99 states and 100 transitions. Second operand 17 states. [2018-07-24 10:55:05,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:05,117 INFO L93 Difference]: Finished difference Result 109 states and 110 transitions. [2018-07-24 10:55:05,117 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-07-24 10:55:05,117 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 96 [2018-07-24 10:55:05,118 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:05,119 INFO L225 Difference]: With dead ends: 109 [2018-07-24 10:55:05,119 INFO L226 Difference]: Without dead ends: 107 [2018-07-24 10:55:05,120 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 409 GetRequests, 354 SyntacticMatches, 38 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 247 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=91, Invalid=251, Unknown=0, NotChecked=0, Total=342 [2018-07-24 10:55:05,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-07-24 10:55:05,125 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 107. [2018-07-24 10:55:05,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 107 states. [2018-07-24 10:55:05,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107 states to 107 states and 108 transitions. [2018-07-24 10:55:05,126 INFO L78 Accepts]: Start accepts. Automaton has 107 states and 108 transitions. Word has length 96 [2018-07-24 10:55:05,127 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:05,127 INFO L471 AbstractCegarLoop]: Abstraction has 107 states and 108 transitions. [2018-07-24 10:55:05,127 INFO L472 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-07-24 10:55:05,127 INFO L276 IsEmpty]: Start isEmpty. Operand 107 states and 108 transitions. [2018-07-24 10:55:05,128 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-07-24 10:55:05,128 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:05,128 INFO L353 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:05,128 INFO L414 AbstractCegarLoop]: === Iteration 20 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:05,129 INFO L82 PathProgramCache]: Analyzing trace with hash 1915395141, now seen corresponding path program 17 times [2018-07-24 10:55:05,129 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:05,129 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:05,130 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:05,130 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:05,130 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:05,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:05,602 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:55:05,602 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:05,602 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:05,609 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:05,609 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:05,645 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-07-24 10:55:05,645 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:05,648 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:06,286 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:55:06,286 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:06,452 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:55:06,472 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:06,472 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:06,487 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:06,487 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:06,622 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-07-24 10:55:06,622 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:06,626 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:06,647 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:55:06,647 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:06,821 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:55:06,823 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:06,823 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 33 [2018-07-24 10:55:06,823 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:06,824 INFO L450 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-07-24 10:55:06,824 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-07-24 10:55:06,824 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=263, Invalid=793, Unknown=0, NotChecked=0, Total=1056 [2018-07-24 10:55:06,825 INFO L87 Difference]: Start difference. First operand 107 states and 108 transitions. Second operand 33 states. [2018-07-24 10:55:07,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:07,236 INFO L93 Difference]: Finished difference Result 158 states and 169 transitions. [2018-07-24 10:55:07,237 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-07-24 10:55:07,237 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 104 [2018-07-24 10:55:07,237 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:07,238 INFO L225 Difference]: With dead ends: 158 [2018-07-24 10:55:07,238 INFO L226 Difference]: Without dead ends: 109 [2018-07-24 10:55:07,239 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 448 GetRequests, 366 SyntacticMatches, 40 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 993 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=472, Invalid=1420, Unknown=0, NotChecked=0, Total=1892 [2018-07-24 10:55:07,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109 states. [2018-07-24 10:55:07,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109 to 109. [2018-07-24 10:55:07,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 109 states. [2018-07-24 10:55:07,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 110 transitions. [2018-07-24 10:55:07,247 INFO L78 Accepts]: Start accepts. Automaton has 109 states and 110 transitions. Word has length 104 [2018-07-24 10:55:07,247 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:07,247 INFO L471 AbstractCegarLoop]: Abstraction has 109 states and 110 transitions. [2018-07-24 10:55:07,248 INFO L472 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-07-24 10:55:07,248 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 110 transitions. [2018-07-24 10:55:07,249 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2018-07-24 10:55:07,249 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:07,249 INFO L353 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:07,249 INFO L414 AbstractCegarLoop]: === Iteration 21 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:07,249 INFO L82 PathProgramCache]: Analyzing trace with hash -924860033, now seen corresponding path program 18 times [2018-07-24 10:55:07,249 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:07,250 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:07,250 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:07,250 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:07,250 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:07,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:07,887 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 127 proven. 196 refuted. 0 times theorem prover too weak. 120 trivial. 0 not checked. [2018-07-24 10:55:07,887 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:07,887 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:07,896 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:07,896 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:07,937 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2018-07-24 10:55:07,937 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:07,940 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:08,149 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 128 proven. 171 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:55:08,149 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:08,334 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 128 proven. 171 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:55:08,353 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:08,353 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:08,369 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:08,369 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:08,518 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2018-07-24 10:55:08,518 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:08,523 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:08,540 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 128 proven. 171 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:55:08,540 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:08,834 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 128 proven. 171 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:55:08,836 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:08,837 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 15, 15, 15, 15] total 18 [2018-07-24 10:55:08,837 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:08,837 INFO L450 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-07-24 10:55:08,838 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-07-24 10:55:08,838 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=90, Invalid=216, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:55:08,838 INFO L87 Difference]: Start difference. First operand 109 states and 110 transitions. Second operand 18 states. [2018-07-24 10:55:09,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:09,124 INFO L93 Difference]: Finished difference Result 119 states and 120 transitions. [2018-07-24 10:55:09,125 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-07-24 10:55:09,125 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 106 [2018-07-24 10:55:09,125 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:09,127 INFO L225 Difference]: With dead ends: 119 [2018-07-24 10:55:09,127 INFO L226 Difference]: Without dead ends: 117 [2018-07-24 10:55:09,127 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 451 GetRequests, 391 SyntacticMatches, 42 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 294 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=103, Invalid=277, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:55:09,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states. [2018-07-24 10:55:09,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2018-07-24 10:55:09,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-07-24 10:55:09,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 118 transitions. [2018-07-24 10:55:09,134 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 118 transitions. Word has length 106 [2018-07-24 10:55:09,134 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:09,134 INFO L471 AbstractCegarLoop]: Abstraction has 117 states and 118 transitions. [2018-07-24 10:55:09,134 INFO L472 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-07-24 10:55:09,134 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 118 transitions. [2018-07-24 10:55:09,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2018-07-24 10:55:09,136 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:09,136 INFO L353 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 11, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:09,136 INFO L414 AbstractCegarLoop]: === Iteration 22 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:09,136 INFO L82 PathProgramCache]: Analyzing trace with hash 1447724963, now seen corresponding path program 19 times [2018-07-24 10:55:09,136 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:09,137 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:09,137 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:09,137 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:09,137 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:09,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:09,426 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:55:09,426 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:09,426 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:09,433 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:09,433 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:09,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:09,467 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:09,784 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:55:09,785 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:09,989 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:55:10,009 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:10,009 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:10,024 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:10,024 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:10,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:10,093 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:10,116 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:55:10,116 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:10,540 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:55:10,542 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:10,542 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 36 [2018-07-24 10:55:10,542 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:10,542 INFO L450 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-07-24 10:55:10,543 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-07-24 10:55:10,543 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=311, Invalid=949, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:55:10,543 INFO L87 Difference]: Start difference. First operand 117 states and 118 transitions. Second operand 36 states. [2018-07-24 10:55:11,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:11,051 INFO L93 Difference]: Finished difference Result 172 states and 184 transitions. [2018-07-24 10:55:11,052 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-07-24 10:55:11,052 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 114 [2018-07-24 10:55:11,053 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:11,054 INFO L225 Difference]: With dead ends: 172 [2018-07-24 10:55:11,054 INFO L226 Difference]: Without dead ends: 119 [2018-07-24 10:55:11,055 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 491 GetRequests, 401 SyntacticMatches, 44 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1208 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=557, Invalid=1699, Unknown=0, NotChecked=0, Total=2256 [2018-07-24 10:55:11,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states. [2018-07-24 10:55:11,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 119. [2018-07-24 10:55:11,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 119 states. [2018-07-24 10:55:11,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 120 transitions. [2018-07-24 10:55:11,062 INFO L78 Accepts]: Start accepts. Automaton has 119 states and 120 transitions. Word has length 114 [2018-07-24 10:55:11,063 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:11,063 INFO L471 AbstractCegarLoop]: Abstraction has 119 states and 120 transitions. [2018-07-24 10:55:11,063 INFO L472 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-07-24 10:55:11,063 INFO L276 IsEmpty]: Start isEmpty. Operand 119 states and 120 transitions. [2018-07-24 10:55:11,064 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-07-24 10:55:11,064 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:11,064 INFO L353 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 11, 11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:11,064 INFO L414 AbstractCegarLoop]: === Iteration 23 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:11,064 INFO L82 PathProgramCache]: Analyzing trace with hash 1483074653, now seen corresponding path program 20 times [2018-07-24 10:55:11,064 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:11,065 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:11,065 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:11,065 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:11,065 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:11,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:11,254 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 151 proven. 238 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-07-24 10:55:11,255 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:11,255 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:11,261 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:11,262 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:11,295 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:11,296 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:11,298 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:11,371 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 152 proven. 210 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:55:11,371 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:11,510 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 152 proven. 210 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:55:11,531 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:11,531 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:11,550 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:11,550 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:11,628 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:11,629 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:11,634 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:11,652 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 152 proven. 210 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:55:11,652 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:12,578 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 152 proven. 210 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:55:12,580 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:12,580 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 16, 16, 16, 16] total 19 [2018-07-24 10:55:12,580 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:12,580 INFO L450 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-07-24 10:55:12,580 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-07-24 10:55:12,581 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=103, Invalid=239, Unknown=0, NotChecked=0, Total=342 [2018-07-24 10:55:12,581 INFO L87 Difference]: Start difference. First operand 119 states and 120 transitions. Second operand 19 states. [2018-07-24 10:55:12,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:12,780 INFO L93 Difference]: Finished difference Result 129 states and 130 transitions. [2018-07-24 10:55:12,780 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-07-24 10:55:12,780 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 116 [2018-07-24 10:55:12,780 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:12,781 INFO L225 Difference]: With dead ends: 129 [2018-07-24 10:55:12,781 INFO L226 Difference]: Without dead ends: 127 [2018-07-24 10:55:12,782 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 493 GetRequests, 428 SyntacticMatches, 46 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 345 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=116, Invalid=304, Unknown=0, NotChecked=0, Total=420 [2018-07-24 10:55:12,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2018-07-24 10:55:12,788 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 127. [2018-07-24 10:55:12,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 127 states. [2018-07-24 10:55:12,790 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127 states to 127 states and 128 transitions. [2018-07-24 10:55:12,790 INFO L78 Accepts]: Start accepts. Automaton has 127 states and 128 transitions. Word has length 116 [2018-07-24 10:55:12,790 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:12,791 INFO L471 AbstractCegarLoop]: Abstraction has 127 states and 128 transitions. [2018-07-24 10:55:12,791 INFO L472 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-07-24 10:55:12,791 INFO L276 IsEmpty]: Start isEmpty. Operand 127 states and 128 transitions. [2018-07-24 10:55:12,791 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 125 [2018-07-24 10:55:12,791 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:12,792 INFO L353 BasicCegarLoop]: trace histogram [12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:12,792 INFO L414 AbstractCegarLoop]: === Iteration 24 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:12,792 INFO L82 PathProgramCache]: Analyzing trace with hash -849415039, now seen corresponding path program 21 times [2018-07-24 10:55:12,792 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:12,793 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:12,793 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:12,793 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:12,793 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:12,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:13,192 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:55:13,192 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:13,192 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:13,199 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:13,200 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:13,389 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-07-24 10:55:13,390 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:13,393 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:13,933 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:55:13,933 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:14,407 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:55:14,427 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:14,427 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:14,443 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:14,443 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:14,628 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-07-24 10:55:14,628 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:14,633 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:14,654 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:55:14,654 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:14,900 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:55:14,901 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:14,901 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 39 [2018-07-24 10:55:14,902 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:14,902 INFO L450 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-07-24 10:55:14,902 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-07-24 10:55:14,903 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=363, Invalid=1119, Unknown=0, NotChecked=0, Total=1482 [2018-07-24 10:55:14,903 INFO L87 Difference]: Start difference. First operand 127 states and 128 transitions. Second operand 39 states. [2018-07-24 10:55:15,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:15,437 INFO L93 Difference]: Finished difference Result 186 states and 199 transitions. [2018-07-24 10:55:15,443 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-07-24 10:55:15,443 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 124 [2018-07-24 10:55:15,443 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:15,444 INFO L225 Difference]: With dead ends: 186 [2018-07-24 10:55:15,444 INFO L226 Difference]: Without dead ends: 129 [2018-07-24 10:55:15,446 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 534 GetRequests, 436 SyntacticMatches, 48 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1444 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=649, Invalid=2003, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:55:15,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129 states. [2018-07-24 10:55:15,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129 to 129. [2018-07-24 10:55:15,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 129 states. [2018-07-24 10:55:15,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 130 transitions. [2018-07-24 10:55:15,455 INFO L78 Accepts]: Start accepts. Automaton has 129 states and 130 transitions. Word has length 124 [2018-07-24 10:55:15,455 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:15,455 INFO L471 AbstractCegarLoop]: Abstraction has 129 states and 130 transitions. [2018-07-24 10:55:15,455 INFO L472 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-07-24 10:55:15,455 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 130 transitions. [2018-07-24 10:55:15,456 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2018-07-24 10:55:15,456 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:15,456 INFO L353 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 12, 12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:15,457 INFO L414 AbstractCegarLoop]: === Iteration 25 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:15,457 INFO L82 PathProgramCache]: Analyzing trace with hash -1380501317, now seen corresponding path program 22 times [2018-07-24 10:55:15,457 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:15,458 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:15,458 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:15,458 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:15,458 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:15,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:15,703 INFO L134 CoverageAnalysis]: Checked inductivity of 651 backedges. 177 proven. 284 refuted. 0 times theorem prover too weak. 190 trivial. 0 not checked. [2018-07-24 10:55:15,703 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:15,703 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:15,730 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:15,730 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:15,767 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:15,767 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:15,769 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:15,821 INFO L134 CoverageAnalysis]: Checked inductivity of 651 backedges. 178 proven. 253 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:55:15,821 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:16,074 INFO L134 CoverageAnalysis]: Checked inductivity of 651 backedges. 178 proven. 253 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:55:16,094 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:16,094 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:16,109 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:16,109 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:16,208 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:16,209 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:16,215 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:16,233 INFO L134 CoverageAnalysis]: Checked inductivity of 651 backedges. 178 proven. 253 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:55:16,233 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:16,492 INFO L134 CoverageAnalysis]: Checked inductivity of 651 backedges. 178 proven. 253 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:55:16,493 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:16,493 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 17, 17, 17, 17] total 20 [2018-07-24 10:55:16,493 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:16,494 INFO L450 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-07-24 10:55:16,494 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-07-24 10:55:16,494 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=117, Invalid=263, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:55:16,494 INFO L87 Difference]: Start difference. First operand 129 states and 130 transitions. Second operand 20 states. [2018-07-24 10:55:16,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:16,713 INFO L93 Difference]: Finished difference Result 139 states and 140 transitions. [2018-07-24 10:55:16,713 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-07-24 10:55:16,713 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 126 [2018-07-24 10:55:16,714 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:16,715 INFO L225 Difference]: With dead ends: 139 [2018-07-24 10:55:16,716 INFO L226 Difference]: Without dead ends: 137 [2018-07-24 10:55:16,716 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 535 GetRequests, 465 SyntacticMatches, 50 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 400 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=130, Invalid=332, Unknown=0, NotChecked=0, Total=462 [2018-07-24 10:55:16,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 137 states. [2018-07-24 10:55:16,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 137 to 137. [2018-07-24 10:55:16,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137 states. [2018-07-24 10:55:16,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 138 transitions. [2018-07-24 10:55:16,723 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 138 transitions. Word has length 126 [2018-07-24 10:55:16,723 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:16,723 INFO L471 AbstractCegarLoop]: Abstraction has 137 states and 138 transitions. [2018-07-24 10:55:16,723 INFO L472 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-07-24 10:55:16,723 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 138 transitions. [2018-07-24 10:55:16,724 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2018-07-24 10:55:16,724 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:16,724 INFO L353 BasicCegarLoop]: trace histogram [13, 13, 13, 13, 13, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:16,725 INFO L414 AbstractCegarLoop]: === Iteration 26 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:16,725 INFO L82 PathProgramCache]: Analyzing trace with hash 63242975, now seen corresponding path program 23 times [2018-07-24 10:55:16,725 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:16,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:16,726 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:16,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:16,726 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:16,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:17,086 INFO L134 CoverageAnalysis]: Checked inductivity of 744 backedges. 324 proven. 156 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2018-07-24 10:55:17,086 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:17,086 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:17,093 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:17,094 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:17,152 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2018-07-24 10:55:17,152 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:17,155 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:17,765 INFO L134 CoverageAnalysis]: Checked inductivity of 744 backedges. 324 proven. 156 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2018-07-24 10:55:17,765 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:18,037 INFO L134 CoverageAnalysis]: Checked inductivity of 744 backedges. 324 proven. 156 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2018-07-24 10:55:18,057 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:18,057 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:18,072 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:18,073 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:18,279 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2018-07-24 10:55:18,279 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:18,285 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:18,315 INFO L134 CoverageAnalysis]: Checked inductivity of 744 backedges. 324 proven. 156 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2018-07-24 10:55:18,315 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:18,696 INFO L134 CoverageAnalysis]: Checked inductivity of 744 backedges. 324 proven. 156 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2018-07-24 10:55:18,697 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:18,697 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 42 [2018-07-24 10:55:18,698 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:18,698 INFO L450 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-07-24 10:55:18,698 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-07-24 10:55:18,699 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=419, Invalid=1303, Unknown=0, NotChecked=0, Total=1722 [2018-07-24 10:55:18,699 INFO L87 Difference]: Start difference. First operand 137 states and 138 transitions. Second operand 42 states. [2018-07-24 10:55:19,551 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:19,552 INFO L93 Difference]: Finished difference Result 200 states and 214 transitions. [2018-07-24 10:55:19,552 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-07-24 10:55:19,552 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 134 [2018-07-24 10:55:19,552 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:19,553 INFO L225 Difference]: With dead ends: 200 [2018-07-24 10:55:19,553 INFO L226 Difference]: Without dead ends: 139 [2018-07-24 10:55:19,554 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 577 GetRequests, 471 SyntacticMatches, 52 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1701 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=748, Invalid=2332, Unknown=0, NotChecked=0, Total=3080 [2018-07-24 10:55:19,554 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2018-07-24 10:55:19,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 139. [2018-07-24 10:55:19,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-07-24 10:55:19,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 140 transitions. [2018-07-24 10:55:19,562 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 140 transitions. Word has length 134 [2018-07-24 10:55:19,562 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:19,562 INFO L471 AbstractCegarLoop]: Abstraction has 139 states and 140 transitions. [2018-07-24 10:55:19,562 INFO L472 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-07-24 10:55:19,563 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 140 transitions. [2018-07-24 10:55:19,563 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2018-07-24 10:55:19,563 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:19,564 INFO L353 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 13, 13, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:19,564 INFO L414 AbstractCegarLoop]: === Iteration 27 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:19,564 INFO L82 PathProgramCache]: Analyzing trace with hash -781662567, now seen corresponding path program 24 times [2018-07-24 10:55:19,564 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:19,565 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:19,565 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:19,565 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:19,565 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:19,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:19,901 INFO L134 CoverageAnalysis]: Checked inductivity of 770 backedges. 205 proven. 334 refuted. 0 times theorem prover too weak. 231 trivial. 0 not checked. [2018-07-24 10:55:19,902 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:19,902 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:19,909 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:19,910 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:19,962 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 14 check-sat command(s) [2018-07-24 10:55:19,962 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:19,966 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:20,195 INFO L134 CoverageAnalysis]: Checked inductivity of 770 backedges. 206 proven. 300 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2018-07-24 10:55:20,195 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:20,370 INFO L134 CoverageAnalysis]: Checked inductivity of 770 backedges. 206 proven. 300 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2018-07-24 10:55:20,389 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:20,389 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:20,417 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:20,418 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:20,668 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 14 check-sat command(s) [2018-07-24 10:55:20,668 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:20,673 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:20,693 INFO L134 CoverageAnalysis]: Checked inductivity of 770 backedges. 206 proven. 300 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2018-07-24 10:55:20,693 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:20,890 INFO L134 CoverageAnalysis]: Checked inductivity of 770 backedges. 206 proven. 300 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2018-07-24 10:55:20,892 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:20,892 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 18, 18, 18, 18] total 21 [2018-07-24 10:55:20,892 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:20,892 INFO L450 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-07-24 10:55:20,892 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-07-24 10:55:20,893 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=132, Invalid=288, Unknown=0, NotChecked=0, Total=420 [2018-07-24 10:55:20,893 INFO L87 Difference]: Start difference. First operand 139 states and 140 transitions. Second operand 21 states. [2018-07-24 10:55:21,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:21,373 INFO L93 Difference]: Finished difference Result 149 states and 150 transitions. [2018-07-24 10:55:21,374 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-07-24 10:55:21,374 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 136 [2018-07-24 10:55:21,374 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:21,375 INFO L225 Difference]: With dead ends: 149 [2018-07-24 10:55:21,375 INFO L226 Difference]: Without dead ends: 147 [2018-07-24 10:55:21,376 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 577 GetRequests, 502 SyntacticMatches, 54 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 459 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=145, Invalid=361, Unknown=0, NotChecked=0, Total=506 [2018-07-24 10:55:21,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2018-07-24 10:55:21,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 147. [2018-07-24 10:55:21,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-07-24 10:55:21,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 148 transitions. [2018-07-24 10:55:21,384 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 148 transitions. Word has length 136 [2018-07-24 10:55:21,384 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:21,384 INFO L471 AbstractCegarLoop]: Abstraction has 147 states and 148 transitions. [2018-07-24 10:55:21,384 INFO L472 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-07-24 10:55:21,384 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 148 transitions. [2018-07-24 10:55:21,385 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2018-07-24 10:55:21,385 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:21,385 INFO L353 BasicCegarLoop]: trace histogram [14, 14, 14, 14, 14, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:21,385 INFO L414 AbstractCegarLoop]: === Iteration 28 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:21,386 INFO L82 PathProgramCache]: Analyzing trace with hash 720491197, now seen corresponding path program 25 times [2018-07-24 10:55:21,386 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:21,386 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:21,387 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:21,387 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:21,387 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:21,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:22,454 INFO L134 CoverageAnalysis]: Checked inductivity of 871 backedges. 377 proven. 182 refuted. 0 times theorem prover too weak. 312 trivial. 0 not checked. [2018-07-24 10:55:22,454 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:22,454 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:22,461 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:22,461 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:22,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:22,507 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:22,870 INFO L134 CoverageAnalysis]: Checked inductivity of 871 backedges. 377 proven. 182 refuted. 0 times theorem prover too weak. 312 trivial. 0 not checked. [2018-07-24 10:55:22,871 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:23,143 INFO L134 CoverageAnalysis]: Checked inductivity of 871 backedges. 377 proven. 182 refuted. 0 times theorem prover too weak. 312 trivial. 0 not checked. [2018-07-24 10:55:23,163 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:23,163 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:23,179 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:23,179 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:23,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:23,275 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:23,300 INFO L134 CoverageAnalysis]: Checked inductivity of 871 backedges. 377 proven. 182 refuted. 0 times theorem prover too weak. 312 trivial. 0 not checked. [2018-07-24 10:55:23,300 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:23,606 INFO L134 CoverageAnalysis]: Checked inductivity of 871 backedges. 377 proven. 182 refuted. 0 times theorem prover too weak. 312 trivial. 0 not checked. [2018-07-24 10:55:23,607 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:23,607 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31, 31, 31, 31] total 45 [2018-07-24 10:55:23,607 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:23,608 INFO L450 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-07-24 10:55:23,608 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-07-24 10:55:23,609 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=479, Invalid=1501, Unknown=0, NotChecked=0, Total=1980 [2018-07-24 10:55:23,609 INFO L87 Difference]: Start difference. First operand 147 states and 148 transitions. Second operand 45 states. [2018-07-24 10:55:25,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:25,368 INFO L93 Difference]: Finished difference Result 214 states and 229 transitions. [2018-07-24 10:55:25,368 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-07-24 10:55:25,368 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 144 [2018-07-24 10:55:25,369 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:25,370 INFO L225 Difference]: With dead ends: 214 [2018-07-24 10:55:25,370 INFO L226 Difference]: Without dead ends: 149 [2018-07-24 10:55:25,372 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 620 GetRequests, 506 SyntacticMatches, 56 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1979 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=854, Invalid=2686, Unknown=0, NotChecked=0, Total=3540 [2018-07-24 10:55:25,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states. [2018-07-24 10:55:25,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 149. [2018-07-24 10:55:25,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-07-24 10:55:25,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 150 transitions. [2018-07-24 10:55:25,383 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 150 transitions. Word has length 144 [2018-07-24 10:55:25,384 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:25,384 INFO L471 AbstractCegarLoop]: Abstraction has 149 states and 150 transitions. [2018-07-24 10:55:25,384 INFO L472 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-07-24 10:55:25,384 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 150 transitions. [2018-07-24 10:55:25,385 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2018-07-24 10:55:25,385 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:25,385 INFO L353 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 14, 14, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:25,385 INFO L414 AbstractCegarLoop]: === Iteration 29 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:25,385 INFO L82 PathProgramCache]: Analyzing trace with hash -349719049, now seen corresponding path program 26 times [2018-07-24 10:55:25,386 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:25,386 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:25,386 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:25,386 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:25,386 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:25,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:25,801 INFO L134 CoverageAnalysis]: Checked inductivity of 899 backedges. 235 proven. 388 refuted. 0 times theorem prover too weak. 276 trivial. 0 not checked. [2018-07-24 10:55:25,801 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:25,802 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:25,811 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:25,811 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:25,856 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:25,856 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:25,858 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:25,980 INFO L134 CoverageAnalysis]: Checked inductivity of 899 backedges. 236 proven. 351 refuted. 0 times theorem prover too weak. 312 trivial. 0 not checked. [2018-07-24 10:55:25,980 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:26,186 INFO L134 CoverageAnalysis]: Checked inductivity of 899 backedges. 236 proven. 351 refuted. 0 times theorem prover too weak. 312 trivial. 0 not checked. [2018-07-24 10:55:26,206 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:26,206 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:26,221 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:26,221 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:26,332 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:26,332 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:26,341 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:26,381 INFO L134 CoverageAnalysis]: Checked inductivity of 899 backedges. 236 proven. 351 refuted. 0 times theorem prover too weak. 312 trivial. 0 not checked. [2018-07-24 10:55:26,381 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:27,026 INFO L134 CoverageAnalysis]: Checked inductivity of 899 backedges. 236 proven. 351 refuted. 0 times theorem prover too weak. 312 trivial. 0 not checked. [2018-07-24 10:55:27,027 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:27,027 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 19, 19, 19, 19] total 22 [2018-07-24 10:55:27,027 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:27,028 INFO L450 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-07-24 10:55:27,028 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-07-24 10:55:27,028 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=148, Invalid=314, Unknown=0, NotChecked=0, Total=462 [2018-07-24 10:55:27,028 INFO L87 Difference]: Start difference. First operand 149 states and 150 transitions. Second operand 22 states. [2018-07-24 10:55:27,972 WARN L169 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 9 DAG size of output: 7 [2018-07-24 10:55:28,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:28,059 INFO L93 Difference]: Finished difference Result 159 states and 160 transitions. [2018-07-24 10:55:28,059 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-07-24 10:55:28,059 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 146 [2018-07-24 10:55:28,060 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:28,060 INFO L225 Difference]: With dead ends: 159 [2018-07-24 10:55:28,061 INFO L226 Difference]: Without dead ends: 157 [2018-07-24 10:55:28,061 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 619 GetRequests, 539 SyntacticMatches, 58 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 522 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=161, Invalid=391, Unknown=0, NotChecked=0, Total=552 [2018-07-24 10:55:28,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-07-24 10:55:28,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 157. [2018-07-24 10:55:28,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 157 states. [2018-07-24 10:55:28,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 158 transitions. [2018-07-24 10:55:28,073 INFO L78 Accepts]: Start accepts. Automaton has 157 states and 158 transitions. Word has length 146 [2018-07-24 10:55:28,073 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:28,073 INFO L471 AbstractCegarLoop]: Abstraction has 157 states and 158 transitions. [2018-07-24 10:55:28,073 INFO L472 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-07-24 10:55:28,074 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 158 transitions. [2018-07-24 10:55:28,075 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 155 [2018-07-24 10:55:28,076 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:28,076 INFO L353 BasicCegarLoop]: trace histogram [15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:28,076 INFO L414 AbstractCegarLoop]: === Iteration 30 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:28,076 INFO L82 PathProgramCache]: Analyzing trace with hash -76381157, now seen corresponding path program 27 times [2018-07-24 10:55:28,076 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:28,077 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:28,077 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:28,077 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:28,077 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:28,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:29,478 INFO L134 CoverageAnalysis]: Checked inductivity of 1008 backedges. 434 proven. 210 refuted. 0 times theorem prover too weak. 364 trivial. 0 not checked. [2018-07-24 10:55:29,478 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:29,479 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:29,486 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:29,486 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:29,556 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2018-07-24 10:55:29,556 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:29,560 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:30,131 INFO L134 CoverageAnalysis]: Checked inductivity of 1008 backedges. 434 proven. 210 refuted. 0 times theorem prover too weak. 364 trivial. 0 not checked. [2018-07-24 10:55:30,131 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:30,452 INFO L134 CoverageAnalysis]: Checked inductivity of 1008 backedges. 434 proven. 210 refuted. 0 times theorem prover too weak. 364 trivial. 0 not checked. [2018-07-24 10:55:30,473 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:30,473 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:30,488 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:30,488 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:30,754 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2018-07-24 10:55:30,754 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:30,761 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:30,787 INFO L134 CoverageAnalysis]: Checked inductivity of 1008 backedges. 434 proven. 210 refuted. 0 times theorem prover too weak. 364 trivial. 0 not checked. [2018-07-24 10:55:30,787 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:31,122 INFO L134 CoverageAnalysis]: Checked inductivity of 1008 backedges. 434 proven. 210 refuted. 0 times theorem prover too weak. 364 trivial. 0 not checked. [2018-07-24 10:55:31,123 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:31,124 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33, 33, 33, 33] total 48 [2018-07-24 10:55:31,124 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:31,124 INFO L450 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-07-24 10:55:31,124 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-07-24 10:55:31,125 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=543, Invalid=1713, Unknown=0, NotChecked=0, Total=2256 [2018-07-24 10:55:31,125 INFO L87 Difference]: Start difference. First operand 157 states and 158 transitions. Second operand 48 states. [2018-07-24 10:55:32,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:32,505 INFO L93 Difference]: Finished difference Result 228 states and 244 transitions. [2018-07-24 10:55:32,505 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-07-24 10:55:32,505 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 154 [2018-07-24 10:55:32,506 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:32,506 INFO L225 Difference]: With dead ends: 228 [2018-07-24 10:55:32,506 INFO L226 Difference]: Without dead ends: 159 [2018-07-24 10:55:32,508 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 663 GetRequests, 541 SyntacticMatches, 60 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2278 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=967, Invalid=3065, Unknown=0, NotChecked=0, Total=4032 [2018-07-24 10:55:32,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 159 states. [2018-07-24 10:55:32,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 159 to 159. [2018-07-24 10:55:32,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159 states. [2018-07-24 10:55:32,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 160 transitions. [2018-07-24 10:55:32,517 INFO L78 Accepts]: Start accepts. Automaton has 159 states and 160 transitions. Word has length 154 [2018-07-24 10:55:32,517 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:32,517 INFO L471 AbstractCegarLoop]: Abstraction has 159 states and 160 transitions. [2018-07-24 10:55:32,518 INFO L472 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-07-24 10:55:32,518 INFO L276 IsEmpty]: Start isEmpty. Operand 159 states and 160 transitions. [2018-07-24 10:55:32,518 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 157 [2018-07-24 10:55:32,519 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:32,519 INFO L353 BasicCegarLoop]: trace histogram [16, 15, 15, 15, 15, 15, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:32,519 INFO L414 AbstractCegarLoop]: === Iteration 31 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:32,519 INFO L82 PathProgramCache]: Analyzing trace with hash 1136207573, now seen corresponding path program 28 times [2018-07-24 10:55:32,519 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:32,520 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:32,520 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:32,520 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:32,520 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:32,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:32,844 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 267 proven. 446 refuted. 0 times theorem prover too weak. 325 trivial. 0 not checked. [2018-07-24 10:55:32,844 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:32,844 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:32,851 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:32,851 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:32,900 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:32,900 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:32,903 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:32,951 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 268 proven. 406 refuted. 0 times theorem prover too weak. 364 trivial. 0 not checked. [2018-07-24 10:55:32,952 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:33,283 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 268 proven. 406 refuted. 0 times theorem prover too weak. 364 trivial. 0 not checked. [2018-07-24 10:55:33,303 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:33,303 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:33,318 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:33,318 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:33,438 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:33,438 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:33,446 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:33,473 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 268 proven. 406 refuted. 0 times theorem prover too weak. 364 trivial. 0 not checked. [2018-07-24 10:55:33,473 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:33,760 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 268 proven. 406 refuted. 0 times theorem prover too weak. 364 trivial. 0 not checked. [2018-07-24 10:55:33,762 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:33,762 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 20, 20, 20, 20] total 23 [2018-07-24 10:55:33,762 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:33,762 INFO L450 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-07-24 10:55:33,762 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-07-24 10:55:33,763 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=165, Invalid=341, Unknown=0, NotChecked=0, Total=506 [2018-07-24 10:55:33,763 INFO L87 Difference]: Start difference. First operand 159 states and 160 transitions. Second operand 23 states. [2018-07-24 10:55:34,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:34,001 INFO L93 Difference]: Finished difference Result 169 states and 170 transitions. [2018-07-24 10:55:34,001 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-07-24 10:55:34,002 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 156 [2018-07-24 10:55:34,002 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:34,004 INFO L225 Difference]: With dead ends: 169 [2018-07-24 10:55:34,004 INFO L226 Difference]: Without dead ends: 167 [2018-07-24 10:55:34,005 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 661 GetRequests, 576 SyntacticMatches, 62 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 589 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=178, Invalid=422, Unknown=0, NotChecked=0, Total=600 [2018-07-24 10:55:34,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 167 states. [2018-07-24 10:55:34,011 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 167 to 167. [2018-07-24 10:55:34,012 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-07-24 10:55:34,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 168 transitions. [2018-07-24 10:55:34,012 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 168 transitions. Word has length 156 [2018-07-24 10:55:34,013 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:34,013 INFO L471 AbstractCegarLoop]: Abstraction has 167 states and 168 transitions. [2018-07-24 10:55:34,013 INFO L472 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-07-24 10:55:34,013 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 168 transitions. [2018-07-24 10:55:34,014 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 165 [2018-07-24 10:55:34,014 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:34,014 INFO L353 BasicCegarLoop]: trace histogram [16, 16, 16, 16, 16, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:34,014 INFO L414 AbstractCegarLoop]: === Iteration 32 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:34,015 INFO L82 PathProgramCache]: Analyzing trace with hash -1226033415, now seen corresponding path program 29 times [2018-07-24 10:55:34,015 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:34,015 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:34,016 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:34,016 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:34,016 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:34,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:35,192 INFO L134 CoverageAnalysis]: Checked inductivity of 1155 backedges. 495 proven. 240 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2018-07-24 10:55:35,193 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:35,193 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:35,199 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:35,200 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:35,261 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2018-07-24 10:55:35,261 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:35,264 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:35,769 INFO L134 CoverageAnalysis]: Checked inductivity of 1155 backedges. 495 proven. 240 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2018-07-24 10:55:35,769 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:36,131 INFO L134 CoverageAnalysis]: Checked inductivity of 1155 backedges. 495 proven. 240 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2018-07-24 10:55:36,161 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:36,161 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:36,189 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:36,189 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:36,502 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2018-07-24 10:55:36,502 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:36,508 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:36,548 INFO L134 CoverageAnalysis]: Checked inductivity of 1155 backedges. 495 proven. 240 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2018-07-24 10:55:36,549 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:36,925 INFO L134 CoverageAnalysis]: Checked inductivity of 1155 backedges. 495 proven. 240 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2018-07-24 10:55:36,927 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:36,927 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35, 35, 35, 35] total 51 [2018-07-24 10:55:36,927 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:36,928 INFO L450 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-07-24 10:55:36,928 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-07-24 10:55:36,929 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=611, Invalid=1939, Unknown=0, NotChecked=0, Total=2550 [2018-07-24 10:55:36,930 INFO L87 Difference]: Start difference. First operand 167 states and 168 transitions. Second operand 51 states. [2018-07-24 10:55:38,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:38,031 INFO L93 Difference]: Finished difference Result 242 states and 259 transitions. [2018-07-24 10:55:38,032 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-07-24 10:55:38,032 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 164 [2018-07-24 10:55:38,032 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:38,033 INFO L225 Difference]: With dead ends: 242 [2018-07-24 10:55:38,033 INFO L226 Difference]: Without dead ends: 169 [2018-07-24 10:55:38,035 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 706 GetRequests, 576 SyntacticMatches, 64 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2598 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=1087, Invalid=3469, Unknown=0, NotChecked=0, Total=4556 [2018-07-24 10:55:38,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 169 states. [2018-07-24 10:55:38,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 169 to 169. [2018-07-24 10:55:38,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 169 states. [2018-07-24 10:55:38,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 169 states to 169 states and 170 transitions. [2018-07-24 10:55:38,044 INFO L78 Accepts]: Start accepts. Automaton has 169 states and 170 transitions. Word has length 164 [2018-07-24 10:55:38,044 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:38,044 INFO L471 AbstractCegarLoop]: Abstraction has 169 states and 170 transitions. [2018-07-24 10:55:38,044 INFO L472 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-07-24 10:55:38,044 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states and 170 transitions. [2018-07-24 10:55:38,045 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 167 [2018-07-24 10:55:38,045 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:38,045 INFO L353 BasicCegarLoop]: trace histogram [17, 16, 16, 16, 16, 16, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:38,046 INFO L414 AbstractCegarLoop]: === Iteration 33 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:38,046 INFO L82 PathProgramCache]: Analyzing trace with hash -956679885, now seen corresponding path program 30 times [2018-07-24 10:55:38,046 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:38,047 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:38,047 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:38,047 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:38,047 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:38,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:38,348 INFO L134 CoverageAnalysis]: Checked inductivity of 1187 backedges. 301 proven. 508 refuted. 0 times theorem prover too weak. 378 trivial. 0 not checked. [2018-07-24 10:55:38,348 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:38,349 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:38,355 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:38,356 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:38,417 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 17 check-sat command(s) [2018-07-24 10:55:38,417 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:38,420 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:38,502 INFO L134 CoverageAnalysis]: Checked inductivity of 1187 backedges. 302 proven. 465 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2018-07-24 10:55:38,502 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:38,782 INFO L134 CoverageAnalysis]: Checked inductivity of 1187 backedges. 302 proven. 465 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2018-07-24 10:55:38,802 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:38,803 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:38,836 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:38,837 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:39,154 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 17 check-sat command(s) [2018-07-24 10:55:39,154 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:39,160 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:39,189 INFO L134 CoverageAnalysis]: Checked inductivity of 1187 backedges. 302 proven. 465 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2018-07-24 10:55:39,189 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:40,037 INFO L134 CoverageAnalysis]: Checked inductivity of 1187 backedges. 302 proven. 465 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2018-07-24 10:55:40,039 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:40,039 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 21, 21, 21, 21] total 24 [2018-07-24 10:55:40,039 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:40,040 INFO L450 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-07-24 10:55:40,040 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-07-24 10:55:40,040 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=183, Invalid=369, Unknown=0, NotChecked=0, Total=552 [2018-07-24 10:55:40,041 INFO L87 Difference]: Start difference. First operand 169 states and 170 transitions. Second operand 24 states. [2018-07-24 10:55:40,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:40,285 INFO L93 Difference]: Finished difference Result 179 states and 180 transitions. [2018-07-24 10:55:40,285 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-07-24 10:55:40,286 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 166 [2018-07-24 10:55:40,286 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:40,288 INFO L225 Difference]: With dead ends: 179 [2018-07-24 10:55:40,288 INFO L226 Difference]: Without dead ends: 177 [2018-07-24 10:55:40,288 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 703 GetRequests, 613 SyntacticMatches, 66 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 660 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=196, Invalid=454, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:55:40,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states. [2018-07-24 10:55:40,296 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 177. [2018-07-24 10:55:40,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 177 states. [2018-07-24 10:55:40,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177 states to 177 states and 178 transitions. [2018-07-24 10:55:40,297 INFO L78 Accepts]: Start accepts. Automaton has 177 states and 178 transitions. Word has length 166 [2018-07-24 10:55:40,297 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:40,297 INFO L471 AbstractCegarLoop]: Abstraction has 177 states and 178 transitions. [2018-07-24 10:55:40,297 INFO L472 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-07-24 10:55:40,297 INFO L276 IsEmpty]: Start isEmpty. Operand 177 states and 178 transitions. [2018-07-24 10:55:40,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 175 [2018-07-24 10:55:40,298 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:40,299 INFO L353 BasicCegarLoop]: trace histogram [17, 17, 17, 17, 17, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:40,299 INFO L414 AbstractCegarLoop]: === Iteration 34 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:40,299 INFO L82 PathProgramCache]: Analyzing trace with hash -1441002665, now seen corresponding path program 31 times [2018-07-24 10:55:40,299 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:40,300 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:40,300 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:40,300 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:40,300 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:40,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:41,185 INFO L134 CoverageAnalysis]: Checked inductivity of 1312 backedges. 560 proven. 272 refuted. 0 times theorem prover too weak. 480 trivial. 0 not checked. [2018-07-24 10:55:41,185 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:41,185 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:41,192 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:41,192 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:41,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:41,245 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:41,820 INFO L134 CoverageAnalysis]: Checked inductivity of 1312 backedges. 560 proven. 272 refuted. 0 times theorem prover too weak. 480 trivial. 0 not checked. [2018-07-24 10:55:41,821 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:42,205 INFO L134 CoverageAnalysis]: Checked inductivity of 1312 backedges. 560 proven. 272 refuted. 0 times theorem prover too weak. 480 trivial. 0 not checked. [2018-07-24 10:55:42,225 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:42,225 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:42,240 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:42,240 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:42,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:42,355 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:42,400 INFO L134 CoverageAnalysis]: Checked inductivity of 1312 backedges. 560 proven. 272 refuted. 0 times theorem prover too weak. 480 trivial. 0 not checked. [2018-07-24 10:55:42,401 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:42,973 INFO L134 CoverageAnalysis]: Checked inductivity of 1312 backedges. 560 proven. 272 refuted. 0 times theorem prover too weak. 480 trivial. 0 not checked. [2018-07-24 10:55:42,974 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:42,974 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37, 37, 37, 37] total 54 [2018-07-24 10:55:42,974 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:42,975 INFO L450 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-07-24 10:55:42,975 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-07-24 10:55:42,976 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=683, Invalid=2179, Unknown=0, NotChecked=0, Total=2862 [2018-07-24 10:55:42,976 INFO L87 Difference]: Start difference. First operand 177 states and 178 transitions. Second operand 54 states. [2018-07-24 10:55:44,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:44,021 INFO L93 Difference]: Finished difference Result 256 states and 274 transitions. [2018-07-24 10:55:44,021 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-07-24 10:55:44,021 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 174 [2018-07-24 10:55:44,022 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:44,023 INFO L225 Difference]: With dead ends: 256 [2018-07-24 10:55:44,023 INFO L226 Difference]: Without dead ends: 179 [2018-07-24 10:55:44,026 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 749 GetRequests, 611 SyntacticMatches, 68 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2939 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=1214, Invalid=3898, Unknown=0, NotChecked=0, Total=5112 [2018-07-24 10:55:44,026 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states. [2018-07-24 10:55:44,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 179. [2018-07-24 10:55:44,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 179 states. [2018-07-24 10:55:44,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 180 transitions. [2018-07-24 10:55:44,035 INFO L78 Accepts]: Start accepts. Automaton has 179 states and 180 transitions. Word has length 174 [2018-07-24 10:55:44,035 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:44,036 INFO L471 AbstractCegarLoop]: Abstraction has 179 states and 180 transitions. [2018-07-24 10:55:44,036 INFO L472 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-07-24 10:55:44,036 INFO L276 IsEmpty]: Start isEmpty. Operand 179 states and 180 transitions. [2018-07-24 10:55:44,037 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2018-07-24 10:55:44,037 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:44,037 INFO L353 BasicCegarLoop]: trace histogram [18, 17, 17, 17, 17, 17, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:44,037 INFO L414 AbstractCegarLoop]: === Iteration 35 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:44,038 INFO L82 PathProgramCache]: Analyzing trace with hash 98569489, now seen corresponding path program 32 times [2018-07-24 10:55:44,038 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:44,038 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:44,038 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:44,038 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:44,039 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:44,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:44,358 INFO L134 CoverageAnalysis]: Checked inductivity of 1346 backedges. 337 proven. 574 refuted. 0 times theorem prover too weak. 435 trivial. 0 not checked. [2018-07-24 10:55:44,359 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:44,359 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:44,385 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:44,385 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:44,431 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:44,432 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:44,434 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:44,506 INFO L134 CoverageAnalysis]: Checked inductivity of 1346 backedges. 338 proven. 528 refuted. 0 times theorem prover too weak. 480 trivial. 0 not checked. [2018-07-24 10:55:44,506 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:45,004 INFO L134 CoverageAnalysis]: Checked inductivity of 1346 backedges. 338 proven. 528 refuted. 0 times theorem prover too weak. 480 trivial. 0 not checked. [2018-07-24 10:55:45,023 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:45,023 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:45,038 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:45,038 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:45,154 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:45,154 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:45,161 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:45,183 INFO L134 CoverageAnalysis]: Checked inductivity of 1346 backedges. 338 proven. 528 refuted. 0 times theorem prover too weak. 480 trivial. 0 not checked. [2018-07-24 10:55:45,183 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:45,492 INFO L134 CoverageAnalysis]: Checked inductivity of 1346 backedges. 338 proven. 528 refuted. 0 times theorem prover too weak. 480 trivial. 0 not checked. [2018-07-24 10:55:45,493 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:45,494 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 22, 22, 22, 22] total 25 [2018-07-24 10:55:45,494 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:45,494 INFO L450 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-07-24 10:55:45,494 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-07-24 10:55:45,495 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=202, Invalid=398, Unknown=0, NotChecked=0, Total=600 [2018-07-24 10:55:45,495 INFO L87 Difference]: Start difference. First operand 179 states and 180 transitions. Second operand 25 states. [2018-07-24 10:55:45,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:45,756 INFO L93 Difference]: Finished difference Result 189 states and 190 transitions. [2018-07-24 10:55:45,756 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-07-24 10:55:45,756 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 176 [2018-07-24 10:55:45,756 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:45,757 INFO L225 Difference]: With dead ends: 189 [2018-07-24 10:55:45,757 INFO L226 Difference]: Without dead ends: 187 [2018-07-24 10:55:45,758 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 745 GetRequests, 650 SyntacticMatches, 70 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 735 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=215, Invalid=487, Unknown=0, NotChecked=0, Total=702 [2018-07-24 10:55:45,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 187 states. [2018-07-24 10:55:45,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 187 to 187. [2018-07-24 10:55:45,766 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 187 states. [2018-07-24 10:55:45,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 187 states to 187 states and 188 transitions. [2018-07-24 10:55:45,767 INFO L78 Accepts]: Start accepts. Automaton has 187 states and 188 transitions. Word has length 176 [2018-07-24 10:55:45,767 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:45,767 INFO L471 AbstractCegarLoop]: Abstraction has 187 states and 188 transitions. [2018-07-24 10:55:45,768 INFO L472 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-07-24 10:55:45,768 INFO L276 IsEmpty]: Start isEmpty. Operand 187 states and 188 transitions. [2018-07-24 10:55:45,769 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 185 [2018-07-24 10:55:45,769 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:45,769 INFO L353 BasicCegarLoop]: trace histogram [18, 18, 18, 18, 18, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:45,769 INFO L414 AbstractCegarLoop]: === Iteration 36 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:45,769 INFO L82 PathProgramCache]: Analyzing trace with hash 785850677, now seen corresponding path program 33 times [2018-07-24 10:55:45,769 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:45,770 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:45,770 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:45,770 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:45,770 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:45,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:46,384 INFO L134 CoverageAnalysis]: Checked inductivity of 1479 backedges. 629 proven. 306 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2018-07-24 10:55:46,385 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:46,385 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:46,391 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:46,392 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:46,455 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2018-07-24 10:55:46,456 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:46,460 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:47,427 INFO L134 CoverageAnalysis]: Checked inductivity of 1479 backedges. 629 proven. 306 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2018-07-24 10:55:47,427 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:47,855 INFO L134 CoverageAnalysis]: Checked inductivity of 1479 backedges. 629 proven. 306 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2018-07-24 10:55:47,875 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:47,875 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:47,890 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:47,890 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:48,263 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2018-07-24 10:55:48,263 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:48,270 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:48,320 INFO L134 CoverageAnalysis]: Checked inductivity of 1479 backedges. 629 proven. 306 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2018-07-24 10:55:48,320 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:49,438 INFO L134 CoverageAnalysis]: Checked inductivity of 1479 backedges. 629 proven. 306 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2018-07-24 10:55:49,440 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:49,440 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39, 39, 39, 39] total 57 [2018-07-24 10:55:49,440 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:49,441 INFO L450 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-07-24 10:55:49,441 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-07-24 10:55:49,442 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=759, Invalid=2433, Unknown=0, NotChecked=0, Total=3192 [2018-07-24 10:55:49,442 INFO L87 Difference]: Start difference. First operand 187 states and 188 transitions. Second operand 57 states. [2018-07-24 10:55:50,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:50,506 INFO L93 Difference]: Finished difference Result 270 states and 289 transitions. [2018-07-24 10:55:50,506 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-07-24 10:55:50,507 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 184 [2018-07-24 10:55:50,507 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:50,508 INFO L225 Difference]: With dead ends: 270 [2018-07-24 10:55:50,508 INFO L226 Difference]: Without dead ends: 189 [2018-07-24 10:55:50,508 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 792 GetRequests, 646 SyntacticMatches, 72 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3301 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=1348, Invalid=4352, Unknown=0, NotChecked=0, Total=5700 [2018-07-24 10:55:50,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2018-07-24 10:55:50,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 189. [2018-07-24 10:55:50,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 189 states. [2018-07-24 10:55:50,518 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 189 states to 189 states and 190 transitions. [2018-07-24 10:55:50,518 INFO L78 Accepts]: Start accepts. Automaton has 189 states and 190 transitions. Word has length 184 [2018-07-24 10:55:50,518 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:50,518 INFO L471 AbstractCegarLoop]: Abstraction has 189 states and 190 transitions. [2018-07-24 10:55:50,518 INFO L472 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-07-24 10:55:50,519 INFO L276 IsEmpty]: Start isEmpty. Operand 189 states and 190 transitions. [2018-07-24 10:55:50,520 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 187 [2018-07-24 10:55:50,520 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:50,520 INFO L353 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 18, 18, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:50,520 INFO L414 AbstractCegarLoop]: === Iteration 37 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:50,520 INFO L82 PathProgramCache]: Analyzing trace with hash -1200110993, now seen corresponding path program 34 times [2018-07-24 10:55:50,520 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:50,521 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:50,521 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:50,521 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:50,521 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:50,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:51,068 INFO L134 CoverageAnalysis]: Checked inductivity of 1515 backedges. 375 proven. 644 refuted. 0 times theorem prover too weak. 496 trivial. 0 not checked. [2018-07-24 10:55:51,068 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:51,068 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:51,075 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:51,075 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:51,129 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:51,129 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:51,132 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:51,530 INFO L134 CoverageAnalysis]: Checked inductivity of 1515 backedges. 376 proven. 595 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2018-07-24 10:55:51,530 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:51,856 INFO L134 CoverageAnalysis]: Checked inductivity of 1515 backedges. 376 proven. 595 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2018-07-24 10:55:51,877 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:51,877 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 69 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:51,892 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:51,892 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:52,030 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:52,031 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:52,037 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:52,062 INFO L134 CoverageAnalysis]: Checked inductivity of 1515 backedges. 376 proven. 595 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2018-07-24 10:55:52,062 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:52,614 INFO L134 CoverageAnalysis]: Checked inductivity of 1515 backedges. 376 proven. 595 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2018-07-24 10:55:52,617 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:52,617 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 23, 23, 23, 23] total 26 [2018-07-24 10:55:52,617 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:52,618 INFO L450 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-07-24 10:55:52,618 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-07-24 10:55:52,618 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=222, Invalid=428, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:55:52,618 INFO L87 Difference]: Start difference. First operand 189 states and 190 transitions. Second operand 26 states. [2018-07-24 10:55:52,851 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:52,851 INFO L93 Difference]: Finished difference Result 199 states and 200 transitions. [2018-07-24 10:55:52,851 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-07-24 10:55:52,851 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 186 [2018-07-24 10:55:52,852 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:52,854 INFO L225 Difference]: With dead ends: 199 [2018-07-24 10:55:52,854 INFO L226 Difference]: Without dead ends: 197 [2018-07-24 10:55:52,854 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 787 GetRequests, 687 SyntacticMatches, 74 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 814 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=235, Invalid=521, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:55:52,854 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states. [2018-07-24 10:55:52,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 197. [2018-07-24 10:55:52,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 197 states. [2018-07-24 10:55:52,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197 states to 197 states and 198 transitions. [2018-07-24 10:55:52,863 INFO L78 Accepts]: Start accepts. Automaton has 197 states and 198 transitions. Word has length 186 [2018-07-24 10:55:52,863 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:52,863 INFO L471 AbstractCegarLoop]: Abstraction has 197 states and 198 transitions. [2018-07-24 10:55:52,863 INFO L472 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-07-24 10:55:52,863 INFO L276 IsEmpty]: Start isEmpty. Operand 197 states and 198 transitions. [2018-07-24 10:55:52,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 195 [2018-07-24 10:55:52,865 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:52,865 INFO L353 BasicCegarLoop]: trace histogram [19, 19, 19, 19, 19, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:52,865 INFO L414 AbstractCegarLoop]: === Iteration 38 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:52,865 INFO L82 PathProgramCache]: Analyzing trace with hash 772446355, now seen corresponding path program 35 times [2018-07-24 10:55:52,865 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:52,866 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:52,866 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:52,866 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:52,866 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:52,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:53,523 INFO L134 CoverageAnalysis]: Checked inductivity of 1656 backedges. 702 proven. 342 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2018-07-24 10:55:53,523 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:53,523 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:53,530 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:53,530 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:53,605 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2018-07-24 10:55:53,605 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:53,608 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:54,283 INFO L134 CoverageAnalysis]: Checked inductivity of 1656 backedges. 702 proven. 342 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2018-07-24 10:55:54,283 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:54,790 INFO L134 CoverageAnalysis]: Checked inductivity of 1656 backedges. 702 proven. 342 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2018-07-24 10:55:54,810 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:54,810 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:54,825 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:54,825 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:55,218 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2018-07-24 10:55:55,219 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:55,225 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:55,279 INFO L134 CoverageAnalysis]: Checked inductivity of 1656 backedges. 702 proven. 342 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2018-07-24 10:55:55,280 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:55,881 INFO L134 CoverageAnalysis]: Checked inductivity of 1656 backedges. 702 proven. 342 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2018-07-24 10:55:55,882 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:55,882 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41, 41, 41, 41] total 60 [2018-07-24 10:55:55,882 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:55,883 INFO L450 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-07-24 10:55:55,883 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-07-24 10:55:55,883 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=839, Invalid=2701, Unknown=0, NotChecked=0, Total=3540 [2018-07-24 10:55:55,884 INFO L87 Difference]: Start difference. First operand 197 states and 198 transitions. Second operand 60 states. [2018-07-24 10:55:56,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:56,948 INFO L93 Difference]: Finished difference Result 284 states and 304 transitions. [2018-07-24 10:55:56,952 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-07-24 10:55:56,952 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 194 [2018-07-24 10:55:56,953 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:56,954 INFO L225 Difference]: With dead ends: 284 [2018-07-24 10:55:56,954 INFO L226 Difference]: Without dead ends: 199 [2018-07-24 10:55:56,955 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 835 GetRequests, 681 SyntacticMatches, 76 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3684 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=1489, Invalid=4831, Unknown=0, NotChecked=0, Total=6320 [2018-07-24 10:55:56,956 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 199 states. [2018-07-24 10:55:56,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 199 to 199. [2018-07-24 10:55:56,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 199 states. [2018-07-24 10:55:56,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199 states to 199 states and 200 transitions. [2018-07-24 10:55:56,965 INFO L78 Accepts]: Start accepts. Automaton has 199 states and 200 transitions. Word has length 194 [2018-07-24 10:55:56,965 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:56,965 INFO L471 AbstractCegarLoop]: Abstraction has 199 states and 200 transitions. [2018-07-24 10:55:56,965 INFO L472 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-07-24 10:55:56,965 INFO L276 IsEmpty]: Start isEmpty. Operand 199 states and 200 transitions. [2018-07-24 10:55:56,966 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 197 [2018-07-24 10:55:56,967 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:56,967 INFO L353 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 19, 19, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:56,967 INFO L414 AbstractCegarLoop]: === Iteration 39 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:56,967 INFO L82 PathProgramCache]: Analyzing trace with hash -1075414707, now seen corresponding path program 36 times [2018-07-24 10:55:56,967 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:56,968 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:56,968 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:56,968 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:56,968 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:56,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:57,337 INFO L134 CoverageAnalysis]: Checked inductivity of 1694 backedges. 415 proven. 718 refuted. 0 times theorem prover too weak. 561 trivial. 0 not checked. [2018-07-24 10:55:57,337 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:57,337 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:57,344 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:57,345 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:57,424 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 20 check-sat command(s) [2018-07-24 10:55:57,425 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:57,428 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:57,500 INFO L134 CoverageAnalysis]: Checked inductivity of 1694 backedges. 416 proven. 666 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2018-07-24 10:55:57,501 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:57,859 INFO L134 CoverageAnalysis]: Checked inductivity of 1694 backedges. 416 proven. 666 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2018-07-24 10:55:57,880 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:57,880 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:57,895 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:57,895 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:58,311 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 20 check-sat command(s) [2018-07-24 10:55:58,311 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:58,318 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:58,345 INFO L134 CoverageAnalysis]: Checked inductivity of 1694 backedges. 416 proven. 666 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2018-07-24 10:55:58,345 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:58,703 INFO L134 CoverageAnalysis]: Checked inductivity of 1694 backedges. 416 proven. 666 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2018-07-24 10:55:58,704 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:58,705 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 24, 24, 24, 24] total 27 [2018-07-24 10:55:58,705 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:58,705 INFO L450 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-07-24 10:55:58,706 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-07-24 10:55:58,706 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=243, Invalid=459, Unknown=0, NotChecked=0, Total=702 [2018-07-24 10:55:58,706 INFO L87 Difference]: Start difference. First operand 199 states and 200 transitions. Second operand 27 states. [2018-07-24 10:55:58,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:58,948 INFO L93 Difference]: Finished difference Result 209 states and 210 transitions. [2018-07-24 10:55:58,948 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-07-24 10:55:58,949 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 196 [2018-07-24 10:55:58,949 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:58,951 INFO L225 Difference]: With dead ends: 209 [2018-07-24 10:55:58,951 INFO L226 Difference]: Without dead ends: 207 [2018-07-24 10:55:58,951 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 829 GetRequests, 724 SyntacticMatches, 78 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 897 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=256, Invalid=556, Unknown=0, NotChecked=0, Total=812 [2018-07-24 10:55:58,952 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 207 states. [2018-07-24 10:55:58,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 207 to 207. [2018-07-24 10:55:58,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2018-07-24 10:55:58,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 208 transitions. [2018-07-24 10:55:58,960 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 208 transitions. Word has length 196 [2018-07-24 10:55:58,960 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:58,960 INFO L471 AbstractCegarLoop]: Abstraction has 207 states and 208 transitions. [2018-07-24 10:55:58,960 INFO L472 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-07-24 10:55:58,960 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 208 transitions. [2018-07-24 10:55:58,961 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 205 [2018-07-24 10:55:58,961 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:58,962 INFO L353 BasicCegarLoop]: trace histogram [20, 20, 20, 20, 20, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:58,962 INFO L414 AbstractCegarLoop]: === Iteration 40 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:58,962 INFO L82 PathProgramCache]: Analyzing trace with hash 565940593, now seen corresponding path program 37 times [2018-07-24 10:55:58,962 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:58,963 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:58,963 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:58,963 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:58,963 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:58,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:59,716 INFO L134 CoverageAnalysis]: Checked inductivity of 1843 backedges. 779 proven. 380 refuted. 0 times theorem prover too weak. 684 trivial. 0 not checked. [2018-07-24 10:55:59,716 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:59,716 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:59,724 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:59,724 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:59,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:59,786 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:00,832 INFO L134 CoverageAnalysis]: Checked inductivity of 1843 backedges. 779 proven. 380 refuted. 0 times theorem prover too weak. 684 trivial. 0 not checked. [2018-07-24 10:56:00,833 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:01,418 INFO L134 CoverageAnalysis]: Checked inductivity of 1843 backedges. 779 proven. 380 refuted. 0 times theorem prover too weak. 684 trivial. 0 not checked. [2018-07-24 10:56:01,439 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:01,439 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 75 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:01,454 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:01,455 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:56:01,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:01,584 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:01,623 INFO L134 CoverageAnalysis]: Checked inductivity of 1843 backedges. 779 proven. 380 refuted. 0 times theorem prover too weak. 684 trivial. 0 not checked. [2018-07-24 10:56:01,623 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:02,220 INFO L134 CoverageAnalysis]: Checked inductivity of 1843 backedges. 779 proven. 380 refuted. 0 times theorem prover too weak. 684 trivial. 0 not checked. [2018-07-24 10:56:02,221 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:02,221 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43, 43, 43, 43] total 63 [2018-07-24 10:56:02,222 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:02,222 INFO L450 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-07-24 10:56:02,222 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-07-24 10:56:02,223 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=923, Invalid=2983, Unknown=0, NotChecked=0, Total=3906 [2018-07-24 10:56:02,223 INFO L87 Difference]: Start difference. First operand 207 states and 208 transitions. Second operand 63 states. [2018-07-24 10:56:03,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:03,458 INFO L93 Difference]: Finished difference Result 298 states and 319 transitions. [2018-07-24 10:56:03,459 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-07-24 10:56:03,459 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 204 [2018-07-24 10:56:03,460 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:03,461 INFO L225 Difference]: With dead ends: 298 [2018-07-24 10:56:03,461 INFO L226 Difference]: Without dead ends: 209 [2018-07-24 10:56:03,463 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 878 GetRequests, 716 SyntacticMatches, 80 SemanticMatches, 82 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4088 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=1637, Invalid=5335, Unknown=0, NotChecked=0, Total=6972 [2018-07-24 10:56:03,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 209 states. [2018-07-24 10:56:03,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 209 to 209. [2018-07-24 10:56:03,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 209 states. [2018-07-24 10:56:03,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 209 states to 209 states and 210 transitions. [2018-07-24 10:56:03,473 INFO L78 Accepts]: Start accepts. Automaton has 209 states and 210 transitions. Word has length 204 [2018-07-24 10:56:03,473 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:03,473 INFO L471 AbstractCegarLoop]: Abstraction has 209 states and 210 transitions. [2018-07-24 10:56:03,473 INFO L472 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-07-24 10:56:03,473 INFO L276 IsEmpty]: Start isEmpty. Operand 209 states and 210 transitions. [2018-07-24 10:56:03,474 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 207 [2018-07-24 10:56:03,474 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:03,474 INFO L353 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 20, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:03,475 INFO L414 AbstractCegarLoop]: === Iteration 41 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:03,475 INFO L82 PathProgramCache]: Analyzing trace with hash -1469492821, now seen corresponding path program 38 times [2018-07-24 10:56:03,475 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:03,475 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:03,476 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:03,476 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:03,476 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:03,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:03,950 INFO L134 CoverageAnalysis]: Checked inductivity of 1883 backedges. 457 proven. 796 refuted. 0 times theorem prover too weak. 630 trivial. 0 not checked. [2018-07-24 10:56:03,950 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:03,951 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:03,959 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:03,960 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:04,020 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:04,021 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:04,024 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:04,103 INFO L134 CoverageAnalysis]: Checked inductivity of 1883 backedges. 458 proven. 741 refuted. 0 times theorem prover too weak. 684 trivial. 0 not checked. [2018-07-24 10:56:04,104 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:04,563 INFO L134 CoverageAnalysis]: Checked inductivity of 1883 backedges. 458 proven. 741 refuted. 0 times theorem prover too weak. 684 trivial. 0 not checked. [2018-07-24 10:56:04,583 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:04,584 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 77 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:04,598 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:04,598 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:04,734 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:04,735 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:04,742 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:04,780 INFO L134 CoverageAnalysis]: Checked inductivity of 1883 backedges. 458 proven. 741 refuted. 0 times theorem prover too weak. 684 trivial. 0 not checked. [2018-07-24 10:56:04,781 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:05,230 INFO L134 CoverageAnalysis]: Checked inductivity of 1883 backedges. 458 proven. 741 refuted. 0 times theorem prover too weak. 684 trivial. 0 not checked. [2018-07-24 10:56:05,232 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:05,232 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 25, 25, 25, 25] total 28 [2018-07-24 10:56:05,232 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:05,233 INFO L450 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-07-24 10:56:05,233 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-07-24 10:56:05,233 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=265, Invalid=491, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:56:05,233 INFO L87 Difference]: Start difference. First operand 209 states and 210 transitions. Second operand 28 states. [2018-07-24 10:56:05,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:05,682 INFO L93 Difference]: Finished difference Result 219 states and 220 transitions. [2018-07-24 10:56:05,683 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-07-24 10:56:05,683 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 206 [2018-07-24 10:56:05,683 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:05,684 INFO L225 Difference]: With dead ends: 219 [2018-07-24 10:56:05,684 INFO L226 Difference]: Without dead ends: 217 [2018-07-24 10:56:05,685 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 871 GetRequests, 761 SyntacticMatches, 82 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 984 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=278, Invalid=592, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:56:05,685 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217 states. [2018-07-24 10:56:05,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217 to 217. [2018-07-24 10:56:05,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 217 states. [2018-07-24 10:56:05,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 217 states to 217 states and 218 transitions. [2018-07-24 10:56:05,693 INFO L78 Accepts]: Start accepts. Automaton has 217 states and 218 transitions. Word has length 206 [2018-07-24 10:56:05,694 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:05,694 INFO L471 AbstractCegarLoop]: Abstraction has 217 states and 218 transitions. [2018-07-24 10:56:05,694 INFO L472 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-07-24 10:56:05,694 INFO L276 IsEmpty]: Start isEmpty. Operand 217 states and 218 transitions. [2018-07-24 10:56:05,695 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 215 [2018-07-24 10:56:05,695 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:05,695 INFO L353 BasicCegarLoop]: trace histogram [21, 21, 21, 21, 21, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:05,696 INFO L414 AbstractCegarLoop]: === Iteration 42 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:05,696 INFO L82 PathProgramCache]: Analyzing trace with hash -1761137713, now seen corresponding path program 39 times [2018-07-24 10:56:05,696 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:05,697 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:05,697 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:05,697 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:05,697 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:05,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:08,224 INFO L134 CoverageAnalysis]: Checked inductivity of 2040 backedges. 860 proven. 420 refuted. 0 times theorem prover too weak. 760 trivial. 0 not checked. [2018-07-24 10:56:08,224 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:08,225 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:08,232 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:56:08,232 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:56:08,315 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2018-07-24 10:56:08,315 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:08,320 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:09,102 INFO L134 CoverageAnalysis]: Checked inductivity of 2040 backedges. 860 proven. 420 refuted. 0 times theorem prover too weak. 760 trivial. 0 not checked. [2018-07-24 10:56:09,102 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:09,707 INFO L134 CoverageAnalysis]: Checked inductivity of 2040 backedges. 860 proven. 420 refuted. 0 times theorem prover too weak. 760 trivial. 0 not checked. [2018-07-24 10:56:09,727 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:09,727 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 79 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:09,742 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:56:09,742 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:56:10,215 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2018-07-24 10:56:10,215 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:10,222 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:10,268 INFO L134 CoverageAnalysis]: Checked inductivity of 2040 backedges. 860 proven. 420 refuted. 0 times theorem prover too weak. 760 trivial. 0 not checked. [2018-07-24 10:56:10,268 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:11,207 INFO L134 CoverageAnalysis]: Checked inductivity of 2040 backedges. 860 proven. 420 refuted. 0 times theorem prover too weak. 760 trivial. 0 not checked. [2018-07-24 10:56:11,208 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:11,209 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45, 45, 45, 45] total 66 [2018-07-24 10:56:11,209 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:11,209 INFO L450 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-07-24 10:56:11,210 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-07-24 10:56:11,210 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1011, Invalid=3279, Unknown=0, NotChecked=0, Total=4290 [2018-07-24 10:56:11,210 INFO L87 Difference]: Start difference. First operand 217 states and 218 transitions. Second operand 66 states. [2018-07-24 10:56:12,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:12,604 INFO L93 Difference]: Finished difference Result 312 states and 334 transitions. [2018-07-24 10:56:12,605 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-07-24 10:56:12,605 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 214 [2018-07-24 10:56:12,605 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:12,606 INFO L225 Difference]: With dead ends: 312 [2018-07-24 10:56:12,606 INFO L226 Difference]: Without dead ends: 219 [2018-07-24 10:56:12,607 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 921 GetRequests, 751 SyntacticMatches, 84 SemanticMatches, 86 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4513 ImplicationChecksByTransitivity, 5.0s TimeCoverageRelationStatistics Valid=1792, Invalid=5864, Unknown=0, NotChecked=0, Total=7656 [2018-07-24 10:56:12,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219 states. [2018-07-24 10:56:12,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219 to 219. [2018-07-24 10:56:12,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 219 states. [2018-07-24 10:56:12,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 219 states to 219 states and 220 transitions. [2018-07-24 10:56:12,617 INFO L78 Accepts]: Start accepts. Automaton has 219 states and 220 transitions. Word has length 214 [2018-07-24 10:56:12,618 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:12,618 INFO L471 AbstractCegarLoop]: Abstraction has 219 states and 220 transitions. [2018-07-24 10:56:12,618 INFO L472 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-07-24 10:56:12,618 INFO L276 IsEmpty]: Start isEmpty. Operand 219 states and 220 transitions. [2018-07-24 10:56:12,619 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 217 [2018-07-24 10:56:12,619 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:12,619 INFO L353 BasicCegarLoop]: trace histogram [22, 21, 21, 21, 21, 21, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:12,619 INFO L414 AbstractCegarLoop]: === Iteration 43 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:12,620 INFO L82 PathProgramCache]: Analyzing trace with hash -1420465271, now seen corresponding path program 40 times [2018-07-24 10:56:12,620 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:12,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:12,621 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:12,621 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:12,621 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:12,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:13,863 INFO L134 CoverageAnalysis]: Checked inductivity of 2082 backedges. 501 proven. 878 refuted. 0 times theorem prover too weak. 703 trivial. 0 not checked. [2018-07-24 10:56:13,863 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:13,863 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:13,871 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:56:13,871 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:56:13,937 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:56:13,937 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:13,941 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:14,021 INFO L134 CoverageAnalysis]: Checked inductivity of 2082 backedges. 502 proven. 820 refuted. 0 times theorem prover too weak. 760 trivial. 0 not checked. [2018-07-24 10:56:14,021 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:14,453 INFO L134 CoverageAnalysis]: Checked inductivity of 2082 backedges. 502 proven. 820 refuted. 0 times theorem prover too weak. 760 trivial. 0 not checked. [2018-07-24 10:56:14,472 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:14,473 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 81 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:14,487 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:56:14,488 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:56:14,649 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:56:14,649 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:14,656 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:14,689 INFO L134 CoverageAnalysis]: Checked inductivity of 2082 backedges. 502 proven. 820 refuted. 0 times theorem prover too weak. 760 trivial. 0 not checked. [2018-07-24 10:56:14,689 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:15,136 INFO L134 CoverageAnalysis]: Checked inductivity of 2082 backedges. 502 proven. 820 refuted. 0 times theorem prover too weak. 760 trivial. 0 not checked. [2018-07-24 10:56:15,137 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:15,138 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 26, 26, 26, 26] total 29 [2018-07-24 10:56:15,138 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:15,138 INFO L450 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-07-24 10:56:15,138 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-07-24 10:56:15,139 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=288, Invalid=524, Unknown=0, NotChecked=0, Total=812 [2018-07-24 10:56:15,139 INFO L87 Difference]: Start difference. First operand 219 states and 220 transitions. Second operand 29 states. [2018-07-24 10:56:15,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:15,459 INFO L93 Difference]: Finished difference Result 229 states and 230 transitions. [2018-07-24 10:56:15,460 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-07-24 10:56:15,460 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 216 [2018-07-24 10:56:15,461 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:15,462 INFO L225 Difference]: With dead ends: 229 [2018-07-24 10:56:15,462 INFO L226 Difference]: Without dead ends: 227 [2018-07-24 10:56:15,463 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 913 GetRequests, 798 SyntacticMatches, 86 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1075 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=301, Invalid=629, Unknown=0, NotChecked=0, Total=930 [2018-07-24 10:56:15,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 227 states. [2018-07-24 10:56:15,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 227 to 227. [2018-07-24 10:56:15,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 227 states. [2018-07-24 10:56:15,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227 states to 227 states and 228 transitions. [2018-07-24 10:56:15,473 INFO L78 Accepts]: Start accepts. Automaton has 227 states and 228 transitions. Word has length 216 [2018-07-24 10:56:15,473 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:15,473 INFO L471 AbstractCegarLoop]: Abstraction has 227 states and 228 transitions. [2018-07-24 10:56:15,473 INFO L472 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-07-24 10:56:15,473 INFO L276 IsEmpty]: Start isEmpty. Operand 227 states and 228 transitions. [2018-07-24 10:56:15,474 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 225 [2018-07-24 10:56:15,474 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:15,475 INFO L353 BasicCegarLoop]: trace histogram [22, 22, 22, 22, 22, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:15,475 INFO L414 AbstractCegarLoop]: === Iteration 44 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:15,475 INFO L82 PathProgramCache]: Analyzing trace with hash 807569325, now seen corresponding path program 41 times [2018-07-24 10:56:15,475 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:15,476 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:15,476 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:15,476 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:15,476 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:15,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:16,374 INFO L134 CoverageAnalysis]: Checked inductivity of 2247 backedges. 945 proven. 462 refuted. 0 times theorem prover too weak. 840 trivial. 0 not checked. [2018-07-24 10:56:16,374 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:16,374 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:16,384 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:56:16,384 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:16,467 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2018-07-24 10:56:16,467 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:16,471 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:17,339 INFO L134 CoverageAnalysis]: Checked inductivity of 2247 backedges. 945 proven. 462 refuted. 0 times theorem prover too weak. 840 trivial. 0 not checked. [2018-07-24 10:56:17,340 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:17,981 INFO L134 CoverageAnalysis]: Checked inductivity of 2247 backedges. 945 proven. 462 refuted. 0 times theorem prover too weak. 840 trivial. 0 not checked. [2018-07-24 10:56:18,001 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:18,001 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 83 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 83 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:18,018 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:56:18,018 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:18,545 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2018-07-24 10:56:18,546 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:18,554 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:18,599 INFO L134 CoverageAnalysis]: Checked inductivity of 2247 backedges. 945 proven. 462 refuted. 0 times theorem prover too weak. 840 trivial. 0 not checked. [2018-07-24 10:56:18,600 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:19,312 INFO L134 CoverageAnalysis]: Checked inductivity of 2247 backedges. 945 proven. 462 refuted. 0 times theorem prover too weak. 840 trivial. 0 not checked. [2018-07-24 10:56:19,314 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:19,314 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47, 47, 47, 47] total 69 [2018-07-24 10:56:19,314 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:19,315 INFO L450 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-07-24 10:56:19,315 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-07-24 10:56:19,316 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1103, Invalid=3589, Unknown=0, NotChecked=0, Total=4692 [2018-07-24 10:56:19,316 INFO L87 Difference]: Start difference. First operand 227 states and 228 transitions. Second operand 69 states. [2018-07-24 10:56:20,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:20,769 INFO L93 Difference]: Finished difference Result 326 states and 349 transitions. [2018-07-24 10:56:20,769 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-07-24 10:56:20,769 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 224 [2018-07-24 10:56:20,770 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:20,771 INFO L225 Difference]: With dead ends: 326 [2018-07-24 10:56:20,771 INFO L226 Difference]: Without dead ends: 229 [2018-07-24 10:56:20,772 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 964 GetRequests, 786 SyntacticMatches, 88 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4959 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=1954, Invalid=6418, Unknown=0, NotChecked=0, Total=8372 [2018-07-24 10:56:20,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 229 states. [2018-07-24 10:56:20,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 229 to 229. [2018-07-24 10:56:20,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 229 states. [2018-07-24 10:56:20,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 229 states to 229 states and 230 transitions. [2018-07-24 10:56:20,783 INFO L78 Accepts]: Start accepts. Automaton has 229 states and 230 transitions. Word has length 224 [2018-07-24 10:56:20,783 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:20,783 INFO L471 AbstractCegarLoop]: Abstraction has 229 states and 230 transitions. [2018-07-24 10:56:20,783 INFO L472 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-07-24 10:56:20,783 INFO L276 IsEmpty]: Start isEmpty. Operand 229 states and 230 transitions. [2018-07-24 10:56:20,785 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 227 [2018-07-24 10:56:20,785 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:20,785 INFO L353 BasicCegarLoop]: trace histogram [23, 22, 22, 22, 22, 22, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:20,785 INFO L414 AbstractCegarLoop]: === Iteration 45 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:20,785 INFO L82 PathProgramCache]: Analyzing trace with hash 823650023, now seen corresponding path program 42 times [2018-07-24 10:56:20,785 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:20,786 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:20,786 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:20,786 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:20,786 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:20,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:21,663 INFO L134 CoverageAnalysis]: Checked inductivity of 2291 backedges. 547 proven. 964 refuted. 0 times theorem prover too weak. 780 trivial. 0 not checked. [2018-07-24 10:56:21,663 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:21,663 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:21,672 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:56:21,672 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:21,758 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 23 check-sat command(s) [2018-07-24 10:56:21,758 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:21,763 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:21,846 INFO L134 CoverageAnalysis]: Checked inductivity of 2291 backedges. 548 proven. 903 refuted. 0 times theorem prover too weak. 840 trivial. 0 not checked. [2018-07-24 10:56:21,846 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:23,143 INFO L134 CoverageAnalysis]: Checked inductivity of 2291 backedges. 548 proven. 903 refuted. 0 times theorem prover too weak. 840 trivial. 0 not checked. [2018-07-24 10:56:23,164 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:23,164 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 85 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 85 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:23,179 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:56:23,179 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:23,711 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 23 check-sat command(s) [2018-07-24 10:56:23,711 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:23,719 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:23,766 INFO L134 CoverageAnalysis]: Checked inductivity of 2291 backedges. 548 proven. 903 refuted. 0 times theorem prover too weak. 840 trivial. 0 not checked. [2018-07-24 10:56:23,766 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:24,275 INFO L134 CoverageAnalysis]: Checked inductivity of 2291 backedges. 548 proven. 903 refuted. 0 times theorem prover too weak. 840 trivial. 0 not checked. [2018-07-24 10:56:24,277 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:24,277 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 27, 27, 27, 27] total 30 [2018-07-24 10:56:24,277 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:24,278 INFO L450 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-07-24 10:56:24,278 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-07-24 10:56:24,278 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=312, Invalid=558, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:56:24,278 INFO L87 Difference]: Start difference. First operand 229 states and 230 transitions. Second operand 30 states. [2018-07-24 10:56:24,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:24,584 INFO L93 Difference]: Finished difference Result 239 states and 240 transitions. [2018-07-24 10:56:24,585 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-07-24 10:56:24,585 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 226 [2018-07-24 10:56:24,585 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:24,587 INFO L225 Difference]: With dead ends: 239 [2018-07-24 10:56:24,587 INFO L226 Difference]: Without dead ends: 237 [2018-07-24 10:56:24,587 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 955 GetRequests, 835 SyntacticMatches, 90 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1170 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=325, Invalid=667, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:56:24,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 237 states. [2018-07-24 10:56:24,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 237 to 237. [2018-07-24 10:56:24,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 237 states. [2018-07-24 10:56:24,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 237 states to 237 states and 238 transitions. [2018-07-24 10:56:24,599 INFO L78 Accepts]: Start accepts. Automaton has 237 states and 238 transitions. Word has length 226 [2018-07-24 10:56:24,599 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:24,599 INFO L471 AbstractCegarLoop]: Abstraction has 237 states and 238 transitions. [2018-07-24 10:56:24,599 INFO L472 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-07-24 10:56:24,600 INFO L276 IsEmpty]: Start isEmpty. Operand 237 states and 238 transitions. [2018-07-24 10:56:24,601 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 235 [2018-07-24 10:56:24,601 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:24,601 INFO L353 BasicCegarLoop]: trace histogram [23, 23, 23, 23, 23, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:24,601 INFO L414 AbstractCegarLoop]: === Iteration 46 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:24,601 INFO L82 PathProgramCache]: Analyzing trace with hash 643482891, now seen corresponding path program 43 times [2018-07-24 10:56:24,602 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:24,603 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:24,603 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:24,603 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:24,603 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:24,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:26,751 INFO L134 CoverageAnalysis]: Checked inductivity of 2464 backedges. 1034 proven. 506 refuted. 0 times theorem prover too weak. 924 trivial. 0 not checked. [2018-07-24 10:56:26,751 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:26,751 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:26,759 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:26,759 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:56:26,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:26,828 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:27,768 INFO L134 CoverageAnalysis]: Checked inductivity of 2464 backedges. 1034 proven. 506 refuted. 0 times theorem prover too weak. 924 trivial. 0 not checked. [2018-07-24 10:56:27,768 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:28,475 INFO L134 CoverageAnalysis]: Checked inductivity of 2464 backedges. 1034 proven. 506 refuted. 0 times theorem prover too weak. 924 trivial. 0 not checked. [2018-07-24 10:56:28,495 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:28,496 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 87 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 87 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:28,512 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:28,513 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:56:28,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:28,669 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:28,749 INFO L134 CoverageAnalysis]: Checked inductivity of 2464 backedges. 1034 proven. 506 refuted. 0 times theorem prover too weak. 924 trivial. 0 not checked. [2018-07-24 10:56:28,749 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:29,502 INFO L134 CoverageAnalysis]: Checked inductivity of 2464 backedges. 1034 proven. 506 refuted. 0 times theorem prover too weak. 924 trivial. 0 not checked. [2018-07-24 10:56:29,504 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:29,504 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49, 49, 49, 49] total 72 [2018-07-24 10:56:29,505 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:29,505 INFO L450 AbstractCegarLoop]: Interpolant automaton has 72 states [2018-07-24 10:56:29,505 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2018-07-24 10:56:29,505 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1199, Invalid=3913, Unknown=0, NotChecked=0, Total=5112 [2018-07-24 10:56:29,506 INFO L87 Difference]: Start difference. First operand 237 states and 238 transitions. Second operand 72 states. [2018-07-24 10:56:30,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:30,692 INFO L93 Difference]: Finished difference Result 340 states and 364 transitions. [2018-07-24 10:56:30,692 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-07-24 10:56:30,692 INFO L78 Accepts]: Start accepts. Automaton has 72 states. Word has length 234 [2018-07-24 10:56:30,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:30,694 INFO L225 Difference]: With dead ends: 340 [2018-07-24 10:56:30,694 INFO L226 Difference]: Without dead ends: 239 [2018-07-24 10:56:30,695 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1007 GetRequests, 821 SyntacticMatches, 92 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5426 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=2123, Invalid=6997, Unknown=0, NotChecked=0, Total=9120 [2018-07-24 10:56:30,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 239 states. [2018-07-24 10:56:30,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 239 to 239. [2018-07-24 10:56:30,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 239 states. [2018-07-24 10:56:30,706 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 239 states to 239 states and 240 transitions. [2018-07-24 10:56:30,706 INFO L78 Accepts]: Start accepts. Automaton has 239 states and 240 transitions. Word has length 234 [2018-07-24 10:56:30,706 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:30,706 INFO L471 AbstractCegarLoop]: Abstraction has 239 states and 240 transitions. [2018-07-24 10:56:30,706 INFO L472 AbstractCegarLoop]: Interpolant automaton has 72 states. [2018-07-24 10:56:30,706 INFO L276 IsEmpty]: Start isEmpty. Operand 239 states and 240 transitions. [2018-07-24 10:56:30,708 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 237 [2018-07-24 10:56:30,708 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:30,708 INFO L353 BasicCegarLoop]: trace histogram [24, 23, 23, 23, 23, 23, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:30,708 INFO L414 AbstractCegarLoop]: === Iteration 47 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:30,708 INFO L82 PathProgramCache]: Analyzing trace with hash -751443003, now seen corresponding path program 44 times [2018-07-24 10:56:30,709 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:30,709 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:30,709 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:30,709 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:30,709 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:30,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:31,438 INFO L134 CoverageAnalysis]: Checked inductivity of 2510 backedges. 595 proven. 1054 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-07-24 10:56:31,439 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:31,439 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:31,445 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:31,446 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:31,514 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:31,515 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:31,518 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:31,598 INFO L134 CoverageAnalysis]: Checked inductivity of 2510 backedges. 596 proven. 990 refuted. 0 times theorem prover too weak. 924 trivial. 0 not checked. [2018-07-24 10:56:31,598 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:32,083 INFO L134 CoverageAnalysis]: Checked inductivity of 2510 backedges. 596 proven. 990 refuted. 0 times theorem prover too weak. 924 trivial. 0 not checked. [2018-07-24 10:56:32,103 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:32,103 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 89 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 89 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:32,118 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:32,118 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:32,277 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:32,278 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:32,286 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:32,322 INFO L134 CoverageAnalysis]: Checked inductivity of 2510 backedges. 596 proven. 990 refuted. 0 times theorem prover too weak. 924 trivial. 0 not checked. [2018-07-24 10:56:32,323 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:32,877 INFO L134 CoverageAnalysis]: Checked inductivity of 2510 backedges. 596 proven. 990 refuted. 0 times theorem prover too weak. 924 trivial. 0 not checked. [2018-07-24 10:56:32,878 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:32,878 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 28, 28, 28, 28] total 31 [2018-07-24 10:56:32,878 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:32,879 INFO L450 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-07-24 10:56:32,879 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-07-24 10:56:32,879 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=337, Invalid=593, Unknown=0, NotChecked=0, Total=930 [2018-07-24 10:56:32,879 INFO L87 Difference]: Start difference. First operand 239 states and 240 transitions. Second operand 31 states. [2018-07-24 10:56:33,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:33,206 INFO L93 Difference]: Finished difference Result 249 states and 250 transitions. [2018-07-24 10:56:33,206 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-07-24 10:56:33,206 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 236 [2018-07-24 10:56:33,207 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:33,209 INFO L225 Difference]: With dead ends: 249 [2018-07-24 10:56:33,209 INFO L226 Difference]: Without dead ends: 247 [2018-07-24 10:56:33,209 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 997 GetRequests, 872 SyntacticMatches, 94 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1269 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=350, Invalid=706, Unknown=0, NotChecked=0, Total=1056 [2018-07-24 10:56:33,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 247 states. [2018-07-24 10:56:33,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 247 to 247. [2018-07-24 10:56:33,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 247 states. [2018-07-24 10:56:33,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 247 states to 247 states and 248 transitions. [2018-07-24 10:56:33,220 INFO L78 Accepts]: Start accepts. Automaton has 247 states and 248 transitions. Word has length 236 [2018-07-24 10:56:33,220 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:33,220 INFO L471 AbstractCegarLoop]: Abstraction has 247 states and 248 transitions. [2018-07-24 10:56:33,220 INFO L472 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-07-24 10:56:33,221 INFO L276 IsEmpty]: Start isEmpty. Operand 247 states and 248 transitions. [2018-07-24 10:56:33,222 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 245 [2018-07-24 10:56:33,222 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:33,222 INFO L353 BasicCegarLoop]: trace histogram [24, 24, 24, 24, 24, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:33,222 INFO L414 AbstractCegarLoop]: === Iteration 48 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:33,223 INFO L82 PathProgramCache]: Analyzing trace with hash 1276445673, now seen corresponding path program 45 times [2018-07-24 10:56:33,223 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:33,223 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:33,223 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:33,224 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:33,224 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:33,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:34,818 INFO L134 CoverageAnalysis]: Checked inductivity of 2691 backedges. 1127 proven. 552 refuted. 0 times theorem prover too weak. 1012 trivial. 0 not checked. [2018-07-24 10:56:34,818 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:34,818 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:34,826 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:56:34,826 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:56:34,918 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2018-07-24 10:56:34,918 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:34,923 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:35,926 INFO L134 CoverageAnalysis]: Checked inductivity of 2691 backedges. 1127 proven. 552 refuted. 0 times theorem prover too weak. 1012 trivial. 0 not checked. [2018-07-24 10:56:35,926 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:36,929 INFO L134 CoverageAnalysis]: Checked inductivity of 2691 backedges. 1127 proven. 552 refuted. 0 times theorem prover too weak. 1012 trivial. 0 not checked. [2018-07-24 10:56:36,949 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:36,949 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 91 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 91 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:36,964 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:56:36,964 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:56:37,575 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2018-07-24 10:56:37,575 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:37,583 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:37,641 INFO L134 CoverageAnalysis]: Checked inductivity of 2691 backedges. 1127 proven. 552 refuted. 0 times theorem prover too weak. 1012 trivial. 0 not checked. [2018-07-24 10:56:37,641 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:38,428 INFO L134 CoverageAnalysis]: Checked inductivity of 2691 backedges. 1127 proven. 552 refuted. 0 times theorem prover too weak. 1012 trivial. 0 not checked. [2018-07-24 10:56:38,429 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:38,430 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 51, 51, 51, 51] total 75 [2018-07-24 10:56:38,430 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:38,430 INFO L450 AbstractCegarLoop]: Interpolant automaton has 75 states [2018-07-24 10:56:38,431 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 75 interpolants. [2018-07-24 10:56:38,431 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1299, Invalid=4251, Unknown=0, NotChecked=0, Total=5550 [2018-07-24 10:56:38,431 INFO L87 Difference]: Start difference. First operand 247 states and 248 transitions. Second operand 75 states. [2018-07-24 10:56:39,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:39,775 INFO L93 Difference]: Finished difference Result 354 states and 379 transitions. [2018-07-24 10:56:39,776 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-07-24 10:56:39,776 INFO L78 Accepts]: Start accepts. Automaton has 75 states. Word has length 244 [2018-07-24 10:56:39,776 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:39,777 INFO L225 Difference]: With dead ends: 354 [2018-07-24 10:56:39,777 INFO L226 Difference]: Without dead ends: 249 [2018-07-24 10:56:39,779 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1050 GetRequests, 856 SyntacticMatches, 96 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5914 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=2299, Invalid=7601, Unknown=0, NotChecked=0, Total=9900 [2018-07-24 10:56:39,779 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 249 states. [2018-07-24 10:56:39,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 249 to 249. [2018-07-24 10:56:39,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 249 states. [2018-07-24 10:56:39,790 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 249 states to 249 states and 250 transitions. [2018-07-24 10:56:39,791 INFO L78 Accepts]: Start accepts. Automaton has 249 states and 250 transitions. Word has length 244 [2018-07-24 10:56:39,791 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:39,791 INFO L471 AbstractCegarLoop]: Abstraction has 249 states and 250 transitions. [2018-07-24 10:56:39,791 INFO L472 AbstractCegarLoop]: Interpolant automaton has 75 states. [2018-07-24 10:56:39,791 INFO L276 IsEmpty]: Start isEmpty. Operand 249 states and 250 transitions. [2018-07-24 10:56:39,792 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 247 [2018-07-24 10:56:39,793 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:39,793 INFO L353 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 24, 24, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:39,793 INFO L414 AbstractCegarLoop]: === Iteration 49 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:39,793 INFO L82 PathProgramCache]: Analyzing trace with hash -565411293, now seen corresponding path program 46 times [2018-07-24 10:56:39,793 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:39,794 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:39,794 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:39,794 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:39,794 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:39,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:40,282 INFO L134 CoverageAnalysis]: Checked inductivity of 2739 backedges. 645 proven. 1148 refuted. 0 times theorem prover too weak. 946 trivial. 0 not checked. [2018-07-24 10:56:40,282 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:40,282 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:40,290 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:56:40,290 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:56:40,365 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:56:40,366 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:40,371 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:40,457 INFO L134 CoverageAnalysis]: Checked inductivity of 2739 backedges. 646 proven. 1081 refuted. 0 times theorem prover too weak. 1012 trivial. 0 not checked. [2018-07-24 10:56:40,458 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:41,007 INFO L134 CoverageAnalysis]: Checked inductivity of 2739 backedges. 646 proven. 1081 refuted. 0 times theorem prover too weak. 1012 trivial. 0 not checked. [2018-07-24 10:56:41,027 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:41,027 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 93 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 93 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:41,041 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:56:41,042 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:56:41,226 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:56:41,226 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:41,234 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:41,269 INFO L134 CoverageAnalysis]: Checked inductivity of 2739 backedges. 646 proven. 1081 refuted. 0 times theorem prover too weak. 1012 trivial. 0 not checked. [2018-07-24 10:56:41,269 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:41,916 INFO L134 CoverageAnalysis]: Checked inductivity of 2739 backedges. 646 proven. 1081 refuted. 0 times theorem prover too weak. 1012 trivial. 0 not checked. [2018-07-24 10:56:41,918 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:41,918 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 29, 29, 29, 29] total 32 [2018-07-24 10:56:41,918 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:41,918 INFO L450 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-07-24 10:56:41,919 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-07-24 10:56:41,919 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=363, Invalid=629, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:56:41,919 INFO L87 Difference]: Start difference. First operand 249 states and 250 transitions. Second operand 32 states. [2018-07-24 10:56:42,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:42,228 INFO L93 Difference]: Finished difference Result 259 states and 260 transitions. [2018-07-24 10:56:42,228 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-07-24 10:56:42,228 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 246 [2018-07-24 10:56:42,229 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:42,230 INFO L225 Difference]: With dead ends: 259 [2018-07-24 10:56:42,230 INFO L226 Difference]: Without dead ends: 257 [2018-07-24 10:56:42,231 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1039 GetRequests, 909 SyntacticMatches, 98 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1372 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=376, Invalid=746, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:56:42,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 257 states. [2018-07-24 10:56:42,242 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 257 to 257. [2018-07-24 10:56:42,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 257 states. [2018-07-24 10:56:42,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 257 states to 257 states and 258 transitions. [2018-07-24 10:56:42,243 INFO L78 Accepts]: Start accepts. Automaton has 257 states and 258 transitions. Word has length 246 [2018-07-24 10:56:42,243 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:42,243 INFO L471 AbstractCegarLoop]: Abstraction has 257 states and 258 transitions. [2018-07-24 10:56:42,244 INFO L472 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-07-24 10:56:42,244 INFO L276 IsEmpty]: Start isEmpty. Operand 257 states and 258 transitions. [2018-07-24 10:56:42,245 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 255 [2018-07-24 10:56:42,245 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:42,245 INFO L353 BasicCegarLoop]: trace histogram [25, 25, 25, 25, 25, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:42,245 INFO L414 AbstractCegarLoop]: === Iteration 50 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:42,246 INFO L82 PathProgramCache]: Analyzing trace with hash -1899076537, now seen corresponding path program 47 times [2018-07-24 10:56:42,246 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:42,246 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:42,247 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:42,247 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:42,247 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:42,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:43,947 INFO L134 CoverageAnalysis]: Checked inductivity of 2928 backedges. 1224 proven. 600 refuted. 0 times theorem prover too weak. 1104 trivial. 0 not checked. [2018-07-24 10:56:43,947 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:43,947 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:43,958 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:56:43,958 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:44,059 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2018-07-24 10:56:44,060 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:44,064 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:45,220 INFO L134 CoverageAnalysis]: Checked inductivity of 2928 backedges. 1224 proven. 600 refuted. 0 times theorem prover too weak. 1104 trivial. 0 not checked. [2018-07-24 10:56:45,220 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:46,057 INFO L134 CoverageAnalysis]: Checked inductivity of 2928 backedges. 1224 proven. 600 refuted. 0 times theorem prover too weak. 1104 trivial. 0 not checked. [2018-07-24 10:56:46,077 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:46,077 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 95 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 95 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:46,096 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:56:46,096 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:46,734 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2018-07-24 10:56:46,734 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:46,742 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:46,818 INFO L134 CoverageAnalysis]: Checked inductivity of 2928 backedges. 1224 proven. 600 refuted. 0 times theorem prover too weak. 1104 trivial. 0 not checked. [2018-07-24 10:56:46,818 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:47,665 INFO L134 CoverageAnalysis]: Checked inductivity of 2928 backedges. 1224 proven. 600 refuted. 0 times theorem prover too weak. 1104 trivial. 0 not checked. [2018-07-24 10:56:47,666 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:47,667 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [53, 53, 53, 53, 53] total 78 [2018-07-24 10:56:47,667 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:47,667 INFO L450 AbstractCegarLoop]: Interpolant automaton has 78 states [2018-07-24 10:56:47,667 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 78 interpolants. [2018-07-24 10:56:47,668 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1403, Invalid=4603, Unknown=0, NotChecked=0, Total=6006 [2018-07-24 10:56:47,668 INFO L87 Difference]: Start difference. First operand 257 states and 258 transitions. Second operand 78 states. [2018-07-24 10:56:49,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:49,088 INFO L93 Difference]: Finished difference Result 368 states and 394 transitions. [2018-07-24 10:56:49,088 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-07-24 10:56:49,088 INFO L78 Accepts]: Start accepts. Automaton has 78 states. Word has length 254 [2018-07-24 10:56:49,089 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:49,090 INFO L225 Difference]: With dead ends: 368 [2018-07-24 10:56:49,090 INFO L226 Difference]: Without dead ends: 259 [2018-07-24 10:56:49,091 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1093 GetRequests, 891 SyntacticMatches, 100 SemanticMatches, 102 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6423 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=2482, Invalid=8230, Unknown=0, NotChecked=0, Total=10712 [2018-07-24 10:56:49,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 259 states. [2018-07-24 10:56:49,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 259 to 259. [2018-07-24 10:56:49,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 259 states. [2018-07-24 10:56:49,104 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 259 states to 259 states and 260 transitions. [2018-07-24 10:56:49,105 INFO L78 Accepts]: Start accepts. Automaton has 259 states and 260 transitions. Word has length 254 [2018-07-24 10:56:49,105 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:49,105 INFO L471 AbstractCegarLoop]: Abstraction has 259 states and 260 transitions. [2018-07-24 10:56:49,105 INFO L472 AbstractCegarLoop]: Interpolant automaton has 78 states. [2018-07-24 10:56:49,105 INFO L276 IsEmpty]: Start isEmpty. Operand 259 states and 260 transitions. [2018-07-24 10:56:49,107 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 257 [2018-07-24 10:56:49,107 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:49,107 INFO L353 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 25, 25, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:49,107 INFO L414 AbstractCegarLoop]: === Iteration 51 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:49,107 INFO L82 PathProgramCache]: Analyzing trace with hash 1410392577, now seen corresponding path program 48 times [2018-07-24 10:56:49,108 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:49,108 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:49,108 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:49,108 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:49,108 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:49,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:50,269 INFO L134 CoverageAnalysis]: Checked inductivity of 2978 backedges. 697 proven. 1246 refuted. 0 times theorem prover too weak. 1035 trivial. 0 not checked. [2018-07-24 10:56:50,269 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:50,269 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 96 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 96 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:50,276 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:56:50,276 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:50,379 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 26 check-sat command(s) [2018-07-24 10:56:50,379 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:50,383 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:50,474 INFO L134 CoverageAnalysis]: Checked inductivity of 2978 backedges. 698 proven. 1176 refuted. 0 times theorem prover too weak. 1104 trivial. 0 not checked. [2018-07-24 10:56:50,474 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:51,029 INFO L134 CoverageAnalysis]: Checked inductivity of 2978 backedges. 698 proven. 1176 refuted. 0 times theorem prover too weak. 1104 trivial. 0 not checked. [2018-07-24 10:56:51,049 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:51,049 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 97 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 97 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:51,078 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:56:51,079 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:51,741 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 26 check-sat command(s) [2018-07-24 10:56:51,741 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:51,749 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:51,795 INFO L134 CoverageAnalysis]: Checked inductivity of 2978 backedges. 698 proven. 1176 refuted. 0 times theorem prover too weak. 1104 trivial. 0 not checked. [2018-07-24 10:56:51,795 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:52,368 INFO L134 CoverageAnalysis]: Checked inductivity of 2978 backedges. 698 proven. 1176 refuted. 0 times theorem prover too weak. 1104 trivial. 0 not checked. [2018-07-24 10:56:52,370 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:52,370 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 30, 30, 30, 30] total 33 [2018-07-24 10:56:52,370 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:52,371 INFO L450 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-07-24 10:56:52,371 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-07-24 10:56:52,371 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=390, Invalid=666, Unknown=0, NotChecked=0, Total=1056 [2018-07-24 10:56:52,371 INFO L87 Difference]: Start difference. First operand 259 states and 260 transitions. Second operand 33 states. [2018-07-24 10:56:52,760 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:52,760 INFO L93 Difference]: Finished difference Result 269 states and 270 transitions. [2018-07-24 10:56:52,761 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-07-24 10:56:52,761 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 256 [2018-07-24 10:56:52,762 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:52,763 INFO L225 Difference]: With dead ends: 269 [2018-07-24 10:56:52,763 INFO L226 Difference]: Without dead ends: 267 [2018-07-24 10:56:52,764 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1081 GetRequests, 946 SyntacticMatches, 102 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1479 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=403, Invalid=787, Unknown=0, NotChecked=0, Total=1190 [2018-07-24 10:56:52,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 267 states. [2018-07-24 10:56:52,773 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 267 to 267. [2018-07-24 10:56:52,773 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 267 states. [2018-07-24 10:56:52,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 267 states to 267 states and 268 transitions. [2018-07-24 10:56:52,774 INFO L78 Accepts]: Start accepts. Automaton has 267 states and 268 transitions. Word has length 256 [2018-07-24 10:56:52,774 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:52,774 INFO L471 AbstractCegarLoop]: Abstraction has 267 states and 268 transitions. [2018-07-24 10:56:52,775 INFO L472 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-07-24 10:56:52,775 INFO L276 IsEmpty]: Start isEmpty. Operand 267 states and 268 transitions. [2018-07-24 10:56:52,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 265 [2018-07-24 10:56:52,776 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:52,776 INFO L353 BasicCegarLoop]: trace histogram [26, 26, 26, 26, 26, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:52,776 INFO L414 AbstractCegarLoop]: === Iteration 52 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:52,777 INFO L82 PathProgramCache]: Analyzing trace with hash -115603931, now seen corresponding path program 49 times [2018-07-24 10:56:52,777 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:52,777 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:52,777 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:52,777 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:52,778 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:52,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:54,029 INFO L134 CoverageAnalysis]: Checked inductivity of 3175 backedges. 1325 proven. 650 refuted. 0 times theorem prover too weak. 1200 trivial. 0 not checked. [2018-07-24 10:56:54,029 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:54,029 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 98 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 98 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:54,037 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:54,037 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:56:54,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:54,115 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:55,248 INFO L134 CoverageAnalysis]: Checked inductivity of 3175 backedges. 1325 proven. 650 refuted. 0 times theorem prover too weak. 1200 trivial. 0 not checked. [2018-07-24 10:56:55,248 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:56,162 INFO L134 CoverageAnalysis]: Checked inductivity of 3175 backedges. 1325 proven. 650 refuted. 0 times theorem prover too weak. 1200 trivial. 0 not checked. [2018-07-24 10:56:56,183 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:56,183 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 99 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 99 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:56,198 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:56,198 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:56:56,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:56,367 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:56,435 INFO L134 CoverageAnalysis]: Checked inductivity of 3175 backedges. 1325 proven. 650 refuted. 0 times theorem prover too weak. 1200 trivial. 0 not checked. [2018-07-24 10:56:56,435 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:57,553 INFO L134 CoverageAnalysis]: Checked inductivity of 3175 backedges. 1325 proven. 650 refuted. 0 times theorem prover too weak. 1200 trivial. 0 not checked. [2018-07-24 10:56:57,555 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:57,555 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [55, 55, 55, 55, 55] total 81 [2018-07-24 10:56:57,555 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:57,556 INFO L450 AbstractCegarLoop]: Interpolant automaton has 81 states [2018-07-24 10:56:57,556 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 81 interpolants. [2018-07-24 10:56:57,556 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1511, Invalid=4969, Unknown=0, NotChecked=0, Total=6480 [2018-07-24 10:56:57,557 INFO L87 Difference]: Start difference. First operand 267 states and 268 transitions. Second operand 81 states. [2018-07-24 10:56:59,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:59,061 INFO L93 Difference]: Finished difference Result 382 states and 409 transitions. [2018-07-24 10:56:59,067 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-07-24 10:56:59,067 INFO L78 Accepts]: Start accepts. Automaton has 81 states. Word has length 264 [2018-07-24 10:56:59,068 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:59,069 INFO L225 Difference]: With dead ends: 382 [2018-07-24 10:56:59,069 INFO L226 Difference]: Without dead ends: 269 [2018-07-24 10:56:59,071 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1136 GetRequests, 926 SyntacticMatches, 104 SemanticMatches, 106 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6953 ImplicationChecksByTransitivity, 4.6s TimeCoverageRelationStatistics Valid=2672, Invalid=8884, Unknown=0, NotChecked=0, Total=11556 [2018-07-24 10:56:59,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 269 states. [2018-07-24 10:56:59,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 269 to 269. [2018-07-24 10:56:59,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 269 states. [2018-07-24 10:56:59,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 269 states to 269 states and 270 transitions. [2018-07-24 10:56:59,082 INFO L78 Accepts]: Start accepts. Automaton has 269 states and 270 transitions. Word has length 264 [2018-07-24 10:56:59,083 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:59,083 INFO L471 AbstractCegarLoop]: Abstraction has 269 states and 270 transitions. [2018-07-24 10:56:59,083 INFO L472 AbstractCegarLoop]: Interpolant automaton has 81 states. [2018-07-24 10:56:59,083 INFO L276 IsEmpty]: Start isEmpty. Operand 269 states and 270 transitions. [2018-07-24 10:56:59,084 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 267 [2018-07-24 10:56:59,084 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:59,084 INFO L353 BasicCegarLoop]: trace histogram [27, 26, 26, 26, 26, 26, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:59,085 INFO L414 AbstractCegarLoop]: === Iteration 53 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:59,085 INFO L82 PathProgramCache]: Analyzing trace with hash 1833968479, now seen corresponding path program 50 times [2018-07-24 10:56:59,085 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:59,085 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:59,085 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:59,085 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:59,085 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:59,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:00,175 INFO L134 CoverageAnalysis]: Checked inductivity of 3227 backedges. 751 proven. 1348 refuted. 0 times theorem prover too weak. 1128 trivial. 0 not checked. [2018-07-24 10:57:00,175 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:00,175 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 100 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 100 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:00,182 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:57:00,182 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:00,260 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:57:00,260 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:00,264 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:00,358 INFO L134 CoverageAnalysis]: Checked inductivity of 3227 backedges. 752 proven. 1275 refuted. 0 times theorem prover too weak. 1200 trivial. 0 not checked. [2018-07-24 10:57:00,359 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:00,963 INFO L134 CoverageAnalysis]: Checked inductivity of 3227 backedges. 752 proven. 1275 refuted. 0 times theorem prover too weak. 1200 trivial. 0 not checked. [2018-07-24 10:57:00,983 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:00,983 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 101 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 101 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:00,998 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:57:00,998 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:01,174 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:57:01,175 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:01,183 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:01,227 INFO L134 CoverageAnalysis]: Checked inductivity of 3227 backedges. 752 proven. 1275 refuted. 0 times theorem prover too weak. 1200 trivial. 0 not checked. [2018-07-24 10:57:01,228 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:02,127 INFO L134 CoverageAnalysis]: Checked inductivity of 3227 backedges. 752 proven. 1275 refuted. 0 times theorem prover too weak. 1200 trivial. 0 not checked. [2018-07-24 10:57:02,128 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:02,129 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 31, 31, 31, 31] total 34 [2018-07-24 10:57:02,129 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:02,129 INFO L450 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-07-24 10:57:02,129 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-07-24 10:57:02,130 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=418, Invalid=704, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:57:02,130 INFO L87 Difference]: Start difference. First operand 269 states and 270 transitions. Second operand 34 states. [2018-07-24 10:57:02,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:02,483 INFO L93 Difference]: Finished difference Result 279 states and 280 transitions. [2018-07-24 10:57:02,484 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-07-24 10:57:02,484 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 266 [2018-07-24 10:57:02,485 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:02,486 INFO L225 Difference]: With dead ends: 279 [2018-07-24 10:57:02,486 INFO L226 Difference]: Without dead ends: 277 [2018-07-24 10:57:02,487 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1123 GetRequests, 983 SyntacticMatches, 106 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1590 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=431, Invalid=829, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:57:02,487 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 277 states. [2018-07-24 10:57:02,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 277 to 277. [2018-07-24 10:57:02,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 277 states. [2018-07-24 10:57:02,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 277 states to 277 states and 278 transitions. [2018-07-24 10:57:02,499 INFO L78 Accepts]: Start accepts. Automaton has 277 states and 278 transitions. Word has length 266 [2018-07-24 10:57:02,500 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:02,500 INFO L471 AbstractCegarLoop]: Abstraction has 277 states and 278 transitions. [2018-07-24 10:57:02,500 INFO L472 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-07-24 10:57:02,500 INFO L276 IsEmpty]: Start isEmpty. Operand 277 states and 278 transitions. [2018-07-24 10:57:02,501 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 275 [2018-07-24 10:57:02,501 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:02,502 INFO L353 BasicCegarLoop]: trace histogram [27, 27, 27, 27, 27, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:02,502 INFO L414 AbstractCegarLoop]: === Iteration 54 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:02,502 INFO L82 PathProgramCache]: Analyzing trace with hash 883624323, now seen corresponding path program 51 times [2018-07-24 10:57:02,502 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:02,503 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:02,503 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:02,503 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:02,503 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:02,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:04,235 INFO L134 CoverageAnalysis]: Checked inductivity of 3432 backedges. 1430 proven. 702 refuted. 0 times theorem prover too weak. 1300 trivial. 0 not checked. [2018-07-24 10:57:04,235 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:04,235 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 102 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 102 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:04,243 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:57:04,244 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:57:04,359 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2018-07-24 10:57:04,359 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:04,365 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:05,610 INFO L134 CoverageAnalysis]: Checked inductivity of 3432 backedges. 1430 proven. 702 refuted. 0 times theorem prover too weak. 1300 trivial. 0 not checked. [2018-07-24 10:57:05,610 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:06,540 INFO L134 CoverageAnalysis]: Checked inductivity of 3432 backedges. 1430 proven. 702 refuted. 0 times theorem prover too weak. 1300 trivial. 0 not checked. [2018-07-24 10:57:06,560 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:06,561 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 103 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 103 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:06,575 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:57:06,575 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:57:07,314 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2018-07-24 10:57:07,314 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:07,324 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:07,411 INFO L134 CoverageAnalysis]: Checked inductivity of 3432 backedges. 1430 proven. 702 refuted. 0 times theorem prover too weak. 1300 trivial. 0 not checked. [2018-07-24 10:57:07,411 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:08,386 INFO L134 CoverageAnalysis]: Checked inductivity of 3432 backedges. 1430 proven. 702 refuted. 0 times theorem prover too weak. 1300 trivial. 0 not checked. [2018-07-24 10:57:08,387 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:08,387 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [57, 57, 57, 57, 57] total 84 [2018-07-24 10:57:08,387 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:08,388 INFO L450 AbstractCegarLoop]: Interpolant automaton has 84 states [2018-07-24 10:57:08,388 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 84 interpolants. [2018-07-24 10:57:08,389 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1623, Invalid=5349, Unknown=0, NotChecked=0, Total=6972 [2018-07-24 10:57:08,389 INFO L87 Difference]: Start difference. First operand 277 states and 278 transitions. Second operand 84 states. [2018-07-24 10:57:10,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:10,026 INFO L93 Difference]: Finished difference Result 396 states and 424 transitions. [2018-07-24 10:57:10,026 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2018-07-24 10:57:10,026 INFO L78 Accepts]: Start accepts. Automaton has 84 states. Word has length 274 [2018-07-24 10:57:10,027 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:10,028 INFO L225 Difference]: With dead ends: 396 [2018-07-24 10:57:10,028 INFO L226 Difference]: Without dead ends: 279 [2018-07-24 10:57:10,029 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1179 GetRequests, 961 SyntacticMatches, 108 SemanticMatches, 110 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7504 ImplicationChecksByTransitivity, 5.1s TimeCoverageRelationStatistics Valid=2869, Invalid=9563, Unknown=0, NotChecked=0, Total=12432 [2018-07-24 10:57:10,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 279 states. [2018-07-24 10:57:10,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 279 to 279. [2018-07-24 10:57:10,039 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 279 states. [2018-07-24 10:57:10,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 279 states to 279 states and 280 transitions. [2018-07-24 10:57:10,040 INFO L78 Accepts]: Start accepts. Automaton has 279 states and 280 transitions. Word has length 274 [2018-07-24 10:57:10,040 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:10,040 INFO L471 AbstractCegarLoop]: Abstraction has 279 states and 280 transitions. [2018-07-24 10:57:10,040 INFO L472 AbstractCegarLoop]: Interpolant automaton has 84 states. [2018-07-24 10:57:10,040 INFO L276 IsEmpty]: Start isEmpty. Operand 279 states and 280 transitions. [2018-07-24 10:57:10,042 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 277 [2018-07-24 10:57:10,042 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:10,042 INFO L353 BasicCegarLoop]: trace histogram [28, 27, 27, 27, 27, 27, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:10,042 INFO L414 AbstractCegarLoop]: === Iteration 55 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:10,042 INFO L82 PathProgramCache]: Analyzing trace with hash -1678809539, now seen corresponding path program 52 times [2018-07-24 10:57:10,042 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:10,043 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:10,043 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:10,043 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:10,043 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:10,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:10,692 INFO L134 CoverageAnalysis]: Checked inductivity of 3486 backedges. 807 proven. 1454 refuted. 0 times theorem prover too weak. 1225 trivial. 0 not checked. [2018-07-24 10:57:10,692 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:10,692 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 104 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 104 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:10,700 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:57:10,700 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:57:10,784 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:57:10,784 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:10,789 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:10,889 INFO L134 CoverageAnalysis]: Checked inductivity of 3486 backedges. 808 proven. 1378 refuted. 0 times theorem prover too weak. 1300 trivial. 0 not checked. [2018-07-24 10:57:10,889 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:11,567 INFO L134 CoverageAnalysis]: Checked inductivity of 3486 backedges. 808 proven. 1378 refuted. 0 times theorem prover too weak. 1300 trivial. 0 not checked. [2018-07-24 10:57:11,587 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:11,587 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 105 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 105 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:11,602 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:57:11,602 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:57:11,815 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:57:11,815 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:11,824 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:11,872 INFO L134 CoverageAnalysis]: Checked inductivity of 3486 backedges. 808 proven. 1378 refuted. 0 times theorem prover too weak. 1300 trivial. 0 not checked. [2018-07-24 10:57:11,872 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:12,734 INFO L134 CoverageAnalysis]: Checked inductivity of 3486 backedges. 808 proven. 1378 refuted. 0 times theorem prover too weak. 1300 trivial. 0 not checked. [2018-07-24 10:57:12,735 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:12,735 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 32, 32, 32, 32] total 35 [2018-07-24 10:57:12,735 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:12,736 INFO L450 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-07-24 10:57:12,736 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-07-24 10:57:12,736 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=447, Invalid=743, Unknown=0, NotChecked=0, Total=1190 [2018-07-24 10:57:12,737 INFO L87 Difference]: Start difference. First operand 279 states and 280 transitions. Second operand 35 states. [2018-07-24 10:57:13,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:13,110 INFO L93 Difference]: Finished difference Result 289 states and 290 transitions. [2018-07-24 10:57:13,110 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-07-24 10:57:13,110 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 276 [2018-07-24 10:57:13,111 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:13,112 INFO L225 Difference]: With dead ends: 289 [2018-07-24 10:57:13,112 INFO L226 Difference]: Without dead ends: 287 [2018-07-24 10:57:13,113 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1165 GetRequests, 1020 SyntacticMatches, 110 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1705 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=460, Invalid=872, Unknown=0, NotChecked=0, Total=1332 [2018-07-24 10:57:13,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 287 states. [2018-07-24 10:57:13,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 287 to 287. [2018-07-24 10:57:13,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 287 states. [2018-07-24 10:57:13,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 287 states to 287 states and 288 transitions. [2018-07-24 10:57:13,125 INFO L78 Accepts]: Start accepts. Automaton has 287 states and 288 transitions. Word has length 276 [2018-07-24 10:57:13,125 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:13,125 INFO L471 AbstractCegarLoop]: Abstraction has 287 states and 288 transitions. [2018-07-24 10:57:13,126 INFO L472 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-07-24 10:57:13,126 INFO L276 IsEmpty]: Start isEmpty. Operand 287 states and 288 transitions. [2018-07-24 10:57:13,127 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 285 [2018-07-24 10:57:13,127 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:13,127 INFO L353 BasicCegarLoop]: trace histogram [28, 28, 28, 28, 28, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:13,128 INFO L414 AbstractCegarLoop]: === Iteration 56 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:13,128 INFO L82 PathProgramCache]: Analyzing trace with hash -1941926303, now seen corresponding path program 53 times [2018-07-24 10:57:13,128 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:13,129 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:13,129 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:13,129 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:13,129 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:13,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:14,664 INFO L134 CoverageAnalysis]: Checked inductivity of 3699 backedges. 1539 proven. 756 refuted. 0 times theorem prover too weak. 1404 trivial. 0 not checked. [2018-07-24 10:57:14,664 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:14,664 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 106 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 106 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:14,671 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:57:14,671 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:14,786 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2018-07-24 10:57:14,786 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:14,791 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:16,080 INFO L134 CoverageAnalysis]: Checked inductivity of 3699 backedges. 1539 proven. 756 refuted. 0 times theorem prover too weak. 1404 trivial. 0 not checked. [2018-07-24 10:57:16,081 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:17,407 INFO L134 CoverageAnalysis]: Checked inductivity of 3699 backedges. 1539 proven. 756 refuted. 0 times theorem prover too weak. 1404 trivial. 0 not checked. [2018-07-24 10:57:17,427 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:17,427 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 107 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 107 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:17,443 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:57:17,444 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:18,249 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2018-07-24 10:57:18,249 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:18,258 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:18,351 INFO L134 CoverageAnalysis]: Checked inductivity of 3699 backedges. 1539 proven. 756 refuted. 0 times theorem prover too weak. 1404 trivial. 0 not checked. [2018-07-24 10:57:18,351 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:19,382 INFO L134 CoverageAnalysis]: Checked inductivity of 3699 backedges. 1539 proven. 756 refuted. 0 times theorem prover too weak. 1404 trivial. 0 not checked. [2018-07-24 10:57:19,384 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:19,384 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59, 59, 59] total 87 [2018-07-24 10:57:19,385 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:19,385 INFO L450 AbstractCegarLoop]: Interpolant automaton has 87 states [2018-07-24 10:57:19,385 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 87 interpolants. [2018-07-24 10:57:19,386 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1739, Invalid=5743, Unknown=0, NotChecked=0, Total=7482 [2018-07-24 10:57:19,386 INFO L87 Difference]: Start difference. First operand 287 states and 288 transitions. Second operand 87 states. [2018-07-24 10:57:21,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:21,158 INFO L93 Difference]: Finished difference Result 410 states and 439 transitions. [2018-07-24 10:57:21,158 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-07-24 10:57:21,158 INFO L78 Accepts]: Start accepts. Automaton has 87 states. Word has length 284 [2018-07-24 10:57:21,158 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:21,159 INFO L225 Difference]: With dead ends: 410 [2018-07-24 10:57:21,159 INFO L226 Difference]: Without dead ends: 289 [2018-07-24 10:57:21,161 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1222 GetRequests, 996 SyntacticMatches, 112 SemanticMatches, 114 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8076 ImplicationChecksByTransitivity, 5.4s TimeCoverageRelationStatistics Valid=3073, Invalid=10267, Unknown=0, NotChecked=0, Total=13340 [2018-07-24 10:57:21,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 289 states. [2018-07-24 10:57:21,174 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 289 to 289. [2018-07-24 10:57:21,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 289 states. [2018-07-24 10:57:21,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 289 states to 289 states and 290 transitions. [2018-07-24 10:57:21,175 INFO L78 Accepts]: Start accepts. Automaton has 289 states and 290 transitions. Word has length 284 [2018-07-24 10:57:21,175 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:21,175 INFO L471 AbstractCegarLoop]: Abstraction has 289 states and 290 transitions. [2018-07-24 10:57:21,175 INFO L472 AbstractCegarLoop]: Interpolant automaton has 87 states. [2018-07-24 10:57:21,175 INFO L276 IsEmpty]: Start isEmpty. Operand 289 states and 290 transitions. [2018-07-24 10:57:21,177 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 287 [2018-07-24 10:57:21,177 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:21,177 INFO L353 BasicCegarLoop]: trace histogram [29, 28, 28, 28, 28, 28, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:21,177 INFO L414 AbstractCegarLoop]: === Iteration 57 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:21,178 INFO L82 PathProgramCache]: Analyzing trace with hash 216779419, now seen corresponding path program 54 times [2018-07-24 10:57:21,178 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:21,178 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:21,178 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:21,179 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:21,179 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:21,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:21,718 INFO L134 CoverageAnalysis]: Checked inductivity of 3755 backedges. 865 proven. 1564 refuted. 0 times theorem prover too weak. 1326 trivial. 0 not checked. [2018-07-24 10:57:21,718 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:21,718 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 108 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 108 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:21,726 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:57:21,726 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:57:21,840 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 29 check-sat command(s) [2018-07-24 10:57:21,840 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:21,845 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:21,970 INFO L134 CoverageAnalysis]: Checked inductivity of 3755 backedges. 866 proven. 1485 refuted. 0 times theorem prover too weak. 1404 trivial. 0 not checked. [2018-07-24 10:57:21,971 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:22,974 INFO L134 CoverageAnalysis]: Checked inductivity of 3755 backedges. 866 proven. 1485 refuted. 0 times theorem prover too weak. 1404 trivial. 0 not checked. [2018-07-24 10:57:22,994 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:22,995 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 109 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 109 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:23,011 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:57:23,011 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:57:23,836 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 29 check-sat command(s) [2018-07-24 10:57:23,836 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:23,846 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:23,895 INFO L134 CoverageAnalysis]: Checked inductivity of 3755 backedges. 866 proven. 1485 refuted. 0 times theorem prover too weak. 1404 trivial. 0 not checked. [2018-07-24 10:57:23,896 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:24,587 INFO L134 CoverageAnalysis]: Checked inductivity of 3755 backedges. 866 proven. 1485 refuted. 0 times theorem prover too weak. 1404 trivial. 0 not checked. [2018-07-24 10:57:24,588 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:24,588 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 33, 33, 33, 33] total 36 [2018-07-24 10:57:24,589 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:24,589 INFO L450 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-07-24 10:57:24,589 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-07-24 10:57:24,589 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=477, Invalid=783, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:57:24,590 INFO L87 Difference]: Start difference. First operand 289 states and 290 transitions. Second operand 36 states. [2018-07-24 10:57:25,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:25,017 INFO L93 Difference]: Finished difference Result 299 states and 300 transitions. [2018-07-24 10:57:25,017 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-07-24 10:57:25,017 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 286 [2018-07-24 10:57:25,018 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:25,019 INFO L225 Difference]: With dead ends: 299 [2018-07-24 10:57:25,020 INFO L226 Difference]: Without dead ends: 297 [2018-07-24 10:57:25,020 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1207 GetRequests, 1057 SyntacticMatches, 114 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1824 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=490, Invalid=916, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:57:25,020 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 297 states. [2018-07-24 10:57:25,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 297 to 297. [2018-07-24 10:57:25,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 297 states. [2018-07-24 10:57:25,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 297 states to 297 states and 298 transitions. [2018-07-24 10:57:25,032 INFO L78 Accepts]: Start accepts. Automaton has 297 states and 298 transitions. Word has length 286 [2018-07-24 10:57:25,032 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:25,032 INFO L471 AbstractCegarLoop]: Abstraction has 297 states and 298 transitions. [2018-07-24 10:57:25,032 INFO L472 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-07-24 10:57:25,032 INFO L276 IsEmpty]: Start isEmpty. Operand 297 states and 298 transitions. [2018-07-24 10:57:25,034 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 295 [2018-07-24 10:57:25,034 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:25,034 INFO L353 BasicCegarLoop]: trace histogram [29, 29, 29, 29, 29, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:25,034 INFO L414 AbstractCegarLoop]: === Iteration 58 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:25,035 INFO L82 PathProgramCache]: Analyzing trace with hash 1840886975, now seen corresponding path program 55 times [2018-07-24 10:57:25,035 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:25,035 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:25,035 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:25,036 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:25,036 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:25,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:26,318 INFO L134 CoverageAnalysis]: Checked inductivity of 3976 backedges. 1652 proven. 812 refuted. 0 times theorem prover too weak. 1512 trivial. 0 not checked. [2018-07-24 10:57:26,318 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:26,318 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 110 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 110 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:26,327 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:26,327 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:57:26,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:26,415 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:28,051 INFO L134 CoverageAnalysis]: Checked inductivity of 3976 backedges. 1652 proven. 812 refuted. 0 times theorem prover too weak. 1512 trivial. 0 not checked. [2018-07-24 10:57:28,052 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:29,163 INFO L134 CoverageAnalysis]: Checked inductivity of 3976 backedges. 1652 proven. 812 refuted. 0 times theorem prover too weak. 1512 trivial. 0 not checked. [2018-07-24 10:57:29,183 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:29,184 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 111 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 111 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:29,198 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:29,198 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:57:29,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:29,392 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:29,472 INFO L134 CoverageAnalysis]: Checked inductivity of 3976 backedges. 1652 proven. 812 refuted. 0 times theorem prover too weak. 1512 trivial. 0 not checked. [2018-07-24 10:57:29,473 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:30,597 INFO L134 CoverageAnalysis]: Checked inductivity of 3976 backedges. 1652 proven. 812 refuted. 0 times theorem prover too weak. 1512 trivial. 0 not checked. [2018-07-24 10:57:30,599 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:30,599 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [61, 61, 61, 61, 61] total 90 [2018-07-24 10:57:30,599 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:30,600 INFO L450 AbstractCegarLoop]: Interpolant automaton has 90 states [2018-07-24 10:57:30,600 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 90 interpolants. [2018-07-24 10:57:30,600 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1859, Invalid=6151, Unknown=0, NotChecked=0, Total=8010 [2018-07-24 10:57:30,601 INFO L87 Difference]: Start difference. First operand 297 states and 298 transitions. Second operand 90 states. [2018-07-24 10:57:32,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:32,539 INFO L93 Difference]: Finished difference Result 424 states and 454 transitions. [2018-07-24 10:57:32,539 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2018-07-24 10:57:32,539 INFO L78 Accepts]: Start accepts. Automaton has 90 states. Word has length 294 [2018-07-24 10:57:32,539 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:32,540 INFO L225 Difference]: With dead ends: 424 [2018-07-24 10:57:32,540 INFO L226 Difference]: Without dead ends: 299 [2018-07-24 10:57:32,541 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1265 GetRequests, 1031 SyntacticMatches, 116 SemanticMatches, 118 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8669 ImplicationChecksByTransitivity, 5.5s TimeCoverageRelationStatistics Valid=3284, Invalid=10996, Unknown=0, NotChecked=0, Total=14280 [2018-07-24 10:57:32,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 299 states. [2018-07-24 10:57:32,553 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 299 to 299. [2018-07-24 10:57:32,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 299 states. [2018-07-24 10:57:32,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 299 states to 299 states and 300 transitions. [2018-07-24 10:57:32,554 INFO L78 Accepts]: Start accepts. Automaton has 299 states and 300 transitions. Word has length 294 [2018-07-24 10:57:32,555 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:32,555 INFO L471 AbstractCegarLoop]: Abstraction has 299 states and 300 transitions. [2018-07-24 10:57:32,555 INFO L472 AbstractCegarLoop]: Interpolant automaton has 90 states. [2018-07-24 10:57:32,555 INFO L276 IsEmpty]: Start isEmpty. Operand 299 states and 300 transitions. [2018-07-24 10:57:32,556 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 297 [2018-07-24 10:57:32,557 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:32,557 INFO L353 BasicCegarLoop]: trace histogram [30, 29, 29, 29, 29, 29, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:32,557 INFO L414 AbstractCegarLoop]: === Iteration 59 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:32,557 INFO L82 PathProgramCache]: Analyzing trace with hash -1436913543, now seen corresponding path program 56 times [2018-07-24 10:57:32,557 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:32,558 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:32,558 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:32,558 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:32,558 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:32,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:33,696 INFO L134 CoverageAnalysis]: Checked inductivity of 4034 backedges. 925 proven. 1678 refuted. 0 times theorem prover too weak. 1431 trivial. 0 not checked. [2018-07-24 10:57:33,696 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:33,696 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 112 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 112 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:33,703 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:57:33,703 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:33,792 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:57:33,793 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:33,797 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:33,910 INFO L134 CoverageAnalysis]: Checked inductivity of 4034 backedges. 926 proven. 1596 refuted. 0 times theorem prover too weak. 1512 trivial. 0 not checked. [2018-07-24 10:57:33,911 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:34,636 INFO L134 CoverageAnalysis]: Checked inductivity of 4034 backedges. 926 proven. 1596 refuted. 0 times theorem prover too weak. 1512 trivial. 0 not checked. [2018-07-24 10:57:34,656 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:34,656 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 113 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 113 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:34,671 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:57:34,671 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:34,869 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:57:34,869 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:34,877 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:34,949 INFO L134 CoverageAnalysis]: Checked inductivity of 4034 backedges. 926 proven. 1596 refuted. 0 times theorem prover too weak. 1512 trivial. 0 not checked. [2018-07-24 10:57:34,950 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:35,719 INFO L134 CoverageAnalysis]: Checked inductivity of 4034 backedges. 926 proven. 1596 refuted. 0 times theorem prover too weak. 1512 trivial. 0 not checked. [2018-07-24 10:57:35,721 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:35,721 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 34, 34, 34, 34] total 37 [2018-07-24 10:57:35,721 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:35,722 INFO L450 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-07-24 10:57:35,722 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-07-24 10:57:35,722 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=508, Invalid=824, Unknown=0, NotChecked=0, Total=1332 [2018-07-24 10:57:35,722 INFO L87 Difference]: Start difference. First operand 299 states and 300 transitions. Second operand 37 states. [2018-07-24 10:57:36,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:36,157 INFO L93 Difference]: Finished difference Result 309 states and 310 transitions. [2018-07-24 10:57:36,157 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-07-24 10:57:36,157 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 296 [2018-07-24 10:57:36,158 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:36,159 INFO L225 Difference]: With dead ends: 309 [2018-07-24 10:57:36,160 INFO L226 Difference]: Without dead ends: 307 [2018-07-24 10:57:36,160 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1249 GetRequests, 1094 SyntacticMatches, 118 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1947 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=521, Invalid=961, Unknown=0, NotChecked=0, Total=1482 [2018-07-24 10:57:36,160 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 307 states. [2018-07-24 10:57:36,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 307 to 307. [2018-07-24 10:57:36,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 307 states. [2018-07-24 10:57:36,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 307 states to 307 states and 308 transitions. [2018-07-24 10:57:36,169 INFO L78 Accepts]: Start accepts. Automaton has 307 states and 308 transitions. Word has length 296 [2018-07-24 10:57:36,170 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:36,170 INFO L471 AbstractCegarLoop]: Abstraction has 307 states and 308 transitions. [2018-07-24 10:57:36,170 INFO L472 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-07-24 10:57:36,170 INFO L276 IsEmpty]: Start isEmpty. Operand 307 states and 308 transitions. [2018-07-24 10:57:36,172 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 305 [2018-07-24 10:57:36,172 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:36,172 INFO L353 BasicCegarLoop]: trace histogram [30, 30, 30, 30, 30, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:36,172 INFO L414 AbstractCegarLoop]: === Iteration 60 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:36,172 INFO L82 PathProgramCache]: Analyzing trace with hash 1812700317, now seen corresponding path program 57 times [2018-07-24 10:57:36,173 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:36,173 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:36,173 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:36,173 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:36,173 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:36,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:37,490 INFO L134 CoverageAnalysis]: Checked inductivity of 4263 backedges. 1769 proven. 870 refuted. 0 times theorem prover too weak. 1624 trivial. 0 not checked. [2018-07-24 10:57:37,490 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:37,490 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 114 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 114 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:37,516 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:57:37,516 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:57:37,639 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2018-07-24 10:57:37,639 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:37,643 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:39,182 INFO L134 CoverageAnalysis]: Checked inductivity of 4263 backedges. 1769 proven. 870 refuted. 0 times theorem prover too weak. 1624 trivial. 0 not checked. [2018-07-24 10:57:39,182 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:40,380 INFO L134 CoverageAnalysis]: Checked inductivity of 4263 backedges. 1769 proven. 870 refuted. 0 times theorem prover too weak. 1624 trivial. 0 not checked. [2018-07-24 10:57:40,400 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:40,401 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 115 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 115 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:40,415 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:57:40,415 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:57:41,383 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2018-07-24 10:57:41,383 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:41,393 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:41,480 INFO L134 CoverageAnalysis]: Checked inductivity of 4263 backedges. 1769 proven. 870 refuted. 0 times theorem prover too weak. 1624 trivial. 0 not checked. [2018-07-24 10:57:41,480 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:42,911 INFO L134 CoverageAnalysis]: Checked inductivity of 4263 backedges. 1769 proven. 870 refuted. 0 times theorem prover too weak. 1624 trivial. 0 not checked. [2018-07-24 10:57:42,913 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:42,913 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [63, 63, 63, 63, 63] total 93 [2018-07-24 10:57:42,914 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:42,914 INFO L450 AbstractCegarLoop]: Interpolant automaton has 93 states [2018-07-24 10:57:42,915 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 93 interpolants. [2018-07-24 10:57:42,915 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1983, Invalid=6573, Unknown=0, NotChecked=0, Total=8556 [2018-07-24 10:57:42,916 INFO L87 Difference]: Start difference. First operand 307 states and 308 transitions. Second operand 93 states. [2018-07-24 10:57:44,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:44,824 INFO L93 Difference]: Finished difference Result 438 states and 469 transitions. [2018-07-24 10:57:44,824 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-07-24 10:57:44,824 INFO L78 Accepts]: Start accepts. Automaton has 93 states. Word has length 304 [2018-07-24 10:57:44,825 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:44,826 INFO L225 Difference]: With dead ends: 438 [2018-07-24 10:57:44,826 INFO L226 Difference]: Without dead ends: 309 [2018-07-24 10:57:44,827 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1308 GetRequests, 1066 SyntacticMatches, 120 SemanticMatches, 122 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9283 ImplicationChecksByTransitivity, 5.8s TimeCoverageRelationStatistics Valid=3502, Invalid=11750, Unknown=0, NotChecked=0, Total=15252 [2018-07-24 10:57:44,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 309 states. [2018-07-24 10:57:44,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 309 to 309. [2018-07-24 10:57:44,839 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 309 states. [2018-07-24 10:57:44,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 309 states to 309 states and 310 transitions. [2018-07-24 10:57:44,840 INFO L78 Accepts]: Start accepts. Automaton has 309 states and 310 transitions. Word has length 304 [2018-07-24 10:57:44,840 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:44,840 INFO L471 AbstractCegarLoop]: Abstraction has 309 states and 310 transitions. [2018-07-24 10:57:44,840 INFO L472 AbstractCegarLoop]: Interpolant automaton has 93 states. [2018-07-24 10:57:44,840 INFO L276 IsEmpty]: Start isEmpty. Operand 309 states and 310 transitions. [2018-07-24 10:57:44,842 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 307 [2018-07-24 10:57:44,842 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:44,842 INFO L353 BasicCegarLoop]: trace histogram [31, 30, 30, 30, 30, 30, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:44,842 INFO L414 AbstractCegarLoop]: === Iteration 61 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:44,843 INFO L82 PathProgramCache]: Analyzing trace with hash -1654097961, now seen corresponding path program 58 times [2018-07-24 10:57:44,843 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:44,843 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:44,844 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:44,844 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:44,844 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:44,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:45,455 INFO L134 CoverageAnalysis]: Checked inductivity of 4323 backedges. 987 proven. 1796 refuted. 0 times theorem prover too weak. 1540 trivial. 0 not checked. [2018-07-24 10:57:45,455 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:45,455 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 116 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 116 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:45,462 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:57:45,462 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:57:45,554 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:57:45,554 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:45,558 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:45,655 INFO L134 CoverageAnalysis]: Checked inductivity of 4323 backedges. 988 proven. 1711 refuted. 0 times theorem prover too weak. 1624 trivial. 0 not checked. [2018-07-24 10:57:45,656 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:46,451 INFO L134 CoverageAnalysis]: Checked inductivity of 4323 backedges. 988 proven. 1711 refuted. 0 times theorem prover too weak. 1624 trivial. 0 not checked. [2018-07-24 10:57:46,471 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:46,471 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 117 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 117 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:46,486 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:57:46,486 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:57:46,737 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:57:46,738 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:46,753 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:46,809 INFO L134 CoverageAnalysis]: Checked inductivity of 4323 backedges. 988 proven. 1711 refuted. 0 times theorem prover too weak. 1624 trivial. 0 not checked. [2018-07-24 10:57:46,809 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:47,600 INFO L134 CoverageAnalysis]: Checked inductivity of 4323 backedges. 988 proven. 1711 refuted. 0 times theorem prover too weak. 1624 trivial. 0 not checked. [2018-07-24 10:57:47,602 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:47,602 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 35, 35, 35, 35] total 38 [2018-07-24 10:57:47,602 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:47,603 INFO L450 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-07-24 10:57:47,603 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-07-24 10:57:47,603 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=540, Invalid=866, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:57:47,603 INFO L87 Difference]: Start difference. First operand 309 states and 310 transitions. Second operand 38 states. [2018-07-24 10:57:48,215 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:48,216 INFO L93 Difference]: Finished difference Result 319 states and 320 transitions. [2018-07-24 10:57:48,216 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-07-24 10:57:48,216 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 306 [2018-07-24 10:57:48,217 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:48,218 INFO L225 Difference]: With dead ends: 319 [2018-07-24 10:57:48,218 INFO L226 Difference]: Without dead ends: 317 [2018-07-24 10:57:48,219 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1291 GetRequests, 1131 SyntacticMatches, 122 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2074 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=553, Invalid=1007, Unknown=0, NotChecked=0, Total=1560 [2018-07-24 10:57:48,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 317 states. [2018-07-24 10:57:48,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 317 to 317. [2018-07-24 10:57:48,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 317 states. [2018-07-24 10:57:48,228 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 317 states to 317 states and 318 transitions. [2018-07-24 10:57:48,228 INFO L78 Accepts]: Start accepts. Automaton has 317 states and 318 transitions. Word has length 306 [2018-07-24 10:57:48,228 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:48,228 INFO L471 AbstractCegarLoop]: Abstraction has 317 states and 318 transitions. [2018-07-24 10:57:48,228 INFO L472 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-07-24 10:57:48,228 INFO L276 IsEmpty]: Start isEmpty. Operand 317 states and 318 transitions. [2018-07-24 10:57:48,230 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 315 [2018-07-24 10:57:48,230 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:48,230 INFO L353 BasicCegarLoop]: trace histogram [31, 31, 31, 31, 31, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:48,230 INFO L414 AbstractCegarLoop]: === Iteration 62 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:48,230 INFO L82 PathProgramCache]: Analyzing trace with hash -1052547589, now seen corresponding path program 59 times [2018-07-24 10:57:48,231 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:48,231 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:48,231 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:48,236 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:48,236 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:48,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:49,645 INFO L134 CoverageAnalysis]: Checked inductivity of 4560 backedges. 1890 proven. 930 refuted. 0 times theorem prover too weak. 1740 trivial. 0 not checked. [2018-07-24 10:57:49,646 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:49,646 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 118 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 118 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:49,654 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:57:49,654 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:49,783 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 31 check-sat command(s) [2018-07-24 10:57:49,783 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:49,788 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:51,838 INFO L134 CoverageAnalysis]: Checked inductivity of 4560 backedges. 1890 proven. 930 refuted. 0 times theorem prover too weak. 1740 trivial. 0 not checked. [2018-07-24 10:57:51,838 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:53,428 INFO L134 CoverageAnalysis]: Checked inductivity of 4560 backedges. 1890 proven. 930 refuted. 0 times theorem prover too weak. 1740 trivial. 0 not checked. [2018-07-24 10:57:53,450 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:53,450 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 119 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 119 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:53,465 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:57:53,465 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:54,434 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 31 check-sat command(s) [2018-07-24 10:57:54,434 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:54,443 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:54,540 INFO L134 CoverageAnalysis]: Checked inductivity of 4560 backedges. 1890 proven. 930 refuted. 0 times theorem prover too weak. 1740 trivial. 0 not checked. [2018-07-24 10:57:54,540 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:55,776 INFO L134 CoverageAnalysis]: Checked inductivity of 4560 backedges. 1890 proven. 930 refuted. 0 times theorem prover too weak. 1740 trivial. 0 not checked. [2018-07-24 10:57:55,777 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:55,778 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [65, 65, 65, 65, 65] total 96 [2018-07-24 10:57:55,778 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:55,778 INFO L450 AbstractCegarLoop]: Interpolant automaton has 96 states [2018-07-24 10:57:55,779 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 96 interpolants. [2018-07-24 10:57:55,779 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2111, Invalid=7009, Unknown=0, NotChecked=0, Total=9120 [2018-07-24 10:57:55,779 INFO L87 Difference]: Start difference. First operand 317 states and 318 transitions. Second operand 96 states. [2018-07-24 10:57:57,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:57,881 INFO L93 Difference]: Finished difference Result 452 states and 484 transitions. [2018-07-24 10:57:57,881 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-07-24 10:57:57,881 INFO L78 Accepts]: Start accepts. Automaton has 96 states. Word has length 314 [2018-07-24 10:57:57,882 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:57,883 INFO L225 Difference]: With dead ends: 452 [2018-07-24 10:57:57,883 INFO L226 Difference]: Without dead ends: 319 [2018-07-24 10:57:57,884 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1351 GetRequests, 1101 SyntacticMatches, 124 SemanticMatches, 126 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9918 ImplicationChecksByTransitivity, 6.6s TimeCoverageRelationStatistics Valid=3727, Invalid=12529, Unknown=0, NotChecked=0, Total=16256 [2018-07-24 10:57:57,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 319 states. [2018-07-24 10:57:57,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 319 to 319. [2018-07-24 10:57:57,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 319 states. [2018-07-24 10:57:57,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 319 states to 319 states and 320 transitions. [2018-07-24 10:57:57,894 INFO L78 Accepts]: Start accepts. Automaton has 319 states and 320 transitions. Word has length 314 [2018-07-24 10:57:57,894 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:57,894 INFO L471 AbstractCegarLoop]: Abstraction has 319 states and 320 transitions. [2018-07-24 10:57:57,894 INFO L472 AbstractCegarLoop]: Interpolant automaton has 96 states. [2018-07-24 10:57:57,894 INFO L276 IsEmpty]: Start isEmpty. Operand 319 states and 320 transitions. [2018-07-24 10:57:57,896 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 317 [2018-07-24 10:57:57,896 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:57,896 INFO L353 BasicCegarLoop]: trace histogram [32, 31, 31, 31, 31, 31, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:57,896 INFO L414 AbstractCegarLoop]: === Iteration 63 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:57,896 INFO L82 PathProgramCache]: Analyzing trace with hash 1348141237, now seen corresponding path program 60 times [2018-07-24 10:57:57,896 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:57,897 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:57,897 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:57,897 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:57,897 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:57,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:58,631 INFO L134 CoverageAnalysis]: Checked inductivity of 4622 backedges. 1051 proven. 1918 refuted. 0 times theorem prover too weak. 1653 trivial. 0 not checked. [2018-07-24 10:57:58,631 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:58,631 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 120 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 120 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:58,639 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:57:58,639 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:57:58,909 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 32 check-sat command(s) [2018-07-24 10:57:58,909 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:58,913 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:59,032 INFO L134 CoverageAnalysis]: Checked inductivity of 4622 backedges. 1052 proven. 1830 refuted. 0 times theorem prover too weak. 1740 trivial. 0 not checked. [2018-07-24 10:57:59,032 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:59,847 INFO L134 CoverageAnalysis]: Checked inductivity of 4622 backedges. 1052 proven. 1830 refuted. 0 times theorem prover too weak. 1740 trivial. 0 not checked. [2018-07-24 10:57:59,868 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:59,868 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 121 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 121 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:59,883 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:57:59,883 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:58:00,876 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 32 check-sat command(s) [2018-07-24 10:58:00,876 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:00,888 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:00,947 INFO L134 CoverageAnalysis]: Checked inductivity of 4622 backedges. 1052 proven. 1830 refuted. 0 times theorem prover too weak. 1740 trivial. 0 not checked. [2018-07-24 10:58:00,948 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:01,780 INFO L134 CoverageAnalysis]: Checked inductivity of 4622 backedges. 1052 proven. 1830 refuted. 0 times theorem prover too weak. 1740 trivial. 0 not checked. [2018-07-24 10:58:01,781 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:01,782 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 36, 36, 36, 36] total 39 [2018-07-24 10:58:01,782 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:01,782 INFO L450 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-07-24 10:58:01,782 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-07-24 10:58:01,783 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=573, Invalid=909, Unknown=0, NotChecked=0, Total=1482 [2018-07-24 10:58:01,783 INFO L87 Difference]: Start difference. First operand 319 states and 320 transitions. Second operand 39 states. [2018-07-24 10:58:02,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:02,225 INFO L93 Difference]: Finished difference Result 329 states and 330 transitions. [2018-07-24 10:58:02,226 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-07-24 10:58:02,226 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 316 [2018-07-24 10:58:02,226 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:02,228 INFO L225 Difference]: With dead ends: 329 [2018-07-24 10:58:02,228 INFO L226 Difference]: Without dead ends: 327 [2018-07-24 10:58:02,229 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1333 GetRequests, 1168 SyntacticMatches, 126 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2205 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=586, Invalid=1054, Unknown=0, NotChecked=0, Total=1640 [2018-07-24 10:58:02,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states. [2018-07-24 10:58:02,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 327. [2018-07-24 10:58:02,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 327 states. [2018-07-24 10:58:02,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 327 states to 327 states and 328 transitions. [2018-07-24 10:58:02,238 INFO L78 Accepts]: Start accepts. Automaton has 327 states and 328 transitions. Word has length 316 [2018-07-24 10:58:02,238 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:02,238 INFO L471 AbstractCegarLoop]: Abstraction has 327 states and 328 transitions. [2018-07-24 10:58:02,238 INFO L472 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-07-24 10:58:02,239 INFO L276 IsEmpty]: Start isEmpty. Operand 327 states and 328 transitions. [2018-07-24 10:58:02,240 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 325 [2018-07-24 10:58:02,240 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:02,240 INFO L353 BasicCegarLoop]: trace histogram [32, 32, 32, 32, 32, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:02,241 INFO L414 AbstractCegarLoop]: === Iteration 64 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:02,241 INFO L82 PathProgramCache]: Analyzing trace with hash 1350971609, now seen corresponding path program 61 times [2018-07-24 10:58:02,241 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:02,242 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:02,242 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:02,242 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:02,242 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:02,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:03,973 INFO L134 CoverageAnalysis]: Checked inductivity of 4867 backedges. 2015 proven. 992 refuted. 0 times theorem prover too weak. 1860 trivial. 0 not checked. [2018-07-24 10:58:03,973 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:03,973 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 122 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 122 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:03,980 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:58:03,980 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:58:04,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:04,091 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:05,766 INFO L134 CoverageAnalysis]: Checked inductivity of 4867 backedges. 2015 proven. 992 refuted. 0 times theorem prover too weak. 1860 trivial. 0 not checked. [2018-07-24 10:58:05,766 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:07,183 INFO L134 CoverageAnalysis]: Checked inductivity of 4867 backedges. 2015 proven. 992 refuted. 0 times theorem prover too weak. 1860 trivial. 0 not checked. [2018-07-24 10:58:07,203 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:07,203 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 123 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 123 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:07,218 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:58:07,218 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:58:07,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:07,424 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:07,516 INFO L134 CoverageAnalysis]: Checked inductivity of 4867 backedges. 2015 proven. 992 refuted. 0 times theorem prover too weak. 1860 trivial. 0 not checked. [2018-07-24 10:58:07,516 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:09,151 INFO L134 CoverageAnalysis]: Checked inductivity of 4867 backedges. 2015 proven. 992 refuted. 0 times theorem prover too weak. 1860 trivial. 0 not checked. [2018-07-24 10:58:09,153 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:09,154 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [67, 67, 67, 67, 67] total 99 [2018-07-24 10:58:09,154 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:09,154 INFO L450 AbstractCegarLoop]: Interpolant automaton has 99 states [2018-07-24 10:58:09,155 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 99 interpolants. [2018-07-24 10:58:09,155 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2243, Invalid=7459, Unknown=0, NotChecked=0, Total=9702 [2018-07-24 10:58:09,156 INFO L87 Difference]: Start difference. First operand 327 states and 328 transitions. Second operand 99 states. [2018-07-24 10:58:11,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:11,119 INFO L93 Difference]: Finished difference Result 466 states and 499 transitions. [2018-07-24 10:58:11,119 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2018-07-24 10:58:11,119 INFO L78 Accepts]: Start accepts. Automaton has 99 states. Word has length 324 [2018-07-24 10:58:11,120 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:11,121 INFO L225 Difference]: With dead ends: 466 [2018-07-24 10:58:11,121 INFO L226 Difference]: Without dead ends: 329 [2018-07-24 10:58:11,123 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1394 GetRequests, 1136 SyntacticMatches, 128 SemanticMatches, 130 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10574 ImplicationChecksByTransitivity, 6.8s TimeCoverageRelationStatistics Valid=3959, Invalid=13333, Unknown=0, NotChecked=0, Total=17292 [2018-07-24 10:58:11,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 329 states. [2018-07-24 10:58:11,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 329 to 329. [2018-07-24 10:58:11,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 329 states. [2018-07-24 10:58:11,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 329 states to 329 states and 330 transitions. [2018-07-24 10:58:11,134 INFO L78 Accepts]: Start accepts. Automaton has 329 states and 330 transitions. Word has length 324 [2018-07-24 10:58:11,134 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:11,134 INFO L471 AbstractCegarLoop]: Abstraction has 329 states and 330 transitions. [2018-07-24 10:58:11,134 INFO L472 AbstractCegarLoop]: Interpolant automaton has 99 states. [2018-07-24 10:58:11,134 INFO L276 IsEmpty]: Start isEmpty. Operand 329 states and 330 transitions. [2018-07-24 10:58:11,136 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 327 [2018-07-24 10:58:11,137 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:11,137 INFO L353 BasicCegarLoop]: trace histogram [33, 32, 32, 32, 32, 32, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:11,142 INFO L414 AbstractCegarLoop]: === Iteration 65 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:11,142 INFO L82 PathProgramCache]: Analyzing trace with hash -259052781, now seen corresponding path program 62 times [2018-07-24 10:58:11,142 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:11,143 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:11,143 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:58:11,143 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:11,143 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:11,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:12,003 INFO L134 CoverageAnalysis]: Checked inductivity of 4931 backedges. 1117 proven. 2044 refuted. 0 times theorem prover too weak. 1770 trivial. 0 not checked. [2018-07-24 10:58:12,003 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:12,004 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 124 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 124 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:12,011 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:58:12,011 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:12,117 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:58:12,117 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:12,121 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:12,246 INFO L134 CoverageAnalysis]: Checked inductivity of 4931 backedges. 1118 proven. 1953 refuted. 0 times theorem prover too weak. 1860 trivial. 0 not checked. [2018-07-24 10:58:12,246 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:13,103 INFO L134 CoverageAnalysis]: Checked inductivity of 4931 backedges. 1118 proven. 1953 refuted. 0 times theorem prover too weak. 1860 trivial. 0 not checked. [2018-07-24 10:58:13,123 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:13,123 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 125 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 125 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:13,138 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:58:13,138 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:13,357 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:58:13,357 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:13,367 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:13,445 INFO L134 CoverageAnalysis]: Checked inductivity of 4931 backedges. 1118 proven. 1953 refuted. 0 times theorem prover too weak. 1860 trivial. 0 not checked. [2018-07-24 10:58:13,445 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:14,439 INFO L134 CoverageAnalysis]: Checked inductivity of 4931 backedges. 1118 proven. 1953 refuted. 0 times theorem prover too weak. 1860 trivial. 0 not checked. [2018-07-24 10:58:14,441 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:14,441 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 37, 37, 37, 37] total 40 [2018-07-24 10:58:14,442 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:14,442 INFO L450 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-07-24 10:58:14,442 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-07-24 10:58:14,442 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=607, Invalid=953, Unknown=0, NotChecked=0, Total=1560 [2018-07-24 10:58:14,443 INFO L87 Difference]: Start difference. First operand 329 states and 330 transitions. Second operand 40 states. [2018-07-24 10:58:14,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:14,898 INFO L93 Difference]: Finished difference Result 339 states and 340 transitions. [2018-07-24 10:58:14,898 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-07-24 10:58:14,899 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 326 [2018-07-24 10:58:14,899 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:14,901 INFO L225 Difference]: With dead ends: 339 [2018-07-24 10:58:14,901 INFO L226 Difference]: Without dead ends: 337 [2018-07-24 10:58:14,901 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1375 GetRequests, 1205 SyntacticMatches, 130 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2340 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=620, Invalid=1102, Unknown=0, NotChecked=0, Total=1722 [2018-07-24 10:58:14,902 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 337 states. [2018-07-24 10:58:14,915 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 337 to 337. [2018-07-24 10:58:14,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 337 states. [2018-07-24 10:58:14,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 337 states to 337 states and 338 transitions. [2018-07-24 10:58:14,917 INFO L78 Accepts]: Start accepts. Automaton has 337 states and 338 transitions. Word has length 326 [2018-07-24 10:58:14,917 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:14,917 INFO L471 AbstractCegarLoop]: Abstraction has 337 states and 338 transitions. [2018-07-24 10:58:14,917 INFO L472 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-07-24 10:58:14,917 INFO L276 IsEmpty]: Start isEmpty. Operand 337 states and 338 transitions. [2018-07-24 10:58:14,919 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 335 [2018-07-24 10:58:14,919 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:14,919 INFO L353 BasicCegarLoop]: trace histogram [33, 33, 33, 33, 33, 32, 32, 32, 32, 32, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:14,920 INFO L414 AbstractCegarLoop]: === Iteration 66 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:14,920 INFO L82 PathProgramCache]: Analyzing trace with hash 672210231, now seen corresponding path program 63 times [2018-07-24 10:58:14,920 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:14,921 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:14,921 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:14,921 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:14,921 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:14,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:16,535 INFO L134 CoverageAnalysis]: Checked inductivity of 5184 backedges. 2144 proven. 1056 refuted. 0 times theorem prover too weak. 1984 trivial. 0 not checked. [2018-07-24 10:58:16,535 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:16,535 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 126 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 126 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:16,545 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:58:16,545 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:58:16,683 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 33 check-sat command(s) [2018-07-24 10:58:16,684 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:16,689 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:18,479 INFO L134 CoverageAnalysis]: Checked inductivity of 5184 backedges. 2144 proven. 1056 refuted. 0 times theorem prover too weak. 1984 trivial. 0 not checked. [2018-07-24 10:58:18,480 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:20,128 INFO L134 CoverageAnalysis]: Checked inductivity of 5184 backedges. 2144 proven. 1056 refuted. 0 times theorem prover too weak. 1984 trivial. 0 not checked. [2018-07-24 10:58:20,150 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:20,150 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 127 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 127 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:20,166 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:58:20,166 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:58:21,288 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 33 check-sat command(s) [2018-07-24 10:58:21,289 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:21,305 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:21,396 INFO L134 CoverageAnalysis]: Checked inductivity of 5184 backedges. 2144 proven. 1056 refuted. 0 times theorem prover too weak. 1984 trivial. 0 not checked. [2018-07-24 10:58:21,396 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:22,794 INFO L134 CoverageAnalysis]: Checked inductivity of 5184 backedges. 2144 proven. 1056 refuted. 0 times theorem prover too weak. 1984 trivial. 0 not checked. [2018-07-24 10:58:22,809 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:22,810 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [69, 69, 69, 69, 69] total 102 [2018-07-24 10:58:22,810 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:22,810 INFO L450 AbstractCegarLoop]: Interpolant automaton has 102 states [2018-07-24 10:58:22,811 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 102 interpolants. [2018-07-24 10:58:22,811 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2379, Invalid=7923, Unknown=0, NotChecked=0, Total=10302 [2018-07-24 10:58:22,812 INFO L87 Difference]: Start difference. First operand 337 states and 338 transitions. Second operand 102 states. [2018-07-24 10:58:25,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:25,471 INFO L93 Difference]: Finished difference Result 480 states and 514 transitions. [2018-07-24 10:58:25,472 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-07-24 10:58:25,472 INFO L78 Accepts]: Start accepts. Automaton has 102 states. Word has length 334 [2018-07-24 10:58:25,472 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:25,473 INFO L225 Difference]: With dead ends: 480 [2018-07-24 10:58:25,473 INFO L226 Difference]: Without dead ends: 339 [2018-07-24 10:58:25,475 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1437 GetRequests, 1171 SyntacticMatches, 132 SemanticMatches, 134 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11251 ImplicationChecksByTransitivity, 7.0s TimeCoverageRelationStatistics Valid=4198, Invalid=14162, Unknown=0, NotChecked=0, Total=18360 [2018-07-24 10:58:25,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 339 states. [2018-07-24 10:58:25,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 339 to 339. [2018-07-24 10:58:25,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 339 states. [2018-07-24 10:58:25,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 339 states to 339 states and 340 transitions. [2018-07-24 10:58:25,489 INFO L78 Accepts]: Start accepts. Automaton has 339 states and 340 transitions. Word has length 334 [2018-07-24 10:58:25,489 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:25,489 INFO L471 AbstractCegarLoop]: Abstraction has 339 states and 340 transitions. [2018-07-24 10:58:25,489 INFO L472 AbstractCegarLoop]: Interpolant automaton has 102 states. [2018-07-24 10:58:25,489 INFO L276 IsEmpty]: Start isEmpty. Operand 339 states and 340 transitions. [2018-07-24 10:58:25,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 337 [2018-07-24 10:58:25,490 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:25,491 INFO L353 BasicCegarLoop]: trace histogram [34, 33, 33, 33, 33, 33, 32, 32, 32, 32, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:25,491 INFO L414 AbstractCegarLoop]: === Iteration 67 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:25,491 INFO L82 PathProgramCache]: Analyzing trace with hash 1887049457, now seen corresponding path program 64 times [2018-07-24 10:58:25,491 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:25,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:25,492 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:25,492 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:25,492 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:25,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:26,293 INFO L134 CoverageAnalysis]: Checked inductivity of 5250 backedges. 1185 proven. 2174 refuted. 0 times theorem prover too weak. 1891 trivial. 0 not checked. [2018-07-24 10:58:26,293 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:26,293 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 128 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 128 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:26,301 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:58:26,301 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:58:26,405 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:58:26,405 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:26,409 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:26,543 INFO L134 CoverageAnalysis]: Checked inductivity of 5250 backedges. 1186 proven. 2080 refuted. 0 times theorem prover too weak. 1984 trivial. 0 not checked. [2018-07-24 10:58:26,543 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:27,525 INFO L134 CoverageAnalysis]: Checked inductivity of 5250 backedges. 1186 proven. 2080 refuted. 0 times theorem prover too weak. 1984 trivial. 0 not checked. [2018-07-24 10:58:27,546 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:27,546 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 129 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 129 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:27,562 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:58:27,562 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:58:27,833 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:58:27,833 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:27,843 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:27,918 INFO L134 CoverageAnalysis]: Checked inductivity of 5250 backedges. 1186 proven. 2080 refuted. 0 times theorem prover too weak. 1984 trivial. 0 not checked. [2018-07-24 10:58:27,918 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:29,194 INFO L134 CoverageAnalysis]: Checked inductivity of 5250 backedges. 1186 proven. 2080 refuted. 0 times theorem prover too weak. 1984 trivial. 0 not checked. [2018-07-24 10:58:29,196 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:29,196 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 38, 38, 38, 38] total 41 [2018-07-24 10:58:29,196 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:29,197 INFO L450 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-07-24 10:58:29,197 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-07-24 10:58:29,197 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=642, Invalid=998, Unknown=0, NotChecked=0, Total=1640 [2018-07-24 10:58:29,198 INFO L87 Difference]: Start difference. First operand 339 states and 340 transitions. Second operand 41 states. [2018-07-24 10:58:29,696 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:29,697 INFO L93 Difference]: Finished difference Result 349 states and 350 transitions. [2018-07-24 10:58:29,697 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-07-24 10:58:29,697 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 336 [2018-07-24 10:58:29,698 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:29,699 INFO L225 Difference]: With dead ends: 349 [2018-07-24 10:58:29,699 INFO L226 Difference]: Without dead ends: 347 [2018-07-24 10:58:29,700 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1417 GetRequests, 1242 SyntacticMatches, 134 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2479 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=655, Invalid=1151, Unknown=0, NotChecked=0, Total=1806 [2018-07-24 10:58:29,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 347 states. [2018-07-24 10:58:29,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 347 to 347. [2018-07-24 10:58:29,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 347 states. [2018-07-24 10:58:29,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 347 states to 347 states and 348 transitions. [2018-07-24 10:58:29,710 INFO L78 Accepts]: Start accepts. Automaton has 347 states and 348 transitions. Word has length 336 [2018-07-24 10:58:29,711 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:29,711 INFO L471 AbstractCegarLoop]: Abstraction has 347 states and 348 transitions. [2018-07-24 10:58:29,711 INFO L472 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-07-24 10:58:29,711 INFO L276 IsEmpty]: Start isEmpty. Operand 347 states and 348 transitions. [2018-07-24 10:58:29,713 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 345 [2018-07-24 10:58:29,713 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:29,713 INFO L353 BasicCegarLoop]: trace histogram [34, 34, 34, 34, 34, 33, 33, 33, 33, 33, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:29,713 INFO L414 AbstractCegarLoop]: === Iteration 68 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_up_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:29,713 INFO L82 PathProgramCache]: Analyzing trace with hash -2093397227, now seen corresponding path program 65 times [2018-07-24 10:58:29,713 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:29,714 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:29,714 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:29,714 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:29,714 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:29,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:31,411 INFO L134 CoverageAnalysis]: Checked inductivity of 5511 backedges. 2277 proven. 1122 refuted. 0 times theorem prover too weak. 2112 trivial. 0 not checked. [2018-07-24 10:58:31,411 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:31,411 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 130 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 130 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:31,418 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:58:31,419 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:31,566 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 34 check-sat command(s) [2018-07-24 10:58:31,566 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:31,571 INFO L273 TraceCheckSpWp]: Computing forward predicates... Received shutdown request... [2018-07-24 10:58:31,840 INFO L177 TraceCheckSpWp]: Timeout while computing interpolants [2018-07-24 10:58:32,041 WARN L512 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 130 z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:32,041 WARN L540 AbstractCegarLoop]: Verification canceled [2018-07-24 10:58:32,047 WARN L202 ceAbstractionStarter]: Timeout [2018-07-24 10:58:32,047 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.07 10:58:32 BoogieIcfgContainer [2018-07-24 10:58:32,047 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-07-24 10:58:32,048 INFO L168 Benchmark]: Toolchain (without parser) took 228313.53 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 729.8 MB). Free memory was 1.4 GB in the beginning and 1.6 GB in the end (delta: -168.8 MB). Peak memory consumption was 561.0 MB. Max. memory is 7.1 GB. [2018-07-24 10:58:32,049 INFO L168 Benchmark]: CDTParser took 0.21 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-24 10:58:32,049 INFO L168 Benchmark]: CACSL2BoogieTranslator took 289.73 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. [2018-07-24 10:58:32,049 INFO L168 Benchmark]: Boogie Procedure Inliner took 23.94 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-24 10:58:32,049 INFO L168 Benchmark]: Boogie Preprocessor took 26.66 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-24 10:58:32,050 INFO L168 Benchmark]: RCFGBuilder took 443.77 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 753.4 MB). Free memory was 1.4 GB in the beginning and 2.2 GB in the end (delta: -806.7 MB). Peak memory consumption was 27.0 MB. Max. memory is 7.1 GB. [2018-07-24 10:58:32,050 INFO L168 Benchmark]: TraceAbstraction took 227524.60 ms. Allocated memory was 2.3 GB in the beginning and 2.3 GB in the end (delta: -23.6 MB). Free memory was 2.2 GB in the beginning and 1.6 GB in the end (delta: 627.3 MB). Peak memory consumption was 603.7 MB. Max. memory is 7.1 GB. [2018-07-24 10:58:32,052 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 289.73 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 23.94 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Preprocessor took 26.66 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * RCFGBuilder took 443.77 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 753.4 MB). Free memory was 1.4 GB in the beginning and 2.2 GB in the end (delta: -806.7 MB). Peak memory consumption was 27.0 MB. Max. memory is 7.1 GB. * TraceAbstraction took 227524.60 ms. Allocated memory was 2.3 GB in the beginning and 2.3 GB in the end (delta: -23.6 MB). Free memory was 2.2 GB in the beginning and 1.6 GB in the end (delta: 627.3 MB). Peak memory consumption was 603.7 MB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 5]: Timeout (TraceAbstraction) Unable to prove that call of __VERIFIER_error() unreachable (line 5). Cancelled while BasicCegarLoop was analyzing trace of length 345 with TraceHistMax 34, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantifier-free) to 77 known predicates. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 22 locations, 1 error locations. TIMEOUT Result, 227.4s OverallTime, 68 OverallIterations, 34 TraceHistogramMax, 46.8s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 3065 SDtfs, 2461 SDslu, 31352 SDs, 0 SdLazy, 37244 SolverSat, 2759 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 24.9s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 49184 GetRequests, 41510 SyntacticMatches, 4544 SemanticMatches, 3130 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 158627 ImplicationChecksByTransitivity, 147.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=347occurred in iteration=67, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.6s AutomataMinimizationTime, 67 MinimizatonAttempts, 5 StatesRemovedByMinimization, 1 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 1.5s SsaConstructionTime, 21.1s SatisfiabilityAnalysisTime, 149.5s InterpolantComputationTime, 34603 NumberOfCodeBlocks, 34603 NumberOfCodeBlocksAsserted, 1293 NumberOfCheckSat, 57320 ConstructedInterpolants, 0 QuantifiedInterpolants, 35420808 SizeOfPredicates, 384 NumberOfNonLiveVariables, 48960 ConjunctsInSsa, 4992 ConjunctsInUnsatCore, 323 InterpolantComputations, 3 PerfectInterpolantSequences, 409762/588162 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/up_true-unreach-call_true-termination.i_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-Benchmark-0-2018-07-24_10-58-32-063.csv Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/up_true-unreach-call_true-termination.i_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-TraceAbstractionBenchmarks-0-2018-07-24_10-58-32-063.csv Completed graceful shutdown