java -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data --generate-csv --csv-dir csv -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml -s ../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf -i ../../../trunk/examples/svcomp/loop-new/count_by_nondet_true-unreach-call_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-3142e50-m [2018-09-10 10:17:52,358 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-09-10 10:17:52,360 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-09-10 10:17:52,372 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-09-10 10:17:52,372 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-09-10 10:17:52,373 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-09-10 10:17:52,374 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-09-10 10:17:52,376 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-09-10 10:17:52,378 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-09-10 10:17:52,379 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-09-10 10:17:52,380 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-09-10 10:17:52,380 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-09-10 10:17:52,381 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-09-10 10:17:52,382 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-09-10 10:17:52,383 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-09-10 10:17:52,384 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-09-10 10:17:52,385 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-09-10 10:17:52,386 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-09-10 10:17:52,388 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-09-10 10:17:52,390 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-09-10 10:17:52,394 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-09-10 10:17:52,396 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-09-10 10:17:52,401 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-09-10 10:17:52,401 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-09-10 10:17:52,402 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-09-10 10:17:52,404 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-09-10 10:17:52,406 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-09-10 10:17:52,407 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-09-10 10:17:52,408 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-09-10 10:17:52,411 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-09-10 10:17:52,413 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-09-10 10:17:52,414 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... 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[2018-09-10 10:17:52,419 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf [2018-09-10 10:17:52,444 INFO L110 SettingsManager]: Loading preferences was successful [2018-09-10 10:17:52,445 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-09-10 10:17:52,447 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-09-10 10:17:52,447 INFO L133 SettingsManager]: * User list type=DISABLED [2018-09-10 10:17:52,447 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-09-10 10:17:52,447 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-09-10 10:17:52,447 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-09-10 10:17:52,448 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-09-10 10:17:52,448 INFO L133 SettingsManager]: * Log string format=TERM [2018-09-10 10:17:52,448 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-09-10 10:17:52,448 INFO L133 SettingsManager]: * Interval Domain=false [2018-09-10 10:17:52,449 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-09-10 10:17:52,449 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-09-10 10:17:52,450 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-09-10 10:17:52,450 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-09-10 10:17:52,450 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-09-10 10:17:52,450 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-09-10 10:17:52,450 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-09-10 10:17:52,451 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-09-10 10:17:52,451 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-09-10 10:17:52,451 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-09-10 10:17:52,451 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-09-10 10:17:52,451 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-09-10 10:17:52,452 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-09-10 10:17:52,452 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-09-10 10:17:52,452 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-09-10 10:17:52,452 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-09-10 10:17:52,452 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-09-10 10:17:52,453 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-09-10 10:17:52,453 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-09-10 10:17:52,453 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-09-10 10:17:52,453 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-09-10 10:17:52,453 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-09-10 10:17:52,495 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-09-10 10:17:52,513 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-09-10 10:17:52,520 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-09-10 10:17:52,522 INFO L271 PluginConnector]: Initializing CDTParser... [2018-09-10 10:17:52,522 INFO L276 PluginConnector]: CDTParser initialized [2018-09-10 10:17:52,523 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-new/count_by_nondet_true-unreach-call_true-termination.i [2018-09-10 10:17:52,786 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6c3269e3b/7d69b013303b4303864f76aaacc3ba11/FLAGb06649472 [2018-09-10 10:17:53,043 INFO L276 CDTParser]: Found 1 translation units. [2018-09-10 10:17:53,044 INFO L158 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-new/count_by_nondet_true-unreach-call_true-termination.i [2018-09-10 10:17:53,054 INFO L324 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6c3269e3b/7d69b013303b4303864f76aaacc3ba11/FLAGb06649472 [2018-09-10 10:17:53,080 INFO L332 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6c3269e3b/7d69b013303b4303864f76aaacc3ba11 [2018-09-10 10:17:53,094 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-09-10 10:17:53,099 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-09-10 10:17:53,100 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-09-10 10:17:53,100 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-09-10 10:17:53,107 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-09-10 10:17:53,108 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.09 10:17:53" (1/1) ... [2018-09-10 10:17:53,112 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@9459f47 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:17:53, skipping insertion in model container [2018-09-10 10:17:53,113 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.09 10:17:53" (1/1) ... [2018-09-10 10:17:53,293 INFO L180 PRDispatcher]: Starting pre-run dispatcher in SV-COMP mode [2018-09-10 10:17:53,337 INFO L175 PostProcessor]: Settings: Checked method=main [2018-09-10 10:17:53,356 INFO L431 MainDispatcher]: Starting main dispatcher in SV-COMP mode [2018-09-10 10:17:53,364 INFO L175 PostProcessor]: Settings: Checked method=main [2018-09-10 10:17:53,379 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:17:53 WrapperNode [2018-09-10 10:17:53,379 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-09-10 10:17:53,380 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-09-10 10:17:53,380 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-09-10 10:17:53,381 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-09-10 10:17:53,391 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:17:53" (1/1) ... [2018-09-10 10:17:53,398 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:17:53" (1/1) ... [2018-09-10 10:17:53,405 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-09-10 10:17:53,406 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-09-10 10:17:53,406 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-09-10 10:17:53,406 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-09-10 10:17:53,417 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:17:53" (1/1) ... [2018-09-10 10:17:53,417 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:17:53" (1/1) ... [2018-09-10 10:17:53,418 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:17:53" (1/1) ... [2018-09-10 10:17:53,419 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:17:53" (1/1) ... [2018-09-10 10:17:53,420 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:17:53" (1/1) ... [2018-09-10 10:17:53,426 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:17:53" (1/1) ... [2018-09-10 10:17:53,427 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:17:53" (1/1) ... [2018-09-10 10:17:53,428 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-09-10 10:17:53,429 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-09-10 10:17:53,429 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-09-10 10:17:53,429 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-09-10 10:17:53,430 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:17:53" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-09-10 10:17:53,500 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-09-10 10:17:53,501 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-09-10 10:17:53,501 INFO L130 BoogieDeclarations]: Found specification of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assert [2018-09-10 10:17:53,501 INFO L138 BoogieDeclarations]: Found implementation of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assert [2018-09-10 10:17:53,501 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-09-10 10:17:53,501 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-09-10 10:17:53,501 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-09-10 10:17:53,502 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-09-10 10:17:53,805 INFO L353 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-09-10 10:17:53,805 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.09 10:17:53 BoogieIcfgContainer [2018-09-10 10:17:53,806 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-09-10 10:17:53,807 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-09-10 10:17:53,807 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-09-10 10:17:53,811 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-09-10 10:17:53,811 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 10.09 10:17:53" (1/3) ... [2018-09-10 10:17:53,812 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@797ff97d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 10.09 10:17:53, skipping insertion in model container [2018-09-10 10:17:53,812 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:17:53" (2/3) ... [2018-09-10 10:17:53,812 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@797ff97d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 10.09 10:17:53, skipping insertion in model container [2018-09-10 10:17:53,813 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.09 10:17:53" (3/3) ... [2018-09-10 10:17:53,814 INFO L112 eAbstractionObserver]: Analyzing ICFG count_by_nondet_true-unreach-call_true-termination.i [2018-09-10 10:17:53,825 INFO L137 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-09-10 10:17:53,841 INFO L149 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-09-10 10:17:53,916 INFO L130 ementStrategyFactory]: Using default assertion order modulation [2018-09-10 10:17:53,917 INFO L381 AbstractCegarLoop]: Interprodecural is true [2018-09-10 10:17:53,917 INFO L382 AbstractCegarLoop]: Hoare is true [2018-09-10 10:17:53,917 INFO L383 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-09-10 10:17:53,917 INFO L384 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-09-10 10:17:53,918 INFO L385 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-09-10 10:17:53,918 INFO L386 AbstractCegarLoop]: Difference is false [2018-09-10 10:17:53,918 INFO L387 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-09-10 10:17:53,918 INFO L392 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-09-10 10:17:53,948 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states. [2018-09-10 10:17:53,957 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2018-09-10 10:17:53,957 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:53,958 INFO L376 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:53,959 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:53,965 INFO L82 PathProgramCache]: Analyzing trace with hash -397369335, now seen corresponding path program 1 times [2018-09-10 10:17:53,968 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:54,019 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:54,020 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:17:54,020 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:54,020 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:54,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:54,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:54,079 INFO L313 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-09-10 10:17:54,079 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-09-10 10:17:54,079 INFO L265 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-09-10 10:17:54,084 INFO L459 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-09-10 10:17:54,097 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-09-10 10:17:54,097 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-09-10 10:17:54,100 INFO L87 Difference]: Start difference. First operand 20 states. Second operand 2 states. [2018-09-10 10:17:54,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:17:54,124 INFO L93 Difference]: Finished difference Result 32 states and 36 transitions. [2018-09-10 10:17:54,124 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-09-10 10:17:54,125 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 10 [2018-09-10 10:17:54,126 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:17:54,136 INFO L225 Difference]: With dead ends: 32 [2018-09-10 10:17:54,137 INFO L226 Difference]: Without dead ends: 13 [2018-09-10 10:17:54,140 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-09-10 10:17:54,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states. [2018-09-10 10:17:54,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 13. [2018-09-10 10:17:54,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13 states. [2018-09-10 10:17:54,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 13 transitions. [2018-09-10 10:17:54,179 INFO L78 Accepts]: Start accepts. Automaton has 13 states and 13 transitions. Word has length 10 [2018-09-10 10:17:54,179 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:17:54,179 INFO L480 AbstractCegarLoop]: Abstraction has 13 states and 13 transitions. [2018-09-10 10:17:54,180 INFO L481 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-09-10 10:17:54,180 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 13 transitions. [2018-09-10 10:17:54,180 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-09-10 10:17:54,181 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:54,181 INFO L376 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:54,181 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:54,182 INFO L82 PathProgramCache]: Analyzing trace with hash 208361744, now seen corresponding path program 1 times [2018-09-10 10:17:54,182 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:54,183 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:54,183 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:17:54,183 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:54,184 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:54,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:54,251 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:54,252 INFO L313 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-09-10 10:17:54,252 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-09-10 10:17:54,252 INFO L265 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-09-10 10:17:54,254 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-09-10 10:17:54,254 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-09-10 10:17:54,263 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-09-10 10:17:54,263 INFO L87 Difference]: Start difference. First operand 13 states and 13 transitions. Second operand 3 states. [2018-09-10 10:17:54,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:17:54,320 INFO L93 Difference]: Finished difference Result 21 states and 21 transitions. [2018-09-10 10:17:54,320 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-09-10 10:17:54,320 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-09-10 10:17:54,321 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:17:54,321 INFO L225 Difference]: With dead ends: 21 [2018-09-10 10:17:54,321 INFO L226 Difference]: Without dead ends: 16 [2018-09-10 10:17:54,322 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-09-10 10:17:54,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2018-09-10 10:17:54,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 15. [2018-09-10 10:17:54,326 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2018-09-10 10:17:54,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 15 transitions. [2018-09-10 10:17:54,327 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 15 transitions. Word has length 11 [2018-09-10 10:17:54,327 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:17:54,327 INFO L480 AbstractCegarLoop]: Abstraction has 15 states and 15 transitions. [2018-09-10 10:17:54,327 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-09-10 10:17:54,327 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 15 transitions. [2018-09-10 10:17:54,328 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-09-10 10:17:54,328 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:54,328 INFO L376 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:54,328 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:54,329 INFO L82 PathProgramCache]: Analyzing trace with hash -371094139, now seen corresponding path program 1 times [2018-09-10 10:17:54,329 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:54,331 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:54,331 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:17:54,331 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:54,331 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:54,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:54,401 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:54,401 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:54,401 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:17:54,411 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:17:54,411 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:17:54,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:54,446 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:54,475 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:54,475 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:54,539 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:54,560 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:54,560 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:17:54,578 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:17:54,579 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:17:54,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:54,598 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:54,605 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:54,605 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:54,675 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:54,681 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:17:54,681 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 4 [2018-09-10 10:17:54,681 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:17:54,682 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-09-10 10:17:54,682 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-09-10 10:17:54,682 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-09-10 10:17:54,683 INFO L87 Difference]: Start difference. First operand 15 states and 15 transitions. Second operand 4 states. [2018-09-10 10:17:54,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:17:54,732 INFO L93 Difference]: Finished difference Result 23 states and 23 transitions. [2018-09-10 10:17:54,733 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-09-10 10:17:54,734 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 14 [2018-09-10 10:17:54,734 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:17:54,734 INFO L225 Difference]: With dead ends: 23 [2018-09-10 10:17:54,735 INFO L226 Difference]: Without dead ends: 18 [2018-09-10 10:17:54,735 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 52 SyntacticMatches, 4 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-09-10 10:17:54,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states. [2018-09-10 10:17:54,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 18. [2018-09-10 10:17:54,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2018-09-10 10:17:54,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 18 transitions. [2018-09-10 10:17:54,742 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 18 transitions. Word has length 14 [2018-09-10 10:17:54,742 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:17:54,742 INFO L480 AbstractCegarLoop]: Abstraction has 18 states and 18 transitions. [2018-09-10 10:17:54,742 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-09-10 10:17:54,742 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 18 transitions. [2018-09-10 10:17:54,743 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-09-10 10:17:54,743 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:54,743 INFO L376 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:54,744 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:54,744 INFO L82 PathProgramCache]: Analyzing trace with hash -1467741968, now seen corresponding path program 2 times [2018-09-10 10:17:54,744 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:54,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:54,746 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:17:54,746 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:54,746 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:54,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:54,990 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:54,991 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:54,991 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:17:55,011 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:17:55,011 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:17:55,057 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:17:55,057 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:55,059 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:55,181 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:55,181 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:55,332 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:55,352 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:55,352 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:17:55,368 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:17:55,368 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:17:55,391 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:17:55,392 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:55,395 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:55,427 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:55,427 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:55,450 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:55,452 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:17:55,452 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 12 [2018-09-10 10:17:55,452 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:17:55,453 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-09-10 10:17:55,453 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-09-10 10:17:55,454 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=94, Unknown=0, NotChecked=0, Total=132 [2018-09-10 10:17:55,454 INFO L87 Difference]: Start difference. First operand 18 states and 18 transitions. Second operand 7 states. [2018-09-10 10:17:55,589 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:17:55,589 INFO L93 Difference]: Finished difference Result 27 states and 27 transitions. [2018-09-10 10:17:55,590 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-09-10 10:17:55,590 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 17 [2018-09-10 10:17:55,590 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:17:55,591 INFO L225 Difference]: With dead ends: 27 [2018-09-10 10:17:55,592 INFO L226 Difference]: Without dead ends: 22 [2018-09-10 10:17:55,592 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 74 GetRequests, 61 SyntacticMatches, 2 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=44, Invalid=112, Unknown=0, NotChecked=0, Total=156 [2018-09-10 10:17:55,593 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2018-09-10 10:17:55,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 21. [2018-09-10 10:17:55,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2018-09-10 10:17:55,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 21 transitions. [2018-09-10 10:17:55,598 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 21 transitions. Word has length 17 [2018-09-10 10:17:55,598 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:17:55,598 INFO L480 AbstractCegarLoop]: Abstraction has 21 states and 21 transitions. [2018-09-10 10:17:55,598 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-09-10 10:17:55,598 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 21 transitions. [2018-09-10 10:17:55,599 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-09-10 10:17:55,599 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:55,599 INFO L376 BasicCegarLoop]: trace histogram [4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:55,600 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:55,600 INFO L82 PathProgramCache]: Analyzing trace with hash 113004965, now seen corresponding path program 3 times [2018-09-10 10:17:55,600 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:55,601 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:55,601 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:17:55,601 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:55,602 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:55,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:55,723 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:55,723 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:55,724 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:17:55,735 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:17:55,735 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:17:55,749 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-09-10 10:17:55,749 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:55,752 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:55,773 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:55,773 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:56,203 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:56,228 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:56,228 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:17:56,253 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:17:56,253 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:17:56,287 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-09-10 10:17:56,287 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:56,291 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:56,318 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:56,319 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:56,340 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:56,342 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:17:56,342 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 14 [2018-09-10 10:17:56,342 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:17:56,343 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-09-10 10:17:56,344 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-09-10 10:17:56,344 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=127, Unknown=0, NotChecked=0, Total=182 [2018-09-10 10:17:56,344 INFO L87 Difference]: Start difference. First operand 21 states and 21 transitions. Second operand 8 states. [2018-09-10 10:17:56,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:17:56,388 INFO L93 Difference]: Finished difference Result 30 states and 30 transitions. [2018-09-10 10:17:56,389 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-09-10 10:17:56,389 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 20 [2018-09-10 10:17:56,389 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:17:56,390 INFO L225 Difference]: With dead ends: 30 [2018-09-10 10:17:56,390 INFO L226 Difference]: Without dead ends: 25 [2018-09-10 10:17:56,391 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 87 GetRequests, 72 SyntacticMatches, 2 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 36 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=61, Invalid=149, Unknown=0, NotChecked=0, Total=210 [2018-09-10 10:17:56,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2018-09-10 10:17:56,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 24. [2018-09-10 10:17:56,396 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-09-10 10:17:56,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 24 transitions. [2018-09-10 10:17:56,397 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 24 transitions. Word has length 20 [2018-09-10 10:17:56,397 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:17:56,398 INFO L480 AbstractCegarLoop]: Abstraction has 24 states and 24 transitions. [2018-09-10 10:17:56,398 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-09-10 10:17:56,398 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 24 transitions. [2018-09-10 10:17:56,399 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-09-10 10:17:56,399 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:56,399 INFO L376 BasicCegarLoop]: trace histogram [5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:56,399 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:56,400 INFO L82 PathProgramCache]: Analyzing trace with hash 2123452624, now seen corresponding path program 4 times [2018-09-10 10:17:56,400 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:56,401 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:56,401 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:17:56,401 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:56,401 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:56,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:56,533 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:56,533 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:56,534 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:17:56,542 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:17:56,542 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:17:56,562 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:17:56,562 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:56,565 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:56,666 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:56,666 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:56,815 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:56,837 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:56,837 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:17:56,854 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:17:56,854 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:17:56,886 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:17:56,887 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:56,891 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:56,960 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:56,960 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:57,001 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:57,003 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:17:57,003 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 16 [2018-09-10 10:17:57,003 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:17:57,004 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-09-10 10:17:57,004 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-09-10 10:17:57,005 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=76, Invalid=164, Unknown=0, NotChecked=0, Total=240 [2018-09-10 10:17:57,005 INFO L87 Difference]: Start difference. First operand 24 states and 24 transitions. Second operand 9 states. [2018-09-10 10:17:57,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:17:57,058 INFO L93 Difference]: Finished difference Result 33 states and 33 transitions. [2018-09-10 10:17:57,060 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-09-10 10:17:57,060 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 23 [2018-09-10 10:17:57,061 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:17:57,061 INFO L225 Difference]: With dead ends: 33 [2018-09-10 10:17:57,062 INFO L226 Difference]: Without dead ends: 28 [2018-09-10 10:17:57,062 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 83 SyntacticMatches, 2 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 46 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=82, Invalid=190, Unknown=0, NotChecked=0, Total=272 [2018-09-10 10:17:57,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2018-09-10 10:17:57,065 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 27. [2018-09-10 10:17:57,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27 states. [2018-09-10 10:17:57,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 27 transitions. [2018-09-10 10:17:57,067 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 27 transitions. Word has length 23 [2018-09-10 10:17:57,067 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:17:57,067 INFO L480 AbstractCegarLoop]: Abstraction has 27 states and 27 transitions. [2018-09-10 10:17:57,068 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-09-10 10:17:57,068 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 27 transitions. [2018-09-10 10:17:57,068 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-09-10 10:17:57,069 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:57,069 INFO L376 BasicCegarLoop]: trace histogram [6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:57,069 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:57,069 INFO L82 PathProgramCache]: Analyzing trace with hash 2050719173, now seen corresponding path program 5 times [2018-09-10 10:17:57,069 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:57,070 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:57,070 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:17:57,071 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:57,071 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:57,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:57,251 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:57,251 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:57,251 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:17:57,267 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:17:57,268 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:17:57,299 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-09-10 10:17:57,300 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:57,303 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:57,321 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:57,322 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:57,691 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:57,712 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:57,712 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:17:57,728 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:17:57,728 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:17:57,772 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-09-10 10:17:57,772 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:57,776 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:57,790 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:57,790 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:57,847 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:57,848 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:17:57,849 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 18 [2018-09-10 10:17:57,849 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:17:57,849 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-09-10 10:17:57,850 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-09-10 10:17:57,850 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=101, Invalid=205, Unknown=0, NotChecked=0, Total=306 [2018-09-10 10:17:57,850 INFO L87 Difference]: Start difference. First operand 27 states and 27 transitions. Second operand 10 states. [2018-09-10 10:17:57,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:17:57,922 INFO L93 Difference]: Finished difference Result 36 states and 36 transitions. [2018-09-10 10:17:57,922 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-09-10 10:17:57,922 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 26 [2018-09-10 10:17:57,923 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:17:57,924 INFO L225 Difference]: With dead ends: 36 [2018-09-10 10:17:57,924 INFO L226 Difference]: Without dead ends: 31 [2018-09-10 10:17:57,925 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 113 GetRequests, 94 SyntacticMatches, 2 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 56 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=107, Invalid=235, Unknown=0, NotChecked=0, Total=342 [2018-09-10 10:17:57,926 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2018-09-10 10:17:57,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 30. [2018-09-10 10:17:57,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-09-10 10:17:57,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 30 transitions. [2018-09-10 10:17:57,930 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 30 transitions. Word has length 26 [2018-09-10 10:17:57,930 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:17:57,930 INFO L480 AbstractCegarLoop]: Abstraction has 30 states and 30 transitions. [2018-09-10 10:17:57,931 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-09-10 10:17:57,931 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 30 transitions. [2018-09-10 10:17:57,932 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-09-10 10:17:57,932 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:57,932 INFO L376 BasicCegarLoop]: trace histogram [7, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:57,932 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:57,932 INFO L82 PathProgramCache]: Analyzing trace with hash -88002384, now seen corresponding path program 6 times [2018-09-10 10:17:57,932 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:57,933 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:57,933 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:17:57,933 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:57,933 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:57,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:58,115 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:58,116 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:58,116 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:17:58,124 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:17:58,124 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:17:58,144 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-09-10 10:17:58,145 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:58,148 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:58,185 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:58,185 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:58,377 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:58,397 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:58,397 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:17:58,413 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:17:58,413 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:17:58,468 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-09-10 10:17:58,468 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:58,472 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:58,494 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:58,494 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:58,503 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:58,505 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:17:58,505 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 20 [2018-09-10 10:17:58,505 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:17:58,506 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-09-10 10:17:58,506 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-09-10 10:17:58,507 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=130, Invalid=250, Unknown=0, NotChecked=0, Total=380 [2018-09-10 10:17:58,507 INFO L87 Difference]: Start difference. First operand 30 states and 30 transitions. Second operand 11 states. [2018-09-10 10:17:58,576 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:17:58,576 INFO L93 Difference]: Finished difference Result 39 states and 39 transitions. [2018-09-10 10:17:58,576 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-09-10 10:17:58,577 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 29 [2018-09-10 10:17:58,577 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:17:58,578 INFO L225 Difference]: With dead ends: 39 [2018-09-10 10:17:58,578 INFO L226 Difference]: Without dead ends: 34 [2018-09-10 10:17:58,578 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 126 GetRequests, 105 SyntacticMatches, 2 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 66 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=136, Invalid=284, Unknown=0, NotChecked=0, Total=420 [2018-09-10 10:17:58,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-09-10 10:17:58,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 33. [2018-09-10 10:17:58,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33 states. [2018-09-10 10:17:58,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 33 transitions. [2018-09-10 10:17:58,583 INFO L78 Accepts]: Start accepts. Automaton has 33 states and 33 transitions. Word has length 29 [2018-09-10 10:17:58,584 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:17:58,584 INFO L480 AbstractCegarLoop]: Abstraction has 33 states and 33 transitions. [2018-09-10 10:17:58,584 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-09-10 10:17:58,584 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 33 transitions. [2018-09-10 10:17:58,585 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-09-10 10:17:58,585 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:58,585 INFO L376 BasicCegarLoop]: trace histogram [8, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:58,585 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:58,586 INFO L82 PathProgramCache]: Analyzing trace with hash 1097929189, now seen corresponding path program 7 times [2018-09-10 10:17:58,586 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:58,587 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:58,587 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:17:58,587 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:58,587 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:58,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:58,788 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:58,788 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:58,788 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:17:58,799 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:17:58,799 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:17:58,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:58,818 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:58,893 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:58,893 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:59,079 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:59,099 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:59,099 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:17:59,116 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:17:59,116 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:17:59,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:59,151 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:59,184 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:59,185 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:59,244 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:59,247 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:17:59,247 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 22 [2018-09-10 10:17:59,247 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:17:59,248 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-09-10 10:17:59,248 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-09-10 10:17:59,248 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=163, Invalid=299, Unknown=0, NotChecked=0, Total=462 [2018-09-10 10:17:59,249 INFO L87 Difference]: Start difference. First operand 33 states and 33 transitions. Second operand 12 states. [2018-09-10 10:17:59,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:17:59,532 INFO L93 Difference]: Finished difference Result 42 states and 42 transitions. [2018-09-10 10:17:59,535 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-09-10 10:17:59,536 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 32 [2018-09-10 10:17:59,536 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:17:59,537 INFO L225 Difference]: With dead ends: 42 [2018-09-10 10:17:59,537 INFO L226 Difference]: Without dead ends: 37 [2018-09-10 10:17:59,538 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 139 GetRequests, 116 SyntacticMatches, 2 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 76 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=169, Invalid=337, Unknown=0, NotChecked=0, Total=506 [2018-09-10 10:17:59,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2018-09-10 10:17:59,543 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 36. [2018-09-10 10:17:59,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2018-09-10 10:17:59,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 36 transitions. [2018-09-10 10:17:59,544 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 36 transitions. Word has length 32 [2018-09-10 10:17:59,544 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:17:59,545 INFO L480 AbstractCegarLoop]: Abstraction has 36 states and 36 transitions. [2018-09-10 10:17:59,545 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-09-10 10:17:59,545 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 36 transitions. [2018-09-10 10:17:59,546 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-09-10 10:17:59,546 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:59,546 INFO L376 BasicCegarLoop]: trace histogram [9, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:59,546 INFO L423 AbstractCegarLoop]: === Iteration 10 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:59,547 INFO L82 PathProgramCache]: Analyzing trace with hash 784443536, now seen corresponding path program 8 times [2018-09-10 10:17:59,547 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:59,548 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:59,548 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:17:59,548 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:59,548 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:59,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:59,710 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:59,710 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:59,710 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:17:59,719 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:17:59,719 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:17:59,760 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:17:59,761 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:59,763 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:59,973 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:17:59,973 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:00,347 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:00,367 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:00,367 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:00,385 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:18:00,386 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:18:00,420 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:18:00,421 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:00,424 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:00,476 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:00,477 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:00,512 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:00,513 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:00,514 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 24 [2018-09-10 10:18:00,514 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:00,514 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-09-10 10:18:00,515 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-09-10 10:18:00,516 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=200, Invalid=352, Unknown=0, NotChecked=0, Total=552 [2018-09-10 10:18:00,516 INFO L87 Difference]: Start difference. First operand 36 states and 36 transitions. Second operand 13 states. [2018-09-10 10:18:00,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:00,562 INFO L93 Difference]: Finished difference Result 45 states and 45 transitions. [2018-09-10 10:18:00,562 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-09-10 10:18:00,562 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 35 [2018-09-10 10:18:00,562 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:00,563 INFO L225 Difference]: With dead ends: 45 [2018-09-10 10:18:00,564 INFO L226 Difference]: Without dead ends: 40 [2018-09-10 10:18:00,565 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 152 GetRequests, 127 SyntacticMatches, 2 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=206, Invalid=394, Unknown=0, NotChecked=0, Total=600 [2018-09-10 10:18:00,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-09-10 10:18:00,569 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 39. [2018-09-10 10:18:00,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2018-09-10 10:18:00,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 39 transitions. [2018-09-10 10:18:00,570 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 39 transitions. Word has length 35 [2018-09-10 10:18:00,570 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:00,570 INFO L480 AbstractCegarLoop]: Abstraction has 39 states and 39 transitions. [2018-09-10 10:18:00,571 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-09-10 10:18:00,571 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 39 transitions. [2018-09-10 10:18:00,571 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-09-10 10:18:00,572 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:00,572 INFO L376 BasicCegarLoop]: trace histogram [10, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:00,572 INFO L423 AbstractCegarLoop]: === Iteration 11 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:00,572 INFO L82 PathProgramCache]: Analyzing trace with hash -1007743483, now seen corresponding path program 9 times [2018-09-10 10:18:00,572 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:00,573 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:00,573 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:00,574 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:00,574 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:00,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:00,906 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:00,906 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:00,906 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:00,916 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:18:00,916 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:18:00,944 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-09-10 10:18:00,944 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:00,947 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:01,012 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:01,012 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:01,453 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:01,477 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:01,477 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:01,491 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:18:01,492 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:18:01,570 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-09-10 10:18:01,570 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:01,574 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:01,592 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:01,593 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:01,631 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:01,633 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:01,633 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 26 [2018-09-10 10:18:01,633 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:01,633 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-09-10 10:18:01,633 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-09-10 10:18:01,634 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=241, Invalid=409, Unknown=0, NotChecked=0, Total=650 [2018-09-10 10:18:01,634 INFO L87 Difference]: Start difference. First operand 39 states and 39 transitions. Second operand 14 states. [2018-09-10 10:18:01,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:01,679 INFO L93 Difference]: Finished difference Result 48 states and 48 transitions. [2018-09-10 10:18:01,680 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-09-10 10:18:01,680 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 38 [2018-09-10 10:18:01,681 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:01,682 INFO L225 Difference]: With dead ends: 48 [2018-09-10 10:18:01,682 INFO L226 Difference]: Without dead ends: 43 [2018-09-10 10:18:01,683 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 165 GetRequests, 138 SyntacticMatches, 2 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 96 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=247, Invalid=455, Unknown=0, NotChecked=0, Total=702 [2018-09-10 10:18:01,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2018-09-10 10:18:01,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 42. [2018-09-10 10:18:01,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2018-09-10 10:18:01,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 42 transitions. [2018-09-10 10:18:01,690 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 42 transitions. Word has length 38 [2018-09-10 10:18:01,690 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:01,690 INFO L480 AbstractCegarLoop]: Abstraction has 42 states and 42 transitions. [2018-09-10 10:18:01,690 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-09-10 10:18:01,690 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 42 transitions. [2018-09-10 10:18:01,691 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-09-10 10:18:01,691 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:01,691 INFO L376 BasicCegarLoop]: trace histogram [11, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:01,691 INFO L423 AbstractCegarLoop]: === Iteration 12 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:01,692 INFO L82 PathProgramCache]: Analyzing trace with hash -1312769936, now seen corresponding path program 10 times [2018-09-10 10:18:01,692 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:01,693 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:01,693 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:01,693 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:01,693 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:01,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:01,932 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:01,932 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:01,932 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:01,940 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:18:01,940 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:18:01,960 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:18:01,961 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:01,963 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:01,989 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:01,989 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:02,273 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:02,294 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:02,294 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:02,311 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:18:02,311 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:18:02,351 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:18:02,352 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:02,355 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:02,385 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:02,385 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:02,398 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:02,400 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:02,400 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 28 [2018-09-10 10:18:02,400 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:02,400 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-09-10 10:18:02,401 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-09-10 10:18:02,401 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=286, Invalid=470, Unknown=0, NotChecked=0, Total=756 [2018-09-10 10:18:02,401 INFO L87 Difference]: Start difference. First operand 42 states and 42 transitions. Second operand 15 states. [2018-09-10 10:18:02,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:02,459 INFO L93 Difference]: Finished difference Result 51 states and 51 transitions. [2018-09-10 10:18:02,459 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-09-10 10:18:02,459 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 41 [2018-09-10 10:18:02,459 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:02,460 INFO L225 Difference]: With dead ends: 51 [2018-09-10 10:18:02,460 INFO L226 Difference]: Without dead ends: 46 [2018-09-10 10:18:02,461 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 178 GetRequests, 149 SyntacticMatches, 2 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 106 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=292, Invalid=520, Unknown=0, NotChecked=0, Total=812 [2018-09-10 10:18:02,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states. [2018-09-10 10:18:02,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 45. [2018-09-10 10:18:02,466 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-09-10 10:18:02,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 45 transitions. [2018-09-10 10:18:02,467 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 45 transitions. Word has length 41 [2018-09-10 10:18:02,467 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:02,467 INFO L480 AbstractCegarLoop]: Abstraction has 45 states and 45 transitions. [2018-09-10 10:18:02,467 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-09-10 10:18:02,468 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 45 transitions. [2018-09-10 10:18:02,468 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-09-10 10:18:02,468 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:02,469 INFO L376 BasicCegarLoop]: trace histogram [12, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:02,469 INFO L423 AbstractCegarLoop]: === Iteration 13 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:02,469 INFO L82 PathProgramCache]: Analyzing trace with hash -205032923, now seen corresponding path program 11 times [2018-09-10 10:18:02,469 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:02,470 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:02,470 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:02,471 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:02,471 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:02,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:02,666 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:02,666 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:02,667 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:02,675 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:18:02,676 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:18:02,705 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2018-09-10 10:18:02,705 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:02,708 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:02,811 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:02,811 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:03,281 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:03,302 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:03,302 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:03,317 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:18:03,317 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:18:03,413 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2018-09-10 10:18:03,413 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:03,416 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:03,509 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:03,509 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:03,520 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:03,521 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:03,522 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 30 [2018-09-10 10:18:03,522 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:03,522 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-09-10 10:18:03,522 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-09-10 10:18:03,523 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=335, Invalid=535, Unknown=0, NotChecked=0, Total=870 [2018-09-10 10:18:03,523 INFO L87 Difference]: Start difference. First operand 45 states and 45 transitions. Second operand 16 states. [2018-09-10 10:18:03,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:03,584 INFO L93 Difference]: Finished difference Result 54 states and 54 transitions. [2018-09-10 10:18:03,584 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-09-10 10:18:03,584 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 44 [2018-09-10 10:18:03,585 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:03,586 INFO L225 Difference]: With dead ends: 54 [2018-09-10 10:18:03,586 INFO L226 Difference]: Without dead ends: 49 [2018-09-10 10:18:03,587 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 191 GetRequests, 160 SyntacticMatches, 2 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 116 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=341, Invalid=589, Unknown=0, NotChecked=0, Total=930 [2018-09-10 10:18:03,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-09-10 10:18:03,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 48. [2018-09-10 10:18:03,592 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-09-10 10:18:03,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 48 transitions. [2018-09-10 10:18:03,592 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 48 transitions. Word has length 44 [2018-09-10 10:18:03,593 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:03,593 INFO L480 AbstractCegarLoop]: Abstraction has 48 states and 48 transitions. [2018-09-10 10:18:03,593 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-09-10 10:18:03,593 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 48 transitions. [2018-09-10 10:18:03,594 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-09-10 10:18:03,594 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:03,594 INFO L376 BasicCegarLoop]: trace histogram [13, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:03,594 INFO L423 AbstractCegarLoop]: === Iteration 14 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:03,594 INFO L82 PathProgramCache]: Analyzing trace with hash -2140381104, now seen corresponding path program 12 times [2018-09-10 10:18:03,595 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:03,595 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:03,595 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:03,596 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:03,596 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:03,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:03,817 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:03,818 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:03,818 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:03,825 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:18:03,826 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:18:03,901 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2018-09-10 10:18:03,901 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:03,905 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:03,925 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:03,925 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:04,271 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:04,298 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:04,298 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:04,314 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:18:04,314 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:18:04,429 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2018-09-10 10:18:04,429 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:04,433 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:04,526 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:04,527 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:04,534 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:04,536 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:04,536 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 32 [2018-09-10 10:18:04,536 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:04,536 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-09-10 10:18:04,537 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-09-10 10:18:04,537 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=388, Invalid=604, Unknown=0, NotChecked=0, Total=992 [2018-09-10 10:18:04,537 INFO L87 Difference]: Start difference. First operand 48 states and 48 transitions. Second operand 17 states. [2018-09-10 10:18:04,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:04,657 INFO L93 Difference]: Finished difference Result 57 states and 57 transitions. [2018-09-10 10:18:04,663 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-09-10 10:18:04,663 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 47 [2018-09-10 10:18:04,663 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:04,664 INFO L225 Difference]: With dead ends: 57 [2018-09-10 10:18:04,664 INFO L226 Difference]: Without dead ends: 52 [2018-09-10 10:18:04,667 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 204 GetRequests, 171 SyntacticMatches, 2 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 126 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=394, Invalid=662, Unknown=0, NotChecked=0, Total=1056 [2018-09-10 10:18:04,667 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2018-09-10 10:18:04,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 51. [2018-09-10 10:18:04,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-09-10 10:18:04,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 51 transitions. [2018-09-10 10:18:04,674 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 51 transitions. Word has length 47 [2018-09-10 10:18:04,674 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:04,674 INFO L480 AbstractCegarLoop]: Abstraction has 51 states and 51 transitions. [2018-09-10 10:18:04,674 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-09-10 10:18:04,674 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 51 transitions. [2018-09-10 10:18:04,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-09-10 10:18:04,675 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:04,675 INFO L376 BasicCegarLoop]: trace histogram [14, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:04,675 INFO L423 AbstractCegarLoop]: === Iteration 15 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:04,676 INFO L82 PathProgramCache]: Analyzing trace with hash 1837907525, now seen corresponding path program 13 times [2018-09-10 10:18:04,676 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:04,677 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:04,677 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:04,677 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:04,677 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:04,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:04,945 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:04,945 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:04,945 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:04,954 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:18:04,954 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:18:04,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:04,980 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:05,011 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:05,012 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:05,371 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:05,391 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:05,391 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:05,406 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:18:05,406 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:18:05,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:05,461 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:05,479 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:05,479 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:05,496 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:05,498 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:05,498 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 34 [2018-09-10 10:18:05,498 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:05,498 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-09-10 10:18:05,499 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-09-10 10:18:05,499 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=445, Invalid=677, Unknown=0, NotChecked=0, Total=1122 [2018-09-10 10:18:05,499 INFO L87 Difference]: Start difference. First operand 51 states and 51 transitions. Second operand 18 states. [2018-09-10 10:18:05,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:05,543 INFO L93 Difference]: Finished difference Result 60 states and 60 transitions. [2018-09-10 10:18:05,543 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-09-10 10:18:05,543 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 50 [2018-09-10 10:18:05,543 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:05,544 INFO L225 Difference]: With dead ends: 60 [2018-09-10 10:18:05,544 INFO L226 Difference]: Without dead ends: 55 [2018-09-10 10:18:05,545 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 217 GetRequests, 182 SyntacticMatches, 2 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 136 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=451, Invalid=739, Unknown=0, NotChecked=0, Total=1190 [2018-09-10 10:18:05,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states. [2018-09-10 10:18:05,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 54. [2018-09-10 10:18:05,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-09-10 10:18:05,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 54 transitions. [2018-09-10 10:18:05,550 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 54 transitions. Word has length 50 [2018-09-10 10:18:05,550 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:05,551 INFO L480 AbstractCegarLoop]: Abstraction has 54 states and 54 transitions. [2018-09-10 10:18:05,551 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-09-10 10:18:05,551 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 54 transitions. [2018-09-10 10:18:05,553 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-09-10 10:18:05,553 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:05,553 INFO L376 BasicCegarLoop]: trace histogram [15, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:05,553 INFO L423 AbstractCegarLoop]: === Iteration 16 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:05,553 INFO L82 PathProgramCache]: Analyzing trace with hash -588079056, now seen corresponding path program 14 times [2018-09-10 10:18:05,553 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:05,554 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:05,554 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:18:05,554 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:05,555 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:05,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:05,787 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:05,787 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:05,787 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:05,797 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:18:05,797 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:18:05,824 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:18:05,825 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:05,827 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:05,858 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:05,858 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:06,629 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:06,649 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:06,650 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:06,664 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:18:06,665 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:18:06,720 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:18:06,720 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:06,724 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:06,759 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:06,759 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:06,782 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:06,783 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:06,783 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 36 [2018-09-10 10:18:06,783 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:06,783 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-09-10 10:18:06,783 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-09-10 10:18:06,784 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=506, Invalid=754, Unknown=0, NotChecked=0, Total=1260 [2018-09-10 10:18:06,784 INFO L87 Difference]: Start difference. First operand 54 states and 54 transitions. Second operand 19 states. [2018-09-10 10:18:06,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:06,841 INFO L93 Difference]: Finished difference Result 63 states and 63 transitions. [2018-09-10 10:18:06,848 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-09-10 10:18:06,849 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 53 [2018-09-10 10:18:06,849 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:06,849 INFO L225 Difference]: With dead ends: 63 [2018-09-10 10:18:06,849 INFO L226 Difference]: Without dead ends: 58 [2018-09-10 10:18:06,850 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 230 GetRequests, 193 SyntacticMatches, 2 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 146 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=512, Invalid=820, Unknown=0, NotChecked=0, Total=1332 [2018-09-10 10:18:06,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2018-09-10 10:18:06,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 57. [2018-09-10 10:18:06,855 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 57 states. [2018-09-10 10:18:06,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 57 transitions. [2018-09-10 10:18:06,857 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 57 transitions. Word has length 53 [2018-09-10 10:18:06,858 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:06,858 INFO L480 AbstractCegarLoop]: Abstraction has 57 states and 57 transitions. [2018-09-10 10:18:06,858 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-09-10 10:18:06,858 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 57 transitions. [2018-09-10 10:18:06,859 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-09-10 10:18:06,859 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:06,859 INFO L376 BasicCegarLoop]: trace histogram [16, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:06,859 INFO L423 AbstractCegarLoop]: === Iteration 17 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:06,860 INFO L82 PathProgramCache]: Analyzing trace with hash -1739623835, now seen corresponding path program 15 times [2018-09-10 10:18:06,860 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:06,863 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:06,864 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:06,864 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:06,864 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:06,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:07,111 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:07,111 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:07,111 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:07,118 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:18:07,118 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:18:07,156 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-09-10 10:18:07,156 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:07,158 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:07,180 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:07,180 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:08,056 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:08,076 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:08,076 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:08,090 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:18:08,091 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:18:08,243 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-09-10 10:18:08,244 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:08,247 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:08,400 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:08,400 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:08,439 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:08,441 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:08,441 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 38 [2018-09-10 10:18:08,441 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:08,442 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-09-10 10:18:08,442 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-09-10 10:18:08,442 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=571, Invalid=835, Unknown=0, NotChecked=0, Total=1406 [2018-09-10 10:18:08,443 INFO L87 Difference]: Start difference. First operand 57 states and 57 transitions. Second operand 20 states. [2018-09-10 10:18:08,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:08,555 INFO L93 Difference]: Finished difference Result 66 states and 66 transitions. [2018-09-10 10:18:08,555 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-09-10 10:18:08,555 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 56 [2018-09-10 10:18:08,555 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:08,555 INFO L225 Difference]: With dead ends: 66 [2018-09-10 10:18:08,556 INFO L226 Difference]: Without dead ends: 61 [2018-09-10 10:18:08,557 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 243 GetRequests, 204 SyntacticMatches, 2 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 156 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=577, Invalid=905, Unknown=0, NotChecked=0, Total=1482 [2018-09-10 10:18:08,557 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2018-09-10 10:18:08,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 60. [2018-09-10 10:18:08,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-09-10 10:18:08,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 60 transitions. [2018-09-10 10:18:08,562 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 60 transitions. Word has length 56 [2018-09-10 10:18:08,562 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:08,562 INFO L480 AbstractCegarLoop]: Abstraction has 60 states and 60 transitions. [2018-09-10 10:18:08,562 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-09-10 10:18:08,562 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 60 transitions. [2018-09-10 10:18:08,563 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-09-10 10:18:08,563 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:08,563 INFO L376 BasicCegarLoop]: trace histogram [17, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:08,564 INFO L423 AbstractCegarLoop]: === Iteration 18 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:08,564 INFO L82 PathProgramCache]: Analyzing trace with hash 788625424, now seen corresponding path program 16 times [2018-09-10 10:18:08,564 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:08,565 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:08,565 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:08,565 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:08,565 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:08,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:09,569 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:09,570 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:09,570 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:09,577 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:18:09,577 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:18:09,603 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:18:09,604 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:09,605 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:09,646 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:09,646 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:10,887 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:10,908 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:10,908 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:10,923 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:18:10,923 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:18:11,009 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:18:11,010 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:11,014 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:11,046 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:11,047 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:11,104 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:11,106 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:11,106 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 40 [2018-09-10 10:18:11,106 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:11,107 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-09-10 10:18:11,107 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-09-10 10:18:11,108 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=640, Invalid=920, Unknown=0, NotChecked=0, Total=1560 [2018-09-10 10:18:11,108 INFO L87 Difference]: Start difference. First operand 60 states and 60 transitions. Second operand 21 states. [2018-09-10 10:18:11,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:11,523 INFO L93 Difference]: Finished difference Result 69 states and 69 transitions. [2018-09-10 10:18:11,523 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-09-10 10:18:11,524 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 59 [2018-09-10 10:18:11,524 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:11,525 INFO L225 Difference]: With dead ends: 69 [2018-09-10 10:18:11,525 INFO L226 Difference]: Without dead ends: 64 [2018-09-10 10:18:11,527 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 256 GetRequests, 215 SyntacticMatches, 2 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 166 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=646, Invalid=994, Unknown=0, NotChecked=0, Total=1640 [2018-09-10 10:18:11,527 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2018-09-10 10:18:11,530 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 63. [2018-09-10 10:18:11,531 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-09-10 10:18:11,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 63 transitions. [2018-09-10 10:18:11,531 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 63 transitions. Word has length 59 [2018-09-10 10:18:11,532 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:11,532 INFO L480 AbstractCegarLoop]: Abstraction has 63 states and 63 transitions. [2018-09-10 10:18:11,532 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-09-10 10:18:11,532 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 63 transitions. [2018-09-10 10:18:11,533 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-09-10 10:18:11,533 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:11,533 INFO L376 BasicCegarLoop]: trace histogram [18, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:11,533 INFO L423 AbstractCegarLoop]: === Iteration 19 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:11,533 INFO L82 PathProgramCache]: Analyzing trace with hash -979169659, now seen corresponding path program 17 times [2018-09-10 10:18:11,534 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:11,534 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:11,534 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:11,534 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:11,534 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:11,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:11,966 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:11,967 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:11,967 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:11,975 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:18:11,975 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:18:12,016 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2018-09-10 10:18:12,017 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:12,019 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:12,042 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:12,042 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:12,473 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:12,493 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:12,493 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:12,509 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:18:12,509 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:18:12,686 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2018-09-10 10:18:12,686 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:12,690 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:12,739 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:12,739 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:12,749 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:12,751 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:12,751 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22, 22, 22] total 42 [2018-09-10 10:18:12,751 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:12,751 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-09-10 10:18:12,752 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-09-10 10:18:12,752 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=713, Invalid=1009, Unknown=0, NotChecked=0, Total=1722 [2018-09-10 10:18:12,753 INFO L87 Difference]: Start difference. First operand 63 states and 63 transitions. Second operand 22 states. [2018-09-10 10:18:12,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:12,807 INFO L93 Difference]: Finished difference Result 72 states and 72 transitions. [2018-09-10 10:18:12,807 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-09-10 10:18:12,807 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 62 [2018-09-10 10:18:12,808 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:12,808 INFO L225 Difference]: With dead ends: 72 [2018-09-10 10:18:12,808 INFO L226 Difference]: Without dead ends: 67 [2018-09-10 10:18:12,809 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 269 GetRequests, 226 SyntacticMatches, 2 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 176 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=719, Invalid=1087, Unknown=0, NotChecked=0, Total=1806 [2018-09-10 10:18:12,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2018-09-10 10:18:12,812 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 66. [2018-09-10 10:18:12,812 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-09-10 10:18:12,813 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 66 transitions. [2018-09-10 10:18:12,813 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 66 transitions. Word has length 62 [2018-09-10 10:18:12,813 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:12,813 INFO L480 AbstractCegarLoop]: Abstraction has 66 states and 66 transitions. [2018-09-10 10:18:12,813 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-09-10 10:18:12,813 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 66 transitions. [2018-09-10 10:18:12,814 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-09-10 10:18:12,814 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:12,814 INFO L376 BasicCegarLoop]: trace histogram [19, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:12,814 INFO L423 AbstractCegarLoop]: === Iteration 20 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:12,815 INFO L82 PathProgramCache]: Analyzing trace with hash -473503760, now seen corresponding path program 18 times [2018-09-10 10:18:12,815 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:12,815 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:12,816 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:12,816 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:12,816 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:12,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:13,746 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:13,746 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:13,746 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:13,755 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:18:13,755 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:18:13,821 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2018-09-10 10:18:13,821 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:13,823 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:13,883 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:13,883 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:14,868 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:14,888 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:14,888 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:14,903 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:18:14,903 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:18:15,113 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2018-09-10 10:18:15,113 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:15,118 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:15,149 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:15,150 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:15,174 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:15,175 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:15,175 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 44 [2018-09-10 10:18:15,175 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:15,176 INFO L459 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-09-10 10:18:15,176 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-09-10 10:18:15,177 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=790, Invalid=1102, Unknown=0, NotChecked=0, Total=1892 [2018-09-10 10:18:15,177 INFO L87 Difference]: Start difference. First operand 66 states and 66 transitions. Second operand 23 states. [2018-09-10 10:18:15,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:15,251 INFO L93 Difference]: Finished difference Result 75 states and 75 transitions. [2018-09-10 10:18:15,252 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-09-10 10:18:15,252 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 65 [2018-09-10 10:18:15,252 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:15,253 INFO L225 Difference]: With dead ends: 75 [2018-09-10 10:18:15,253 INFO L226 Difference]: Without dead ends: 70 [2018-09-10 10:18:15,254 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 282 GetRequests, 237 SyntacticMatches, 2 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 186 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=796, Invalid=1184, Unknown=0, NotChecked=0, Total=1980 [2018-09-10 10:18:15,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states. [2018-09-10 10:18:15,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 69. [2018-09-10 10:18:15,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2018-09-10 10:18:15,260 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 69 transitions. [2018-09-10 10:18:15,260 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 69 transitions. Word has length 65 [2018-09-10 10:18:15,260 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:15,260 INFO L480 AbstractCegarLoop]: Abstraction has 69 states and 69 transitions. [2018-09-10 10:18:15,260 INFO L481 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-09-10 10:18:15,260 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 69 transitions. [2018-09-10 10:18:15,261 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-09-10 10:18:15,261 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:15,262 INFO L376 BasicCegarLoop]: trace histogram [20, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:15,262 INFO L423 AbstractCegarLoop]: === Iteration 21 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:15,262 INFO L82 PathProgramCache]: Analyzing trace with hash 1368986277, now seen corresponding path program 19 times [2018-09-10 10:18:15,262 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:15,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:15,263 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:15,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:15,263 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:15,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:15,558 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:15,559 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:15,559 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:15,567 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:18:15,567 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:18:15,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:15,603 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:15,631 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:15,631 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:16,158 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:16,177 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:16,178 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:16,193 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:18:16,193 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:18:16,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:16,266 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:16,305 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:16,305 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:16,355 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:16,356 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:16,357 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 46 [2018-09-10 10:18:16,357 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:16,357 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-09-10 10:18:16,357 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-09-10 10:18:16,358 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=871, Invalid=1199, Unknown=0, NotChecked=0, Total=2070 [2018-09-10 10:18:16,359 INFO L87 Difference]: Start difference. First operand 69 states and 69 transitions. Second operand 24 states. [2018-09-10 10:18:16,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:16,545 INFO L93 Difference]: Finished difference Result 78 states and 78 transitions. [2018-09-10 10:18:16,546 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-09-10 10:18:16,546 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 68 [2018-09-10 10:18:16,546 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:16,547 INFO L225 Difference]: With dead ends: 78 [2018-09-10 10:18:16,547 INFO L226 Difference]: Without dead ends: 73 [2018-09-10 10:18:16,548 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 295 GetRequests, 248 SyntacticMatches, 2 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 196 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=877, Invalid=1285, Unknown=0, NotChecked=0, Total=2162 [2018-09-10 10:18:16,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2018-09-10 10:18:16,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 72. [2018-09-10 10:18:16,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-09-10 10:18:16,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 72 transitions. [2018-09-10 10:18:16,553 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 72 transitions. Word has length 68 [2018-09-10 10:18:16,553 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:16,553 INFO L480 AbstractCegarLoop]: Abstraction has 72 states and 72 transitions. [2018-09-10 10:18:16,553 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-09-10 10:18:16,553 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 72 transitions. [2018-09-10 10:18:16,554 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-09-10 10:18:16,554 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:16,554 INFO L376 BasicCegarLoop]: trace histogram [21, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:16,554 INFO L423 AbstractCegarLoop]: === Iteration 22 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:16,555 INFO L82 PathProgramCache]: Analyzing trace with hash 1307635664, now seen corresponding path program 20 times [2018-09-10 10:18:16,555 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:16,555 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:16,555 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:18:16,556 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:16,556 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:16,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:16,995 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:16,996 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:16,996 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:17,005 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:18:17,005 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:18:17,042 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:18:17,042 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:17,044 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:17,069 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:17,069 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:17,645 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:17,666 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:17,666 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:17,681 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:18:17,681 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:18:17,760 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:18:17,760 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:17,765 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:17,819 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:17,819 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:17,849 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:17,850 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:17,850 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 48 [2018-09-10 10:18:17,850 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:17,850 INFO L459 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-09-10 10:18:17,851 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-09-10 10:18:17,851 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=956, Invalid=1300, Unknown=0, NotChecked=0, Total=2256 [2018-09-10 10:18:17,852 INFO L87 Difference]: Start difference. First operand 72 states and 72 transitions. Second operand 25 states. [2018-09-10 10:18:17,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:17,920 INFO L93 Difference]: Finished difference Result 81 states and 81 transitions. [2018-09-10 10:18:17,922 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-09-10 10:18:17,923 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 71 [2018-09-10 10:18:17,923 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:17,924 INFO L225 Difference]: With dead ends: 81 [2018-09-10 10:18:17,924 INFO L226 Difference]: Without dead ends: 76 [2018-09-10 10:18:17,926 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 308 GetRequests, 259 SyntacticMatches, 2 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 206 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=962, Invalid=1390, Unknown=0, NotChecked=0, Total=2352 [2018-09-10 10:18:17,926 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states. [2018-09-10 10:18:17,928 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 75. [2018-09-10 10:18:17,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 75 states. [2018-09-10 10:18:17,929 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 75 transitions. [2018-09-10 10:18:17,929 INFO L78 Accepts]: Start accepts. Automaton has 75 states and 75 transitions. Word has length 71 [2018-09-10 10:18:17,930 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:17,930 INFO L480 AbstractCegarLoop]: Abstraction has 75 states and 75 transitions. [2018-09-10 10:18:17,930 INFO L481 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-09-10 10:18:17,930 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 75 transitions. [2018-09-10 10:18:17,930 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-09-10 10:18:17,931 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:17,931 INFO L376 BasicCegarLoop]: trace histogram [22, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:17,931 INFO L423 AbstractCegarLoop]: === Iteration 23 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:17,931 INFO L82 PathProgramCache]: Analyzing trace with hash -1027375419, now seen corresponding path program 21 times [2018-09-10 10:18:17,931 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:17,932 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:17,932 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:17,932 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:17,932 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:17,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:18,271 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:18,272 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:18,272 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:18,281 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:18:18,281 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:18:18,325 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2018-09-10 10:18:18,325 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:18,327 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:18,362 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:18,362 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:19,018 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:19,039 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:19,039 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:19,054 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:18:19,054 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:18:19,319 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2018-09-10 10:18:19,320 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:19,324 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:19,368 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:19,368 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:19,436 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:19,437 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:19,438 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 50 [2018-09-10 10:18:19,438 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:19,438 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-09-10 10:18:19,438 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-09-10 10:18:19,439 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1045, Invalid=1405, Unknown=0, NotChecked=0, Total=2450 [2018-09-10 10:18:19,439 INFO L87 Difference]: Start difference. First operand 75 states and 75 transitions. Second operand 26 states. [2018-09-10 10:18:19,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:19,585 INFO L93 Difference]: Finished difference Result 84 states and 84 transitions. [2018-09-10 10:18:19,586 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-09-10 10:18:19,586 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 74 [2018-09-10 10:18:19,587 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:19,587 INFO L225 Difference]: With dead ends: 84 [2018-09-10 10:18:19,587 INFO L226 Difference]: Without dead ends: 79 [2018-09-10 10:18:19,589 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 321 GetRequests, 270 SyntacticMatches, 2 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 216 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1051, Invalid=1499, Unknown=0, NotChecked=0, Total=2550 [2018-09-10 10:18:19,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states. [2018-09-10 10:18:19,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 78. [2018-09-10 10:18:19,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-09-10 10:18:19,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 78 transitions. [2018-09-10 10:18:19,592 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 78 transitions. Word has length 74 [2018-09-10 10:18:19,592 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:19,592 INFO L480 AbstractCegarLoop]: Abstraction has 78 states and 78 transitions. [2018-09-10 10:18:19,592 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-09-10 10:18:19,592 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 78 transitions. [2018-09-10 10:18:19,593 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-09-10 10:18:19,593 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:19,593 INFO L376 BasicCegarLoop]: trace histogram [23, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:19,593 INFO L423 AbstractCegarLoop]: === Iteration 24 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:19,593 INFO L82 PathProgramCache]: Analyzing trace with hash -2052223056, now seen corresponding path program 22 times [2018-09-10 10:18:19,594 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:19,594 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:19,594 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:19,594 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:19,595 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:19,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:20,344 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:20,344 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:20,344 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:20,356 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:18:20,357 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:18:20,396 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:18:20,396 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:20,398 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:20,532 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:20,532 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:21,456 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:21,478 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:21,478 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:21,494 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:18:21,494 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:18:21,581 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:18:21,582 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:21,586 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:21,627 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:21,627 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:21,656 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:21,657 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:21,657 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 52 [2018-09-10 10:18:21,657 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:21,657 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-09-10 10:18:21,658 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-09-10 10:18:21,658 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1138, Invalid=1514, Unknown=0, NotChecked=0, Total=2652 [2018-09-10 10:18:21,659 INFO L87 Difference]: Start difference. First operand 78 states and 78 transitions. Second operand 27 states. [2018-09-10 10:18:21,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:21,732 INFO L93 Difference]: Finished difference Result 87 states and 87 transitions. [2018-09-10 10:18:21,732 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-09-10 10:18:21,733 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 77 [2018-09-10 10:18:21,733 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:21,734 INFO L225 Difference]: With dead ends: 87 [2018-09-10 10:18:21,734 INFO L226 Difference]: Without dead ends: 82 [2018-09-10 10:18:21,735 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 334 GetRequests, 281 SyntacticMatches, 2 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 226 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1144, Invalid=1612, Unknown=0, NotChecked=0, Total=2756 [2018-09-10 10:18:21,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2018-09-10 10:18:21,738 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 81. [2018-09-10 10:18:21,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-09-10 10:18:21,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 81 transitions. [2018-09-10 10:18:21,739 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 81 transitions. Word has length 77 [2018-09-10 10:18:21,739 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:21,739 INFO L480 AbstractCegarLoop]: Abstraction has 81 states and 81 transitions. [2018-09-10 10:18:21,739 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-09-10 10:18:21,739 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 81 transitions. [2018-09-10 10:18:21,740 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-09-10 10:18:21,740 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:21,740 INFO L376 BasicCegarLoop]: trace histogram [24, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:21,740 INFO L423 AbstractCegarLoop]: === Iteration 25 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:21,741 INFO L82 PathProgramCache]: Analyzing trace with hash -365669659, now seen corresponding path program 23 times [2018-09-10 10:18:21,741 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:21,741 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:21,741 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:21,742 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:21,742 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:21,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:22,355 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:22,355 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:22,355 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:22,363 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:18:22,363 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:18:22,413 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2018-09-10 10:18:22,413 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:22,416 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:22,455 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:22,455 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:23,153 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:23,175 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:23,175 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:23,189 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:18:23,190 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:18:23,483 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2018-09-10 10:18:23,484 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:23,489 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:23,535 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:23,535 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:23,549 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:23,550 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:23,550 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28, 28, 28] total 54 [2018-09-10 10:18:23,550 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:23,551 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-09-10 10:18:23,551 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-09-10 10:18:23,552 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1235, Invalid=1627, Unknown=0, NotChecked=0, Total=2862 [2018-09-10 10:18:23,552 INFO L87 Difference]: Start difference. First operand 81 states and 81 transitions. Second operand 28 states. [2018-09-10 10:18:23,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:23,626 INFO L93 Difference]: Finished difference Result 90 states and 90 transitions. [2018-09-10 10:18:23,626 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-09-10 10:18:23,626 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 80 [2018-09-10 10:18:23,626 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:23,627 INFO L225 Difference]: With dead ends: 90 [2018-09-10 10:18:23,627 INFO L226 Difference]: Without dead ends: 85 [2018-09-10 10:18:23,628 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 347 GetRequests, 292 SyntacticMatches, 2 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 236 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1241, Invalid=1729, Unknown=0, NotChecked=0, Total=2970 [2018-09-10 10:18:23,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-09-10 10:18:23,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 84. [2018-09-10 10:18:23,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-09-10 10:18:23,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 84 transitions. [2018-09-10 10:18:23,632 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 84 transitions. Word has length 80 [2018-09-10 10:18:23,632 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:23,632 INFO L480 AbstractCegarLoop]: Abstraction has 84 states and 84 transitions. [2018-09-10 10:18:23,632 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-09-10 10:18:23,632 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 84 transitions. [2018-09-10 10:18:23,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-09-10 10:18:23,633 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:23,633 INFO L376 BasicCegarLoop]: trace histogram [25, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:23,634 INFO L423 AbstractCegarLoop]: === Iteration 26 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:23,634 INFO L82 PathProgramCache]: Analyzing trace with hash 1219151760, now seen corresponding path program 24 times [2018-09-10 10:18:23,634 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:23,634 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:23,635 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:23,635 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:23,635 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:23,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:24,066 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:24,066 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:24,067 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:24,075 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:18:24,075 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:18:24,125 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) [2018-09-10 10:18:24,126 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:24,129 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:24,221 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:24,221 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:25,502 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:25,523 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:25,523 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:25,538 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:18:25,538 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:18:25,863 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) [2018-09-10 10:18:25,863 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:25,868 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:25,920 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:25,920 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:25,932 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:25,933 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:25,933 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 56 [2018-09-10 10:18:25,933 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:25,934 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-09-10 10:18:25,934 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-09-10 10:18:25,935 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1336, Invalid=1744, Unknown=0, NotChecked=0, Total=3080 [2018-09-10 10:18:25,936 INFO L87 Difference]: Start difference. First operand 84 states and 84 transitions. Second operand 29 states. [2018-09-10 10:18:26,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:26,003 INFO L93 Difference]: Finished difference Result 93 states and 93 transitions. [2018-09-10 10:18:26,003 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-09-10 10:18:26,004 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 83 [2018-09-10 10:18:26,004 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:26,005 INFO L225 Difference]: With dead ends: 93 [2018-09-10 10:18:26,005 INFO L226 Difference]: Without dead ends: 88 [2018-09-10 10:18:26,007 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 360 GetRequests, 303 SyntacticMatches, 2 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 246 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1342, Invalid=1850, Unknown=0, NotChecked=0, Total=3192 [2018-09-10 10:18:26,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states. [2018-09-10 10:18:26,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 87. [2018-09-10 10:18:26,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2018-09-10 10:18:26,010 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 87 transitions. [2018-09-10 10:18:26,010 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 87 transitions. Word has length 83 [2018-09-10 10:18:26,010 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:26,011 INFO L480 AbstractCegarLoop]: Abstraction has 87 states and 87 transitions. [2018-09-10 10:18:26,011 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-09-10 10:18:26,011 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 87 transitions. [2018-09-10 10:18:26,011 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-09-10 10:18:26,011 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:26,011 INFO L376 BasicCegarLoop]: trace histogram [26, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:26,011 INFO L423 AbstractCegarLoop]: === Iteration 27 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:26,012 INFO L82 PathProgramCache]: Analyzing trace with hash 58560261, now seen corresponding path program 25 times [2018-09-10 10:18:26,012 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:26,012 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:26,012 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:26,012 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:26,013 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:26,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:26,429 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:26,429 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:26,429 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:26,437 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:18:26,437 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:18:26,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:26,486 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:26,785 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:26,785 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:27,636 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:27,658 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:27,658 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:27,674 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:18:27,674 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:18:27,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:27,773 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:27,817 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:27,817 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:27,889 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:27,891 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:27,891 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 30, 30] total 58 [2018-09-10 10:18:27,891 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:27,892 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-09-10 10:18:27,892 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-09-10 10:18:27,893 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1441, Invalid=1865, Unknown=0, NotChecked=0, Total=3306 [2018-09-10 10:18:27,893 INFO L87 Difference]: Start difference. First operand 87 states and 87 transitions. Second operand 30 states. [2018-09-10 10:18:28,057 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:28,057 INFO L93 Difference]: Finished difference Result 96 states and 96 transitions. [2018-09-10 10:18:28,058 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-09-10 10:18:28,058 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 86 [2018-09-10 10:18:28,058 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:28,059 INFO L225 Difference]: With dead ends: 96 [2018-09-10 10:18:28,059 INFO L226 Difference]: Without dead ends: 91 [2018-09-10 10:18:28,060 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 373 GetRequests, 314 SyntacticMatches, 2 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 256 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1447, Invalid=1975, Unknown=0, NotChecked=0, Total=3422 [2018-09-10 10:18:28,060 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states. [2018-09-10 10:18:28,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 90. [2018-09-10 10:18:28,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. [2018-09-10 10:18:28,063 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 90 transitions. [2018-09-10 10:18:28,063 INFO L78 Accepts]: Start accepts. Automaton has 90 states and 90 transitions. Word has length 86 [2018-09-10 10:18:28,064 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:28,064 INFO L480 AbstractCegarLoop]: Abstraction has 90 states and 90 transitions. [2018-09-10 10:18:28,064 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-09-10 10:18:28,064 INFO L276 IsEmpty]: Start isEmpty. Operand 90 states and 90 transitions. [2018-09-10 10:18:28,064 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-09-10 10:18:28,065 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:28,065 INFO L376 BasicCegarLoop]: trace histogram [27, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:28,065 INFO L423 AbstractCegarLoop]: === Iteration 28 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:28,065 INFO L82 PathProgramCache]: Analyzing trace with hash -636053648, now seen corresponding path program 26 times [2018-09-10 10:18:28,065 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:28,066 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:28,066 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:18:28,066 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:28,066 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:28,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:28,627 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:28,628 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:28,628 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:28,637 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:18:28,638 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:18:28,681 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:18:28,681 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:28,683 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:28,729 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:28,729 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:29,643 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:29,663 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:29,664 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:29,678 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:18:29,678 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:18:29,778 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:18:29,778 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:29,784 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:29,831 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:29,832 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:29,844 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:29,846 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:29,846 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31, 31, 31, 31] total 60 [2018-09-10 10:18:29,846 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:29,846 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-09-10 10:18:29,847 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-09-10 10:18:29,847 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1550, Invalid=1990, Unknown=0, NotChecked=0, Total=3540 [2018-09-10 10:18:29,847 INFO L87 Difference]: Start difference. First operand 90 states and 90 transitions. Second operand 31 states. [2018-09-10 10:18:29,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:29,932 INFO L93 Difference]: Finished difference Result 99 states and 99 transitions. [2018-09-10 10:18:29,940 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-09-10 10:18:29,941 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 89 [2018-09-10 10:18:29,941 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:29,942 INFO L225 Difference]: With dead ends: 99 [2018-09-10 10:18:29,942 INFO L226 Difference]: Without dead ends: 94 [2018-09-10 10:18:29,943 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 386 GetRequests, 325 SyntacticMatches, 2 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 266 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1556, Invalid=2104, Unknown=0, NotChecked=0, Total=3660 [2018-09-10 10:18:29,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-09-10 10:18:29,945 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 93. [2018-09-10 10:18:29,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93 states. [2018-09-10 10:18:29,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 93 transitions. [2018-09-10 10:18:29,946 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 93 transitions. Word has length 89 [2018-09-10 10:18:29,946 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:29,946 INFO L480 AbstractCegarLoop]: Abstraction has 93 states and 93 transitions. [2018-09-10 10:18:29,947 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-09-10 10:18:29,947 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 93 transitions. [2018-09-10 10:18:29,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-09-10 10:18:29,947 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:29,947 INFO L376 BasicCegarLoop]: trace histogram [28, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:29,948 INFO L423 AbstractCegarLoop]: === Iteration 29 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:29,948 INFO L82 PathProgramCache]: Analyzing trace with hash -726584539, now seen corresponding path program 27 times [2018-09-10 10:18:29,948 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:29,949 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:29,949 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:29,949 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:29,949 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:29,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:30,706 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:30,707 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:30,707 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:30,715 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:18:30,716 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:18:30,773 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2018-09-10 10:18:30,773 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:30,776 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:31,189 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:31,189 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:32,546 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:32,567 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:32,567 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:32,582 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:18:32,582 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:18:32,975 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2018-09-10 10:18:32,975 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:32,981 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:33,098 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:33,098 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:33,130 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:33,131 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:33,131 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32, 32, 32, 32] total 62 [2018-09-10 10:18:33,131 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:33,131 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-09-10 10:18:33,132 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-09-10 10:18:33,132 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1663, Invalid=2119, Unknown=0, NotChecked=0, Total=3782 [2018-09-10 10:18:33,132 INFO L87 Difference]: Start difference. First operand 93 states and 93 transitions. Second operand 32 states. [2018-09-10 10:18:33,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:33,196 INFO L93 Difference]: Finished difference Result 102 states and 102 transitions. [2018-09-10 10:18:33,196 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-09-10 10:18:33,196 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 92 [2018-09-10 10:18:33,197 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:33,197 INFO L225 Difference]: With dead ends: 102 [2018-09-10 10:18:33,198 INFO L226 Difference]: Without dead ends: 97 [2018-09-10 10:18:33,199 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 399 GetRequests, 336 SyntacticMatches, 2 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 276 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=1669, Invalid=2237, Unknown=0, NotChecked=0, Total=3906 [2018-09-10 10:18:33,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states. [2018-09-10 10:18:33,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 96. [2018-09-10 10:18:33,202 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 96 states. [2018-09-10 10:18:33,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96 states to 96 states and 96 transitions. [2018-09-10 10:18:33,203 INFO L78 Accepts]: Start accepts. Automaton has 96 states and 96 transitions. Word has length 92 [2018-09-10 10:18:33,203 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:33,203 INFO L480 AbstractCegarLoop]: Abstraction has 96 states and 96 transitions. [2018-09-10 10:18:33,203 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-09-10 10:18:33,204 INFO L276 IsEmpty]: Start isEmpty. Operand 96 states and 96 transitions. [2018-09-10 10:18:33,204 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-09-10 10:18:33,204 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:33,204 INFO L376 BasicCegarLoop]: trace histogram [29, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:33,205 INFO L423 AbstractCegarLoop]: === Iteration 30 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:33,205 INFO L82 PathProgramCache]: Analyzing trace with hash -492896432, now seen corresponding path program 28 times [2018-09-10 10:18:33,205 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:33,205 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:33,206 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:33,206 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:33,206 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:33,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:33,697 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:33,697 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:33,698 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:33,705 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:18:33,705 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:18:33,757 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:18:33,757 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:33,759 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:34,057 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:34,057 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:35,383 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:35,414 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:35,414 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:35,442 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:18:35,442 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:18:35,540 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:18:35,541 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:35,545 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:35,593 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:35,593 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:35,659 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:35,661 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:35,661 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33, 33, 33, 33] total 64 [2018-09-10 10:18:35,661 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:35,661 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-09-10 10:18:35,662 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-09-10 10:18:35,662 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1780, Invalid=2252, Unknown=0, NotChecked=0, Total=4032 [2018-09-10 10:18:35,663 INFO L87 Difference]: Start difference. First operand 96 states and 96 transitions. Second operand 33 states. [2018-09-10 10:18:35,809 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:35,809 INFO L93 Difference]: Finished difference Result 105 states and 105 transitions. [2018-09-10 10:18:35,816 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-09-10 10:18:35,817 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 95 [2018-09-10 10:18:35,817 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:35,818 INFO L225 Difference]: With dead ends: 105 [2018-09-10 10:18:35,818 INFO L226 Difference]: Without dead ends: 100 [2018-09-10 10:18:35,819 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 412 GetRequests, 347 SyntacticMatches, 2 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 286 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1786, Invalid=2374, Unknown=0, NotChecked=0, Total=4160 [2018-09-10 10:18:35,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states. [2018-09-10 10:18:35,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 99. [2018-09-10 10:18:35,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2018-09-10 10:18:35,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 99 transitions. [2018-09-10 10:18:35,822 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 99 transitions. Word has length 95 [2018-09-10 10:18:35,822 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:35,823 INFO L480 AbstractCegarLoop]: Abstraction has 99 states and 99 transitions. [2018-09-10 10:18:35,823 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-09-10 10:18:35,823 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 99 transitions. [2018-09-10 10:18:35,823 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-09-10 10:18:35,824 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:35,824 INFO L376 BasicCegarLoop]: trace histogram [30, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:35,824 INFO L423 AbstractCegarLoop]: === Iteration 31 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:35,824 INFO L82 PathProgramCache]: Analyzing trace with hash -832487611, now seen corresponding path program 29 times [2018-09-10 10:18:35,824 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:35,825 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:35,825 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:35,825 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:35,825 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:35,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:36,555 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:36,555 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:36,556 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:36,576 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:18:36,576 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:18:36,635 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 30 check-sat command(s) [2018-09-10 10:18:36,636 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:36,639 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:36,776 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:36,777 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:37,905 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:37,926 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:37,927 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:37,942 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:18:37,943 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:18:38,360 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 30 check-sat command(s) [2018-09-10 10:18:38,360 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:38,367 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:38,419 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:38,419 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:38,499 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:38,501 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:38,501 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34, 34, 34, 34] total 66 [2018-09-10 10:18:38,502 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:38,502 INFO L459 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-09-10 10:18:38,502 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-09-10 10:18:38,503 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1901, Invalid=2389, Unknown=0, NotChecked=0, Total=4290 [2018-09-10 10:18:38,503 INFO L87 Difference]: Start difference. First operand 99 states and 99 transitions. Second operand 34 states. [2018-09-10 10:18:38,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:38,646 INFO L93 Difference]: Finished difference Result 108 states and 108 transitions. [2018-09-10 10:18:38,647 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-09-10 10:18:38,647 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 98 [2018-09-10 10:18:38,647 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:38,648 INFO L225 Difference]: With dead ends: 108 [2018-09-10 10:18:38,648 INFO L226 Difference]: Without dead ends: 103 [2018-09-10 10:18:38,649 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 425 GetRequests, 358 SyntacticMatches, 2 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 296 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1907, Invalid=2515, Unknown=0, NotChecked=0, Total=4422 [2018-09-10 10:18:38,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states. [2018-09-10 10:18:38,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 102. [2018-09-10 10:18:38,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-09-10 10:18:38,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 102 transitions. [2018-09-10 10:18:38,653 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 102 transitions. Word has length 98 [2018-09-10 10:18:38,653 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:38,653 INFO L480 AbstractCegarLoop]: Abstraction has 102 states and 102 transitions. [2018-09-10 10:18:38,653 INFO L481 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-09-10 10:18:38,653 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 102 transitions. [2018-09-10 10:18:38,654 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2018-09-10 10:18:38,654 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:38,654 INFO L376 BasicCegarLoop]: trace histogram [31, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:38,654 INFO L423 AbstractCegarLoop]: === Iteration 32 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:38,655 INFO L82 PathProgramCache]: Analyzing trace with hash 1349648176, now seen corresponding path program 30 times [2018-09-10 10:18:38,655 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:38,655 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:38,655 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:38,656 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:38,656 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:38,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:39,256 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:39,257 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:39,257 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:39,264 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:18:39,264 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:18:39,326 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 31 check-sat command(s) [2018-09-10 10:18:39,327 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:39,329 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:39,376 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:39,376 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:40,833 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:40,854 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:40,854 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:40,869 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:18:40,869 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:18:41,427 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 31 check-sat command(s) [2018-09-10 10:18:41,427 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:41,432 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:41,462 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:41,462 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:41,481 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:41,482 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:41,482 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35, 35, 35, 35] total 68 [2018-09-10 10:18:41,482 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:41,483 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-09-10 10:18:41,483 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-09-10 10:18:41,483 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=2026, Invalid=2530, Unknown=0, NotChecked=0, Total=4556 [2018-09-10 10:18:41,484 INFO L87 Difference]: Start difference. First operand 102 states and 102 transitions. Second operand 35 states. [2018-09-10 10:18:41,658 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:41,658 INFO L93 Difference]: Finished difference Result 111 states and 111 transitions. [2018-09-10 10:18:41,658 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-09-10 10:18:41,659 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 101 [2018-09-10 10:18:41,659 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:41,660 INFO L225 Difference]: With dead ends: 111 [2018-09-10 10:18:41,660 INFO L226 Difference]: Without dead ends: 106 [2018-09-10 10:18:41,661 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 438 GetRequests, 369 SyntacticMatches, 2 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 306 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=2032, Invalid=2660, Unknown=0, NotChecked=0, Total=4692 [2018-09-10 10:18:41,661 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2018-09-10 10:18:41,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 105. [2018-09-10 10:18:41,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-09-10 10:18:41,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 105 transitions. [2018-09-10 10:18:41,665 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 105 transitions. Word has length 101 [2018-09-10 10:18:41,665 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:41,666 INFO L480 AbstractCegarLoop]: Abstraction has 105 states and 105 transitions. [2018-09-10 10:18:41,666 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-09-10 10:18:41,666 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 105 transitions. [2018-09-10 10:18:41,666 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-09-10 10:18:41,666 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:41,667 INFO L376 BasicCegarLoop]: trace histogram [32, 31, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:41,667 INFO L423 AbstractCegarLoop]: === Iteration 33 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:41,667 INFO L82 PathProgramCache]: Analyzing trace with hash 731886437, now seen corresponding path program 31 times [2018-09-10 10:18:41,667 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:41,668 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:41,668 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:41,668 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:41,668 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:41,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:42,241 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:42,241 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:42,241 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:42,251 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:18:42,251 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:18:42,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:42,303 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:42,330 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:42,330 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:43,592 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:43,612 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:43,612 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:43,627 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:18:43,627 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:18:43,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:43,740 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:43,855 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:43,855 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:43,924 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:43,926 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:43,926 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36, 36, 36, 36] total 70 [2018-09-10 10:18:43,926 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:43,927 INFO L459 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-09-10 10:18:43,927 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-09-10 10:18:43,928 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=2155, Invalid=2675, Unknown=0, NotChecked=0, Total=4830 [2018-09-10 10:18:43,928 INFO L87 Difference]: Start difference. First operand 105 states and 105 transitions. Second operand 36 states. [2018-09-10 10:18:44,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:44,139 INFO L93 Difference]: Finished difference Result 114 states and 114 transitions. [2018-09-10 10:18:44,140 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-09-10 10:18:44,140 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 104 [2018-09-10 10:18:44,140 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:44,141 INFO L225 Difference]: With dead ends: 114 [2018-09-10 10:18:44,141 INFO L226 Difference]: Without dead ends: 109 [2018-09-10 10:18:44,142 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 451 GetRequests, 380 SyntacticMatches, 2 SemanticMatches, 69 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 316 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=2161, Invalid=2809, Unknown=0, NotChecked=0, Total=4970 [2018-09-10 10:18:44,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109 states. [2018-09-10 10:18:44,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109 to 108. [2018-09-10 10:18:44,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108 states. [2018-09-10 10:18:44,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 108 transitions. [2018-09-10 10:18:44,147 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 108 transitions. Word has length 104 [2018-09-10 10:18:44,148 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:44,148 INFO L480 AbstractCegarLoop]: Abstraction has 108 states and 108 transitions. [2018-09-10 10:18:44,148 INFO L481 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-09-10 10:18:44,148 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 108 transitions. [2018-09-10 10:18:44,148 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-09-10 10:18:44,148 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:44,149 INFO L376 BasicCegarLoop]: trace histogram [33, 32, 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:44,149 INFO L423 AbstractCegarLoop]: === Iteration 34 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:44,149 INFO L82 PathProgramCache]: Analyzing trace with hash 926783248, now seen corresponding path program 32 times [2018-09-10 10:18:44,149 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:44,150 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:44,150 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:18:44,150 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:44,150 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:44,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:44,861 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:44,861 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:44,861 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:44,869 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:18:44,869 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:18:44,935 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:18:44,935 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:44,938 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:45,450 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:45,451 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:46,990 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:47,011 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:47,012 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:47,026 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:18:47,027 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:18:47,150 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:18:47,150 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:47,155 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:47,447 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:47,448 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:47,502 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:47,503 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:47,503 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37, 37, 37, 37] total 72 [2018-09-10 10:18:47,503 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:47,504 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-09-10 10:18:47,504 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-09-10 10:18:47,505 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=2288, Invalid=2824, Unknown=0, NotChecked=0, Total=5112 [2018-09-10 10:18:47,505 INFO L87 Difference]: Start difference. First operand 108 states and 108 transitions. Second operand 37 states. [2018-09-10 10:18:47,634 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:47,635 INFO L93 Difference]: Finished difference Result 117 states and 117 transitions. [2018-09-10 10:18:47,635 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-09-10 10:18:47,635 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 107 [2018-09-10 10:18:47,636 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:47,637 INFO L225 Difference]: With dead ends: 117 [2018-09-10 10:18:47,637 INFO L226 Difference]: Without dead ends: 112 [2018-09-10 10:18:47,638 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 464 GetRequests, 391 SyntacticMatches, 2 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 326 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=2294, Invalid=2962, Unknown=0, NotChecked=0, Total=5256 [2018-09-10 10:18:47,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-09-10 10:18:47,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 111. [2018-09-10 10:18:47,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-09-10 10:18:47,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 111 transitions. [2018-09-10 10:18:47,642 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 111 transitions. Word has length 107 [2018-09-10 10:18:47,642 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:47,642 INFO L480 AbstractCegarLoop]: Abstraction has 111 states and 111 transitions. [2018-09-10 10:18:47,643 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-09-10 10:18:47,643 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 111 transitions. [2018-09-10 10:18:47,643 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-09-10 10:18:47,643 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:47,643 INFO L376 BasicCegarLoop]: trace histogram [34, 33, 33, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:47,644 INFO L423 AbstractCegarLoop]: === Iteration 35 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:47,644 INFO L82 PathProgramCache]: Analyzing trace with hash 301895557, now seen corresponding path program 33 times [2018-09-10 10:18:47,644 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:47,644 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:47,645 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:47,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:47,645 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:47,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:48,923 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:48,924 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:48,924 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:48,930 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:18:48,930 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:18:49,390 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 34 check-sat command(s) [2018-09-10 10:18:49,391 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:49,394 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:49,519 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:49,519 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:51,185 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:51,207 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:51,207 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:51,221 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:18:51,222 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:18:51,762 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 34 check-sat command(s) [2018-09-10 10:18:51,762 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:51,768 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:51,821 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:51,822 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:51,838 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:51,839 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:51,840 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38, 38, 38, 38] total 74 [2018-09-10 10:18:51,840 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:51,840 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-09-10 10:18:51,840 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-09-10 10:18:51,841 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=2425, Invalid=2977, Unknown=0, NotChecked=0, Total=5402 [2018-09-10 10:18:51,841 INFO L87 Difference]: Start difference. First operand 111 states and 111 transitions. Second operand 38 states. [2018-09-10 10:18:51,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:51,925 INFO L93 Difference]: Finished difference Result 120 states and 120 transitions. [2018-09-10 10:18:51,925 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-09-10 10:18:51,925 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 110 [2018-09-10 10:18:51,925 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:51,926 INFO L225 Difference]: With dead ends: 120 [2018-09-10 10:18:51,926 INFO L226 Difference]: Without dead ends: 115 [2018-09-10 10:18:51,927 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 477 GetRequests, 402 SyntacticMatches, 2 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 336 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=2431, Invalid=3119, Unknown=0, NotChecked=0, Total=5550 [2018-09-10 10:18:51,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-09-10 10:18:51,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 114. [2018-09-10 10:18:51,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-09-10 10:18:51,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 114 transitions. [2018-09-10 10:18:51,930 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 114 transitions. Word has length 110 [2018-09-10 10:18:51,930 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:51,930 INFO L480 AbstractCegarLoop]: Abstraction has 114 states and 114 transitions. [2018-09-10 10:18:51,930 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-09-10 10:18:51,930 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 114 transitions. [2018-09-10 10:18:51,931 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-09-10 10:18:51,931 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:51,931 INFO L376 BasicCegarLoop]: trace histogram [35, 34, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:51,931 INFO L423 AbstractCegarLoop]: === Iteration 36 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:51,932 INFO L82 PathProgramCache]: Analyzing trace with hash -1339046160, now seen corresponding path program 34 times [2018-09-10 10:18:51,932 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:51,932 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:51,932 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:51,932 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:51,933 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:51,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:53,107 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:53,107 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:53,107 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:53,114 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:18:53,114 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:18:53,169 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:18:53,169 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:53,172 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:53,375 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:53,376 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:54,869 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:54,892 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:54,893 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 69 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:54,910 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:18:54,910 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:18:55,032 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:18:55,032 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:55,038 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:55,089 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:55,090 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:55,110 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:55,112 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:55,112 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39, 39, 39, 39] total 76 [2018-09-10 10:18:55,112 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:55,112 INFO L459 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-09-10 10:18:55,113 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-09-10 10:18:55,113 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=2566, Invalid=3134, Unknown=0, NotChecked=0, Total=5700 [2018-09-10 10:18:55,113 INFO L87 Difference]: Start difference. First operand 114 states and 114 transitions. Second operand 39 states. [2018-09-10 10:18:55,216 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:55,217 INFO L93 Difference]: Finished difference Result 123 states and 123 transitions. [2018-09-10 10:18:55,217 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-09-10 10:18:55,217 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 113 [2018-09-10 10:18:55,218 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:55,219 INFO L225 Difference]: With dead ends: 123 [2018-09-10 10:18:55,219 INFO L226 Difference]: Without dead ends: 118 [2018-09-10 10:18:55,219 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 490 GetRequests, 413 SyntacticMatches, 2 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 346 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=2572, Invalid=3280, Unknown=0, NotChecked=0, Total=5852 [2018-09-10 10:18:55,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states. [2018-09-10 10:18:55,222 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 117. [2018-09-10 10:18:55,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-09-10 10:18:55,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 117 transitions. [2018-09-10 10:18:55,223 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 117 transitions. Word has length 113 [2018-09-10 10:18:55,223 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:55,223 INFO L480 AbstractCegarLoop]: Abstraction has 117 states and 117 transitions. [2018-09-10 10:18:55,223 INFO L481 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-09-10 10:18:55,223 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 117 transitions. [2018-09-10 10:18:55,224 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-09-10 10:18:55,224 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:55,224 INFO L376 BasicCegarLoop]: trace histogram [36, 35, 35, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:55,224 INFO L423 AbstractCegarLoop]: === Iteration 37 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:55,224 INFO L82 PathProgramCache]: Analyzing trace with hash -1315974235, now seen corresponding path program 35 times [2018-09-10 10:18:55,225 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:55,225 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:55,225 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:55,225 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:55,225 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:55,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:56,467 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:56,467 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:56,467 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:56,474 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:18:56,474 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:18:56,552 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 36 check-sat command(s) [2018-09-10 10:18:56,552 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:56,555 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:56,609 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:56,609 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:58,121 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:58,143 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:58,143 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:58,158 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:18:58,158 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:18:58,719 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 36 check-sat command(s) [2018-09-10 10:18:58,719 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:58,725 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:58,797 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:58,797 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:58,819 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:58,820 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:58,821 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40, 40, 40, 40] total 78 [2018-09-10 10:18:58,821 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:58,821 INFO L459 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-09-10 10:18:58,821 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-09-10 10:18:58,822 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=2711, Invalid=3295, Unknown=0, NotChecked=0, Total=6006 [2018-09-10 10:18:58,822 INFO L87 Difference]: Start difference. First operand 117 states and 117 transitions. Second operand 40 states. [2018-09-10 10:18:58,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:58,912 INFO L93 Difference]: Finished difference Result 126 states and 126 transitions. [2018-09-10 10:18:58,913 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-09-10 10:18:58,913 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 116 [2018-09-10 10:18:58,913 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:58,914 INFO L225 Difference]: With dead ends: 126 [2018-09-10 10:18:58,915 INFO L226 Difference]: Without dead ends: 121 [2018-09-10 10:18:58,916 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 503 GetRequests, 424 SyntacticMatches, 2 SemanticMatches, 77 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 356 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=2717, Invalid=3445, Unknown=0, NotChecked=0, Total=6162 [2018-09-10 10:18:58,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2018-09-10 10:18:58,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 120. [2018-09-10 10:18:58,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 120 states. [2018-09-10 10:18:58,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 120 transitions. [2018-09-10 10:18:58,920 INFO L78 Accepts]: Start accepts. Automaton has 120 states and 120 transitions. Word has length 116 [2018-09-10 10:18:58,920 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:58,920 INFO L480 AbstractCegarLoop]: Abstraction has 120 states and 120 transitions. [2018-09-10 10:18:58,920 INFO L481 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-09-10 10:18:58,921 INFO L276 IsEmpty]: Start isEmpty. Operand 120 states and 120 transitions. [2018-09-10 10:18:58,921 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-10 10:18:58,921 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:58,921 INFO L376 BasicCegarLoop]: trace histogram [37, 36, 36, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:58,922 INFO L423 AbstractCegarLoop]: === Iteration 38 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:58,922 INFO L82 PathProgramCache]: Analyzing trace with hash -1175023920, now seen corresponding path program 36 times [2018-09-10 10:18:58,922 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:58,922 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:58,923 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:58,923 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:58,923 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:58,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:59,850 INFO L134 CoverageAnalysis]: Checked inductivity of 1962 backedges. 0 proven. 1962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:59,850 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:59,850 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:59,857 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:18:59,857 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:18:59,934 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 37 check-sat command(s) [2018-09-10 10:18:59,934 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:59,937 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:59,996 INFO L134 CoverageAnalysis]: Checked inductivity of 1962 backedges. 0 proven. 1962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:18:59,997 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:01,988 INFO L134 CoverageAnalysis]: Checked inductivity of 1962 backedges. 0 proven. 1962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:02,010 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:02,011 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:19:02,025 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:19:02,025 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:19:02,625 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 37 check-sat command(s) [2018-09-10 10:19:02,626 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:19:02,632 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:02,754 INFO L134 CoverageAnalysis]: Checked inductivity of 1962 backedges. 0 proven. 1962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:02,754 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:02,774 INFO L134 CoverageAnalysis]: Checked inductivity of 1962 backedges. 0 proven. 1962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:02,775 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:19:02,776 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41, 41, 41, 41] total 80 [2018-09-10 10:19:02,776 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:19:02,776 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-09-10 10:19:02,776 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-09-10 10:19:02,777 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=2860, Invalid=3460, Unknown=0, NotChecked=0, Total=6320 [2018-09-10 10:19:02,777 INFO L87 Difference]: Start difference. First operand 120 states and 120 transitions. Second operand 41 states. [2018-09-10 10:19:02,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:19:02,867 INFO L93 Difference]: Finished difference Result 129 states and 129 transitions. [2018-09-10 10:19:02,867 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-09-10 10:19:02,867 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 119 [2018-09-10 10:19:02,868 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:19:02,869 INFO L225 Difference]: With dead ends: 129 [2018-09-10 10:19:02,869 INFO L226 Difference]: Without dead ends: 124 [2018-09-10 10:19:02,869 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 516 GetRequests, 435 SyntacticMatches, 2 SemanticMatches, 79 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 366 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=2866, Invalid=3614, Unknown=0, NotChecked=0, Total=6480 [2018-09-10 10:19:02,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124 states. [2018-09-10 10:19:02,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124 to 123. [2018-09-10 10:19:02,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 123 states. [2018-09-10 10:19:02,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 123 transitions. [2018-09-10 10:19:02,873 INFO L78 Accepts]: Start accepts. Automaton has 123 states and 123 transitions. Word has length 119 [2018-09-10 10:19:02,873 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:19:02,874 INFO L480 AbstractCegarLoop]: Abstraction has 123 states and 123 transitions. [2018-09-10 10:19:02,874 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-09-10 10:19:02,874 INFO L276 IsEmpty]: Start isEmpty. Operand 123 states and 123 transitions. [2018-09-10 10:19:02,874 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-09-10 10:19:02,874 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:19:02,874 INFO L376 BasicCegarLoop]: trace histogram [38, 37, 37, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:19:02,874 INFO L423 AbstractCegarLoop]: === Iteration 39 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:19:02,875 INFO L82 PathProgramCache]: Analyzing trace with hash 1692762053, now seen corresponding path program 37 times [2018-09-10 10:19:02,875 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:19:02,875 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:02,875 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:19:02,875 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:02,876 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:19:02,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:19:03,618 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 0 proven. 2072 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:03,618 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:03,618 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:19:03,628 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:19:03,628 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:19:03,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:19:03,688 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:03,786 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 0 proven. 2072 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:03,787 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:05,486 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 0 proven. 2072 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:05,507 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:05,507 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 75 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:19:05,522 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:19:05,522 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:19:05,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:19:05,653 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:05,710 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 0 proven. 2072 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:05,710 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:05,754 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 0 proven. 2072 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:05,756 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:19:05,756 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42, 42, 42, 42] total 82 [2018-09-10 10:19:05,756 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:19:05,756 INFO L459 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-09-10 10:19:05,757 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-09-10 10:19:05,757 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=3013, Invalid=3629, Unknown=0, NotChecked=0, Total=6642 [2018-09-10 10:19:05,757 INFO L87 Difference]: Start difference. First operand 123 states and 123 transitions. Second operand 42 states. [2018-09-10 10:19:05,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:19:05,858 INFO L93 Difference]: Finished difference Result 132 states and 132 transitions. [2018-09-10 10:19:05,858 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-09-10 10:19:05,858 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 122 [2018-09-10 10:19:05,858 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:19:05,859 INFO L225 Difference]: With dead ends: 132 [2018-09-10 10:19:05,859 INFO L226 Difference]: Without dead ends: 127 [2018-09-10 10:19:05,860 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 529 GetRequests, 446 SyntacticMatches, 2 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 376 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=3019, Invalid=3787, Unknown=0, NotChecked=0, Total=6806 [2018-09-10 10:19:05,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2018-09-10 10:19:05,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 126. [2018-09-10 10:19:05,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 126 states. [2018-09-10 10:19:05,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 126 transitions. [2018-09-10 10:19:05,864 INFO L78 Accepts]: Start accepts. Automaton has 126 states and 126 transitions. Word has length 122 [2018-09-10 10:19:05,864 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:19:05,864 INFO L480 AbstractCegarLoop]: Abstraction has 126 states and 126 transitions. [2018-09-10 10:19:05,865 INFO L481 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-09-10 10:19:05,865 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 126 transitions. [2018-09-10 10:19:05,865 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 126 [2018-09-10 10:19:05,865 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:19:05,866 INFO L376 BasicCegarLoop]: trace histogram [39, 38, 38, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:19:05,866 INFO L423 AbstractCegarLoop]: === Iteration 40 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:19:05,866 INFO L82 PathProgramCache]: Analyzing trace with hash 415231664, now seen corresponding path program 38 times [2018-09-10 10:19:05,866 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:19:05,867 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:05,867 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:19:05,867 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:05,867 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:19:05,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:19:07,686 INFO L134 CoverageAnalysis]: Checked inductivity of 2185 backedges. 0 proven. 2185 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:07,687 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:07,687 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:19:07,694 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:19:07,694 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:19:07,755 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:19:07,756 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:19:07,758 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:07,829 INFO L134 CoverageAnalysis]: Checked inductivity of 2185 backedges. 0 proven. 2185 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:07,829 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:09,585 INFO L134 CoverageAnalysis]: Checked inductivity of 2185 backedges. 0 proven. 2185 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:09,605 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:09,606 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 77 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:19:09,621 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:19:09,621 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:19:09,756 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:19:09,756 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:19:09,763 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:09,818 INFO L134 CoverageAnalysis]: Checked inductivity of 2185 backedges. 0 proven. 2185 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:09,819 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:09,844 INFO L134 CoverageAnalysis]: Checked inductivity of 2185 backedges. 0 proven. 2185 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:09,845 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:19:09,845 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43, 43, 43, 43] total 84 [2018-09-10 10:19:09,845 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:19:09,846 INFO L459 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-09-10 10:19:09,846 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-09-10 10:19:09,846 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=3170, Invalid=3802, Unknown=0, NotChecked=0, Total=6972 [2018-09-10 10:19:09,847 INFO L87 Difference]: Start difference. First operand 126 states and 126 transitions. Second operand 43 states. [2018-09-10 10:19:10,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:19:10,083 INFO L93 Difference]: Finished difference Result 135 states and 135 transitions. [2018-09-10 10:19:10,083 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-09-10 10:19:10,083 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 125 [2018-09-10 10:19:10,083 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:19:10,084 INFO L225 Difference]: With dead ends: 135 [2018-09-10 10:19:10,085 INFO L226 Difference]: Without dead ends: 130 [2018-09-10 10:19:10,086 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 542 GetRequests, 457 SyntacticMatches, 2 SemanticMatches, 83 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 386 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=3176, Invalid=3964, Unknown=0, NotChecked=0, Total=7140 [2018-09-10 10:19:10,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states. [2018-09-10 10:19:10,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 129. [2018-09-10 10:19:10,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 129 states. [2018-09-10 10:19:10,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 129 transitions. [2018-09-10 10:19:10,090 INFO L78 Accepts]: Start accepts. Automaton has 129 states and 129 transitions. Word has length 125 [2018-09-10 10:19:10,090 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:19:10,090 INFO L480 AbstractCegarLoop]: Abstraction has 129 states and 129 transitions. [2018-09-10 10:19:10,090 INFO L481 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-09-10 10:19:10,090 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 129 transitions. [2018-09-10 10:19:10,091 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2018-09-10 10:19:10,091 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:19:10,091 INFO L376 BasicCegarLoop]: trace histogram [40, 39, 39, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:19:10,091 INFO L423 AbstractCegarLoop]: === Iteration 41 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:19:10,092 INFO L82 PathProgramCache]: Analyzing trace with hash -787377179, now seen corresponding path program 39 times [2018-09-10 10:19:10,092 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:19:10,092 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:10,092 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:19:10,093 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:10,093 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:19:10,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:19:10,950 INFO L134 CoverageAnalysis]: Checked inductivity of 2301 backedges. 0 proven. 2301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:10,951 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:10,951 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:19:10,958 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:19:10,959 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:19:11,051 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 40 check-sat command(s) [2018-09-10 10:19:11,051 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:19:11,054 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:11,144 INFO L134 CoverageAnalysis]: Checked inductivity of 2301 backedges. 0 proven. 2301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:11,145 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:13,333 INFO L134 CoverageAnalysis]: Checked inductivity of 2301 backedges. 0 proven. 2301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:13,354 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:13,354 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 79 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:19:13,369 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:19:13,369 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:19:14,058 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 40 check-sat command(s) [2018-09-10 10:19:14,058 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:19:14,064 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:14,157 INFO L134 CoverageAnalysis]: Checked inductivity of 2301 backedges. 0 proven. 2301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:14,157 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:14,181 INFO L134 CoverageAnalysis]: Checked inductivity of 2301 backedges. 0 proven. 2301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:14,183 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:19:14,183 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44, 44, 44, 44] total 86 [2018-09-10 10:19:14,183 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:19:14,184 INFO L459 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-09-10 10:19:14,184 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-09-10 10:19:14,185 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=3331, Invalid=3979, Unknown=0, NotChecked=0, Total=7310 [2018-09-10 10:19:14,185 INFO L87 Difference]: Start difference. First operand 129 states and 129 transitions. Second operand 44 states. [2018-09-10 10:19:14,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:19:14,365 INFO L93 Difference]: Finished difference Result 138 states and 138 transitions. [2018-09-10 10:19:14,365 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-09-10 10:19:14,366 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 128 [2018-09-10 10:19:14,366 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:19:14,367 INFO L225 Difference]: With dead ends: 138 [2018-09-10 10:19:14,367 INFO L226 Difference]: Without dead ends: 133 [2018-09-10 10:19:14,368 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 555 GetRequests, 468 SyntacticMatches, 2 SemanticMatches, 85 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 396 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=3337, Invalid=4145, Unknown=0, NotChecked=0, Total=7482 [2018-09-10 10:19:14,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133 states. [2018-09-10 10:19:14,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133 to 132. [2018-09-10 10:19:14,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 132 states. [2018-09-10 10:19:14,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 132 transitions. [2018-09-10 10:19:14,372 INFO L78 Accepts]: Start accepts. Automaton has 132 states and 132 transitions. Word has length 128 [2018-09-10 10:19:14,372 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:19:14,373 INFO L480 AbstractCegarLoop]: Abstraction has 132 states and 132 transitions. [2018-09-10 10:19:14,373 INFO L481 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-09-10 10:19:14,373 INFO L276 IsEmpty]: Start isEmpty. Operand 132 states and 132 transitions. [2018-09-10 10:19:14,373 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2018-09-10 10:19:14,373 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:19:14,374 INFO L376 BasicCegarLoop]: trace histogram [41, 40, 40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:19:14,374 INFO L423 AbstractCegarLoop]: === Iteration 42 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:19:14,374 INFO L82 PathProgramCache]: Analyzing trace with hash 909764240, now seen corresponding path program 40 times [2018-09-10 10:19:14,374 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:19:14,375 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:14,375 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:19:14,375 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:14,375 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:19:14,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:19:15,928 INFO L134 CoverageAnalysis]: Checked inductivity of 2420 backedges. 0 proven. 2420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:15,928 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:15,928 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:19:15,936 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:19:15,936 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:19:15,996 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:19:15,996 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:19:15,999 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:16,185 INFO L134 CoverageAnalysis]: Checked inductivity of 2420 backedges. 0 proven. 2420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:16,186 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:18,358 INFO L134 CoverageAnalysis]: Checked inductivity of 2420 backedges. 0 proven. 2420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:18,378 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:18,378 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 81 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:19:18,393 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:19:18,393 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:19:18,531 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:19:18,532 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:19:18,538 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:18,593 INFO L134 CoverageAnalysis]: Checked inductivity of 2420 backedges. 0 proven. 2420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:18,593 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:18,663 INFO L134 CoverageAnalysis]: Checked inductivity of 2420 backedges. 0 proven. 2420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:18,665 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:19:18,666 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45, 45, 45, 45] total 88 [2018-09-10 10:19:18,666 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:19:18,667 INFO L459 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-09-10 10:19:18,667 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-09-10 10:19:18,667 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=3496, Invalid=4160, Unknown=0, NotChecked=0, Total=7656 [2018-09-10 10:19:18,668 INFO L87 Difference]: Start difference. First operand 132 states and 132 transitions. Second operand 45 states. [2018-09-10 10:19:18,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:19:18,775 INFO L93 Difference]: Finished difference Result 141 states and 141 transitions. [2018-09-10 10:19:18,777 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-09-10 10:19:18,777 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 131 [2018-09-10 10:19:18,777 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:19:18,778 INFO L225 Difference]: With dead ends: 141 [2018-09-10 10:19:18,778 INFO L226 Difference]: Without dead ends: 136 [2018-09-10 10:19:18,779 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 568 GetRequests, 479 SyntacticMatches, 2 SemanticMatches, 87 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 406 ImplicationChecksByTransitivity, 3.8s TimeCoverageRelationStatistics Valid=3502, Invalid=4330, Unknown=0, NotChecked=0, Total=7832 [2018-09-10 10:19:18,779 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states. [2018-09-10 10:19:18,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 135. [2018-09-10 10:19:18,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-09-10 10:19:18,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 135 transitions. [2018-09-10 10:19:18,783 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 135 transitions. Word has length 131 [2018-09-10 10:19:18,783 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:19:18,783 INFO L480 AbstractCegarLoop]: Abstraction has 135 states and 135 transitions. [2018-09-10 10:19:18,783 INFO L481 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-09-10 10:19:18,783 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 135 transitions. [2018-09-10 10:19:18,784 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2018-09-10 10:19:18,784 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:19:18,784 INFO L376 BasicCegarLoop]: trace histogram [42, 41, 41, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:19:18,785 INFO L423 AbstractCegarLoop]: === Iteration 43 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:19:18,785 INFO L82 PathProgramCache]: Analyzing trace with hash 94769157, now seen corresponding path program 41 times [2018-09-10 10:19:18,785 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:19:18,785 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:18,786 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:19:18,786 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:18,786 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:19:18,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:19:19,610 INFO L134 CoverageAnalysis]: Checked inductivity of 2542 backedges. 0 proven. 2542 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:19,610 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:19,610 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:19:19,620 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:19:19,620 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:19:19,705 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 42 check-sat command(s) [2018-09-10 10:19:19,705 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:19:19,708 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:19,765 INFO L134 CoverageAnalysis]: Checked inductivity of 2542 backedges. 0 proven. 2542 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:19,765 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:22,034 INFO L134 CoverageAnalysis]: Checked inductivity of 2542 backedges. 0 proven. 2542 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:22,056 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:22,056 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 83 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 83 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:19:22,071 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:19:22,071 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:19:22,825 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 42 check-sat command(s) [2018-09-10 10:19:22,825 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:19:22,832 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:22,892 INFO L134 CoverageAnalysis]: Checked inductivity of 2542 backedges. 0 proven. 2542 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:22,892 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:22,913 INFO L134 CoverageAnalysis]: Checked inductivity of 2542 backedges. 0 proven. 2542 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:22,914 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:19:22,915 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46, 46, 46, 46] total 90 [2018-09-10 10:19:22,915 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:19:22,915 INFO L459 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-09-10 10:19:22,916 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-09-10 10:19:22,916 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=3665, Invalid=4345, Unknown=0, NotChecked=0, Total=8010 [2018-09-10 10:19:22,917 INFO L87 Difference]: Start difference. First operand 135 states and 135 transitions. Second operand 46 states. [2018-09-10 10:19:23,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:19:23,584 INFO L93 Difference]: Finished difference Result 144 states and 144 transitions. [2018-09-10 10:19:23,584 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-09-10 10:19:23,585 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 134 [2018-09-10 10:19:23,585 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:19:23,586 INFO L225 Difference]: With dead ends: 144 [2018-09-10 10:19:23,586 INFO L226 Difference]: Without dead ends: 139 [2018-09-10 10:19:23,587 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 581 GetRequests, 490 SyntacticMatches, 2 SemanticMatches, 89 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 416 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=3671, Invalid=4519, Unknown=0, NotChecked=0, Total=8190 [2018-09-10 10:19:23,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2018-09-10 10:19:23,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 138. [2018-09-10 10:19:23,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2018-09-10 10:19:23,591 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 138 transitions. [2018-09-10 10:19:23,591 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 138 transitions. Word has length 134 [2018-09-10 10:19:23,591 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:19:23,592 INFO L480 AbstractCegarLoop]: Abstraction has 138 states and 138 transitions. [2018-09-10 10:19:23,592 INFO L481 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-09-10 10:19:23,592 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 138 transitions. [2018-09-10 10:19:23,592 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2018-09-10 10:19:23,593 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:19:23,593 INFO L376 BasicCegarLoop]: trace histogram [43, 42, 42, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:19:23,593 INFO L423 AbstractCegarLoop]: === Iteration 44 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:19:23,593 INFO L82 PathProgramCache]: Analyzing trace with hash 26375792, now seen corresponding path program 42 times [2018-09-10 10:19:23,593 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:19:23,594 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:23,594 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:19:23,594 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:23,594 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:19:23,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:19:24,474 INFO L134 CoverageAnalysis]: Checked inductivity of 2667 backedges. 0 proven. 2667 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:24,474 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:24,474 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:19:24,484 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:19:24,484 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:19:24,579 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 43 check-sat command(s) [2018-09-10 10:19:24,580 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:19:24,582 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:24,642 INFO L134 CoverageAnalysis]: Checked inductivity of 2667 backedges. 0 proven. 2667 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:24,642 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:27,109 INFO L134 CoverageAnalysis]: Checked inductivity of 2667 backedges. 0 proven. 2667 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:27,130 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:27,130 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 85 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 85 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:19:27,144 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:19:27,145 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:19:27,949 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 43 check-sat command(s) [2018-09-10 10:19:27,949 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:19:27,956 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:28,017 INFO L134 CoverageAnalysis]: Checked inductivity of 2667 backedges. 0 proven. 2667 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:28,017 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:28,039 INFO L134 CoverageAnalysis]: Checked inductivity of 2667 backedges. 0 proven. 2667 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:28,041 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:19:28,041 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47, 47, 47, 47] total 92 [2018-09-10 10:19:28,041 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:19:28,042 INFO L459 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-09-10 10:19:28,042 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-09-10 10:19:28,043 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=3838, Invalid=4534, Unknown=0, NotChecked=0, Total=8372 [2018-09-10 10:19:28,043 INFO L87 Difference]: Start difference. First operand 138 states and 138 transitions. Second operand 47 states. [2018-09-10 10:19:28,185 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:19:28,185 INFO L93 Difference]: Finished difference Result 147 states and 147 transitions. [2018-09-10 10:19:28,185 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-09-10 10:19:28,185 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 137 [2018-09-10 10:19:28,186 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:19:28,187 INFO L225 Difference]: With dead ends: 147 [2018-09-10 10:19:28,187 INFO L226 Difference]: Without dead ends: 142 [2018-09-10 10:19:28,189 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 594 GetRequests, 501 SyntacticMatches, 2 SemanticMatches, 91 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 426 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=3844, Invalid=4712, Unknown=0, NotChecked=0, Total=8556 [2018-09-10 10:19:28,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2018-09-10 10:19:28,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 141. [2018-09-10 10:19:28,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-09-10 10:19:28,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 141 transitions. [2018-09-10 10:19:28,193 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 141 transitions. Word has length 137 [2018-09-10 10:19:28,194 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:19:28,194 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 141 transitions. [2018-09-10 10:19:28,194 INFO L481 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-09-10 10:19:28,194 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 141 transitions. [2018-09-10 10:19:28,195 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2018-09-10 10:19:28,195 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:19:28,195 INFO L376 BasicCegarLoop]: trace histogram [44, 43, 43, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:19:28,195 INFO L423 AbstractCegarLoop]: === Iteration 45 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:19:28,195 INFO L82 PathProgramCache]: Analyzing trace with hash -1665862619, now seen corresponding path program 43 times [2018-09-10 10:19:28,195 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:19:28,196 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:28,196 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:19:28,196 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:28,196 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:19:28,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:19:29,387 INFO L134 CoverageAnalysis]: Checked inductivity of 2795 backedges. 0 proven. 2795 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:29,388 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:29,388 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:19:29,396 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:19:29,396 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:19:29,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:19:29,467 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:29,533 INFO L134 CoverageAnalysis]: Checked inductivity of 2795 backedges. 0 proven. 2795 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:29,533 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:32,117 INFO L134 CoverageAnalysis]: Checked inductivity of 2795 backedges. 0 proven. 2795 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:32,138 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:32,138 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 87 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 87 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:19:32,153 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:19:32,153 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:19:32,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:19:32,296 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:32,359 INFO L134 CoverageAnalysis]: Checked inductivity of 2795 backedges. 0 proven. 2795 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:32,359 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:32,389 INFO L134 CoverageAnalysis]: Checked inductivity of 2795 backedges. 0 proven. 2795 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:32,390 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:19:32,391 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48, 48, 48] total 94 [2018-09-10 10:19:32,391 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:19:32,391 INFO L459 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-09-10 10:19:32,392 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-09-10 10:19:32,392 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=4015, Invalid=4727, Unknown=0, NotChecked=0, Total=8742 [2018-09-10 10:19:32,392 INFO L87 Difference]: Start difference. First operand 141 states and 141 transitions. Second operand 48 states. [2018-09-10 10:19:32,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:19:32,502 INFO L93 Difference]: Finished difference Result 150 states and 150 transitions. [2018-09-10 10:19:32,503 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-09-10 10:19:32,503 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 140 [2018-09-10 10:19:32,503 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:19:32,504 INFO L225 Difference]: With dead ends: 150 [2018-09-10 10:19:32,504 INFO L226 Difference]: Without dead ends: 145 [2018-09-10 10:19:32,505 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 607 GetRequests, 512 SyntacticMatches, 2 SemanticMatches, 93 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 436 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=4021, Invalid=4909, Unknown=0, NotChecked=0, Total=8930 [2018-09-10 10:19:32,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2018-09-10 10:19:32,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 144. [2018-09-10 10:19:32,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-09-10 10:19:32,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 144 transitions. [2018-09-10 10:19:32,510 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 144 transitions. Word has length 140 [2018-09-10 10:19:32,510 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:19:32,510 INFO L480 AbstractCegarLoop]: Abstraction has 144 states and 144 transitions. [2018-09-10 10:19:32,511 INFO L481 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-09-10 10:19:32,511 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 144 transitions. [2018-09-10 10:19:32,511 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 144 [2018-09-10 10:19:32,511 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:19:32,512 INFO L376 BasicCegarLoop]: trace histogram [45, 44, 44, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:19:32,512 INFO L423 AbstractCegarLoop]: === Iteration 46 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:19:32,512 INFO L82 PathProgramCache]: Analyzing trace with hash -814244272, now seen corresponding path program 44 times [2018-09-10 10:19:32,512 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:19:32,513 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:32,513 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:19:32,513 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:32,513 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:19:32,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:19:33,713 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:33,714 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:33,714 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:19:33,724 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:19:33,724 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:19:33,802 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:19:33,802 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:19:33,805 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:33,846 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:33,846 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:36,174 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:36,194 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:36,194 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 89 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 89 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:19:36,209 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:19:36,209 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:19:36,369 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:19:36,369 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:19:36,377 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:36,419 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:36,419 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:36,448 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:36,449 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:19:36,449 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49, 49, 49, 49] total 96 [2018-09-10 10:19:36,449 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:19:36,450 INFO L459 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-09-10 10:19:36,451 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-09-10 10:19:36,451 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=4196, Invalid=4924, Unknown=0, NotChecked=0, Total=9120 [2018-09-10 10:19:36,451 INFO L87 Difference]: Start difference. First operand 144 states and 144 transitions. Second operand 49 states. [2018-09-10 10:19:36,714 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:19:36,714 INFO L93 Difference]: Finished difference Result 153 states and 153 transitions. [2018-09-10 10:19:36,714 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-09-10 10:19:36,714 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 143 [2018-09-10 10:19:36,715 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:19:36,716 INFO L225 Difference]: With dead ends: 153 [2018-09-10 10:19:36,716 INFO L226 Difference]: Without dead ends: 148 [2018-09-10 10:19:36,717 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 620 GetRequests, 523 SyntacticMatches, 2 SemanticMatches, 95 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 446 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=4202, Invalid=5110, Unknown=0, NotChecked=0, Total=9312 [2018-09-10 10:19:36,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2018-09-10 10:19:36,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 147. [2018-09-10 10:19:36,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-09-10 10:19:36,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 147 transitions. [2018-09-10 10:19:36,721 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 147 transitions. Word has length 143 [2018-09-10 10:19:36,722 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:19:36,722 INFO L480 AbstractCegarLoop]: Abstraction has 147 states and 147 transitions. [2018-09-10 10:19:36,722 INFO L481 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-09-10 10:19:36,722 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 147 transitions. [2018-09-10 10:19:36,723 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2018-09-10 10:19:36,723 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:19:36,723 INFO L376 BasicCegarLoop]: trace histogram [46, 45, 45, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:19:36,723 INFO L423 AbstractCegarLoop]: === Iteration 47 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:19:36,723 INFO L82 PathProgramCache]: Analyzing trace with hash -623886267, now seen corresponding path program 45 times [2018-09-10 10:19:36,724 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:19:36,724 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:36,724 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:19:36,724 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:36,724 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:19:36,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:19:37,891 INFO L134 CoverageAnalysis]: Checked inductivity of 3060 backedges. 0 proven. 3060 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:37,891 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:37,891 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:19:37,899 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:19:37,900 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:19:38,007 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 46 check-sat command(s) [2018-09-10 10:19:38,008 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:19:38,011 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:38,075 INFO L134 CoverageAnalysis]: Checked inductivity of 3060 backedges. 0 proven. 3060 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:38,076 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:40,477 INFO L134 CoverageAnalysis]: Checked inductivity of 3060 backedges. 0 proven. 3060 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:40,498 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:40,498 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 91 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 91 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:19:40,513 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:19:40,514 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:19:41,432 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 46 check-sat command(s) [2018-09-10 10:19:41,433 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:19:41,440 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:41,503 INFO L134 CoverageAnalysis]: Checked inductivity of 3060 backedges. 0 proven. 3060 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:41,504 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:41,529 INFO L134 CoverageAnalysis]: Checked inductivity of 3060 backedges. 0 proven. 3060 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:41,531 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:19:41,531 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50, 50, 50, 50] total 98 [2018-09-10 10:19:41,531 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:19:41,531 INFO L459 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-09-10 10:19:41,532 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-09-10 10:19:41,532 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=4381, Invalid=5125, Unknown=0, NotChecked=0, Total=9506 [2018-09-10 10:19:41,532 INFO L87 Difference]: Start difference. First operand 147 states and 147 transitions. Second operand 50 states. [2018-09-10 10:19:41,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:19:41,652 INFO L93 Difference]: Finished difference Result 156 states and 156 transitions. [2018-09-10 10:19:41,652 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-09-10 10:19:41,653 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 146 [2018-09-10 10:19:41,653 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:19:41,654 INFO L225 Difference]: With dead ends: 156 [2018-09-10 10:19:41,654 INFO L226 Difference]: Without dead ends: 151 [2018-09-10 10:19:41,655 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 633 GetRequests, 534 SyntacticMatches, 2 SemanticMatches, 97 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 456 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=4387, Invalid=5315, Unknown=0, NotChecked=0, Total=9702 [2018-09-10 10:19:41,655 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2018-09-10 10:19:41,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 150. [2018-09-10 10:19:41,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-09-10 10:19:41,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 150 transitions. [2018-09-10 10:19:41,659 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 150 transitions. Word has length 146 [2018-09-10 10:19:41,659 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:19:41,659 INFO L480 AbstractCegarLoop]: Abstraction has 150 states and 150 transitions. [2018-09-10 10:19:41,659 INFO L481 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-09-10 10:19:41,659 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 150 transitions. [2018-09-10 10:19:41,660 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 150 [2018-09-10 10:19:41,660 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:19:41,660 INFO L376 BasicCegarLoop]: trace histogram [47, 46, 46, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:19:41,660 INFO L423 AbstractCegarLoop]: === Iteration 48 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:19:41,661 INFO L82 PathProgramCache]: Analyzing trace with hash 974609968, now seen corresponding path program 46 times [2018-09-10 10:19:41,661 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:19:41,661 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:41,661 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:19:41,662 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:41,662 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:19:41,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:19:42,857 INFO L134 CoverageAnalysis]: Checked inductivity of 3197 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:42,857 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:42,857 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:19:42,866 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:19:42,867 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:19:42,941 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:19:42,941 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:19:42,944 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:43,005 INFO L134 CoverageAnalysis]: Checked inductivity of 3197 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:43,005 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:45,544 INFO L134 CoverageAnalysis]: Checked inductivity of 3197 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:45,565 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:45,565 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 93 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 93 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:19:45,580 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:19:45,580 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:19:45,743 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:19:45,744 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:19:45,751 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:45,816 INFO L134 CoverageAnalysis]: Checked inductivity of 3197 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:45,816 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:45,846 INFO L134 CoverageAnalysis]: Checked inductivity of 3197 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:45,847 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:19:45,847 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 51, 51, 51, 51] total 100 [2018-09-10 10:19:45,847 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:19:45,848 INFO L459 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-09-10 10:19:45,848 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-09-10 10:19:45,849 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=4570, Invalid=5330, Unknown=0, NotChecked=0, Total=9900 [2018-09-10 10:19:45,849 INFO L87 Difference]: Start difference. First operand 150 states and 150 transitions. Second operand 51 states. [2018-09-10 10:19:45,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:19:45,957 INFO L93 Difference]: Finished difference Result 159 states and 159 transitions. [2018-09-10 10:19:45,958 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-09-10 10:19:45,958 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 149 [2018-09-10 10:19:45,958 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:19:45,959 INFO L225 Difference]: With dead ends: 159 [2018-09-10 10:19:45,959 INFO L226 Difference]: Without dead ends: 154 [2018-09-10 10:19:45,960 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 646 GetRequests, 545 SyntacticMatches, 2 SemanticMatches, 99 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 466 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=4576, Invalid=5524, Unknown=0, NotChecked=0, Total=10100 [2018-09-10 10:19:45,960 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154 states. [2018-09-10 10:19:45,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154 to 153. [2018-09-10 10:19:45,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 153 states. [2018-09-10 10:19:45,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153 states to 153 states and 153 transitions. [2018-09-10 10:19:45,964 INFO L78 Accepts]: Start accepts. Automaton has 153 states and 153 transitions. Word has length 149 [2018-09-10 10:19:45,964 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:19:45,964 INFO L480 AbstractCegarLoop]: Abstraction has 153 states and 153 transitions. [2018-09-10 10:19:45,964 INFO L481 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-09-10 10:19:45,964 INFO L276 IsEmpty]: Start isEmpty. Operand 153 states and 153 transitions. [2018-09-10 10:19:45,965 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2018-09-10 10:19:45,965 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:19:45,965 INFO L376 BasicCegarLoop]: trace histogram [48, 47, 47, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:19:45,966 INFO L423 AbstractCegarLoop]: === Iteration 49 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:19:45,966 INFO L82 PathProgramCache]: Analyzing trace with hash -821431195, now seen corresponding path program 47 times [2018-09-10 10:19:45,966 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:19:45,966 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:45,967 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:19:45,967 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:45,967 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:19:45,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:19:47,330 INFO L134 CoverageAnalysis]: Checked inductivity of 3337 backedges. 0 proven. 3337 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:47,330 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:47,330 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:19:47,337 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:19:47,338 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:19:47,444 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 48 check-sat command(s) [2018-09-10 10:19:47,444 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:19:47,448 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:47,519 INFO L134 CoverageAnalysis]: Checked inductivity of 3337 backedges. 0 proven. 3337 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:47,519 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:50,114 INFO L134 CoverageAnalysis]: Checked inductivity of 3337 backedges. 0 proven. 3337 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:50,134 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:50,135 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 95 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 95 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:19:50,149 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:19:50,149 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:19:51,104 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 48 check-sat command(s) [2018-09-10 10:19:51,104 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:19:51,112 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:51,180 INFO L134 CoverageAnalysis]: Checked inductivity of 3337 backedges. 0 proven. 3337 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:51,181 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:51,213 INFO L134 CoverageAnalysis]: Checked inductivity of 3337 backedges. 0 proven. 3337 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:51,215 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:19:51,215 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 52, 52, 52, 52] total 102 [2018-09-10 10:19:51,215 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:19:51,215 INFO L459 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-09-10 10:19:51,216 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-09-10 10:19:51,216 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=4763, Invalid=5539, Unknown=0, NotChecked=0, Total=10302 [2018-09-10 10:19:51,216 INFO L87 Difference]: Start difference. First operand 153 states and 153 transitions. Second operand 52 states. [2018-09-10 10:19:51,339 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:19:51,340 INFO L93 Difference]: Finished difference Result 162 states and 162 transitions. [2018-09-10 10:19:51,340 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-09-10 10:19:51,340 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 152 [2018-09-10 10:19:51,340 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:19:51,341 INFO L225 Difference]: With dead ends: 162 [2018-09-10 10:19:51,341 INFO L226 Difference]: Without dead ends: 157 [2018-09-10 10:19:51,343 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 659 GetRequests, 556 SyntacticMatches, 2 SemanticMatches, 101 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 476 ImplicationChecksByTransitivity, 3.9s TimeCoverageRelationStatistics Valid=4769, Invalid=5737, Unknown=0, NotChecked=0, Total=10506 [2018-09-10 10:19:51,343 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-09-10 10:19:51,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 156. [2018-09-10 10:19:51,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156 states. [2018-09-10 10:19:51,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 156 transitions. [2018-09-10 10:19:51,347 INFO L78 Accepts]: Start accepts. Automaton has 156 states and 156 transitions. Word has length 152 [2018-09-10 10:19:51,348 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:19:51,348 INFO L480 AbstractCegarLoop]: Abstraction has 156 states and 156 transitions. [2018-09-10 10:19:51,348 INFO L481 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-09-10 10:19:51,348 INFO L276 IsEmpty]: Start isEmpty. Operand 156 states and 156 transitions. [2018-09-10 10:19:51,349 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2018-09-10 10:19:51,349 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:19:51,349 INFO L376 BasicCegarLoop]: trace histogram [49, 48, 48, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:19:51,349 INFO L423 AbstractCegarLoop]: === Iteration 50 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:19:51,349 INFO L82 PathProgramCache]: Analyzing trace with hash 18855440, now seen corresponding path program 48 times [2018-09-10 10:19:51,350 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:19:51,350 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:51,350 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:19:51,350 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:51,350 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:19:51,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:19:52,732 INFO L134 CoverageAnalysis]: Checked inductivity of 3480 backedges. 0 proven. 3480 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:52,733 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:52,733 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 96 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 96 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:19:52,739 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:19:52,740 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:19:52,846 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2018-09-10 10:19:52,846 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:19:52,849 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:52,918 INFO L134 CoverageAnalysis]: Checked inductivity of 3480 backedges. 0 proven. 3480 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:52,918 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:55,599 INFO L134 CoverageAnalysis]: Checked inductivity of 3480 backedges. 0 proven. 3480 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:55,619 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:55,619 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 97 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 97 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:19:55,634 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:19:55,634 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:19:56,620 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2018-09-10 10:19:56,620 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:19:56,629 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:56,700 INFO L134 CoverageAnalysis]: Checked inductivity of 3480 backedges. 0 proven. 3480 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:56,700 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:19:56,734 INFO L134 CoverageAnalysis]: Checked inductivity of 3480 backedges. 0 proven. 3480 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:56,735 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:19:56,736 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [53, 53, 53, 53, 53] total 104 [2018-09-10 10:19:56,736 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:19:56,736 INFO L459 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-09-10 10:19:56,737 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-09-10 10:19:56,737 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=4960, Invalid=5752, Unknown=0, NotChecked=0, Total=10712 [2018-09-10 10:19:56,737 INFO L87 Difference]: Start difference. First operand 156 states and 156 transitions. Second operand 53 states. [2018-09-10 10:19:56,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:19:56,906 INFO L93 Difference]: Finished difference Result 165 states and 165 transitions. [2018-09-10 10:19:56,906 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-09-10 10:19:56,906 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 155 [2018-09-10 10:19:56,907 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:19:56,907 INFO L225 Difference]: With dead ends: 165 [2018-09-10 10:19:56,907 INFO L226 Difference]: Without dead ends: 160 [2018-09-10 10:19:56,908 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 672 GetRequests, 567 SyntacticMatches, 2 SemanticMatches, 103 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 486 ImplicationChecksByTransitivity, 4.0s TimeCoverageRelationStatistics Valid=4966, Invalid=5954, Unknown=0, NotChecked=0, Total=10920 [2018-09-10 10:19:56,908 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states. [2018-09-10 10:19:56,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 159. [2018-09-10 10:19:56,912 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159 states. [2018-09-10 10:19:56,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 159 transitions. [2018-09-10 10:19:56,912 INFO L78 Accepts]: Start accepts. Automaton has 159 states and 159 transitions. Word has length 155 [2018-09-10 10:19:56,913 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:19:56,913 INFO L480 AbstractCegarLoop]: Abstraction has 159 states and 159 transitions. [2018-09-10 10:19:56,913 INFO L481 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-09-10 10:19:56,913 INFO L276 IsEmpty]: Start isEmpty. Operand 159 states and 159 transitions. [2018-09-10 10:19:56,914 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 159 [2018-09-10 10:19:56,914 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:19:56,914 INFO L376 BasicCegarLoop]: trace histogram [50, 49, 49, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:19:56,914 INFO L423 AbstractCegarLoop]: === Iteration 51 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:19:56,915 INFO L82 PathProgramCache]: Analyzing trace with hash 1928597637, now seen corresponding path program 49 times [2018-09-10 10:19:56,915 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:19:56,915 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:56,915 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:19:56,915 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:19:56,916 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:19:56,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:19:58,370 INFO L134 CoverageAnalysis]: Checked inductivity of 3626 backedges. 0 proven. 3626 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:58,370 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:19:58,370 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 98 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 98 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:19:58,378 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:19:58,378 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:19:58,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:19:58,463 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:19:58,536 INFO L134 CoverageAnalysis]: Checked inductivity of 3626 backedges. 0 proven. 3626 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:19:58,537 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:20:01,489 INFO L134 CoverageAnalysis]: Checked inductivity of 3626 backedges. 0 proven. 3626 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:01,509 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:20:01,509 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 99 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 99 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:20:01,524 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:20:01,524 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:20:01,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:20:01,700 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:20:01,747 INFO L134 CoverageAnalysis]: Checked inductivity of 3626 backedges. 0 proven. 3626 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:01,748 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:20:01,797 INFO L134 CoverageAnalysis]: Checked inductivity of 3626 backedges. 0 proven. 3626 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:01,798 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:20:01,799 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 54, 54, 54, 54] total 106 [2018-09-10 10:20:01,799 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:20:01,799 INFO L459 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-09-10 10:20:01,799 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-09-10 10:20:01,800 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=5161, Invalid=5969, Unknown=0, NotChecked=0, Total=11130 [2018-09-10 10:20:01,800 INFO L87 Difference]: Start difference. First operand 159 states and 159 transitions. Second operand 54 states. [2018-09-10 10:20:01,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:20:01,963 INFO L93 Difference]: Finished difference Result 168 states and 168 transitions. [2018-09-10 10:20:01,964 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-09-10 10:20:01,964 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 158 [2018-09-10 10:20:01,964 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:20:01,965 INFO L225 Difference]: With dead ends: 168 [2018-09-10 10:20:01,965 INFO L226 Difference]: Without dead ends: 163 [2018-09-10 10:20:01,965 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 685 GetRequests, 578 SyntacticMatches, 2 SemanticMatches, 105 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 496 ImplicationChecksByTransitivity, 4.3s TimeCoverageRelationStatistics Valid=5167, Invalid=6175, Unknown=0, NotChecked=0, Total=11342 [2018-09-10 10:20:01,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states. [2018-09-10 10:20:01,968 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 162. [2018-09-10 10:20:01,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-09-10 10:20:01,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 162 transitions. [2018-09-10 10:20:01,969 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 162 transitions. Word has length 158 [2018-09-10 10:20:01,969 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:20:01,969 INFO L480 AbstractCegarLoop]: Abstraction has 162 states and 162 transitions. [2018-09-10 10:20:01,969 INFO L481 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-09-10 10:20:01,969 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 162 transitions. [2018-09-10 10:20:01,970 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 162 [2018-09-10 10:20:01,970 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:20:01,970 INFO L376 BasicCegarLoop]: trace histogram [51, 50, 50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:20:01,971 INFO L423 AbstractCegarLoop]: === Iteration 52 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:20:01,971 INFO L82 PathProgramCache]: Analyzing trace with hash -373381648, now seen corresponding path program 50 times [2018-09-10 10:20:01,971 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:20:01,971 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:20:01,971 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:20:01,972 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:20:01,972 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:20:01,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:20:03,407 INFO L134 CoverageAnalysis]: Checked inductivity of 3775 backedges. 0 proven. 3775 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:03,408 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:20:03,408 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 100 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 100 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:20:03,416 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:20:03,417 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:20:03,500 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:20:03,500 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:20:03,503 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:20:03,577 INFO L134 CoverageAnalysis]: Checked inductivity of 3775 backedges. 0 proven. 3775 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:03,577 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:20:06,679 INFO L134 CoverageAnalysis]: Checked inductivity of 3775 backedges. 0 proven. 3775 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:06,700 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:20:06,700 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 101 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 101 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:20:06,714 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:20:06,715 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:20:06,895 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:20:06,895 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:20:06,904 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:20:06,977 INFO L134 CoverageAnalysis]: Checked inductivity of 3775 backedges. 0 proven. 3775 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:06,977 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:20:07,006 INFO L134 CoverageAnalysis]: Checked inductivity of 3775 backedges. 0 proven. 3775 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:07,008 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:20:07,008 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [55, 55, 55, 55, 55] total 108 [2018-09-10 10:20:07,008 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:20:07,009 INFO L459 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-09-10 10:20:07,009 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-09-10 10:20:07,010 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=5366, Invalid=6190, Unknown=0, NotChecked=0, Total=11556 [2018-09-10 10:20:07,010 INFO L87 Difference]: Start difference. First operand 162 states and 162 transitions. Second operand 55 states. [2018-09-10 10:20:07,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:20:07,164 INFO L93 Difference]: Finished difference Result 171 states and 171 transitions. [2018-09-10 10:20:07,165 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-09-10 10:20:07,165 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 161 [2018-09-10 10:20:07,165 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:20:07,166 INFO L225 Difference]: With dead ends: 171 [2018-09-10 10:20:07,166 INFO L226 Difference]: Without dead ends: 166 [2018-09-10 10:20:07,167 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 698 GetRequests, 589 SyntacticMatches, 2 SemanticMatches, 107 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 506 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=5372, Invalid=6400, Unknown=0, NotChecked=0, Total=11772 [2018-09-10 10:20:07,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166 states. [2018-09-10 10:20:07,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166 to 165. [2018-09-10 10:20:07,170 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-09-10 10:20:07,170 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 165 transitions. [2018-09-10 10:20:07,170 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 165 transitions. Word has length 161 [2018-09-10 10:20:07,171 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:20:07,171 INFO L480 AbstractCegarLoop]: Abstraction has 165 states and 165 transitions. [2018-09-10 10:20:07,171 INFO L481 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-09-10 10:20:07,171 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 165 transitions. [2018-09-10 10:20:07,171 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 165 [2018-09-10 10:20:07,171 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:20:07,172 INFO L376 BasicCegarLoop]: trace histogram [52, 51, 51, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:20:07,172 INFO L423 AbstractCegarLoop]: === Iteration 53 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:20:07,172 INFO L82 PathProgramCache]: Analyzing trace with hash -895445851, now seen corresponding path program 51 times [2018-09-10 10:20:07,172 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:20:07,172 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:20:07,173 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:20:07,173 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:20:07,173 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:20:07,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:20:08,633 INFO L134 CoverageAnalysis]: Checked inductivity of 3927 backedges. 0 proven. 3927 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:08,633 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:20:08,633 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 102 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 102 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:20:08,640 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:20:08,640 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:20:08,757 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 52 check-sat command(s) [2018-09-10 10:20:08,757 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:20:08,760 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:20:08,853 INFO L134 CoverageAnalysis]: Checked inductivity of 3927 backedges. 0 proven. 3927 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:08,853 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:20:11,909 INFO L134 CoverageAnalysis]: Checked inductivity of 3927 backedges. 0 proven. 3927 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:11,930 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:20:11,931 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 103 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 103 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:20:11,945 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:20:11,945 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:20:13,051 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 52 check-sat command(s) [2018-09-10 10:20:13,051 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:20:13,059 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:20:13,136 INFO L134 CoverageAnalysis]: Checked inductivity of 3927 backedges. 0 proven. 3927 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:13,136 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:20:13,172 INFO L134 CoverageAnalysis]: Checked inductivity of 3927 backedges. 0 proven. 3927 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:13,174 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:20:13,174 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 56, 56, 56, 56] total 110 [2018-09-10 10:20:13,174 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:20:13,175 INFO L459 AbstractCegarLoop]: Interpolant automaton has 56 states [2018-09-10 10:20:13,175 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2018-09-10 10:20:13,176 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=5575, Invalid=6415, Unknown=0, NotChecked=0, Total=11990 [2018-09-10 10:20:13,176 INFO L87 Difference]: Start difference. First operand 165 states and 165 transitions. Second operand 56 states. [2018-09-10 10:20:13,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:20:13,329 INFO L93 Difference]: Finished difference Result 174 states and 174 transitions. [2018-09-10 10:20:13,329 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-09-10 10:20:13,330 INFO L78 Accepts]: Start accepts. Automaton has 56 states. Word has length 164 [2018-09-10 10:20:13,330 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:20:13,330 INFO L225 Difference]: With dead ends: 174 [2018-09-10 10:20:13,330 INFO L226 Difference]: Without dead ends: 169 [2018-09-10 10:20:13,331 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 711 GetRequests, 600 SyntacticMatches, 2 SemanticMatches, 109 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 516 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=5581, Invalid=6629, Unknown=0, NotChecked=0, Total=12210 [2018-09-10 10:20:13,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 169 states. [2018-09-10 10:20:13,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 169 to 168. [2018-09-10 10:20:13,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 168 states. [2018-09-10 10:20:13,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 168 states to 168 states and 168 transitions. [2018-09-10 10:20:13,335 INFO L78 Accepts]: Start accepts. Automaton has 168 states and 168 transitions. Word has length 164 [2018-09-10 10:20:13,335 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:20:13,335 INFO L480 AbstractCegarLoop]: Abstraction has 168 states and 168 transitions. [2018-09-10 10:20:13,335 INFO L481 AbstractCegarLoop]: Interpolant automaton has 56 states. [2018-09-10 10:20:13,335 INFO L276 IsEmpty]: Start isEmpty. Operand 168 states and 168 transitions. [2018-09-10 10:20:13,336 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2018-09-10 10:20:13,336 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:20:13,336 INFO L376 BasicCegarLoop]: trace histogram [53, 52, 52, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:20:13,337 INFO L423 AbstractCegarLoop]: === Iteration 54 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:20:13,337 INFO L82 PathProgramCache]: Analyzing trace with hash -1633538608, now seen corresponding path program 52 times [2018-09-10 10:20:13,337 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:20:13,338 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:20:13,338 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:20:13,338 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:20:13,338 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:20:13,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:20:14,542 INFO L134 CoverageAnalysis]: Checked inductivity of 4082 backedges. 0 proven. 4082 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:14,543 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:20:14,543 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 104 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 104 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:20:14,552 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:20:14,552 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:20:14,638 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:20:14,638 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:20:14,642 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:20:14,720 INFO L134 CoverageAnalysis]: Checked inductivity of 4082 backedges. 0 proven. 4082 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:14,720 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:20:18,178 INFO L134 CoverageAnalysis]: Checked inductivity of 4082 backedges. 0 proven. 4082 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:18,200 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:20:18,200 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 105 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 105 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:20:18,215 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:20:18,215 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:20:18,394 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:20:18,395 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:20:18,402 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:20:18,474 INFO L134 CoverageAnalysis]: Checked inductivity of 4082 backedges. 0 proven. 4082 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:18,475 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:20:18,514 INFO L134 CoverageAnalysis]: Checked inductivity of 4082 backedges. 0 proven. 4082 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:18,516 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:20:18,516 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [57, 57, 57, 57, 57] total 112 [2018-09-10 10:20:18,516 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:20:18,517 INFO L459 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-09-10 10:20:18,517 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-09-10 10:20:18,518 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=5788, Invalid=6644, Unknown=0, NotChecked=0, Total=12432 [2018-09-10 10:20:18,518 INFO L87 Difference]: Start difference. First operand 168 states and 168 transitions. Second operand 57 states. [2018-09-10 10:20:18,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:20:18,656 INFO L93 Difference]: Finished difference Result 177 states and 177 transitions. [2018-09-10 10:20:18,656 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2018-09-10 10:20:18,656 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 167 [2018-09-10 10:20:18,657 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:20:18,658 INFO L225 Difference]: With dead ends: 177 [2018-09-10 10:20:18,658 INFO L226 Difference]: Without dead ends: 172 [2018-09-10 10:20:18,659 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 724 GetRequests, 611 SyntacticMatches, 2 SemanticMatches, 111 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 526 ImplicationChecksByTransitivity, 4.6s TimeCoverageRelationStatistics Valid=5794, Invalid=6862, Unknown=0, NotChecked=0, Total=12656 [2018-09-10 10:20:18,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states. [2018-09-10 10:20:18,662 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 171. [2018-09-10 10:20:18,662 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 171 states. [2018-09-10 10:20:18,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 171 transitions. [2018-09-10 10:20:18,663 INFO L78 Accepts]: Start accepts. Automaton has 171 states and 171 transitions. Word has length 167 [2018-09-10 10:20:18,663 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:20:18,663 INFO L480 AbstractCegarLoop]: Abstraction has 171 states and 171 transitions. [2018-09-10 10:20:18,663 INFO L481 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-09-10 10:20:18,663 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states and 171 transitions. [2018-09-10 10:20:18,664 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 171 [2018-09-10 10:20:18,664 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:20:18,664 INFO L376 BasicCegarLoop]: trace histogram [54, 53, 53, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:20:18,664 INFO L423 AbstractCegarLoop]: === Iteration 55 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:20:18,665 INFO L82 PathProgramCache]: Analyzing trace with hash 77693125, now seen corresponding path program 53 times [2018-09-10 10:20:18,665 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:20:18,665 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:20:18,665 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:20:18,665 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:20:18,665 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:20:18,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:20:19,963 INFO L134 CoverageAnalysis]: Checked inductivity of 4240 backedges. 0 proven. 4240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:19,963 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:20:19,963 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 106 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 106 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:20:19,971 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:20:19,971 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:20:20,090 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 54 check-sat command(s) [2018-09-10 10:20:20,090 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:20:20,095 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:20:20,169 INFO L134 CoverageAnalysis]: Checked inductivity of 4240 backedges. 0 proven. 4240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:20,170 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:20:23,675 INFO L134 CoverageAnalysis]: Checked inductivity of 4240 backedges. 0 proven. 4240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:23,697 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:20:23,697 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 107 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 107 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:20:23,711 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:20:23,712 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:20:24,865 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 54 check-sat command(s) [2018-09-10 10:20:24,865 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:20:24,873 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:20:24,947 INFO L134 CoverageAnalysis]: Checked inductivity of 4240 backedges. 0 proven. 4240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:24,947 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:20:24,983 INFO L134 CoverageAnalysis]: Checked inductivity of 4240 backedges. 0 proven. 4240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:24,984 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:20:24,985 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 58, 58, 58, 58] total 114 [2018-09-10 10:20:24,985 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:20:24,985 INFO L459 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-09-10 10:20:24,986 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-09-10 10:20:24,986 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=6005, Invalid=6877, Unknown=0, NotChecked=0, Total=12882 [2018-09-10 10:20:24,986 INFO L87 Difference]: Start difference. First operand 171 states and 171 transitions. Second operand 58 states. [2018-09-10 10:20:25,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:20:25,144 INFO L93 Difference]: Finished difference Result 180 states and 180 transitions. [2018-09-10 10:20:25,144 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2018-09-10 10:20:25,144 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 170 [2018-09-10 10:20:25,144 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:20:25,145 INFO L225 Difference]: With dead ends: 180 [2018-09-10 10:20:25,145 INFO L226 Difference]: Without dead ends: 175 [2018-09-10 10:20:25,146 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 737 GetRequests, 622 SyntacticMatches, 2 SemanticMatches, 113 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 536 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=6011, Invalid=7099, Unknown=0, NotChecked=0, Total=13110 [2018-09-10 10:20:25,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175 states. [2018-09-10 10:20:25,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175 to 174. [2018-09-10 10:20:25,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-09-10 10:20:25,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 174 transitions. [2018-09-10 10:20:25,148 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 174 transitions. Word has length 170 [2018-09-10 10:20:25,148 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:20:25,148 INFO L480 AbstractCegarLoop]: Abstraction has 174 states and 174 transitions. [2018-09-10 10:20:25,149 INFO L481 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-09-10 10:20:25,149 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 174 transitions. [2018-09-10 10:20:25,149 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2018-09-10 10:20:25,149 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:20:25,149 INFO L376 BasicCegarLoop]: trace histogram [55, 54, 54, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:20:25,150 INFO L423 AbstractCegarLoop]: === Iteration 56 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:20:25,150 INFO L82 PathProgramCache]: Analyzing trace with hash -1879552592, now seen corresponding path program 54 times [2018-09-10 10:20:25,150 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:20:25,150 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:20:25,151 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:20:25,151 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:20:25,151 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:20:25,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:20:26,457 INFO L134 CoverageAnalysis]: Checked inductivity of 4401 backedges. 0 proven. 4401 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:26,458 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:20:26,458 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 108 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 108 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:20:26,466 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:20:26,466 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:20:26,592 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 55 check-sat command(s) [2018-09-10 10:20:26,592 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:20:26,595 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:20:26,672 INFO L134 CoverageAnalysis]: Checked inductivity of 4401 backedges. 0 proven. 4401 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:26,672 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:20:30,371 INFO L134 CoverageAnalysis]: Checked inductivity of 4401 backedges. 0 proven. 4401 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:30,392 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:20:30,392 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 109 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 109 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:20:30,407 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:20:30,407 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:20:31,620 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 55 check-sat command(s) [2018-09-10 10:20:31,620 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:20:31,628 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:20:31,701 INFO L134 CoverageAnalysis]: Checked inductivity of 4401 backedges. 0 proven. 4401 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:31,701 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:20:31,738 INFO L134 CoverageAnalysis]: Checked inductivity of 4401 backedges. 0 proven. 4401 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:31,739 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:20:31,739 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59, 59, 59] total 116 [2018-09-10 10:20:31,739 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:20:31,740 INFO L459 AbstractCegarLoop]: Interpolant automaton has 59 states [2018-09-10 10:20:31,740 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2018-09-10 10:20:31,741 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=6226, Invalid=7114, Unknown=0, NotChecked=0, Total=13340 [2018-09-10 10:20:31,741 INFO L87 Difference]: Start difference. First operand 174 states and 174 transitions. Second operand 59 states. [2018-09-10 10:20:31,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:20:31,918 INFO L93 Difference]: Finished difference Result 183 states and 183 transitions. [2018-09-10 10:20:31,918 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-09-10 10:20:31,918 INFO L78 Accepts]: Start accepts. Automaton has 59 states. Word has length 173 [2018-09-10 10:20:31,918 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:20:31,919 INFO L225 Difference]: With dead ends: 183 [2018-09-10 10:20:31,919 INFO L226 Difference]: Without dead ends: 178 [2018-09-10 10:20:31,920 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 750 GetRequests, 633 SyntacticMatches, 2 SemanticMatches, 115 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 546 ImplicationChecksByTransitivity, 4.9s TimeCoverageRelationStatistics Valid=6232, Invalid=7340, Unknown=0, NotChecked=0, Total=13572 [2018-09-10 10:20:31,921 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states. [2018-09-10 10:20:31,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 177. [2018-09-10 10:20:31,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 177 states. [2018-09-10 10:20:31,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177 states to 177 states and 177 transitions. [2018-09-10 10:20:31,924 INFO L78 Accepts]: Start accepts. Automaton has 177 states and 177 transitions. Word has length 173 [2018-09-10 10:20:31,925 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:20:31,925 INFO L480 AbstractCegarLoop]: Abstraction has 177 states and 177 transitions. [2018-09-10 10:20:31,925 INFO L481 AbstractCegarLoop]: Interpolant automaton has 59 states. [2018-09-10 10:20:31,925 INFO L276 IsEmpty]: Start isEmpty. Operand 177 states and 177 transitions. [2018-09-10 10:20:31,926 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2018-09-10 10:20:31,926 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:20:31,926 INFO L376 BasicCegarLoop]: trace histogram [56, 55, 55, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:20:31,926 INFO L423 AbstractCegarLoop]: === Iteration 57 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:20:31,927 INFO L82 PathProgramCache]: Analyzing trace with hash -1710697243, now seen corresponding path program 55 times [2018-09-10 10:20:31,927 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:20:31,927 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:20:31,927 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:20:31,927 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:20:31,928 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:20:31,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:20:33,605 INFO L134 CoverageAnalysis]: Checked inductivity of 4565 backedges. 0 proven. 4565 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:33,605 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:20:33,605 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 110 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 110 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:20:33,614 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:20:33,614 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:20:33,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:20:33,705 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:20:33,790 INFO L134 CoverageAnalysis]: Checked inductivity of 4565 backedges. 0 proven. 4565 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:33,791 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:20:37,355 INFO L134 CoverageAnalysis]: Checked inductivity of 4565 backedges. 0 proven. 4565 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:37,376 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:20:37,376 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 111 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 111 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:20:37,391 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:20:37,391 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:20:37,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:20:37,586 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:20:37,664 INFO L134 CoverageAnalysis]: Checked inductivity of 4565 backedges. 0 proven. 4565 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:37,664 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:20:37,704 INFO L134 CoverageAnalysis]: Checked inductivity of 4565 backedges. 0 proven. 4565 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:37,706 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:20:37,706 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 60, 60, 60, 60] total 118 [2018-09-10 10:20:37,706 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:20:37,707 INFO L459 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-09-10 10:20:37,707 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-09-10 10:20:37,708 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=6451, Invalid=7355, Unknown=0, NotChecked=0, Total=13806 [2018-09-10 10:20:37,708 INFO L87 Difference]: Start difference. First operand 177 states and 177 transitions. Second operand 60 states. [2018-09-10 10:20:37,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:20:37,867 INFO L93 Difference]: Finished difference Result 186 states and 186 transitions. [2018-09-10 10:20:37,867 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-09-10 10:20:37,867 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 176 [2018-09-10 10:20:37,867 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:20:37,868 INFO L225 Difference]: With dead ends: 186 [2018-09-10 10:20:37,868 INFO L226 Difference]: Without dead ends: 181 [2018-09-10 10:20:37,869 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 763 GetRequests, 644 SyntacticMatches, 2 SemanticMatches, 117 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 556 ImplicationChecksByTransitivity, 5.2s TimeCoverageRelationStatistics Valid=6457, Invalid=7585, Unknown=0, NotChecked=0, Total=14042 [2018-09-10 10:20:37,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181 states. [2018-09-10 10:20:37,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181 to 180. [2018-09-10 10:20:37,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 180 states. [2018-09-10 10:20:37,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 180 transitions. [2018-09-10 10:20:37,874 INFO L78 Accepts]: Start accepts. Automaton has 180 states and 180 transitions. Word has length 176 [2018-09-10 10:20:37,874 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:20:37,874 INFO L480 AbstractCegarLoop]: Abstraction has 180 states and 180 transitions. [2018-09-10 10:20:37,875 INFO L481 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-09-10 10:20:37,875 INFO L276 IsEmpty]: Start isEmpty. Operand 180 states and 180 transitions. [2018-09-10 10:20:37,875 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2018-09-10 10:20:37,876 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:20:37,876 INFO L376 BasicCegarLoop]: trace histogram [57, 56, 56, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:20:37,876 INFO L423 AbstractCegarLoop]: === Iteration 58 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:20:37,876 INFO L82 PathProgramCache]: Analyzing trace with hash -747698800, now seen corresponding path program 56 times [2018-09-10 10:20:37,876 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:20:37,877 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:20:37,877 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:20:37,877 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:20:37,877 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:20:37,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:20:39,485 INFO L134 CoverageAnalysis]: Checked inductivity of 4732 backedges. 0 proven. 4732 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:39,485 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:20:39,485 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 112 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 112 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:20:39,493 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:20:39,493 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:20:39,587 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:20:39,587 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:20:39,590 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:20:39,665 INFO L134 CoverageAnalysis]: Checked inductivity of 4732 backedges. 0 proven. 4732 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:39,666 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:20:43,521 INFO L134 CoverageAnalysis]: Checked inductivity of 4732 backedges. 0 proven. 4732 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:43,542 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:20:43,542 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 113 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 113 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:20:43,556 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:20:43,557 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:20:43,750 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:20:43,751 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:20:43,759 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:20:43,847 INFO L134 CoverageAnalysis]: Checked inductivity of 4732 backedges. 0 proven. 4732 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:43,847 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:20:43,886 INFO L134 CoverageAnalysis]: Checked inductivity of 4732 backedges. 0 proven. 4732 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:43,887 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:20:43,888 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [61, 61, 61, 61, 61] total 120 [2018-09-10 10:20:43,888 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:20:43,888 INFO L459 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-09-10 10:20:43,889 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-09-10 10:20:43,889 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=6680, Invalid=7600, Unknown=0, NotChecked=0, Total=14280 [2018-09-10 10:20:43,889 INFO L87 Difference]: Start difference. First operand 180 states and 180 transitions. Second operand 61 states. [2018-09-10 10:20:44,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:20:44,074 INFO L93 Difference]: Finished difference Result 189 states and 189 transitions. [2018-09-10 10:20:44,074 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2018-09-10 10:20:44,074 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 179 [2018-09-10 10:20:44,074 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:20:44,075 INFO L225 Difference]: With dead ends: 189 [2018-09-10 10:20:44,075 INFO L226 Difference]: Without dead ends: 184 [2018-09-10 10:20:44,076 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 776 GetRequests, 655 SyntacticMatches, 2 SemanticMatches, 119 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 566 ImplicationChecksByTransitivity, 5.4s TimeCoverageRelationStatistics Valid=6686, Invalid=7834, Unknown=0, NotChecked=0, Total=14520 [2018-09-10 10:20:44,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states. [2018-09-10 10:20:44,079 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 183. [2018-09-10 10:20:44,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 183 states. [2018-09-10 10:20:44,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 183 states to 183 states and 183 transitions. [2018-09-10 10:20:44,080 INFO L78 Accepts]: Start accepts. Automaton has 183 states and 183 transitions. Word has length 179 [2018-09-10 10:20:44,080 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:20:44,080 INFO L480 AbstractCegarLoop]: Abstraction has 183 states and 183 transitions. [2018-09-10 10:20:44,081 INFO L481 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-09-10 10:20:44,081 INFO L276 IsEmpty]: Start isEmpty. Operand 183 states and 183 transitions. [2018-09-10 10:20:44,082 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2018-09-10 10:20:44,082 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:20:44,082 INFO L376 BasicCegarLoop]: trace histogram [58, 57, 57, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:20:44,082 INFO L423 AbstractCegarLoop]: === Iteration 59 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:20:44,082 INFO L82 PathProgramCache]: Analyzing trace with hash 1852346629, now seen corresponding path program 57 times [2018-09-10 10:20:44,082 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:20:44,083 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:20:44,083 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:20:44,083 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:20:44,083 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:20:44,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:20:45,512 INFO L134 CoverageAnalysis]: Checked inductivity of 4902 backedges. 0 proven. 4902 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:45,513 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:20:45,513 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 114 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 114 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:20:45,520 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:20:45,521 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:20:45,658 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 58 check-sat command(s) [2018-09-10 10:20:45,659 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:20:45,662 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:20:45,762 INFO L134 CoverageAnalysis]: Checked inductivity of 4902 backedges. 0 proven. 4902 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:45,763 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:20:49,841 INFO L134 CoverageAnalysis]: Checked inductivity of 4902 backedges. 0 proven. 4902 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:49,862 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:20:49,862 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 115 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 115 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:20:49,876 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:20:49,877 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:20:51,251 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 58 check-sat command(s) [2018-09-10 10:20:51,252 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:20:51,261 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:20:51,339 INFO L134 CoverageAnalysis]: Checked inductivity of 4902 backedges. 0 proven. 4902 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:51,339 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:20:51,377 INFO L134 CoverageAnalysis]: Checked inductivity of 4902 backedges. 0 proven. 4902 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:51,379 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:20:51,379 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 62, 62, 62, 62] total 122 [2018-09-10 10:20:51,379 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:20:51,379 INFO L459 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-09-10 10:20:51,380 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-09-10 10:20:51,380 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=6913, Invalid=7849, Unknown=0, NotChecked=0, Total=14762 [2018-09-10 10:20:51,381 INFO L87 Difference]: Start difference. First operand 183 states and 183 transitions. Second operand 62 states. [2018-09-10 10:20:51,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:20:51,556 INFO L93 Difference]: Finished difference Result 192 states and 192 transitions. [2018-09-10 10:20:51,556 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-09-10 10:20:51,556 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 182 [2018-09-10 10:20:51,556 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:20:51,557 INFO L225 Difference]: With dead ends: 192 [2018-09-10 10:20:51,557 INFO L226 Difference]: Without dead ends: 187 [2018-09-10 10:20:51,558 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 789 GetRequests, 666 SyntacticMatches, 2 SemanticMatches, 121 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 576 ImplicationChecksByTransitivity, 5.4s TimeCoverageRelationStatistics Valid=6919, Invalid=8087, Unknown=0, NotChecked=0, Total=15006 [2018-09-10 10:20:51,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 187 states. [2018-09-10 10:20:51,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 187 to 186. [2018-09-10 10:20:51,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-09-10 10:20:51,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 186 transitions. [2018-09-10 10:20:51,561 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 186 transitions. Word has length 182 [2018-09-10 10:20:51,561 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:20:51,562 INFO L480 AbstractCegarLoop]: Abstraction has 186 states and 186 transitions. [2018-09-10 10:20:51,562 INFO L481 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-09-10 10:20:51,562 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 186 transitions. [2018-09-10 10:20:51,563 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2018-09-10 10:20:51,563 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:20:51,563 INFO L376 BasicCegarLoop]: trace histogram [59, 58, 58, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:20:51,563 INFO L423 AbstractCegarLoop]: === Iteration 60 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:20:51,563 INFO L82 PathProgramCache]: Analyzing trace with hash 70538608, now seen corresponding path program 58 times [2018-09-10 10:20:51,564 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:20:51,564 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:20:51,564 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:20:51,564 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:20:51,564 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:20:51,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:20:53,381 INFO L134 CoverageAnalysis]: Checked inductivity of 5075 backedges. 0 proven. 5075 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:53,382 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:20:53,382 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 116 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 116 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:20:53,409 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:20:53,410 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:20:53,502 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:20:53,502 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:20:53,506 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:20:53,574 INFO L134 CoverageAnalysis]: Checked inductivity of 5075 backedges. 0 proven. 5075 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:53,575 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:20:57,569 INFO L134 CoverageAnalysis]: Checked inductivity of 5075 backedges. 0 proven. 5075 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:57,590 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:20:57,590 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 117 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 117 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:20:57,605 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:20:57,605 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:20:57,808 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:20:57,808 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:20:57,817 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:20:57,874 INFO L134 CoverageAnalysis]: Checked inductivity of 5075 backedges. 0 proven. 5075 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:57,874 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:20:57,917 INFO L134 CoverageAnalysis]: Checked inductivity of 5075 backedges. 0 proven. 5075 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:20:57,918 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:20:57,919 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [63, 63, 63, 63, 63] total 124 [2018-09-10 10:20:57,919 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:20:57,919 INFO L459 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-09-10 10:20:57,920 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-09-10 10:20:57,920 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=7150, Invalid=8102, Unknown=0, NotChecked=0, Total=15252 [2018-09-10 10:20:57,920 INFO L87 Difference]: Start difference. First operand 186 states and 186 transitions. Second operand 63 states. [2018-09-10 10:20:58,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:20:58,072 INFO L93 Difference]: Finished difference Result 195 states and 195 transitions. [2018-09-10 10:20:58,072 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-09-10 10:20:58,073 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 185 [2018-09-10 10:20:58,073 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:20:58,075 INFO L225 Difference]: With dead ends: 195 [2018-09-10 10:20:58,075 INFO L226 Difference]: Without dead ends: 190 [2018-09-10 10:20:58,076 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 802 GetRequests, 677 SyntacticMatches, 2 SemanticMatches, 123 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 586 ImplicationChecksByTransitivity, 5.7s TimeCoverageRelationStatistics Valid=7156, Invalid=8344, Unknown=0, NotChecked=0, Total=15500 [2018-09-10 10:20:58,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 190 states. [2018-09-10 10:20:58,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 190 to 189. [2018-09-10 10:20:58,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 189 states. [2018-09-10 10:20:58,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 189 states to 189 states and 189 transitions. [2018-09-10 10:20:58,079 INFO L78 Accepts]: Start accepts. Automaton has 189 states and 189 transitions. Word has length 185 [2018-09-10 10:20:58,079 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:20:58,079 INFO L480 AbstractCegarLoop]: Abstraction has 189 states and 189 transitions. [2018-09-10 10:20:58,079 INFO L481 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-09-10 10:20:58,079 INFO L276 IsEmpty]: Start isEmpty. Operand 189 states and 189 transitions. [2018-09-10 10:20:58,080 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 189 [2018-09-10 10:20:58,080 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:20:58,080 INFO L376 BasicCegarLoop]: trace histogram [60, 59, 59, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:20:58,081 INFO L423 AbstractCegarLoop]: === Iteration 61 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:20:58,081 INFO L82 PathProgramCache]: Analyzing trace with hash -271403739, now seen corresponding path program 59 times [2018-09-10 10:20:58,081 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:20:58,081 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:20:58,082 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:20:58,082 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:20:58,082 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:20:58,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:21:00,747 INFO L134 CoverageAnalysis]: Checked inductivity of 5251 backedges. 0 proven. 5251 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:00,748 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:21:00,748 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 118 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 118 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:21:00,758 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:21:00,759 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:21:00,912 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 60 check-sat command(s) [2018-09-10 10:21:00,913 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:21:00,916 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:21:01,000 INFO L134 CoverageAnalysis]: Checked inductivity of 5251 backedges. 0 proven. 5251 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:01,000 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:21:05,361 INFO L134 CoverageAnalysis]: Checked inductivity of 5251 backedges. 0 proven. 5251 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:05,382 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:21:05,382 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 119 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 119 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:21:05,398 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:21:05,398 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:21:06,826 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 60 check-sat command(s) [2018-09-10 10:21:06,826 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:21:06,835 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:21:06,916 INFO L134 CoverageAnalysis]: Checked inductivity of 5251 backedges. 0 proven. 5251 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:06,916 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:21:06,956 INFO L134 CoverageAnalysis]: Checked inductivity of 5251 backedges. 0 proven. 5251 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:06,958 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:21:06,958 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 64, 64, 64, 64] total 126 [2018-09-10 10:21:06,958 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:21:06,958 INFO L459 AbstractCegarLoop]: Interpolant automaton has 64 states [2018-09-10 10:21:06,959 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2018-09-10 10:21:06,959 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=7391, Invalid=8359, Unknown=0, NotChecked=0, Total=15750 [2018-09-10 10:21:06,960 INFO L87 Difference]: Start difference. First operand 189 states and 189 transitions. Second operand 64 states. [2018-09-10 10:21:07,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:21:07,186 INFO L93 Difference]: Finished difference Result 198 states and 198 transitions. [2018-09-10 10:21:07,187 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2018-09-10 10:21:07,187 INFO L78 Accepts]: Start accepts. Automaton has 64 states. Word has length 188 [2018-09-10 10:21:07,187 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:21:07,189 INFO L225 Difference]: With dead ends: 198 [2018-09-10 10:21:07,189 INFO L226 Difference]: Without dead ends: 193 [2018-09-10 10:21:07,190 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 815 GetRequests, 688 SyntacticMatches, 2 SemanticMatches, 125 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 596 ImplicationChecksByTransitivity, 6.9s TimeCoverageRelationStatistics Valid=7397, Invalid=8605, Unknown=0, NotChecked=0, Total=16002 [2018-09-10 10:21:07,190 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 193 states. [2018-09-10 10:21:07,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 193 to 192. [2018-09-10 10:21:07,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 192 states. [2018-09-10 10:21:07,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192 states to 192 states and 192 transitions. [2018-09-10 10:21:07,193 INFO L78 Accepts]: Start accepts. Automaton has 192 states and 192 transitions. Word has length 188 [2018-09-10 10:21:07,193 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:21:07,194 INFO L480 AbstractCegarLoop]: Abstraction has 192 states and 192 transitions. [2018-09-10 10:21:07,194 INFO L481 AbstractCegarLoop]: Interpolant automaton has 64 states. [2018-09-10 10:21:07,194 INFO L276 IsEmpty]: Start isEmpty. Operand 192 states and 192 transitions. [2018-09-10 10:21:07,195 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 192 [2018-09-10 10:21:07,195 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:21:07,195 INFO L376 BasicCegarLoop]: trace histogram [61, 60, 60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:21:07,195 INFO L423 AbstractCegarLoop]: === Iteration 62 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:21:07,195 INFO L82 PathProgramCache]: Analyzing trace with hash 586562896, now seen corresponding path program 60 times [2018-09-10 10:21:07,195 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:21:07,196 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:21:07,196 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:21:07,196 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:21:07,196 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:21:07,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:21:08,643 INFO L134 CoverageAnalysis]: Checked inductivity of 5430 backedges. 0 proven. 5430 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:08,644 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:21:08,644 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 120 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 120 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:21:08,651 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:21:08,651 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:21:08,808 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 61 check-sat command(s) [2018-09-10 10:21:08,809 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:21:08,812 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:21:08,936 INFO L134 CoverageAnalysis]: Checked inductivity of 5430 backedges. 0 proven. 5430 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:08,937 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:21:13,203 INFO L134 CoverageAnalysis]: Checked inductivity of 5430 backedges. 0 proven. 5430 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:13,223 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:21:13,224 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 121 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 121 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:21:13,238 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:21:13,238 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:21:14,719 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 61 check-sat command(s) [2018-09-10 10:21:14,719 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:21:14,728 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:21:14,809 INFO L134 CoverageAnalysis]: Checked inductivity of 5430 backedges. 0 proven. 5430 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:14,809 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:21:14,850 INFO L134 CoverageAnalysis]: Checked inductivity of 5430 backedges. 0 proven. 5430 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:14,851 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:21:14,852 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [65, 65, 65, 65, 65] total 128 [2018-09-10 10:21:14,852 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:21:14,852 INFO L459 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-09-10 10:21:14,853 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-09-10 10:21:14,854 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=7636, Invalid=8620, Unknown=0, NotChecked=0, Total=16256 [2018-09-10 10:21:14,854 INFO L87 Difference]: Start difference. First operand 192 states and 192 transitions. Second operand 65 states. [2018-09-10 10:21:15,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:21:15,002 INFO L93 Difference]: Finished difference Result 201 states and 201 transitions. [2018-09-10 10:21:15,003 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-09-10 10:21:15,003 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 191 [2018-09-10 10:21:15,003 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:21:15,005 INFO L225 Difference]: With dead ends: 201 [2018-09-10 10:21:15,005 INFO L226 Difference]: Without dead ends: 196 [2018-09-10 10:21:15,006 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 828 GetRequests, 699 SyntacticMatches, 2 SemanticMatches, 127 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 606 ImplicationChecksByTransitivity, 5.7s TimeCoverageRelationStatistics Valid=7642, Invalid=8870, Unknown=0, NotChecked=0, Total=16512 [2018-09-10 10:21:15,006 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196 states. [2018-09-10 10:21:15,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196 to 195. [2018-09-10 10:21:15,009 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 195 states. [2018-09-10 10:21:15,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 195 transitions. [2018-09-10 10:21:15,010 INFO L78 Accepts]: Start accepts. Automaton has 195 states and 195 transitions. Word has length 191 [2018-09-10 10:21:15,010 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:21:15,010 INFO L480 AbstractCegarLoop]: Abstraction has 195 states and 195 transitions. [2018-09-10 10:21:15,010 INFO L481 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-09-10 10:21:15,010 INFO L276 IsEmpty]: Start isEmpty. Operand 195 states and 195 transitions. [2018-09-10 10:21:15,011 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 195 [2018-09-10 10:21:15,011 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:21:15,011 INFO L376 BasicCegarLoop]: trace histogram [62, 61, 61, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:21:15,011 INFO L423 AbstractCegarLoop]: === Iteration 63 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:21:15,011 INFO L82 PathProgramCache]: Analyzing trace with hash 920207685, now seen corresponding path program 61 times [2018-09-10 10:21:15,011 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:21:15,012 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:21:15,012 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:21:15,012 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:21:15,012 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:21:15,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:21:16,696 INFO L134 CoverageAnalysis]: Checked inductivity of 5612 backedges. 0 proven. 5612 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:16,696 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:21:16,696 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 122 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 122 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:21:16,704 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:21:16,704 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:21:16,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:21:16,800 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:21:16,886 INFO L134 CoverageAnalysis]: Checked inductivity of 5612 backedges. 0 proven. 5612 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:16,886 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:21:21,520 INFO L134 CoverageAnalysis]: Checked inductivity of 5612 backedges. 0 proven. 5612 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:21,541 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:21:21,541 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 123 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 123 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:21:21,556 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:21:21,556 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:21:21,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:21:21,759 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:21:21,841 INFO L134 CoverageAnalysis]: Checked inductivity of 5612 backedges. 0 proven. 5612 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:21,841 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:21:21,883 INFO L134 CoverageAnalysis]: Checked inductivity of 5612 backedges. 0 proven. 5612 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:21,884 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:21:21,885 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 66, 66, 66, 66] total 130 [2018-09-10 10:21:21,885 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:21:21,885 INFO L459 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-09-10 10:21:21,886 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-09-10 10:21:21,887 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=7885, Invalid=8885, Unknown=0, NotChecked=0, Total=16770 [2018-09-10 10:21:21,887 INFO L87 Difference]: Start difference. First operand 195 states and 195 transitions. Second operand 66 states. [2018-09-10 10:21:22,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:21:22,043 INFO L93 Difference]: Finished difference Result 204 states and 204 transitions. [2018-09-10 10:21:22,044 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 66 states. [2018-09-10 10:21:22,044 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 194 [2018-09-10 10:21:22,044 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:21:22,045 INFO L225 Difference]: With dead ends: 204 [2018-09-10 10:21:22,045 INFO L226 Difference]: Without dead ends: 199 [2018-09-10 10:21:22,045 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 841 GetRequests, 710 SyntacticMatches, 2 SemanticMatches, 129 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 616 ImplicationChecksByTransitivity, 6.2s TimeCoverageRelationStatistics Valid=7891, Invalid=9139, Unknown=0, NotChecked=0, Total=17030 [2018-09-10 10:21:22,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 199 states. [2018-09-10 10:21:22,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 199 to 198. [2018-09-10 10:21:22,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 198 states. [2018-09-10 10:21:22,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198 states to 198 states and 198 transitions. [2018-09-10 10:21:22,050 INFO L78 Accepts]: Start accepts. Automaton has 198 states and 198 transitions. Word has length 194 [2018-09-10 10:21:22,050 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:21:22,050 INFO L480 AbstractCegarLoop]: Abstraction has 198 states and 198 transitions. [2018-09-10 10:21:22,050 INFO L481 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-09-10 10:21:22,050 INFO L276 IsEmpty]: Start isEmpty. Operand 198 states and 198 transitions. [2018-09-10 10:21:22,051 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 198 [2018-09-10 10:21:22,052 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:21:22,052 INFO L376 BasicCegarLoop]: trace histogram [63, 62, 62, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:21:22,052 INFO L423 AbstractCegarLoop]: === Iteration 64 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:21:22,052 INFO L82 PathProgramCache]: Analyzing trace with hash 1977793840, now seen corresponding path program 62 times [2018-09-10 10:21:22,052 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:21:22,053 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:21:22,053 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:21:22,053 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:21:22,053 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:21:22,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:21:23,681 INFO L134 CoverageAnalysis]: Checked inductivity of 5797 backedges. 0 proven. 5797 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:23,681 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:21:23,681 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 124 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 124 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:21:23,688 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:21:23,688 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:21:23,787 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:21:23,787 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:21:23,790 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:21:23,874 INFO L134 CoverageAnalysis]: Checked inductivity of 5797 backedges. 0 proven. 5797 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:23,874 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:21:28,609 INFO L134 CoverageAnalysis]: Checked inductivity of 5797 backedges. 0 proven. 5797 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:28,630 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:21:28,630 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 125 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 125 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:21:28,649 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:21:28,649 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:21:28,873 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:21:28,873 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:21:28,883 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:21:28,982 INFO L134 CoverageAnalysis]: Checked inductivity of 5797 backedges. 0 proven. 5797 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:28,982 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:21:29,027 INFO L134 CoverageAnalysis]: Checked inductivity of 5797 backedges. 0 proven. 5797 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:29,029 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:21:29,029 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [67, 67, 67, 67, 67] total 132 [2018-09-10 10:21:29,029 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:21:29,029 INFO L459 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-09-10 10:21:29,030 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-09-10 10:21:29,030 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=8138, Invalid=9154, Unknown=0, NotChecked=0, Total=17292 [2018-09-10 10:21:29,031 INFO L87 Difference]: Start difference. First operand 198 states and 198 transitions. Second operand 67 states. [2018-09-10 10:21:29,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:21:29,291 INFO L93 Difference]: Finished difference Result 207 states and 207 transitions. [2018-09-10 10:21:29,292 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2018-09-10 10:21:29,292 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 197 [2018-09-10 10:21:29,292 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:21:29,293 INFO L225 Difference]: With dead ends: 207 [2018-09-10 10:21:29,293 INFO L226 Difference]: Without dead ends: 202 [2018-09-10 10:21:29,294 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 854 GetRequests, 721 SyntacticMatches, 2 SemanticMatches, 131 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 626 ImplicationChecksByTransitivity, 6.3s TimeCoverageRelationStatistics Valid=8144, Invalid=9412, Unknown=0, NotChecked=0, Total=17556 [2018-09-10 10:21:29,295 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 202 states. [2018-09-10 10:21:29,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 202 to 201. [2018-09-10 10:21:29,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 201 states. [2018-09-10 10:21:29,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 201 transitions. [2018-09-10 10:21:29,300 INFO L78 Accepts]: Start accepts. Automaton has 201 states and 201 transitions. Word has length 197 [2018-09-10 10:21:29,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:21:29,300 INFO L480 AbstractCegarLoop]: Abstraction has 201 states and 201 transitions. [2018-09-10 10:21:29,300 INFO L481 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-09-10 10:21:29,300 INFO L276 IsEmpty]: Start isEmpty. Operand 201 states and 201 transitions. [2018-09-10 10:21:29,301 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 201 [2018-09-10 10:21:29,301 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:21:29,302 INFO L376 BasicCegarLoop]: trace histogram [64, 63, 63, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:21:29,302 INFO L423 AbstractCegarLoop]: === Iteration 65 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:21:29,302 INFO L82 PathProgramCache]: Analyzing trace with hash 646853989, now seen corresponding path program 63 times [2018-09-10 10:21:29,302 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:21:29,303 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:21:29,303 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:21:29,303 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:21:29,303 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:21:29,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:21:31,103 INFO L134 CoverageAnalysis]: Checked inductivity of 5985 backedges. 0 proven. 5985 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:31,104 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:21:31,104 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 126 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 126 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:21:31,112 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:21:31,112 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:21:31,384 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 64 check-sat command(s) [2018-09-10 10:21:31,384 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:21:31,388 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:21:31,497 INFO L134 CoverageAnalysis]: Checked inductivity of 5985 backedges. 0 proven. 5985 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:31,497 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:21:36,344 INFO L134 CoverageAnalysis]: Checked inductivity of 5985 backedges. 0 proven. 5985 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:36,364 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:21:36,365 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 127 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 127 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:21:36,379 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:21:36,379 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:21:38,019 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 64 check-sat command(s) [2018-09-10 10:21:38,019 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:21:38,028 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:21:38,114 INFO L134 CoverageAnalysis]: Checked inductivity of 5985 backedges. 0 proven. 5985 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:38,115 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:21:38,182 INFO L134 CoverageAnalysis]: Checked inductivity of 5985 backedges. 0 proven. 5985 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:38,183 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:21:38,184 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 68, 68, 68, 68] total 134 [2018-09-10 10:21:38,184 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:21:38,184 INFO L459 AbstractCegarLoop]: Interpolant automaton has 68 states [2018-09-10 10:21:38,185 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2018-09-10 10:21:38,185 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=8395, Invalid=9427, Unknown=0, NotChecked=0, Total=17822 [2018-09-10 10:21:38,185 INFO L87 Difference]: Start difference. First operand 201 states and 201 transitions. Second operand 68 states. [2018-09-10 10:21:38,417 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:21:38,417 INFO L93 Difference]: Finished difference Result 210 states and 210 transitions. [2018-09-10 10:21:38,417 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-09-10 10:21:38,417 INFO L78 Accepts]: Start accepts. Automaton has 68 states. Word has length 200 [2018-09-10 10:21:38,418 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:21:38,418 INFO L225 Difference]: With dead ends: 210 [2018-09-10 10:21:38,418 INFO L226 Difference]: Without dead ends: 205 [2018-09-10 10:21:38,419 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 867 GetRequests, 732 SyntacticMatches, 2 SemanticMatches, 133 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 636 ImplicationChecksByTransitivity, 6.6s TimeCoverageRelationStatistics Valid=8401, Invalid=9689, Unknown=0, NotChecked=0, Total=18090 [2018-09-10 10:21:38,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 205 states. [2018-09-10 10:21:38,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 205 to 204. [2018-09-10 10:21:38,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 204 states. [2018-09-10 10:21:38,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 204 transitions. [2018-09-10 10:21:38,423 INFO L78 Accepts]: Start accepts. Automaton has 204 states and 204 transitions. Word has length 200 [2018-09-10 10:21:38,423 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:21:38,423 INFO L480 AbstractCegarLoop]: Abstraction has 204 states and 204 transitions. [2018-09-10 10:21:38,423 INFO L481 AbstractCegarLoop]: Interpolant automaton has 68 states. [2018-09-10 10:21:38,423 INFO L276 IsEmpty]: Start isEmpty. Operand 204 states and 204 transitions. [2018-09-10 10:21:38,424 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 204 [2018-09-10 10:21:38,424 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:21:38,425 INFO L376 BasicCegarLoop]: trace histogram [65, 64, 64, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:21:38,425 INFO L423 AbstractCegarLoop]: === Iteration 66 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:21:38,425 INFO L82 PathProgramCache]: Analyzing trace with hash 1755829520, now seen corresponding path program 64 times [2018-09-10 10:21:38,425 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:21:38,426 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:21:38,426 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:21:38,426 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:21:38,426 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:21:38,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:21:40,511 INFO L134 CoverageAnalysis]: Checked inductivity of 6176 backedges. 0 proven. 6176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:40,512 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:21:40,512 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 128 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 128 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:21:40,520 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:21:40,520 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:21:40,624 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:21:40,624 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:21:40,627 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:21:40,733 INFO L134 CoverageAnalysis]: Checked inductivity of 6176 backedges. 0 proven. 6176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:40,734 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:21:45,761 INFO L134 CoverageAnalysis]: Checked inductivity of 6176 backedges. 0 proven. 6176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:45,784 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:21:45,784 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 129 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 129 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:21:45,822 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:21:45,822 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:21:46,046 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:21:46,046 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:21:46,056 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:21:46,143 INFO L134 CoverageAnalysis]: Checked inductivity of 6176 backedges. 0 proven. 6176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:46,144 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:21:46,204 INFO L134 CoverageAnalysis]: Checked inductivity of 6176 backedges. 0 proven. 6176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:46,206 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:21:46,206 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [69, 69, 69, 69, 69] total 136 [2018-09-10 10:21:46,206 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:21:46,207 INFO L459 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-09-10 10:21:46,207 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-09-10 10:21:46,207 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=8656, Invalid=9704, Unknown=0, NotChecked=0, Total=18360 [2018-09-10 10:21:46,208 INFO L87 Difference]: Start difference. First operand 204 states and 204 transitions. Second operand 69 states. [2018-09-10 10:21:46,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:21:46,465 INFO L93 Difference]: Finished difference Result 213 states and 213 transitions. [2018-09-10 10:21:46,465 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-09-10 10:21:46,466 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 203 [2018-09-10 10:21:46,466 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:21:46,467 INFO L225 Difference]: With dead ends: 213 [2018-09-10 10:21:46,467 INFO L226 Difference]: Without dead ends: 208 [2018-09-10 10:21:46,468 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 880 GetRequests, 743 SyntacticMatches, 2 SemanticMatches, 135 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 646 ImplicationChecksByTransitivity, 7.0s TimeCoverageRelationStatistics Valid=8662, Invalid=9970, Unknown=0, NotChecked=0, Total=18632 [2018-09-10 10:21:46,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 208 states. [2018-09-10 10:21:46,472 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 208 to 207. [2018-09-10 10:21:46,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2018-09-10 10:21:46,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 207 transitions. [2018-09-10 10:21:46,472 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 207 transitions. Word has length 203 [2018-09-10 10:21:46,472 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:21:46,473 INFO L480 AbstractCegarLoop]: Abstraction has 207 states and 207 transitions. [2018-09-10 10:21:46,473 INFO L481 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-09-10 10:21:46,473 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 207 transitions. [2018-09-10 10:21:46,473 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 207 [2018-09-10 10:21:46,473 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:21:46,474 INFO L376 BasicCegarLoop]: trace histogram [66, 65, 65, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:21:46,474 INFO L423 AbstractCegarLoop]: === Iteration 67 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by_nondet_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:21:46,474 INFO L82 PathProgramCache]: Analyzing trace with hash -1937534587, now seen corresponding path program 65 times [2018-09-10 10:21:46,474 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:21:46,475 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:21:46,475 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:21:46,475 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:21:46,475 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:21:46,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:21:48,267 INFO L134 CoverageAnalysis]: Checked inductivity of 6370 backedges. 0 proven. 6370 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:48,267 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:21:48,267 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 130 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 130 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:21:48,275 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:21:48,276 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:21:48,448 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 66 check-sat command(s) [2018-09-10 10:21:48,448 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:21:48,452 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:21:48,543 INFO L134 CoverageAnalysis]: Checked inductivity of 6370 backedges. 0 proven. 6370 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:21:48,543 INFO L316 TraceCheckSpWp]: Computing backward predicates... Received shutdown request... [2018-09-10 10:21:50,572 INFO L177 TraceCheckSpWp]: Timeout while computing interpolants [2018-09-10 10:21:50,773 WARN L521 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 130 z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:21:50,773 WARN L549 AbstractCegarLoop]: Verification canceled [2018-09-10 10:21:50,779 WARN L206 ceAbstractionStarter]: Timeout [2018-09-10 10:21:50,779 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 10.09 10:21:50 BoogieIcfgContainer [2018-09-10 10:21:50,779 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-09-10 10:21:50,780 INFO L168 Benchmark]: Toolchain (without parser) took 237685.22 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 707.3 MB). Free memory was 1.4 GB in the beginning and 2.1 GB in the end (delta: -686.2 MB). Peak memory consumption was 21.1 MB. Max. memory is 7.1 GB. [2018-09-10 10:21:50,781 INFO L168 Benchmark]: CDTParser took 0.20 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-09-10 10:21:50,781 INFO L168 Benchmark]: CACSL2BoogieTranslator took 279.73 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. [2018-09-10 10:21:50,782 INFO L168 Benchmark]: Boogie Procedure Inliner took 25.17 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-09-10 10:21:50,782 INFO L168 Benchmark]: Boogie Preprocessor took 22.65 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-09-10 10:21:50,782 INFO L168 Benchmark]: RCFGBuilder took 377.23 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 751.3 MB). Free memory was 1.4 GB in the beginning and 2.2 GB in the end (delta: -803.1 MB). Peak memory consumption was 26.6 MB. Max. memory is 7.1 GB. [2018-09-10 10:21:50,783 INFO L168 Benchmark]: TraceAbstraction took 236972.21 ms. Allocated memory was 2.3 GB in the beginning and 2.3 GB in the end (delta: -44.0 MB). Free memory was 2.2 GB in the beginning and 2.1 GB in the end (delta: 106.3 MB). Peak memory consumption was 62.3 MB. Max. memory is 7.1 GB. [2018-09-10 10:21:50,785 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 279.73 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 25.17 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Preprocessor took 22.65 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * RCFGBuilder took 377.23 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 751.3 MB). Free memory was 1.4 GB in the beginning and 2.2 GB in the end (delta: -803.1 MB). Peak memory consumption was 26.6 MB. Max. memory is 7.1 GB. * TraceAbstraction took 236972.21 ms. Allocated memory was 2.3 GB in the beginning and 2.3 GB in the end (delta: -44.0 MB). Free memory was 2.2 GB in the beginning and 2.1 GB in the end (delta: 106.3 MB). Peak memory consumption was 62.3 MB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 5]: Timeout (TraceAbstraction) Unable to prove that call of __VERIFIER_error() unreachable (line 5). Cancelled while BasicCegarLoop was analyzing trace of length 207 with TraceHistMax 66, while TraceCheckSpWp was constructing backward predicates, while PredicateComparison was comparing new predicate (quantifier-free) to 100 known predicates. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 20 locations, 1 error locations. TIMEOUT Result, 236.8s OverallTime, 67 OverallIterations, 66 TraceHistogramMax, 9.4s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 736 SDtfs, 2208 SDslu, 15450 SDs, 0 SdLazy, 3892 SolverSat, 104 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 5.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 30114 GetRequests, 25382 SyntacticMatches, 130 SemanticMatches, 4602 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21170 ImplicationChecksByTransitivity, 181.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=207occurred in iteration=66, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.2s AutomataMinimizationTime, 66 MinimizatonAttempts, 64 StatesRemovedByMinimization, 64 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 1.4s SsaConstructionTime, 27.9s SatisfiabilityAnalysisTime, 189.0s InterpolantComputationTime, 20853 NumberOfCodeBlocks, 20853 NumberOfCodeBlocksAsserted, 2264 NumberOfCheckSat, 34419 ConstructedInterpolants, 0 QuantifiedInterpolants, 13725699 SizeOfPredicates, 258 NumberOfNonLiveVariables, 53120 ConjunctsInSsa, 5048 ConjunctsInUnsatCore, 322 InterpolantComputations, 2 PerfectInterpolantSequences, 0/676000 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/count_by_nondet_true-unreach-call_true-termination.i_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-Benchmark-0-2018-09-10_10-21-50-793.csv Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/count_by_nondet_true-unreach-call_true-termination.i_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-TraceAbstractionBenchmarks-0-2018-09-10_10-21-50-793.csv Completed graceful shutdown