java -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data --generate-csv --csv-dir csv -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml -s ../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf -i ../../../trunk/examples/svcomp/loop-invgen/seq_true-unreach-call_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-3142e50-m [2018-09-10 10:14:20,047 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-09-10 10:14:20,051 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-09-10 10:14:20,065 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-09-10 10:14:20,065 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-09-10 10:14:20,066 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-09-10 10:14:20,067 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-09-10 10:14:20,069 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-09-10 10:14:20,071 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-09-10 10:14:20,072 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-09-10 10:14:20,073 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-09-10 10:14:20,073 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-09-10 10:14:20,074 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-09-10 10:14:20,075 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-09-10 10:14:20,076 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-09-10 10:14:20,077 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-09-10 10:14:20,078 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-09-10 10:14:20,079 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-09-10 10:14:20,081 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-09-10 10:14:20,083 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-09-10 10:14:20,084 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-09-10 10:14:20,085 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-09-10 10:14:20,088 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-09-10 10:14:20,088 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-09-10 10:14:20,088 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-09-10 10:14:20,089 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-09-10 10:14:20,090 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-09-10 10:14:20,091 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-09-10 10:14:20,091 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-09-10 10:14:20,093 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-09-10 10:14:20,093 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-09-10 10:14:20,093 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-09-10 10:14:20,094 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-09-10 10:14:20,094 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-09-10 10:14:20,095 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-09-10 10:14:20,096 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-09-10 10:14:20,096 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf [2018-09-10 10:14:20,125 INFO L110 SettingsManager]: Loading preferences was successful [2018-09-10 10:14:20,127 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-09-10 10:14:20,127 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-09-10 10:14:20,128 INFO L133 SettingsManager]: * User list type=DISABLED [2018-09-10 10:14:20,128 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-09-10 10:14:20,128 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-09-10 10:14:20,128 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-09-10 10:14:20,129 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-09-10 10:14:20,129 INFO L133 SettingsManager]: * Log string format=TERM [2018-09-10 10:14:20,129 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-09-10 10:14:20,129 INFO L133 SettingsManager]: * Interval Domain=false [2018-09-10 10:14:20,130 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-09-10 10:14:20,130 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-09-10 10:14:20,131 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-09-10 10:14:20,131 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-09-10 10:14:20,131 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-09-10 10:14:20,131 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-09-10 10:14:20,131 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-09-10 10:14:20,133 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-09-10 10:14:20,133 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-09-10 10:14:20,133 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-09-10 10:14:20,133 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-09-10 10:14:20,133 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-09-10 10:14:20,134 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-09-10 10:14:20,134 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-09-10 10:14:20,134 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-09-10 10:14:20,134 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-09-10 10:14:20,135 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-09-10 10:14:20,135 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-09-10 10:14:20,135 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-09-10 10:14:20,135 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-09-10 10:14:20,136 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-09-10 10:14:20,136 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-09-10 10:14:20,203 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-09-10 10:14:20,219 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-09-10 10:14:20,226 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-09-10 10:14:20,227 INFO L271 PluginConnector]: Initializing CDTParser... [2018-09-10 10:14:20,228 INFO L276 PluginConnector]: CDTParser initialized [2018-09-10 10:14:20,228 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-invgen/seq_true-unreach-call_true-termination.i [2018-09-10 10:14:20,568 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4761d78b8/8e7fc0798101471ebc7d58cac54012fc/FLAG3ea10faa6 [2018-09-10 10:14:20,729 INFO L276 CDTParser]: Found 1 translation units. [2018-09-10 10:14:20,730 INFO L158 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-invgen/seq_true-unreach-call_true-termination.i [2018-09-10 10:14:20,738 INFO L324 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4761d78b8/8e7fc0798101471ebc7d58cac54012fc/FLAG3ea10faa6 [2018-09-10 10:14:20,756 INFO L332 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4761d78b8/8e7fc0798101471ebc7d58cac54012fc [2018-09-10 10:14:20,765 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-09-10 10:14:20,768 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-09-10 10:14:20,769 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-09-10 10:14:20,769 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-09-10 10:14:20,776 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-09-10 10:14:20,777 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.09 10:14:20" (1/1) ... [2018-09-10 10:14:20,780 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@78e567f7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:14:20, skipping insertion in model container [2018-09-10 10:14:20,781 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.09 10:14:20" (1/1) ... [2018-09-10 10:14:20,985 INFO L180 PRDispatcher]: Starting pre-run dispatcher in SV-COMP mode [2018-09-10 10:14:21,029 INFO L175 PostProcessor]: Settings: Checked method=main [2018-09-10 10:14:21,047 INFO L431 MainDispatcher]: Starting main dispatcher in SV-COMP mode [2018-09-10 10:14:21,059 INFO L175 PostProcessor]: Settings: Checked method=main [2018-09-10 10:14:21,075 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:14:21 WrapperNode [2018-09-10 10:14:21,075 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-09-10 10:14:21,076 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-09-10 10:14:21,076 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-09-10 10:14:21,076 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-09-10 10:14:21,085 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:14:21" (1/1) ... [2018-09-10 10:14:21,092 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:14:21" (1/1) ... [2018-09-10 10:14:21,098 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-09-10 10:14:21,099 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-09-10 10:14:21,099 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-09-10 10:14:21,099 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-09-10 10:14:21,108 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:14:21" (1/1) ... [2018-09-10 10:14:21,109 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:14:21" (1/1) ... [2018-09-10 10:14:21,110 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:14:21" (1/1) ... [2018-09-10 10:14:21,110 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:14:21" (1/1) ... [2018-09-10 10:14:21,112 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:14:21" (1/1) ... [2018-09-10 10:14:21,118 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:14:21" (1/1) ... [2018-09-10 10:14:21,119 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:14:21" (1/1) ... [2018-09-10 10:14:21,121 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-09-10 10:14:21,121 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-09-10 10:14:21,121 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-09-10 10:14:21,122 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-09-10 10:14:21,123 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:14:21" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-09-10 10:14:21,193 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-09-10 10:14:21,194 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-09-10 10:14:21,194 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-09-10 10:14:21,194 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-09-10 10:14:21,194 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-09-10 10:14:21,194 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-09-10 10:14:21,195 INFO L130 BoogieDeclarations]: Found specification of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assert [2018-09-10 10:14:21,195 INFO L138 BoogieDeclarations]: Found implementation of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assert [2018-09-10 10:14:21,619 INFO L353 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-09-10 10:14:21,619 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.09 10:14:21 BoogieIcfgContainer [2018-09-10 10:14:21,620 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-09-10 10:14:21,621 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-09-10 10:14:21,621 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-09-10 10:14:21,631 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-09-10 10:14:21,631 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 10.09 10:14:20" (1/3) ... [2018-09-10 10:14:21,632 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4e1d97cb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 10.09 10:14:21, skipping insertion in model container [2018-09-10 10:14:21,632 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.09 10:14:21" (2/3) ... [2018-09-10 10:14:21,632 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4e1d97cb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 10.09 10:14:21, skipping insertion in model container [2018-09-10 10:14:21,633 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.09 10:14:21" (3/3) ... [2018-09-10 10:14:21,634 INFO L112 eAbstractionObserver]: Analyzing ICFG seq_true-unreach-call_true-termination.i [2018-09-10 10:14:21,643 INFO L137 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-09-10 10:14:21,650 INFO L149 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-09-10 10:14:21,699 INFO L130 ementStrategyFactory]: Using default assertion order modulation [2018-09-10 10:14:21,700 INFO L381 AbstractCegarLoop]: Interprodecural is true [2018-09-10 10:14:21,700 INFO L382 AbstractCegarLoop]: Hoare is true [2018-09-10 10:14:21,701 INFO L383 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-09-10 10:14:21,701 INFO L384 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-09-10 10:14:21,701 INFO L385 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-09-10 10:14:21,701 INFO L386 AbstractCegarLoop]: Difference is false [2018-09-10 10:14:21,701 INFO L387 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-09-10 10:14:21,701 INFO L392 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-09-10 10:14:21,720 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states. [2018-09-10 10:14:21,726 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-09-10 10:14:21,726 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:21,727 INFO L376 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:21,728 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:21,733 INFO L82 PathProgramCache]: Analyzing trace with hash 301890663, now seen corresponding path program 1 times [2018-09-10 10:14:21,736 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:21,788 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:21,789 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:14:21,789 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:21,789 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:21,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:21,860 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:14:21,862 INFO L313 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-09-10 10:14:21,862 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-09-10 10:14:21,862 INFO L265 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-09-10 10:14:21,867 INFO L459 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-09-10 10:14:21,879 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-09-10 10:14:21,880 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-09-10 10:14:21,882 INFO L87 Difference]: Start difference. First operand 27 states. Second operand 2 states. [2018-09-10 10:14:21,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:21,905 INFO L93 Difference]: Finished difference Result 45 states and 58 transitions. [2018-09-10 10:14:21,905 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-09-10 10:14:21,906 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 17 [2018-09-10 10:14:21,907 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:21,916 INFO L225 Difference]: With dead ends: 45 [2018-09-10 10:14:21,916 INFO L226 Difference]: Without dead ends: 23 [2018-09-10 10:14:21,920 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-09-10 10:14:21,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states. [2018-09-10 10:14:21,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 23. [2018-09-10 10:14:21,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23 states. [2018-09-10 10:14:21,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 25 transitions. [2018-09-10 10:14:21,959 INFO L78 Accepts]: Start accepts. Automaton has 23 states and 25 transitions. Word has length 17 [2018-09-10 10:14:21,959 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:21,959 INFO L480 AbstractCegarLoop]: Abstraction has 23 states and 25 transitions. [2018-09-10 10:14:21,960 INFO L481 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-09-10 10:14:21,960 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states and 25 transitions. [2018-09-10 10:14:21,961 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-09-10 10:14:21,961 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:21,961 INFO L376 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:21,961 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:21,962 INFO L82 PathProgramCache]: Analyzing trace with hash 1130037681, now seen corresponding path program 1 times [2018-09-10 10:14:21,962 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:21,963 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:21,963 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:14:21,964 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:21,964 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:21,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:22,239 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:14:22,239 INFO L313 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-09-10 10:14:22,240 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-09-10 10:14:22,240 INFO L265 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-09-10 10:14:22,244 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-09-10 10:14:22,245 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-09-10 10:14:22,245 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-09-10 10:14:22,246 INFO L87 Difference]: Start difference. First operand 23 states and 25 transitions. Second operand 7 states. [2018-09-10 10:14:22,666 WARN L175 SmtUtils]: Spent 118.00 ms on a formula simplification that was a NOOP. DAG size: 14 [2018-09-10 10:14:22,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:22,721 INFO L93 Difference]: Finished difference Result 48 states and 54 transitions. [2018-09-10 10:14:22,721 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-09-10 10:14:22,722 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 19 [2018-09-10 10:14:22,722 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:22,728 INFO L225 Difference]: With dead ends: 48 [2018-09-10 10:14:22,728 INFO L226 Difference]: Without dead ends: 35 [2018-09-10 10:14:22,729 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=39, Invalid=71, Unknown=0, NotChecked=0, Total=110 [2018-09-10 10:14:22,729 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states. [2018-09-10 10:14:22,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 28. [2018-09-10 10:14:22,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28 states. [2018-09-10 10:14:22,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 31 transitions. [2018-09-10 10:14:22,741 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 31 transitions. Word has length 19 [2018-09-10 10:14:22,741 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:22,741 INFO L480 AbstractCegarLoop]: Abstraction has 28 states and 31 transitions. [2018-09-10 10:14:22,741 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-09-10 10:14:22,742 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 31 transitions. [2018-09-10 10:14:22,742 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-09-10 10:14:22,742 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:22,743 INFO L376 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:22,743 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:22,745 INFO L82 PathProgramCache]: Analyzing trace with hash -1499928661, now seen corresponding path program 1 times [2018-09-10 10:14:22,745 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:22,746 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:22,746 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:14:22,746 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:22,746 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:22,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:22,852 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:14:22,852 INFO L313 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-09-10 10:14:22,853 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-09-10 10:14:22,854 INFO L265 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-09-10 10:14:22,855 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-09-10 10:14:22,855 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-09-10 10:14:22,855 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-09-10 10:14:22,856 INFO L87 Difference]: Start difference. First operand 28 states and 31 transitions. Second operand 6 states. [2018-09-10 10:14:22,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:22,937 INFO L93 Difference]: Finished difference Result 42 states and 46 transitions. [2018-09-10 10:14:22,939 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-09-10 10:14:22,939 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 21 [2018-09-10 10:14:22,939 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:22,940 INFO L225 Difference]: With dead ends: 42 [2018-09-10 10:14:22,941 INFO L226 Difference]: Without dead ends: 40 [2018-09-10 10:14:22,942 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-09-10 10:14:22,942 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-09-10 10:14:22,948 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 35. [2018-09-10 10:14:22,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35 states. [2018-09-10 10:14:22,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 38 transitions. [2018-09-10 10:14:22,949 INFO L78 Accepts]: Start accepts. Automaton has 35 states and 38 transitions. Word has length 21 [2018-09-10 10:14:22,950 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:22,950 INFO L480 AbstractCegarLoop]: Abstraction has 35 states and 38 transitions. [2018-09-10 10:14:22,950 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-09-10 10:14:22,950 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 38 transitions. [2018-09-10 10:14:22,951 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-09-10 10:14:22,951 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:22,951 INFO L376 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:22,952 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:22,952 INFO L82 PathProgramCache]: Analyzing trace with hash -1355895601, now seen corresponding path program 1 times [2018-09-10 10:14:22,952 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:22,953 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:22,953 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:14:22,954 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:22,954 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:22,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:23,205 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:14:23,205 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:23,206 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:23,215 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:14:23,215 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:14:23,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:23,242 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:23,687 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:14:23,687 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:23,979 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:14:24,001 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:24,001 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:24,022 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:14:24,023 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:14:24,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:24,048 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:24,059 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:14:24,059 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:24,150 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:14:24,152 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:24,152 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 14 [2018-09-10 10:14:24,152 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:24,153 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-09-10 10:14:24,153 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-09-10 10:14:24,154 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=137, Unknown=0, NotChecked=0, Total=182 [2018-09-10 10:14:24,155 INFO L87 Difference]: Start difference. First operand 35 states and 38 transitions. Second operand 14 states. [2018-09-10 10:14:24,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:24,525 INFO L93 Difference]: Finished difference Result 64 states and 72 transitions. [2018-09-10 10:14:24,525 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-09-10 10:14:24,525 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 29 [2018-09-10 10:14:24,526 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:24,528 INFO L225 Difference]: With dead ends: 64 [2018-09-10 10:14:24,528 INFO L226 Difference]: Without dead ends: 47 [2018-09-10 10:14:24,529 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 129 GetRequests, 99 SyntacticMatches, 12 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 122 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=105, Invalid=275, Unknown=0, NotChecked=0, Total=380 [2018-09-10 10:14:24,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2018-09-10 10:14:24,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 37. [2018-09-10 10:14:24,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2018-09-10 10:14:24,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 40 transitions. [2018-09-10 10:14:24,537 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 40 transitions. Word has length 29 [2018-09-10 10:14:24,537 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:24,538 INFO L480 AbstractCegarLoop]: Abstraction has 37 states and 40 transitions. [2018-09-10 10:14:24,538 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-09-10 10:14:24,538 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 40 transitions. [2018-09-10 10:14:24,539 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-09-10 10:14:24,540 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:24,540 INFO L376 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:24,540 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:24,541 INFO L82 PathProgramCache]: Analyzing trace with hash 95654235, now seen corresponding path program 1 times [2018-09-10 10:14:24,541 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:24,542 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:24,542 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:14:24,542 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:24,542 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:24,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:24,704 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:14:24,704 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:24,704 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-09-10 10:14:24,721 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:14:24,721 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:24,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:24,744 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:24,875 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:14:24,875 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:24,976 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:14:24,996 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:24,996 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:25,013 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:14:25,013 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:14:25,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:25,037 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:25,046 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:14:25,047 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:25,207 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:14:25,210 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:25,210 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 13 [2018-09-10 10:14:25,211 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:25,211 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-09-10 10:14:25,211 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-09-10 10:14:25,211 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=117, Unknown=0, NotChecked=0, Total=156 [2018-09-10 10:14:25,212 INFO L87 Difference]: Start difference. First operand 37 states and 40 transitions. Second operand 13 states. [2018-09-10 10:14:25,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:25,687 INFO L93 Difference]: Finished difference Result 79 states and 91 transitions. [2018-09-10 10:14:25,689 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-09-10 10:14:25,689 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 29 [2018-09-10 10:14:25,690 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:25,691 INFO L225 Difference]: With dead ends: 79 [2018-09-10 10:14:25,691 INFO L226 Difference]: Without dead ends: 62 [2018-09-10 10:14:25,692 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 130 GetRequests, 100 SyntacticMatches, 12 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 103 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=105, Invalid=275, Unknown=0, NotChecked=0, Total=380 [2018-09-10 10:14:25,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2018-09-10 10:14:25,700 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 40. [2018-09-10 10:14:25,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40 states. [2018-09-10 10:14:25,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 44 transitions. [2018-09-10 10:14:25,701 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 44 transitions. Word has length 29 [2018-09-10 10:14:25,701 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:25,702 INFO L480 AbstractCegarLoop]: Abstraction has 40 states and 44 transitions. [2018-09-10 10:14:25,702 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-09-10 10:14:25,702 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 44 transitions. [2018-09-10 10:14:25,703 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-09-10 10:14:25,703 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:25,703 INFO L376 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:25,703 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:25,704 INFO L82 PathProgramCache]: Analyzing trace with hash -446111159, now seen corresponding path program 2 times [2018-09-10 10:14:25,704 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:25,705 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:25,705 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:14:25,705 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:25,705 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:25,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:25,803 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 7 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:14:25,804 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:25,804 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:25,822 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:14:25,823 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:14:25,869 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:14:25,869 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:25,873 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:25,983 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:14:25,985 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:26,030 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:14:26,050 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:26,050 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:26,066 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:14:26,067 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:14:26,093 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:14:26,094 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:26,098 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:26,105 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:14:26,106 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:26,163 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-10 10:14:26,164 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:26,165 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7, 7, 7] total 10 [2018-09-10 10:14:26,165 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:26,165 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-09-10 10:14:26,165 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-09-10 10:14:26,166 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=68, Unknown=0, NotChecked=0, Total=90 [2018-09-10 10:14:26,166 INFO L87 Difference]: Start difference. First operand 40 states and 44 transitions. Second operand 10 states. [2018-09-10 10:14:26,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:26,308 INFO L93 Difference]: Finished difference Result 50 states and 54 transitions. [2018-09-10 10:14:26,309 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-09-10 10:14:26,309 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 31 [2018-09-10 10:14:26,310 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:26,311 INFO L225 Difference]: With dead ends: 50 [2018-09-10 10:14:26,311 INFO L226 Difference]: Without dead ends: 48 [2018-09-10 10:14:26,312 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 135 GetRequests, 117 SyntacticMatches, 8 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=35, Invalid=97, Unknown=0, NotChecked=0, Total=132 [2018-09-10 10:14:26,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states. [2018-09-10 10:14:26,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 48. [2018-09-10 10:14:26,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-09-10 10:14:26,319 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 52 transitions. [2018-09-10 10:14:26,319 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 52 transitions. Word has length 31 [2018-09-10 10:14:26,320 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:26,320 INFO L480 AbstractCegarLoop]: Abstraction has 48 states and 52 transitions. [2018-09-10 10:14:26,320 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-09-10 10:14:26,320 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 52 transitions. [2018-09-10 10:14:26,321 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-09-10 10:14:26,321 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:26,322 INFO L376 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:26,322 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:26,322 INFO L82 PathProgramCache]: Analyzing trace with hash 94447981, now seen corresponding path program 3 times [2018-09-10 10:14:26,322 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:26,323 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:26,323 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:14:26,324 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:26,324 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:26,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:26,455 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-10 10:14:26,455 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:26,455 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:26,473 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:14:26,473 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:14:26,503 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-09-10 10:14:26,504 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:26,507 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:26,735 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-10 10:14:26,736 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:26,830 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-10 10:14:26,851 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:26,851 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:26,866 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:14:26,867 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:14:26,905 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-09-10 10:14:26,905 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:26,910 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:26,923 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-10 10:14:26,923 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:27,021 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-10 10:14:27,023 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:27,023 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 18 [2018-09-10 10:14:27,024 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:27,024 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-09-10 10:14:27,024 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-09-10 10:14:27,025 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=71, Invalid=235, Unknown=0, NotChecked=0, Total=306 [2018-09-10 10:14:27,025 INFO L87 Difference]: Start difference. First operand 48 states and 52 transitions. Second operand 18 states. [2018-09-10 10:14:27,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:27,511 INFO L93 Difference]: Finished difference Result 87 states and 98 transitions. [2018-09-10 10:14:27,511 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-09-10 10:14:27,511 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 39 [2018-09-10 10:14:27,512 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:27,513 INFO L225 Difference]: With dead ends: 87 [2018-09-10 10:14:27,513 INFO L226 Difference]: Without dead ends: 66 [2018-09-10 10:14:27,514 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 173 GetRequests, 133 SyntacticMatches, 16 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 267 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=163, Invalid=487, Unknown=0, NotChecked=0, Total=650 [2018-09-10 10:14:27,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2018-09-10 10:14:27,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 50. [2018-09-10 10:14:27,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-09-10 10:14:27,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2018-09-10 10:14:27,524 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 39 [2018-09-10 10:14:27,524 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:27,524 INFO L480 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2018-09-10 10:14:27,524 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-09-10 10:14:27,525 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2018-09-10 10:14:27,526 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-09-10 10:14:27,526 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:27,526 INFO L376 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:27,526 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:27,527 INFO L82 PathProgramCache]: Analyzing trace with hash 594202361, now seen corresponding path program 1 times [2018-09-10 10:14:27,527 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:27,528 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:27,528 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:14:27,528 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:27,528 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:27,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:27,784 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 14 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-10 10:14:27,784 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:27,784 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:27,792 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:14:27,792 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:14:27,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:27,810 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:27,930 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 14 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-10 10:14:27,930 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:28,101 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 14 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-10 10:14:28,121 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:28,121 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:28,140 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:14:28,140 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:14:28,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:28,169 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:28,178 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 14 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-10 10:14:28,178 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:28,333 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 14 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-10 10:14:28,335 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:28,336 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 17 [2018-09-10 10:14:28,336 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:28,337 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-09-10 10:14:28,337 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-09-10 10:14:28,337 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=210, Unknown=0, NotChecked=0, Total=272 [2018-09-10 10:14:28,338 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 17 states. [2018-09-10 10:14:28,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:28,685 INFO L93 Difference]: Finished difference Result 103 states and 118 transitions. [2018-09-10 10:14:28,686 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-09-10 10:14:28,686 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 39 [2018-09-10 10:14:28,686 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:28,687 INFO L225 Difference]: With dead ends: 103 [2018-09-10 10:14:28,687 INFO L226 Difference]: Without dead ends: 82 [2018-09-10 10:14:28,690 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 175 GetRequests, 134 SyntacticMatches, 16 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 251 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=171, Invalid=531, Unknown=0, NotChecked=0, Total=702 [2018-09-10 10:14:28,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2018-09-10 10:14:28,700 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 50. [2018-09-10 10:14:28,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-09-10 10:14:28,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2018-09-10 10:14:28,701 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 39 [2018-09-10 10:14:28,701 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:28,702 INFO L480 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2018-09-10 10:14:28,702 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-09-10 10:14:28,702 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2018-09-10 10:14:28,703 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-09-10 10:14:28,703 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:28,703 INFO L376 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:28,703 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:28,704 INFO L82 PathProgramCache]: Analyzing trace with hash -1103599739, now seen corresponding path program 2 times [2018-09-10 10:14:28,704 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:28,705 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:28,705 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:14:28,705 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:28,705 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:28,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:28,871 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-10 10:14:28,871 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:28,871 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:28,880 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:14:28,880 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:14:28,893 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:14:28,893 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:28,896 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:29,103 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-10 10:14:29,104 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:29,208 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-10 10:14:29,229 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:29,229 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:29,245 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:14:29,245 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:14:29,278 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:14:29,278 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:29,281 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:29,291 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-10 10:14:29,292 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:29,405 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-10 10:14:29,406 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:29,407 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 16 [2018-09-10 10:14:29,407 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:29,408 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-09-10 10:14:29,408 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-09-10 10:14:29,409 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=183, Unknown=0, NotChecked=0, Total=240 [2018-09-10 10:14:29,409 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 16 states. [2018-09-10 10:14:30,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:30,113 INFO L93 Difference]: Finished difference Result 122 states and 142 transitions. [2018-09-10 10:14:30,115 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-09-10 10:14:30,115 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 39 [2018-09-10 10:14:30,115 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:30,116 INFO L225 Difference]: With dead ends: 122 [2018-09-10 10:14:30,117 INFO L226 Difference]: Without dead ends: 101 [2018-09-10 10:14:30,118 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 175 GetRequests, 135 SyntacticMatches, 16 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 212 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=163, Invalid=487, Unknown=0, NotChecked=0, Total=650 [2018-09-10 10:14:30,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states. [2018-09-10 10:14:30,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 53. [2018-09-10 10:14:30,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53 states. [2018-09-10 10:14:30,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 58 transitions. [2018-09-10 10:14:30,136 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 58 transitions. Word has length 39 [2018-09-10 10:14:30,136 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:30,136 INFO L480 AbstractCegarLoop]: Abstraction has 53 states and 58 transitions. [2018-09-10 10:14:30,136 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-09-10 10:14:30,136 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 58 transitions. [2018-09-10 10:14:30,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-09-10 10:14:30,137 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:30,137 INFO L376 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:30,137 INFO L423 AbstractCegarLoop]: === Iteration 10 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:30,141 INFO L82 PathProgramCache]: Analyzing trace with hash -1990570393, now seen corresponding path program 4 times [2018-09-10 10:14:30,141 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:30,142 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:30,142 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:14:30,142 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:30,142 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:30,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:30,262 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 15 proven. 14 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-10 10:14:30,263 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:30,263 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:30,281 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:14:30,281 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:14:30,303 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:14:30,303 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:30,305 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:30,348 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-10 10:14:30,348 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:30,389 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-10 10:14:30,409 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:30,409 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:30,426 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:14:30,426 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:14:30,462 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:14:30,462 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:30,466 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:30,473 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-10 10:14:30,473 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:30,546 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-10 10:14:30,547 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:30,548 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 8, 8, 8] total 11 [2018-09-10 10:14:30,548 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:30,548 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-09-10 10:14:30,548 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-09-10 10:14:30,548 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2018-09-10 10:14:30,549 INFO L87 Difference]: Start difference. First operand 53 states and 58 transitions. Second operand 11 states. [2018-09-10 10:14:30,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:30,791 INFO L93 Difference]: Finished difference Result 63 states and 68 transitions. [2018-09-10 10:14:30,791 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-09-10 10:14:30,791 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 41 [2018-09-10 10:14:30,792 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:30,793 INFO L225 Difference]: With dead ends: 63 [2018-09-10 10:14:30,793 INFO L226 Difference]: Without dead ends: 61 [2018-09-10 10:14:30,794 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 177 GetRequests, 154 SyntacticMatches, 12 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=40, Invalid=116, Unknown=0, NotChecked=0, Total=156 [2018-09-10 10:14:30,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2018-09-10 10:14:30,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 61. [2018-09-10 10:14:30,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61 states. [2018-09-10 10:14:30,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 66 transitions. [2018-09-10 10:14:30,804 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 66 transitions. Word has length 41 [2018-09-10 10:14:30,804 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:30,804 INFO L480 AbstractCegarLoop]: Abstraction has 61 states and 66 transitions. [2018-09-10 10:14:30,804 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-09-10 10:14:30,804 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 66 transitions. [2018-09-10 10:14:30,805 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-09-10 10:14:30,805 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:30,805 INFO L376 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:30,806 INFO L423 AbstractCegarLoop]: === Iteration 11 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:30,806 INFO L82 PathProgramCache]: Analyzing trace with hash 1735104395, now seen corresponding path program 5 times [2018-09-10 10:14:30,806 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:30,807 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:30,807 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:14:30,807 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:30,807 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:30,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:30,983 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:30,983 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:30,983 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:30,991 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:14:30,991 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:14:31,050 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2018-09-10 10:14:31,051 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:31,053 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:31,608 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:31,608 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:31,680 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:31,703 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:31,703 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:31,721 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:14:31,721 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:14:31,768 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2018-09-10 10:14:31,768 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:31,771 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:31,782 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:31,783 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:31,943 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:31,944 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:31,945 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 22 [2018-09-10 10:14:31,945 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:31,945 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-09-10 10:14:31,945 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-09-10 10:14:31,946 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=103, Invalid=359, Unknown=0, NotChecked=0, Total=462 [2018-09-10 10:14:31,946 INFO L87 Difference]: Start difference. First operand 61 states and 66 transitions. Second operand 22 states. [2018-09-10 10:14:32,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:32,359 INFO L93 Difference]: Finished difference Result 110 states and 124 transitions. [2018-09-10 10:14:32,360 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-09-10 10:14:32,360 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 49 [2018-09-10 10:14:32,360 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:32,361 INFO L225 Difference]: With dead ends: 110 [2018-09-10 10:14:32,361 INFO L226 Difference]: Without dead ends: 85 [2018-09-10 10:14:32,362 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 217 GetRequests, 167 SyntacticMatches, 20 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 467 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=233, Invalid=759, Unknown=0, NotChecked=0, Total=992 [2018-09-10 10:14:32,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-09-10 10:14:32,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 63. [2018-09-10 10:14:32,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-09-10 10:14:32,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 68 transitions. [2018-09-10 10:14:32,373 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 68 transitions. Word has length 49 [2018-09-10 10:14:32,374 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:32,374 INFO L480 AbstractCegarLoop]: Abstraction has 63 states and 68 transitions. [2018-09-10 10:14:32,374 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-09-10 10:14:32,374 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 68 transitions. [2018-09-10 10:14:32,375 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-09-10 10:14:32,375 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:32,375 INFO L376 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:32,375 INFO L423 AbstractCegarLoop]: === Iteration 12 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:32,375 INFO L82 PathProgramCache]: Analyzing trace with hash 1916583447, now seen corresponding path program 2 times [2018-09-10 10:14:32,376 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:32,376 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:32,377 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:14:32,377 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:32,377 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:32,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:32,511 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:32,512 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:32,512 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:32,519 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:14:32,519 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:14:32,536 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:14:32,537 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:32,538 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:32,666 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:32,666 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:32,937 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:32,959 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:32,959 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:32,974 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:14:32,974 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:14:33,010 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:14:33,011 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:33,014 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:33,023 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:33,023 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:33,102 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:33,103 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:33,104 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 21 [2018-09-10 10:14:33,104 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:33,104 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-09-10 10:14:33,104 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-09-10 10:14:33,105 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=329, Unknown=0, NotChecked=0, Total=420 [2018-09-10 10:14:33,105 INFO L87 Difference]: Start difference. First operand 63 states and 68 transitions. Second operand 21 states. [2018-09-10 10:14:33,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:33,512 INFO L93 Difference]: Finished difference Result 132 states and 151 transitions. [2018-09-10 10:14:33,512 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-09-10 10:14:33,512 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 49 [2018-09-10 10:14:33,513 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:33,513 INFO L225 Difference]: With dead ends: 132 [2018-09-10 10:14:33,514 INFO L226 Difference]: Without dead ends: 107 [2018-09-10 10:14:33,515 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 220 GetRequests, 168 SyntacticMatches, 20 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 464 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=253, Invalid=869, Unknown=0, NotChecked=0, Total=1122 [2018-09-10 10:14:33,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-09-10 10:14:33,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 63. [2018-09-10 10:14:33,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-09-10 10:14:33,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 68 transitions. [2018-09-10 10:14:33,528 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 68 transitions. Word has length 49 [2018-09-10 10:14:33,528 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:33,528 INFO L480 AbstractCegarLoop]: Abstraction has 63 states and 68 transitions. [2018-09-10 10:14:33,528 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-09-10 10:14:33,528 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 68 transitions. [2018-09-10 10:14:33,529 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-09-10 10:14:33,529 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:33,529 INFO L376 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:33,530 INFO L423 AbstractCegarLoop]: === Iteration 13 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:33,530 INFO L82 PathProgramCache]: Analyzing trace with hash -402778205, now seen corresponding path program 3 times [2018-09-10 10:14:33,530 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:33,531 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:33,531 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:14:33,531 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:33,531 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:33,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:33,669 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:33,670 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:33,670 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:33,678 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:14:33,679 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:14:33,696 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-09-10 10:14:33,696 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:33,698 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:33,844 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:33,844 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:33,922 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:33,943 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:33,943 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:33,958 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:14:33,958 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:14:34,003 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-09-10 10:14:34,004 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:34,007 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:34,016 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:34,016 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:34,103 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:34,105 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:34,105 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 20 [2018-09-10 10:14:34,105 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:34,105 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-09-10 10:14:34,106 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-09-10 10:14:34,106 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=297, Unknown=0, NotChecked=0, Total=380 [2018-09-10 10:14:34,107 INFO L87 Difference]: Start difference. First operand 63 states and 68 transitions. Second operand 20 states. [2018-09-10 10:14:34,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:34,427 INFO L93 Difference]: Finished difference Result 152 states and 176 transitions. [2018-09-10 10:14:34,435 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-09-10 10:14:34,436 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 49 [2018-09-10 10:14:34,436 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:34,438 INFO L225 Difference]: With dead ends: 152 [2018-09-10 10:14:34,438 INFO L226 Difference]: Without dead ends: 127 [2018-09-10 10:14:34,441 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 221 GetRequests, 169 SyntacticMatches, 20 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 430 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=253, Invalid=869, Unknown=0, NotChecked=0, Total=1122 [2018-09-10 10:14:34,442 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2018-09-10 10:14:34,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 63. [2018-09-10 10:14:34,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-09-10 10:14:34,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 68 transitions. [2018-09-10 10:14:34,467 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 68 transitions. Word has length 49 [2018-09-10 10:14:34,467 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:34,467 INFO L480 AbstractCegarLoop]: Abstraction has 63 states and 68 transitions. [2018-09-10 10:14:34,467 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-09-10 10:14:34,467 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 68 transitions. [2018-09-10 10:14:34,468 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-09-10 10:14:34,470 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:34,470 INFO L376 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:34,470 INFO L423 AbstractCegarLoop]: === Iteration 14 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:34,471 INFO L82 PathProgramCache]: Analyzing trace with hash 488662063, now seen corresponding path program 3 times [2018-09-10 10:14:34,471 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:34,472 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:34,472 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:14:34,472 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:34,473 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:34,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:34,696 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:34,696 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:34,696 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:34,703 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:14:34,703 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:14:34,718 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-09-10 10:14:34,719 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:34,721 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:35,182 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:35,182 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:35,260 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:35,279 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:35,280 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:35,294 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:14:35,294 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:14:35,341 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-09-10 10:14:35,341 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:35,344 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:35,354 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:35,354 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:35,431 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:35,432 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:35,433 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 19 [2018-09-10 10:14:35,433 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:35,433 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-09-10 10:14:35,433 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-09-10 10:14:35,434 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=79, Invalid=263, Unknown=0, NotChecked=0, Total=342 [2018-09-10 10:14:35,434 INFO L87 Difference]: Start difference. First operand 63 states and 68 transitions. Second operand 19 states. [2018-09-10 10:14:35,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:35,984 INFO L93 Difference]: Finished difference Result 175 states and 205 transitions. [2018-09-10 10:14:35,984 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-09-10 10:14:35,984 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 49 [2018-09-10 10:14:35,985 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:35,986 INFO L225 Difference]: With dead ends: 175 [2018-09-10 10:14:35,986 INFO L226 Difference]: Without dead ends: 150 [2018-09-10 10:14:35,987 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 220 GetRequests, 170 SyntacticMatches, 20 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 359 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=233, Invalid=759, Unknown=0, NotChecked=0, Total=992 [2018-09-10 10:14:35,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-09-10 10:14:36,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 66. [2018-09-10 10:14:36,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-09-10 10:14:36,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 72 transitions. [2018-09-10 10:14:36,003 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 72 transitions. Word has length 49 [2018-09-10 10:14:36,003 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:36,003 INFO L480 AbstractCegarLoop]: Abstraction has 66 states and 72 transitions. [2018-09-10 10:14:36,003 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-09-10 10:14:36,003 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 72 transitions. [2018-09-10 10:14:36,004 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-09-10 10:14:36,004 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:36,004 INFO L376 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:36,005 INFO L423 AbstractCegarLoop]: === Iteration 15 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:36,005 INFO L82 PathProgramCache]: Analyzing trace with hash -396473339, now seen corresponding path program 6 times [2018-09-10 10:14:36,005 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:36,006 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:36,006 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:14:36,006 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:36,006 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:36,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:36,104 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 25 proven. 28 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-09-10 10:14:36,104 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:36,104 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:36,112 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:14:36,113 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:14:36,133 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2018-09-10 10:14:36,134 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:36,137 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:36,174 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 26 proven. 21 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:36,175 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:36,271 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 26 proven. 21 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:36,292 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:36,292 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:36,318 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:14:36,319 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:14:36,369 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2018-09-10 10:14:36,370 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:36,373 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:36,378 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 26 proven. 21 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:36,378 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:36,517 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 26 proven. 21 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-10 10:14:36,518 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:36,518 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 9, 9, 9] total 12 [2018-09-10 10:14:36,518 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:36,518 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-09-10 10:14:36,519 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-09-10 10:14:36,519 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=99, Unknown=0, NotChecked=0, Total=132 [2018-09-10 10:14:36,519 INFO L87 Difference]: Start difference. First operand 66 states and 72 transitions. Second operand 12 states. [2018-09-10 10:14:36,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:36,697 INFO L93 Difference]: Finished difference Result 76 states and 82 transitions. [2018-09-10 10:14:36,698 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-09-10 10:14:36,698 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 51 [2018-09-10 10:14:36,698 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:36,699 INFO L225 Difference]: With dead ends: 76 [2018-09-10 10:14:36,699 INFO L226 Difference]: Without dead ends: 74 [2018-09-10 10:14:36,700 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 219 GetRequests, 191 SyntacticMatches, 16 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 62 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=46, Invalid=136, Unknown=0, NotChecked=0, Total=182 [2018-09-10 10:14:36,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states. [2018-09-10 10:14:36,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 74. [2018-09-10 10:14:36,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-09-10 10:14:36,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 80 transitions. [2018-09-10 10:14:36,712 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 80 transitions. Word has length 51 [2018-09-10 10:14:36,713 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:36,713 INFO L480 AbstractCegarLoop]: Abstraction has 74 states and 80 transitions. [2018-09-10 10:14:36,713 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-09-10 10:14:36,713 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 80 transitions. [2018-09-10 10:14:36,714 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-09-10 10:14:36,714 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:36,714 INFO L376 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:36,715 INFO L423 AbstractCegarLoop]: === Iteration 16 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:36,715 INFO L82 PathProgramCache]: Analyzing trace with hash 928978729, now seen corresponding path program 7 times [2018-09-10 10:14:36,715 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:36,716 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:36,716 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:14:36,716 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:36,716 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:36,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:36,953 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:36,953 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:36,953 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:36,962 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:14:36,962 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:14:36,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:36,979 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:37,155 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:37,155 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:37,264 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:37,284 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:37,284 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:37,300 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:14:37,300 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:14:37,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:37,342 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:37,353 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:37,353 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:37,530 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:37,531 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:37,532 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 26 [2018-09-10 10:14:37,532 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:37,532 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-09-10 10:14:37,532 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-09-10 10:14:37,532 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=509, Unknown=0, NotChecked=0, Total=650 [2018-09-10 10:14:37,533 INFO L87 Difference]: Start difference. First operand 74 states and 80 transitions. Second operand 26 states. [2018-09-10 10:14:37,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:37,921 INFO L93 Difference]: Finished difference Result 133 states and 150 transitions. [2018-09-10 10:14:37,921 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-09-10 10:14:37,922 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 59 [2018-09-10 10:14:37,922 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:37,923 INFO L225 Difference]: With dead ends: 133 [2018-09-10 10:14:37,923 INFO L226 Difference]: Without dead ends: 104 [2018-09-10 10:14:37,924 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 261 GetRequests, 201 SyntacticMatches, 24 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 722 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=315, Invalid=1091, Unknown=0, NotChecked=0, Total=1406 [2018-09-10 10:14:37,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states. [2018-09-10 10:14:37,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 76. [2018-09-10 10:14:37,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76 states. [2018-09-10 10:14:37,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 82 transitions. [2018-09-10 10:14:37,937 INFO L78 Accepts]: Start accepts. Automaton has 76 states and 82 transitions. Word has length 59 [2018-09-10 10:14:37,937 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:37,937 INFO L480 AbstractCegarLoop]: Abstraction has 76 states and 82 transitions. [2018-09-10 10:14:37,937 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-09-10 10:14:37,938 INFO L276 IsEmpty]: Start isEmpty. Operand 76 states and 82 transitions. [2018-09-10 10:14:37,938 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-09-10 10:14:37,938 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:37,938 INFO L376 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 4, 4, 4, 4, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:37,939 INFO L423 AbstractCegarLoop]: === Iteration 17 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:37,939 INFO L82 PathProgramCache]: Analyzing trace with hash 277511861, now seen corresponding path program 4 times [2018-09-10 10:14:37,939 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:37,940 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:37,940 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:14:37,940 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:37,940 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:37,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:38,082 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:38,082 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:38,082 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:38,090 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:14:38,091 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:14:38,109 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:14:38,110 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:38,111 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:38,302 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:38,302 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:38,393 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:38,423 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:38,423 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:38,444 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:14:38,445 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:14:38,493 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:14:38,493 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:38,496 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:38,508 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:38,508 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:38,619 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:38,620 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:38,620 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 25 [2018-09-10 10:14:38,620 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:38,621 INFO L459 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-09-10 10:14:38,621 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-09-10 10:14:38,621 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=126, Invalid=474, Unknown=0, NotChecked=0, Total=600 [2018-09-10 10:14:38,622 INFO L87 Difference]: Start difference. First operand 76 states and 82 transitions. Second operand 25 states. [2018-09-10 10:14:39,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:39,236 INFO L93 Difference]: Finished difference Result 161 states and 184 transitions. [2018-09-10 10:14:39,236 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-09-10 10:14:39,236 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 59 [2018-09-10 10:14:39,236 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:39,237 INFO L225 Difference]: With dead ends: 161 [2018-09-10 10:14:39,237 INFO L226 Difference]: Without dead ends: 132 [2018-09-10 10:14:39,238 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 265 GetRequests, 202 SyntacticMatches, 24 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 742 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=351, Invalid=1289, Unknown=0, NotChecked=0, Total=1640 [2018-09-10 10:14:39,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-09-10 10:14:39,256 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 76. [2018-09-10 10:14:39,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76 states. [2018-09-10 10:14:39,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 82 transitions. [2018-09-10 10:14:39,257 INFO L78 Accepts]: Start accepts. Automaton has 76 states and 82 transitions. Word has length 59 [2018-09-10 10:14:39,257 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:39,257 INFO L480 AbstractCegarLoop]: Abstraction has 76 states and 82 transitions. [2018-09-10 10:14:39,257 INFO L481 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-09-10 10:14:39,257 INFO L276 IsEmpty]: Start isEmpty. Operand 76 states and 82 transitions. [2018-09-10 10:14:39,258 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-09-10 10:14:39,258 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:39,258 INFO L376 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 4, 4, 4, 4, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:39,258 INFO L423 AbstractCegarLoop]: === Iteration 18 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:39,258 INFO L82 PathProgramCache]: Analyzing trace with hash -129869503, now seen corresponding path program 5 times [2018-09-10 10:14:39,258 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:39,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:39,259 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:14:39,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:39,259 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:39,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:39,432 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 44 proven. 12 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:39,432 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:39,432 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:39,440 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:14:39,440 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:14:39,463 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2018-09-10 10:14:39,464 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:39,466 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:39,622 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 44 proven. 12 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:39,622 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:39,789 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 44 proven. 12 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:39,809 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:39,809 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:39,823 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:14:39,824 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:14:39,875 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2018-09-10 10:14:39,875 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:39,878 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:39,886 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 44 proven. 12 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:39,886 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:40,046 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 44 proven. 12 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:40,047 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:40,048 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 24 [2018-09-10 10:14:40,048 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:40,048 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-09-10 10:14:40,048 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-09-10 10:14:40,049 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=115, Invalid=437, Unknown=0, NotChecked=0, Total=552 [2018-09-10 10:14:40,049 INFO L87 Difference]: Start difference. First operand 76 states and 82 transitions. Second operand 24 states. [2018-09-10 10:14:40,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:40,529 INFO L93 Difference]: Finished difference Result 187 states and 216 transitions. [2018-09-10 10:14:40,529 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-09-10 10:14:40,529 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 59 [2018-09-10 10:14:40,530 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:40,531 INFO L225 Difference]: With dead ends: 187 [2018-09-10 10:14:40,531 INFO L226 Difference]: Without dead ends: 158 [2018-09-10 10:14:40,532 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 267 GetRequests, 203 SyntacticMatches, 24 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 724 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=364, Invalid=1358, Unknown=0, NotChecked=0, Total=1722 [2018-09-10 10:14:40,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states. [2018-09-10 10:14:40,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 76. [2018-09-10 10:14:40,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76 states. [2018-09-10 10:14:40,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 82 transitions. [2018-09-10 10:14:40,548 INFO L78 Accepts]: Start accepts. Automaton has 76 states and 82 transitions. Word has length 59 [2018-09-10 10:14:40,548 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:40,548 INFO L480 AbstractCegarLoop]: Abstraction has 76 states and 82 transitions. [2018-09-10 10:14:40,548 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-09-10 10:14:40,548 INFO L276 IsEmpty]: Start isEmpty. Operand 76 states and 82 transitions. [2018-09-10 10:14:40,549 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-09-10 10:14:40,549 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:40,549 INFO L376 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 4, 4, 4, 4, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:40,549 INFO L423 AbstractCegarLoop]: === Iteration 19 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:40,550 INFO L82 PathProgramCache]: Analyzing trace with hash -49846579, now seen corresponding path program 6 times [2018-09-10 10:14:40,550 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:40,550 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:40,551 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:14:40,551 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:40,551 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:40,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:40,801 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:40,802 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:40,802 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:40,811 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:14:40,811 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:14:40,838 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2018-09-10 10:14:40,838 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:40,840 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:41,055 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:41,055 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:41,178 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:41,197 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:41,198 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:41,217 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:14:41,218 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:14:41,275 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2018-09-10 10:14:41,276 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:41,279 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:41,292 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:41,292 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:41,490 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:41,491 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:41,492 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 23 [2018-09-10 10:14:41,492 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:41,492 INFO L459 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-09-10 10:14:41,493 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-09-10 10:14:41,493 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=108, Invalid=398, Unknown=0, NotChecked=0, Total=506 [2018-09-10 10:14:41,493 INFO L87 Difference]: Start difference. First operand 76 states and 82 transitions. Second operand 23 states. [2018-09-10 10:14:42,035 WARN L175 SmtUtils]: Spent 144.00 ms on a formula simplification that was a NOOP. DAG size: 13 [2018-09-10 10:14:42,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:42,147 INFO L93 Difference]: Finished difference Result 211 states and 246 transitions. [2018-09-10 10:14:42,147 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-09-10 10:14:42,147 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 59 [2018-09-10 10:14:42,147 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:42,149 INFO L225 Difference]: With dead ends: 211 [2018-09-10 10:14:42,149 INFO L226 Difference]: Without dead ends: 182 [2018-09-10 10:14:42,150 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 267 GetRequests, 204 SyntacticMatches, 24 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 659 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=351, Invalid=1289, Unknown=0, NotChecked=0, Total=1640 [2018-09-10 10:14:42,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states. [2018-09-10 10:14:42,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 76. [2018-09-10 10:14:42,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76 states. [2018-09-10 10:14:42,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 82 transitions. [2018-09-10 10:14:42,172 INFO L78 Accepts]: Start accepts. Automaton has 76 states and 82 transitions. Word has length 59 [2018-09-10 10:14:42,172 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:42,172 INFO L480 AbstractCegarLoop]: Abstraction has 76 states and 82 transitions. [2018-09-10 10:14:42,172 INFO L481 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-09-10 10:14:42,172 INFO L276 IsEmpty]: Start isEmpty. Operand 76 states and 82 transitions. [2018-09-10 10:14:42,173 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-09-10 10:14:42,173 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:42,173 INFO L376 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:42,173 INFO L423 AbstractCegarLoop]: === Iteration 20 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:42,174 INFO L82 PathProgramCache]: Analyzing trace with hash 1451911001, now seen corresponding path program 4 times [2018-09-10 10:14:42,174 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:42,174 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:42,174 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:14:42,175 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:42,175 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:42,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:43,121 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:43,121 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:43,121 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:43,129 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:14:43,130 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:14:43,147 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:14:43,148 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:43,149 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:43,278 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:43,278 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:43,353 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:43,373 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:43,373 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:43,388 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:14:43,388 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:14:43,431 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:14:43,431 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:43,435 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:43,443 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:43,444 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:43,546 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:43,547 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:43,547 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 22 [2018-09-10 10:14:43,547 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:43,548 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-09-10 10:14:43,548 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-09-10 10:14:43,548 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=357, Unknown=0, NotChecked=0, Total=462 [2018-09-10 10:14:43,548 INFO L87 Difference]: Start difference. First operand 76 states and 82 transitions. Second operand 22 states. [2018-09-10 10:14:43,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:43,958 INFO L93 Difference]: Finished difference Result 238 states and 280 transitions. [2018-09-10 10:14:43,958 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-09-10 10:14:43,958 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 59 [2018-09-10 10:14:43,958 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:43,960 INFO L225 Difference]: With dead ends: 238 [2018-09-10 10:14:43,960 INFO L226 Difference]: Without dead ends: 209 [2018-09-10 10:14:43,961 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 265 GetRequests, 205 SyntacticMatches, 24 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 544 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=315, Invalid=1091, Unknown=0, NotChecked=0, Total=1406 [2018-09-10 10:14:43,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 209 states. [2018-09-10 10:14:43,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 209 to 79. [2018-09-10 10:14:43,984 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79 states. [2018-09-10 10:14:43,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 86 transitions. [2018-09-10 10:14:43,984 INFO L78 Accepts]: Start accepts. Automaton has 79 states and 86 transitions. Word has length 59 [2018-09-10 10:14:43,985 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:43,985 INFO L480 AbstractCegarLoop]: Abstraction has 79 states and 86 transitions. [2018-09-10 10:14:43,985 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-09-10 10:14:43,985 INFO L276 IsEmpty]: Start isEmpty. Operand 79 states and 86 transitions. [2018-09-10 10:14:43,985 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-09-10 10:14:43,986 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:43,986 INFO L376 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:43,986 INFO L423 AbstractCegarLoop]: === Iteration 21 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:43,986 INFO L82 PathProgramCache]: Analyzing trace with hash 1954413347, now seen corresponding path program 8 times [2018-09-10 10:14:43,986 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:43,987 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:43,987 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:14:43,987 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:43,987 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:43,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:44,253 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 37 proven. 46 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-09-10 10:14:44,254 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:44,254 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:44,262 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:14:44,262 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:14:44,280 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:14:44,281 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:44,282 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:44,305 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 36 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:44,305 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:44,345 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 36 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:44,365 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:44,366 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:44,381 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:14:44,381 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:14:44,424 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:14:44,425 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:44,428 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:44,435 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 36 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:44,435 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:44,502 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 36 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-10 10:14:44,503 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:44,503 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 10, 10, 10] total 13 [2018-09-10 10:14:44,503 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:44,503 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-09-10 10:14:44,504 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-09-10 10:14:44,504 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=116, Unknown=0, NotChecked=0, Total=156 [2018-09-10 10:14:44,504 INFO L87 Difference]: Start difference. First operand 79 states and 86 transitions. Second operand 13 states. [2018-09-10 10:14:44,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:44,653 INFO L93 Difference]: Finished difference Result 89 states and 96 transitions. [2018-09-10 10:14:44,653 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-09-10 10:14:44,653 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 61 [2018-09-10 10:14:44,654 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:44,655 INFO L225 Difference]: With dead ends: 89 [2018-09-10 10:14:44,655 INFO L226 Difference]: Without dead ends: 87 [2018-09-10 10:14:44,656 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 261 GetRequests, 228 SyntacticMatches, 20 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 87 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=53, Invalid=157, Unknown=0, NotChecked=0, Total=210 [2018-09-10 10:14:44,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2018-09-10 10:14:44,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 87. [2018-09-10 10:14:44,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2018-09-10 10:14:44,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 94 transitions. [2018-09-10 10:14:44,676 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 94 transitions. Word has length 61 [2018-09-10 10:14:44,676 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:44,676 INFO L480 AbstractCegarLoop]: Abstraction has 87 states and 94 transitions. [2018-09-10 10:14:44,676 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-09-10 10:14:44,676 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 94 transitions. [2018-09-10 10:14:44,677 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-09-10 10:14:44,677 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:44,677 INFO L376 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:44,677 INFO L423 AbstractCegarLoop]: === Iteration 22 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:44,677 INFO L82 PathProgramCache]: Analyzing trace with hash 1550108743, now seen corresponding path program 9 times [2018-09-10 10:14:44,678 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:44,678 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:44,678 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:14:44,678 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:44,679 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:44,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:45,065 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:45,065 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:45,065 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:45,073 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:14:45,073 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:14:45,097 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-09-10 10:14:45,097 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:45,099 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:45,499 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:45,500 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:45,598 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:45,618 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:45,618 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:45,633 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:14:45,633 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:14:45,707 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-09-10 10:14:45,707 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:45,710 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:45,723 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:45,723 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:45,846 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:45,847 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:45,847 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 30 [2018-09-10 10:14:45,847 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:45,847 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-09-10 10:14:45,848 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-09-10 10:14:45,848 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=185, Invalid=685, Unknown=0, NotChecked=0, Total=870 [2018-09-10 10:14:45,848 INFO L87 Difference]: Start difference. First operand 87 states and 94 transitions. Second operand 30 states. [2018-09-10 10:14:46,288 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:46,288 INFO L93 Difference]: Finished difference Result 156 states and 176 transitions. [2018-09-10 10:14:46,289 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-09-10 10:14:46,289 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 69 [2018-09-10 10:14:46,290 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:46,291 INFO L225 Difference]: With dead ends: 156 [2018-09-10 10:14:46,291 INFO L226 Difference]: Without dead ends: 123 [2018-09-10 10:14:46,292 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 305 GetRequests, 235 SyntacticMatches, 28 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1032 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=409, Invalid=1483, Unknown=0, NotChecked=0, Total=1892 [2018-09-10 10:14:46,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states. [2018-09-10 10:14:46,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 89. [2018-09-10 10:14:46,313 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-09-10 10:14:46,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 96 transitions. [2018-09-10 10:14:46,314 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 96 transitions. Word has length 69 [2018-09-10 10:14:46,314 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:46,314 INFO L480 AbstractCegarLoop]: Abstraction has 89 states and 96 transitions. [2018-09-10 10:14:46,314 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-09-10 10:14:46,314 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 96 transitions. [2018-09-10 10:14:46,315 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-09-10 10:14:46,315 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:46,315 INFO L376 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 5, 5, 5, 5, 5, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:46,315 INFO L423 AbstractCegarLoop]: === Iteration 23 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:46,316 INFO L82 PathProgramCache]: Analyzing trace with hash 1825386707, now seen corresponding path program 7 times [2018-09-10 10:14:46,316 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:46,316 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:46,316 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:14:46,317 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:46,317 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:46,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:46,519 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:46,520 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:46,520 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:46,527 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:14:46,528 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:14:46,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:46,550 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:47,028 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:47,028 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:47,654 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:47,679 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:47,679 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:47,694 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:14:47,695 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:14:47,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:47,743 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:47,755 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:47,755 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:47,884 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:47,885 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:47,885 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 29 [2018-09-10 10:14:47,886 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:47,886 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-09-10 10:14:47,886 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-09-10 10:14:47,886 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=167, Invalid=645, Unknown=0, NotChecked=0, Total=812 [2018-09-10 10:14:47,887 INFO L87 Difference]: Start difference. First operand 89 states and 96 transitions. Second operand 29 states. [2018-09-10 10:14:48,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:48,406 INFO L93 Difference]: Finished difference Result 190 states and 217 transitions. [2018-09-10 10:14:48,406 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-09-10 10:14:48,406 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 69 [2018-09-10 10:14:48,406 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:48,407 INFO L225 Difference]: With dead ends: 190 [2018-09-10 10:14:48,407 INFO L226 Difference]: Without dead ends: 157 [2018-09-10 10:14:48,408 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 310 GetRequests, 236 SyntacticMatches, 28 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1085 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=465, Invalid=1791, Unknown=0, NotChecked=0, Total=2256 [2018-09-10 10:14:48,409 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-09-10 10:14:48,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 89. [2018-09-10 10:14:48,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-09-10 10:14:48,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 96 transitions. [2018-09-10 10:14:48,433 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 96 transitions. Word has length 69 [2018-09-10 10:14:48,433 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:48,433 INFO L480 AbstractCegarLoop]: Abstraction has 89 states and 96 transitions. [2018-09-10 10:14:48,433 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-09-10 10:14:48,433 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 96 transitions. [2018-09-10 10:14:48,434 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-09-10 10:14:48,434 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:48,434 INFO L376 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 5, 5, 5, 5, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:48,434 INFO L423 AbstractCegarLoop]: === Iteration 24 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:48,434 INFO L82 PathProgramCache]: Analyzing trace with hash -1995551649, now seen corresponding path program 8 times [2018-09-10 10:14:48,435 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:48,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:48,435 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:14:48,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:48,436 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:48,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:48,593 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:48,593 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:48,594 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:48,605 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:14:48,605 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:14:48,624 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:14:48,625 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:48,626 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:48,818 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:48,819 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:48,908 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:48,930 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:48,930 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:48,945 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:14:48,945 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:14:48,994 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:14:48,994 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:48,998 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:49,012 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:49,013 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:49,160 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:49,161 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:49,161 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 28 [2018-09-10 10:14:49,161 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:49,162 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-09-10 10:14:49,162 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-09-10 10:14:49,162 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=603, Unknown=0, NotChecked=0, Total=756 [2018-09-10 10:14:49,162 INFO L87 Difference]: Start difference. First operand 89 states and 96 transitions. Second operand 28 states. [2018-09-10 10:14:49,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:49,671 INFO L93 Difference]: Finished difference Result 222 states and 256 transitions. [2018-09-10 10:14:49,672 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-09-10 10:14:49,672 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 69 [2018-09-10 10:14:49,672 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:49,673 INFO L225 Difference]: With dead ends: 222 [2018-09-10 10:14:49,673 INFO L226 Difference]: Without dead ends: 189 [2018-09-10 10:14:49,674 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 313 GetRequests, 237 SyntacticMatches, 28 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1095 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=496, Invalid=1954, Unknown=0, NotChecked=0, Total=2450 [2018-09-10 10:14:49,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2018-09-10 10:14:49,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 89. [2018-09-10 10:14:49,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-09-10 10:14:49,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 96 transitions. [2018-09-10 10:14:49,707 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 96 transitions. Word has length 69 [2018-09-10 10:14:49,707 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:49,707 INFO L480 AbstractCegarLoop]: Abstraction has 89 states and 96 transitions. [2018-09-10 10:14:49,708 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-09-10 10:14:49,708 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 96 transitions. [2018-09-10 10:14:49,708 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-09-10 10:14:49,708 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:49,709 INFO L376 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 5, 5, 5, 5, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:49,709 INFO L423 AbstractCegarLoop]: === Iteration 25 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:49,709 INFO L82 PathProgramCache]: Analyzing trace with hash 632871659, now seen corresponding path program 9 times [2018-09-10 10:14:49,709 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:49,710 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:49,710 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:14:49,710 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:49,710 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:49,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:49,904 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:49,904 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:49,904 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:49,913 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:14:49,913 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:14:49,937 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-09-10 10:14:49,937 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:49,940 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:50,293 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:50,294 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:50,379 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:50,398 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:50,398 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:50,413 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:14:50,413 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:14:50,496 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-09-10 10:14:50,496 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:50,499 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:50,510 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:50,510 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:50,626 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:50,627 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:50,627 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 27 [2018-09-10 10:14:50,627 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:50,628 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-09-10 10:14:50,628 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-09-10 10:14:50,628 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=143, Invalid=559, Unknown=0, NotChecked=0, Total=702 [2018-09-10 10:14:50,628 INFO L87 Difference]: Start difference. First operand 89 states and 96 transitions. Second operand 27 states. [2018-09-10 10:14:51,528 WARN L175 SmtUtils]: Spent 148.00 ms on a formula simplification that was a NOOP. DAG size: 14 [2018-09-10 10:14:51,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:51,595 INFO L93 Difference]: Finished difference Result 252 states and 293 transitions. [2018-09-10 10:14:51,595 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-09-10 10:14:51,595 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 69 [2018-09-10 10:14:51,596 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:51,597 INFO L225 Difference]: With dead ends: 252 [2018-09-10 10:14:51,597 INFO L226 Difference]: Without dead ends: 219 [2018-09-10 10:14:51,598 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 314 GetRequests, 238 SyntacticMatches, 28 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1048 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=496, Invalid=1954, Unknown=0, NotChecked=0, Total=2450 [2018-09-10 10:14:51,598 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219 states. [2018-09-10 10:14:51,632 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219 to 89. [2018-09-10 10:14:51,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-09-10 10:14:51,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 96 transitions. [2018-09-10 10:14:51,634 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 96 transitions. Word has length 69 [2018-09-10 10:14:51,634 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:51,634 INFO L480 AbstractCegarLoop]: Abstraction has 89 states and 96 transitions. [2018-09-10 10:14:51,634 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-09-10 10:14:51,634 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 96 transitions. [2018-09-10 10:14:51,635 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-09-10 10:14:51,635 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:51,635 INFO L376 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 5, 5, 5, 5, 5, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:51,636 INFO L423 AbstractCegarLoop]: === Iteration 26 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:51,636 INFO L82 PathProgramCache]: Analyzing trace with hash 613260407, now seen corresponding path program 10 times [2018-09-10 10:14:51,636 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:51,636 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:51,637 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:14:51,637 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:51,637 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:51,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:51,888 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:51,889 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:51,889 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:51,897 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:14:51,897 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:14:51,917 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:14:51,918 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:51,919 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:52,186 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:52,187 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:52,271 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:52,292 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:52,292 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:52,308 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:14:52,308 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:14:52,363 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:14:52,363 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:52,367 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:52,380 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:52,380 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:52,516 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:52,518 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:52,518 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 26 [2018-09-10 10:14:52,518 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:52,518 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-09-10 10:14:52,519 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-09-10 10:14:52,519 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=137, Invalid=513, Unknown=0, NotChecked=0, Total=650 [2018-09-10 10:14:52,519 INFO L87 Difference]: Start difference. First operand 89 states and 96 transitions. Second operand 26 states. [2018-09-10 10:14:53,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:53,065 INFO L93 Difference]: Finished difference Result 280 states and 328 transitions. [2018-09-10 10:14:53,065 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-09-10 10:14:53,065 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 69 [2018-09-10 10:14:53,066 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:53,067 INFO L225 Difference]: With dead ends: 280 [2018-09-10 10:14:53,067 INFO L226 Difference]: Without dead ends: 247 [2018-09-10 10:14:53,068 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 313 GetRequests, 239 SyntacticMatches, 28 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 938 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=465, Invalid=1791, Unknown=0, NotChecked=0, Total=2256 [2018-09-10 10:14:53,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 247 states. [2018-09-10 10:14:53,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 247 to 89. [2018-09-10 10:14:53,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-09-10 10:14:53,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 96 transitions. [2018-09-10 10:14:53,099 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 96 transitions. Word has length 69 [2018-09-10 10:14:53,099 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:53,099 INFO L480 AbstractCegarLoop]: Abstraction has 89 states and 96 transitions. [2018-09-10 10:14:53,100 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-09-10 10:14:53,100 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 96 transitions. [2018-09-10 10:14:53,100 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-09-10 10:14:53,100 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:53,100 INFO L376 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:53,101 INFO L423 AbstractCegarLoop]: === Iteration 27 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:53,101 INFO L82 PathProgramCache]: Analyzing trace with hash 1618825475, now seen corresponding path program 5 times [2018-09-10 10:14:53,101 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:53,101 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:53,101 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:14:53,102 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:53,102 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:53,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:53,308 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:53,308 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:53,308 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:53,315 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:14:53,315 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:14:53,343 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-09-10 10:14:53,343 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:53,346 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:53,680 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:53,681 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:53,791 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:53,811 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:53,811 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:53,839 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:14:53,839 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:14:53,910 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-09-10 10:14:53,910 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:53,913 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:53,923 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:53,924 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:54,027 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:54,028 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:54,028 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 25 [2018-09-10 10:14:54,029 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:54,029 INFO L459 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-09-10 10:14:54,029 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-09-10 10:14:54,029 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=135, Invalid=465, Unknown=0, NotChecked=0, Total=600 [2018-09-10 10:14:54,030 INFO L87 Difference]: Start difference. First operand 89 states and 96 transitions. Second operand 25 states. [2018-09-10 10:14:54,663 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:54,663 INFO L93 Difference]: Finished difference Result 311 states and 367 transitions. [2018-09-10 10:14:54,664 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-09-10 10:14:54,664 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 69 [2018-09-10 10:14:54,664 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:54,665 INFO L225 Difference]: With dead ends: 311 [2018-09-10 10:14:54,665 INFO L226 Difference]: Without dead ends: 278 [2018-09-10 10:14:54,666 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 310 GetRequests, 240 SyntacticMatches, 28 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 767 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=409, Invalid=1483, Unknown=0, NotChecked=0, Total=1892 [2018-09-10 10:14:54,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 278 states. [2018-09-10 10:14:54,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 278 to 92. [2018-09-10 10:14:54,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2018-09-10 10:14:54,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 100 transitions. [2018-09-10 10:14:54,697 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 100 transitions. Word has length 69 [2018-09-10 10:14:54,697 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:54,697 INFO L480 AbstractCegarLoop]: Abstraction has 92 states and 100 transitions. [2018-09-10 10:14:54,697 INFO L481 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-09-10 10:14:54,697 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 100 transitions. [2018-09-10 10:14:54,698 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-09-10 10:14:54,698 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:54,698 INFO L376 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 6, 6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:54,698 INFO L423 AbstractCegarLoop]: === Iteration 28 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:54,699 INFO L82 PathProgramCache]: Analyzing trace with hash 2111470529, now seen corresponding path program 10 times [2018-09-10 10:14:54,699 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:54,699 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:54,699 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:14:54,700 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:54,700 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:54,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:55,782 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 51 proven. 68 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-09-10 10:14:55,783 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:55,783 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:55,797 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:14:55,798 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:14:55,843 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:14:55,844 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:55,846 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:56,078 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 52 proven. 55 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:56,078 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:56,140 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 52 proven. 55 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:56,162 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:56,162 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:56,176 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:14:56,177 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:14:56,232 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:14:56,232 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:56,236 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:56,245 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 52 proven. 55 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:56,245 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:56,344 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 52 proven. 55 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-10 10:14:56,345 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:56,345 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11, 11, 11, 11] total 14 [2018-09-10 10:14:56,345 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:56,345 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-09-10 10:14:56,346 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-09-10 10:14:56,346 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=134, Unknown=0, NotChecked=0, Total=182 [2018-09-10 10:14:56,346 INFO L87 Difference]: Start difference. First operand 92 states and 100 transitions. Second operand 14 states. [2018-09-10 10:14:57,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:57,134 INFO L93 Difference]: Finished difference Result 102 states and 110 transitions. [2018-09-10 10:14:57,135 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-09-10 10:14:57,135 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 71 [2018-09-10 10:14:57,135 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:57,136 INFO L225 Difference]: With dead ends: 102 [2018-09-10 10:14:57,136 INFO L226 Difference]: Without dead ends: 100 [2018-09-10 10:14:57,136 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 303 GetRequests, 265 SyntacticMatches, 24 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 116 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=61, Invalid=179, Unknown=0, NotChecked=0, Total=240 [2018-09-10 10:14:57,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states. [2018-09-10 10:14:57,173 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 100. [2018-09-10 10:14:57,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 100 states. [2018-09-10 10:14:57,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 108 transitions. [2018-09-10 10:14:57,173 INFO L78 Accepts]: Start accepts. Automaton has 100 states and 108 transitions. Word has length 71 [2018-09-10 10:14:57,174 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:57,174 INFO L480 AbstractCegarLoop]: Abstraction has 100 states and 108 transitions. [2018-09-10 10:14:57,174 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-09-10 10:14:57,174 INFO L276 IsEmpty]: Start isEmpty. Operand 100 states and 108 transitions. [2018-09-10 10:14:57,174 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-09-10 10:14:57,175 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:57,175 INFO L376 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:57,175 INFO L423 AbstractCegarLoop]: === Iteration 29 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:57,175 INFO L82 PathProgramCache]: Analyzing trace with hash 58575589, now seen corresponding path program 11 times [2018-09-10 10:14:57,175 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:57,176 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:57,176 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:14:57,176 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:57,176 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:57,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:14:57,385 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:14:57,386 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:57,386 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:14:57,394 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:14:57,395 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:14:57,424 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-09-10 10:14:57,424 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:57,427 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:58,737 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:14:58,737 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:58,861 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:14:58,882 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:14:58,882 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:14:58,897 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:14:58,898 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:14:58,988 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-09-10 10:14:58,988 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:14:58,992 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:14:59,015 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:14:59,015 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:14:59,152 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:14:59,153 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:14:59,154 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 34 [2018-09-10 10:14:59,154 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:14:59,154 INFO L459 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-09-10 10:14:59,154 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-09-10 10:14:59,155 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=235, Invalid=887, Unknown=0, NotChecked=0, Total=1122 [2018-09-10 10:14:59,155 INFO L87 Difference]: Start difference. First operand 100 states and 108 transitions. Second operand 34 states. [2018-09-10 10:14:59,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:14:59,850 INFO L93 Difference]: Finished difference Result 179 states and 202 transitions. [2018-09-10 10:14:59,850 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-09-10 10:14:59,850 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 79 [2018-09-10 10:14:59,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:14:59,851 INFO L225 Difference]: With dead ends: 179 [2018-09-10 10:14:59,851 INFO L226 Difference]: Without dead ends: 142 [2018-09-10 10:14:59,852 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 349 GetRequests, 269 SyntacticMatches, 32 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1397 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=515, Invalid=1935, Unknown=0, NotChecked=0, Total=2450 [2018-09-10 10:14:59,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2018-09-10 10:14:59,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 102. [2018-09-10 10:14:59,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-09-10 10:14:59,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 110 transitions. [2018-09-10 10:14:59,886 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 110 transitions. Word has length 79 [2018-09-10 10:14:59,886 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:14:59,886 INFO L480 AbstractCegarLoop]: Abstraction has 102 states and 110 transitions. [2018-09-10 10:14:59,887 INFO L481 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-09-10 10:14:59,887 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 110 transitions. [2018-09-10 10:14:59,887 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-09-10 10:14:59,887 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:14:59,888 INFO L376 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 6, 6, 6, 6, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:14:59,888 INFO L423 AbstractCegarLoop]: === Iteration 30 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:14:59,888 INFO L82 PathProgramCache]: Analyzing trace with hash 127267953, now seen corresponding path program 11 times [2018-09-10 10:14:59,888 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:14:59,889 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:59,889 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:14:59,889 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:14:59,889 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:14:59,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:00,372 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:00,372 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:00,373 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:15:00,379 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:15:00,379 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:15:00,495 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-09-10 10:15:00,496 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:00,498 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:00,810 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:00,810 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:00,924 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:00,944 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:00,944 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:15:00,959 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:15:00,959 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:15:01,042 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-09-10 10:15:01,042 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:01,046 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:01,061 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:01,062 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:01,237 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:01,238 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:15:01,238 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 33 [2018-09-10 10:15:01,238 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:15:01,238 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-09-10 10:15:01,239 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-09-10 10:15:01,239 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=214, Invalid=842, Unknown=0, NotChecked=0, Total=1056 [2018-09-10 10:15:01,239 INFO L87 Difference]: Start difference. First operand 102 states and 110 transitions. Second operand 33 states. [2018-09-10 10:15:01,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:15:01,935 INFO L93 Difference]: Finished difference Result 219 states and 250 transitions. [2018-09-10 10:15:01,936 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-09-10 10:15:01,936 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 79 [2018-09-10 10:15:01,936 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:15:01,937 INFO L225 Difference]: With dead ends: 219 [2018-09-10 10:15:01,937 INFO L226 Difference]: Without dead ends: 182 [2018-09-10 10:15:01,939 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 355 GetRequests, 270 SyntacticMatches, 32 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1493 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=595, Invalid=2375, Unknown=0, NotChecked=0, Total=2970 [2018-09-10 10:15:01,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states. [2018-09-10 10:15:01,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 102. [2018-09-10 10:15:01,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-09-10 10:15:01,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 110 transitions. [2018-09-10 10:15:01,998 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 110 transitions. Word has length 79 [2018-09-10 10:15:01,998 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:15:01,998 INFO L480 AbstractCegarLoop]: Abstraction has 102 states and 110 transitions. [2018-09-10 10:15:01,998 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-09-10 10:15:01,998 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 110 transitions. [2018-09-10 10:15:01,999 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-09-10 10:15:01,999 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:15:01,999 INFO L376 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 6, 6, 6, 6, 5, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:15:02,000 INFO L423 AbstractCegarLoop]: === Iteration 31 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:15:02,000 INFO L82 PathProgramCache]: Analyzing trace with hash 310579453, now seen corresponding path program 12 times [2018-09-10 10:15:02,000 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:15:02,001 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:02,001 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:15:02,001 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:02,001 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:15:02,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:02,250 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:02,250 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:02,250 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:15:02,258 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:15:02,258 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:15:02,286 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-09-10 10:15:02,286 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:02,288 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:02,587 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:02,587 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:02,698 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:02,718 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:02,718 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:15:02,733 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:15:02,733 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:15:02,819 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-09-10 10:15:02,819 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:02,823 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:02,835 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:02,836 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:03,338 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:03,339 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:15:03,340 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 32 [2018-09-10 10:15:03,340 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:15:03,340 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-09-10 10:15:03,340 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-09-10 10:15:03,341 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=197, Invalid=795, Unknown=0, NotChecked=0, Total=992 [2018-09-10 10:15:03,341 INFO L87 Difference]: Start difference. First operand 102 states and 110 transitions. Second operand 32 states. [2018-09-10 10:15:04,752 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:15:04,753 INFO L93 Difference]: Finished difference Result 257 states and 296 transitions. [2018-09-10 10:15:04,753 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-09-10 10:15:04,753 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 79 [2018-09-10 10:15:04,753 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:15:04,755 INFO L225 Difference]: With dead ends: 257 [2018-09-10 10:15:04,755 INFO L226 Difference]: Without dead ends: 220 [2018-09-10 10:15:04,757 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 359 GetRequests, 271 SyntacticMatches, 32 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1543 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=649, Invalid=2657, Unknown=0, NotChecked=0, Total=3306 [2018-09-10 10:15:04,757 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 220 states. [2018-09-10 10:15:04,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 220 to 102. [2018-09-10 10:15:04,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-09-10 10:15:04,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 110 transitions. [2018-09-10 10:15:04,823 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 110 transitions. Word has length 79 [2018-09-10 10:15:04,823 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:15:04,823 INFO L480 AbstractCegarLoop]: Abstraction has 102 states and 110 transitions. [2018-09-10 10:15:04,824 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-09-10 10:15:04,824 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 110 transitions. [2018-09-10 10:15:04,824 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-09-10 10:15:04,824 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:15:04,824 INFO L376 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 6, 6, 6, 6, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:15:04,825 INFO L423 AbstractCegarLoop]: === Iteration 32 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:15:04,825 INFO L82 PathProgramCache]: Analyzing trace with hash -1427775351, now seen corresponding path program 13 times [2018-09-10 10:15:04,825 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:15:04,826 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:04,826 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:15:04,826 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:04,826 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:15:04,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:05,488 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 90 proven. 24 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:05,488 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:05,488 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:15:05,498 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:15:05,499 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:15:05,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:05,523 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:05,782 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 90 proven. 24 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:05,782 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:05,948 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 90 proven. 24 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:05,968 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:05,968 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:15:05,982 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:15:05,983 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:15:06,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:06,037 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:06,049 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 90 proven. 24 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:06,049 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:06,219 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 90 proven. 24 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:06,220 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:15:06,221 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 31 [2018-09-10 10:15:06,221 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:15:06,221 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-09-10 10:15:06,222 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-09-10 10:15:06,222 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=184, Invalid=746, Unknown=0, NotChecked=0, Total=930 [2018-09-10 10:15:06,222 INFO L87 Difference]: Start difference. First operand 102 states and 110 transitions. Second operand 31 states. [2018-09-10 10:15:06,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:15:06,985 INFO L93 Difference]: Finished difference Result 293 states and 340 transitions. [2018-09-10 10:15:06,985 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-09-10 10:15:06,985 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 79 [2018-09-10 10:15:06,985 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:15:06,987 INFO L225 Difference]: With dead ends: 293 [2018-09-10 10:15:06,987 INFO L226 Difference]: Without dead ends: 256 [2018-09-10 10:15:06,988 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 361 GetRequests, 272 SyntacticMatches, 32 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1527 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=668, Invalid=2754, Unknown=0, NotChecked=0, Total=3422 [2018-09-10 10:15:06,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states. [2018-09-10 10:15:07,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 102. [2018-09-10 10:15:07,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-09-10 10:15:07,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 110 transitions. [2018-09-10 10:15:07,032 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 110 transitions. Word has length 79 [2018-09-10 10:15:07,032 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:15:07,032 INFO L480 AbstractCegarLoop]: Abstraction has 102 states and 110 transitions. [2018-09-10 10:15:07,032 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-09-10 10:15:07,032 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 110 transitions. [2018-09-10 10:15:07,033 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-09-10 10:15:07,033 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:15:07,033 INFO L376 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 6, 6, 6, 6, 5, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:15:07,033 INFO L423 AbstractCegarLoop]: === Iteration 33 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:15:07,033 INFO L82 PathProgramCache]: Analyzing trace with hash 143598357, now seen corresponding path program 14 times [2018-09-10 10:15:07,033 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:15:07,034 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:07,034 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:15:07,034 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:07,034 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:15:07,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:07,478 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:07,478 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:07,478 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:15:07,487 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:15:07,487 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:15:07,510 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:15:07,510 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:07,511 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:07,819 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:07,819 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:07,929 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:07,948 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:07,948 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:15:07,963 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:15:07,963 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:15:08,017 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:15:08,018 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:08,021 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:08,039 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:08,039 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:08,169 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:08,170 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:15:08,170 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 30 [2018-09-10 10:15:08,170 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:15:08,170 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-09-10 10:15:08,171 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-09-10 10:15:08,171 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=175, Invalid=695, Unknown=0, NotChecked=0, Total=870 [2018-09-10 10:15:08,171 INFO L87 Difference]: Start difference. First operand 102 states and 110 transitions. Second operand 30 states. [2018-09-10 10:15:09,069 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:15:09,069 INFO L93 Difference]: Finished difference Result 327 states and 382 transitions. [2018-09-10 10:15:09,070 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-09-10 10:15:09,070 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 79 [2018-09-10 10:15:09,070 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:15:09,071 INFO L225 Difference]: With dead ends: 327 [2018-09-10 10:15:09,072 INFO L226 Difference]: Without dead ends: 290 [2018-09-10 10:15:09,073 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 361 GetRequests, 273 SyntacticMatches, 32 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1436 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=649, Invalid=2657, Unknown=0, NotChecked=0, Total=3306 [2018-09-10 10:15:09,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 290 states. [2018-09-10 10:15:09,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 290 to 102. [2018-09-10 10:15:09,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-09-10 10:15:09,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 110 transitions. [2018-09-10 10:15:09,154 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 110 transitions. Word has length 79 [2018-09-10 10:15:09,154 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:15:09,154 INFO L480 AbstractCegarLoop]: Abstraction has 102 states and 110 transitions. [2018-09-10 10:15:09,154 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-09-10 10:15:09,154 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 110 transitions. [2018-09-10 10:15:09,154 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-09-10 10:15:09,155 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:15:09,155 INFO L376 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 6, 6, 6, 6, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:15:09,155 INFO L423 AbstractCegarLoop]: === Iteration 34 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:15:09,155 INFO L82 PathProgramCache]: Analyzing trace with hash -1602250591, now seen corresponding path program 15 times [2018-09-10 10:15:09,155 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:15:09,156 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:09,156 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:15:09,156 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:09,156 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:15:09,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:09,387 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:09,387 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:09,387 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:15:09,396 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:15:09,396 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:15:09,490 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2018-09-10 10:15:09,491 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:09,493 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:09,791 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:09,792 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:09,908 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:09,928 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:09,928 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:15:09,943 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:15:09,943 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:15:10,034 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2018-09-10 10:15:10,034 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:10,038 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:10,053 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:10,054 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:10,322 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:10,323 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:15:10,324 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 29 [2018-09-10 10:15:10,324 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:15:10,324 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-09-10 10:15:10,324 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-09-10 10:15:10,325 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=170, Invalid=642, Unknown=0, NotChecked=0, Total=812 [2018-09-10 10:15:10,325 INFO L87 Difference]: Start difference. First operand 102 states and 110 transitions. Second operand 29 states. [2018-09-10 10:15:11,051 WARN L175 SmtUtils]: Spent 102.00 ms on a formula simplification that was a NOOP. DAG size: 10 [2018-09-10 10:15:11,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:15:11,753 INFO L93 Difference]: Finished difference Result 359 states and 422 transitions. [2018-09-10 10:15:11,753 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-09-10 10:15:11,753 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 79 [2018-09-10 10:15:11,754 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:15:11,755 INFO L225 Difference]: With dead ends: 359 [2018-09-10 10:15:11,756 INFO L226 Difference]: Without dead ends: 322 [2018-09-10 10:15:11,757 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 359 GetRequests, 274 SyntacticMatches, 32 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1267 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=595, Invalid=2375, Unknown=0, NotChecked=0, Total=2970 [2018-09-10 10:15:11,757 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 322 states. [2018-09-10 10:15:11,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 322 to 102. [2018-09-10 10:15:11,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-09-10 10:15:11,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 110 transitions. [2018-09-10 10:15:11,823 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 110 transitions. Word has length 79 [2018-09-10 10:15:11,823 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:15:11,824 INFO L480 AbstractCegarLoop]: Abstraction has 102 states and 110 transitions. [2018-09-10 10:15:11,824 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-09-10 10:15:11,824 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 110 transitions. [2018-09-10 10:15:11,824 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-09-10 10:15:11,824 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:15:11,825 INFO L376 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:15:11,825 INFO L423 AbstractCegarLoop]: === Iteration 35 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:15:11,825 INFO L82 PathProgramCache]: Analyzing trace with hash -1326972627, now seen corresponding path program 6 times [2018-09-10 10:15:11,825 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:15:11,826 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:11,826 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:15:11,826 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:11,826 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:15:11,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:12,577 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:12,577 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:12,577 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:15:12,586 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:15:12,586 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:15:12,616 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-09-10 10:15:12,617 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:12,619 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:12,823 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:12,824 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:12,933 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:12,952 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:12,952 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:15:12,968 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:15:12,968 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:15:13,052 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-09-10 10:15:13,052 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:13,056 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:13,067 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:13,067 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:13,202 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:13,203 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:15:13,203 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 28 [2018-09-10 10:15:13,203 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:15:13,203 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-09-10 10:15:13,204 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-09-10 10:15:13,204 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=169, Invalid=587, Unknown=0, NotChecked=0, Total=756 [2018-09-10 10:15:13,204 INFO L87 Difference]: Start difference. First operand 102 states and 110 transitions. Second operand 28 states. [2018-09-10 10:15:14,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:15:14,003 INFO L93 Difference]: Finished difference Result 394 states and 466 transitions. [2018-09-10 10:15:14,003 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-09-10 10:15:14,003 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 79 [2018-09-10 10:15:14,003 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:15:14,005 INFO L225 Difference]: With dead ends: 394 [2018-09-10 10:15:14,005 INFO L226 Difference]: Without dead ends: 357 [2018-09-10 10:15:14,006 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 355 GetRequests, 275 SyntacticMatches, 32 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1028 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=515, Invalid=1935, Unknown=0, NotChecked=0, Total=2450 [2018-09-10 10:15:14,006 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 357 states. [2018-09-10 10:15:14,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 357 to 105. [2018-09-10 10:15:14,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-09-10 10:15:14,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 114 transitions. [2018-09-10 10:15:14,062 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 114 transitions. Word has length 79 [2018-09-10 10:15:14,062 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:15:14,062 INFO L480 AbstractCegarLoop]: Abstraction has 105 states and 114 transitions. [2018-09-10 10:15:14,062 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-09-10 10:15:14,062 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 114 transitions. [2018-09-10 10:15:14,062 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-09-10 10:15:14,063 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:15:14,063 INFO L376 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:15:14,063 INFO L423 AbstractCegarLoop]: === Iteration 36 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:15:14,063 INFO L82 PathProgramCache]: Analyzing trace with hash 1957490143, now seen corresponding path program 12 times [2018-09-10 10:15:14,063 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:15:14,064 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:14,064 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:15:14,064 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:14,064 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:15:14,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:14,308 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 67 proven. 94 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-09-10 10:15:14,308 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:14,308 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:15:14,316 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:15:14,316 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:15:14,344 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-09-10 10:15:14,344 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:14,346 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:14,399 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 68 proven. 78 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:14,399 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:14,464 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 68 proven. 78 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:14,485 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:14,485 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:15:14,500 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:15:14,500 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:15:14,592 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-09-10 10:15:14,592 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:14,596 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:14,604 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 68 proven. 78 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:14,604 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:14,688 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 68 proven. 78 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-10 10:15:14,689 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:15:14,690 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 12, 12, 12, 12] total 15 [2018-09-10 10:15:14,690 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:15:14,690 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-09-10 10:15:14,690 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-09-10 10:15:14,690 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=153, Unknown=0, NotChecked=0, Total=210 [2018-09-10 10:15:14,691 INFO L87 Difference]: Start difference. First operand 105 states and 114 transitions. Second operand 15 states. [2018-09-10 10:15:14,953 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:15:14,953 INFO L93 Difference]: Finished difference Result 115 states and 124 transitions. [2018-09-10 10:15:14,953 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-09-10 10:15:14,953 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 81 [2018-09-10 10:15:14,954 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:15:14,955 INFO L225 Difference]: With dead ends: 115 [2018-09-10 10:15:14,955 INFO L226 Difference]: Without dead ends: 113 [2018-09-10 10:15:14,955 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 345 GetRequests, 302 SyntacticMatches, 28 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 149 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=70, Invalid=202, Unknown=0, NotChecked=0, Total=272 [2018-09-10 10:15:14,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2018-09-10 10:15:15,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 113. [2018-09-10 10:15:15,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-09-10 10:15:15,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 122 transitions. [2018-09-10 10:15:15,025 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 122 transitions. Word has length 81 [2018-09-10 10:15:15,026 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:15:15,026 INFO L480 AbstractCegarLoop]: Abstraction has 113 states and 122 transitions. [2018-09-10 10:15:15,026 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-09-10 10:15:15,026 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 122 transitions. [2018-09-10 10:15:15,027 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-09-10 10:15:15,027 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:15:15,027 INFO L376 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:15:15,027 INFO L423 AbstractCegarLoop]: === Iteration 37 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:15:15,027 INFO L82 PathProgramCache]: Analyzing trace with hash -507298045, now seen corresponding path program 13 times [2018-09-10 10:15:15,027 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:15:15,028 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:15,028 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:15:15,028 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:15,028 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:15:15,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:15,888 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:15,889 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:15,889 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:15:15,897 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:15:15,897 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:15:15,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:15,924 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:16,248 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:16,248 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:16,392 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:16,414 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:16,414 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 69 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:15:16,429 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:15:16,429 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:15:16,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:16,488 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:16,506 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:16,506 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:16,675 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:16,676 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:15:16,676 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 38 [2018-09-10 10:15:16,676 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:15:16,676 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-09-10 10:15:16,677 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-09-10 10:15:16,677 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=291, Invalid=1115, Unknown=0, NotChecked=0, Total=1406 [2018-09-10 10:15:16,677 INFO L87 Difference]: Start difference. First operand 113 states and 122 transitions. Second operand 38 states. [2018-09-10 10:15:17,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:15:17,291 INFO L93 Difference]: Finished difference Result 202 states and 228 transitions. [2018-09-10 10:15:17,292 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-09-10 10:15:17,292 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 89 [2018-09-10 10:15:17,292 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:15:17,293 INFO L225 Difference]: With dead ends: 202 [2018-09-10 10:15:17,293 INFO L226 Difference]: Without dead ends: 161 [2018-09-10 10:15:17,294 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 393 GetRequests, 303 SyntacticMatches, 36 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1817 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=633, Invalid=2447, Unknown=0, NotChecked=0, Total=3080 [2018-09-10 10:15:17,294 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161 states. [2018-09-10 10:15:17,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161 to 115. [2018-09-10 10:15:17,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-09-10 10:15:17,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 124 transitions. [2018-09-10 10:15:17,348 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 124 transitions. Word has length 89 [2018-09-10 10:15:17,348 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:15:17,348 INFO L480 AbstractCegarLoop]: Abstraction has 115 states and 124 transitions. [2018-09-10 10:15:17,348 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-09-10 10:15:17,349 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 124 transitions. [2018-09-10 10:15:17,349 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-09-10 10:15:17,349 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:15:17,349 INFO L376 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 7, 7, 7, 7, 7, 6, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:15:17,350 INFO L423 AbstractCegarLoop]: === Iteration 38 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:15:17,350 INFO L82 PathProgramCache]: Analyzing trace with hash -1248990833, now seen corresponding path program 16 times [2018-09-10 10:15:17,350 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:15:17,351 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:17,351 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:15:17,351 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:17,351 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:15:17,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:17,595 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:17,595 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:17,595 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:15:17,603 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:15:17,603 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:15:17,630 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:15:17,630 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:17,632 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:17,995 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:17,995 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:18,147 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:18,166 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:18,166 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:15:18,181 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:15:18,181 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:15:18,245 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:15:18,246 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:18,249 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:18,268 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:18,268 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:18,435 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:18,436 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:15:18,436 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 37 [2018-09-10 10:15:18,436 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:15:18,437 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-09-10 10:15:18,437 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-09-10 10:15:18,437 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=267, Invalid=1065, Unknown=0, NotChecked=0, Total=1332 [2018-09-10 10:15:18,437 INFO L87 Difference]: Start difference. First operand 115 states and 124 transitions. Second operand 37 states. [2018-09-10 10:15:19,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:15:19,107 INFO L93 Difference]: Finished difference Result 248 states and 283 transitions. [2018-09-10 10:15:19,107 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-09-10 10:15:19,107 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 89 [2018-09-10 10:15:19,108 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:15:19,109 INFO L225 Difference]: With dead ends: 248 [2018-09-10 10:15:19,109 INFO L226 Difference]: Without dead ends: 207 [2018-09-10 10:15:19,110 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 400 GetRequests, 304 SyntacticMatches, 36 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1966 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=741, Invalid=3041, Unknown=0, NotChecked=0, Total=3782 [2018-09-10 10:15:19,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 207 states. [2018-09-10 10:15:19,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 207 to 115. [2018-09-10 10:15:19,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-09-10 10:15:19,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 124 transitions. [2018-09-10 10:15:19,196 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 124 transitions. Word has length 89 [2018-09-10 10:15:19,196 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:15:19,196 INFO L480 AbstractCegarLoop]: Abstraction has 115 states and 124 transitions. [2018-09-10 10:15:19,197 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-09-10 10:15:19,197 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 124 transitions. [2018-09-10 10:15:19,197 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-09-10 10:15:19,197 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:15:19,198 INFO L376 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 7, 7, 7, 7, 6, 5, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:15:19,198 INFO L423 AbstractCegarLoop]: === Iteration 39 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:15:19,198 INFO L82 PathProgramCache]: Analyzing trace with hash 752469787, now seen corresponding path program 17 times [2018-09-10 10:15:19,198 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:15:19,199 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:19,199 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:15:19,199 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:19,199 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:15:19,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:19,473 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:19,473 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:19,473 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:15:19,481 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:15:19,481 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:15:19,610 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2018-09-10 10:15:19,611 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:19,613 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:20,171 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:20,171 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:20,315 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:20,336 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:20,337 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:15:20,351 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:15:20,351 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:15:20,448 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2018-09-10 10:15:20,449 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:20,452 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:20,467 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:20,467 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:20,690 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:20,691 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:15:20,692 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 36 [2018-09-10 10:15:20,692 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:15:20,692 INFO L459 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-09-10 10:15:20,692 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-09-10 10:15:20,692 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=247, Invalid=1013, Unknown=0, NotChecked=0, Total=1260 [2018-09-10 10:15:20,693 INFO L87 Difference]: Start difference. First operand 115 states and 124 transitions. Second operand 36 states. [2018-09-10 10:15:21,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:15:21,666 INFO L93 Difference]: Finished difference Result 292 states and 336 transitions. [2018-09-10 10:15:21,667 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-09-10 10:15:21,667 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 89 [2018-09-10 10:15:21,667 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:15:21,668 INFO L225 Difference]: With dead ends: 292 [2018-09-10 10:15:21,668 INFO L226 Difference]: Without dead ends: 251 [2018-09-10 10:15:21,669 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 405 GetRequests, 305 SyntacticMatches, 36 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2068 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=823, Invalid=3467, Unknown=0, NotChecked=0, Total=4290 [2018-09-10 10:15:21,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 251 states. [2018-09-10 10:15:21,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 251 to 115. [2018-09-10 10:15:21,766 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-09-10 10:15:21,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 124 transitions. [2018-09-10 10:15:21,767 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 124 transitions. Word has length 89 [2018-09-10 10:15:21,768 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:15:21,768 INFO L480 AbstractCegarLoop]: Abstraction has 115 states and 124 transitions. [2018-09-10 10:15:21,768 INFO L481 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-09-10 10:15:21,768 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 124 transitions. [2018-09-10 10:15:21,769 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-09-10 10:15:21,769 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:15:21,769 INFO L376 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 7, 7, 7, 7, 5, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:15:21,769 INFO L423 AbstractCegarLoop]: === Iteration 40 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:15:21,769 INFO L82 PathProgramCache]: Analyzing trace with hash -1940416601, now seen corresponding path program 18 times [2018-09-10 10:15:21,770 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:15:21,770 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:21,770 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:15:21,770 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:21,771 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:15:21,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:22,488 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:22,488 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:22,488 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:15:22,496 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:15:22,496 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:15:22,521 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-09-10 10:15:22,521 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:22,524 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:22,837 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:22,837 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:22,978 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:22,998 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:22,998 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 75 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:15:23,013 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:15:23,013 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:15:23,115 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-09-10 10:15:23,116 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:23,119 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:23,133 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:23,134 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:23,291 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:23,292 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:15:23,292 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 35 [2018-09-10 10:15:23,293 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:15:23,293 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-09-10 10:15:23,293 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-09-10 10:15:23,293 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=959, Unknown=0, NotChecked=0, Total=1190 [2018-09-10 10:15:23,293 INFO L87 Difference]: Start difference. First operand 115 states and 124 transitions. Second operand 35 states. [2018-09-10 10:15:24,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:15:24,445 INFO L93 Difference]: Finished difference Result 334 states and 387 transitions. [2018-09-10 10:15:24,445 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-09-10 10:15:24,445 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 89 [2018-09-10 10:15:24,446 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:15:24,447 INFO L225 Difference]: With dead ends: 334 [2018-09-10 10:15:24,447 INFO L226 Difference]: Without dead ends: 293 [2018-09-10 10:15:24,448 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 408 GetRequests, 306 SyntacticMatches, 36 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2097 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=867, Invalid=3689, Unknown=0, NotChecked=0, Total=4556 [2018-09-10 10:15:24,449 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 293 states. [2018-09-10 10:15:24,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 293 to 115. [2018-09-10 10:15:24,515 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-09-10 10:15:24,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 124 transitions. [2018-09-10 10:15:24,516 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 124 transitions. Word has length 89 [2018-09-10 10:15:24,516 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:15:24,516 INFO L480 AbstractCegarLoop]: Abstraction has 115 states and 124 transitions. [2018-09-10 10:15:24,516 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-09-10 10:15:24,516 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 124 transitions. [2018-09-10 10:15:24,517 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-09-10 10:15:24,517 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:15:24,517 INFO L376 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 7, 7, 7, 7, 5, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:15:24,517 INFO L423 AbstractCegarLoop]: === Iteration 41 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:15:24,517 INFO L82 PathProgramCache]: Analyzing trace with hash 233315123, now seen corresponding path program 19 times [2018-09-10 10:15:24,518 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:15:24,518 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:24,518 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:15:24,518 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:24,519 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:15:24,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:25,566 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:25,567 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:25,567 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:15:25,574 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:15:25,575 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:15:25,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:25,601 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:26,107 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:26,107 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:26,247 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:26,266 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:26,266 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 77 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:15:26,283 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:15:26,283 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:15:26,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:26,343 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:26,360 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:26,361 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:26,511 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:26,512 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:15:26,512 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 34 [2018-09-10 10:15:26,512 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:15:26,512 INFO L459 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-09-10 10:15:26,513 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-09-10 10:15:26,513 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=219, Invalid=903, Unknown=0, NotChecked=0, Total=1122 [2018-09-10 10:15:26,513 INFO L87 Difference]: Start difference. First operand 115 states and 124 transitions. Second operand 34 states. [2018-09-10 10:15:27,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:15:27,592 INFO L93 Difference]: Finished difference Result 374 states and 436 transitions. [2018-09-10 10:15:27,592 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-09-10 10:15:27,592 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 89 [2018-09-10 10:15:27,592 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:15:27,594 INFO L225 Difference]: With dead ends: 374 [2018-09-10 10:15:27,594 INFO L226 Difference]: Without dead ends: 333 [2018-09-10 10:15:27,595 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 409 GetRequests, 307 SyntacticMatches, 36 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2039 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=867, Invalid=3689, Unknown=0, NotChecked=0, Total=4556 [2018-09-10 10:15:27,595 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 333 states. [2018-09-10 10:15:27,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 333 to 115. [2018-09-10 10:15:27,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-09-10 10:15:27,668 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 124 transitions. [2018-09-10 10:15:27,668 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 124 transitions. Word has length 89 [2018-09-10 10:15:27,668 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:15:27,668 INFO L480 AbstractCegarLoop]: Abstraction has 115 states and 124 transitions. [2018-09-10 10:15:27,668 INFO L481 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-09-10 10:15:27,668 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 124 transitions. [2018-09-10 10:15:27,669 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-09-10 10:15:27,669 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:15:27,669 INFO L376 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 7, 7, 7, 7, 6, 5, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:15:27,669 INFO L423 AbstractCegarLoop]: === Iteration 42 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:15:27,669 INFO L82 PathProgramCache]: Analyzing trace with hash 1822167487, now seen corresponding path program 20 times [2018-09-10 10:15:27,669 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:15:27,670 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:27,670 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:15:27,670 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:27,670 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:15:27,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:27,913 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:27,913 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:27,913 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:15:27,920 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:15:27,920 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:15:27,947 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:15:27,947 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:27,949 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:28,199 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:28,199 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:28,331 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:28,351 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:28,351 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 79 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:15:28,382 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:15:28,382 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:15:28,439 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:15:28,439 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:28,443 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:28,461 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:28,461 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:29,746 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:29,747 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:15:29,747 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 33 [2018-09-10 10:15:29,747 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:15:29,748 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-09-10 10:15:29,748 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-09-10 10:15:29,748 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=211, Invalid=845, Unknown=0, NotChecked=0, Total=1056 [2018-09-10 10:15:29,748 INFO L87 Difference]: Start difference. First operand 115 states and 124 transitions. Second operand 33 states. [2018-09-10 10:15:30,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:15:30,905 INFO L93 Difference]: Finished difference Result 412 states and 483 transitions. [2018-09-10 10:15:30,906 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-09-10 10:15:30,906 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 89 [2018-09-10 10:15:30,906 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:15:30,908 INFO L225 Difference]: With dead ends: 412 [2018-09-10 10:15:30,908 INFO L226 Difference]: Without dead ends: 371 [2018-09-10 10:15:30,909 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 408 GetRequests, 308 SyntacticMatches, 36 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1888 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=823, Invalid=3467, Unknown=0, NotChecked=0, Total=4290 [2018-09-10 10:15:30,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 371 states. [2018-09-10 10:15:30,973 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 371 to 115. [2018-09-10 10:15:30,973 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-09-10 10:15:30,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 124 transitions. [2018-09-10 10:15:30,974 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 124 transitions. Word has length 89 [2018-09-10 10:15:30,974 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:15:30,974 INFO L480 AbstractCegarLoop]: Abstraction has 115 states and 124 transitions. [2018-09-10 10:15:30,974 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-09-10 10:15:30,974 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 124 transitions. [2018-09-10 10:15:30,975 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-09-10 10:15:30,975 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:15:30,975 INFO L376 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 7, 7, 7, 7, 7, 6, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:15:30,975 INFO L423 AbstractCegarLoop]: === Iteration 43 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:15:30,975 INFO L82 PathProgramCache]: Analyzing trace with hash 1890859851, now seen corresponding path program 21 times [2018-09-10 10:15:30,975 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:15:30,976 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:30,976 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:15:30,976 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:30,976 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:15:30,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:31,521 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:31,521 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:31,521 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:15:31,528 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:15:31,528 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:15:31,557 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2018-09-10 10:15:31,557 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:31,561 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:31,801 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:31,801 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:31,932 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:31,952 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:31,952 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 81 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:15:31,967 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:15:31,967 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:15:32,075 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2018-09-10 10:15:32,076 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:32,079 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:32,098 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:32,098 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:32,256 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:32,257 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:15:32,257 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 32 [2018-09-10 10:15:32,257 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:15:32,258 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-09-10 10:15:32,258 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-09-10 10:15:32,258 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=207, Invalid=785, Unknown=0, NotChecked=0, Total=992 [2018-09-10 10:15:32,259 INFO L87 Difference]: Start difference. First operand 115 states and 124 transitions. Second operand 32 states. [2018-09-10 10:15:33,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:15:33,691 INFO L93 Difference]: Finished difference Result 448 states and 528 transitions. [2018-09-10 10:15:33,691 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-09-10 10:15:33,691 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 89 [2018-09-10 10:15:33,692 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:15:33,693 INFO L225 Difference]: With dead ends: 448 [2018-09-10 10:15:33,693 INFO L226 Difference]: Without dead ends: 407 [2018-09-10 10:15:33,694 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 405 GetRequests, 309 SyntacticMatches, 36 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1646 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=741, Invalid=3041, Unknown=0, NotChecked=0, Total=3782 [2018-09-10 10:15:33,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 407 states. [2018-09-10 10:15:33,763 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 407 to 115. [2018-09-10 10:15:33,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-09-10 10:15:33,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 124 transitions. [2018-09-10 10:15:33,764 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 124 transitions. Word has length 89 [2018-09-10 10:15:33,764 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:15:33,764 INFO L480 AbstractCegarLoop]: Abstraction has 115 states and 124 transitions. [2018-09-10 10:15:33,764 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-09-10 10:15:33,764 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 124 transitions. [2018-09-10 10:15:33,765 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-09-10 10:15:33,765 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:15:33,765 INFO L376 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:15:33,765 INFO L423 AbstractCegarLoop]: === Iteration 44 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:15:33,766 INFO L82 PathProgramCache]: Analyzing trace with hash 2074171351, now seen corresponding path program 7 times [2018-09-10 10:15:33,766 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:15:33,766 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:33,766 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:15:33,767 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:33,767 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:15:33,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:34,037 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:34,037 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:34,037 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:15:34,047 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:15:34,047 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:15:34,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:34,073 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:34,292 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:34,292 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:34,431 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:34,452 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:34,452 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 83 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 83 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:15:34,466 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:15:34,467 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:15:34,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:34,525 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:34,542 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:34,542 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:34,684 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:34,685 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:15:34,685 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 31 [2018-09-10 10:15:34,686 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:15:34,686 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-09-10 10:15:34,686 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-09-10 10:15:34,686 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=207, Invalid=723, Unknown=0, NotChecked=0, Total=930 [2018-09-10 10:15:34,686 INFO L87 Difference]: Start difference. First operand 115 states and 124 transitions. Second operand 31 states. [2018-09-10 10:15:35,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:15:35,830 INFO L93 Difference]: Finished difference Result 487 states and 577 transitions. [2018-09-10 10:15:35,831 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-09-10 10:15:35,831 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 89 [2018-09-10 10:15:35,831 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:15:35,833 INFO L225 Difference]: With dead ends: 487 [2018-09-10 10:15:35,833 INFO L226 Difference]: Without dead ends: 446 [2018-09-10 10:15:35,833 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 400 GetRequests, 310 SyntacticMatches, 36 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1327 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=633, Invalid=2447, Unknown=0, NotChecked=0, Total=3080 [2018-09-10 10:15:35,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 446 states. [2018-09-10 10:15:35,931 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 446 to 118. [2018-09-10 10:15:35,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-09-10 10:15:35,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 128 transitions. [2018-09-10 10:15:35,932 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 128 transitions. Word has length 89 [2018-09-10 10:15:35,932 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:15:35,932 INFO L480 AbstractCegarLoop]: Abstraction has 118 states and 128 transitions. [2018-09-10 10:15:35,932 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-09-10 10:15:35,932 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 128 transitions. [2018-09-10 10:15:35,933 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-09-10 10:15:35,933 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:15:35,933 INFO L376 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:15:35,933 INFO L423 AbstractCegarLoop]: === Iteration 45 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:15:35,934 INFO L82 PathProgramCache]: Analyzing trace with hash -1421446787, now seen corresponding path program 14 times [2018-09-10 10:15:35,934 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:15:35,934 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:35,935 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:15:35,935 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:35,935 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:15:35,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:36,230 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 85 proven. 124 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2018-09-10 10:15:36,231 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:36,231 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:15:36,238 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:15:36,238 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:15:36,264 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:15:36,264 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:36,266 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:36,312 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 86 proven. 105 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:36,312 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:36,414 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 86 proven. 105 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:36,433 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:36,434 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 85 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 85 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:15:36,448 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:15:36,449 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:15:36,511 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:15:36,511 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:36,515 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:36,527 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 86 proven. 105 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:36,527 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:36,758 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 86 proven. 105 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-10 10:15:36,759 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:15:36,759 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13, 13, 13, 13] total 16 [2018-09-10 10:15:36,759 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:15:36,760 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-09-10 10:15:36,760 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-09-10 10:15:36,760 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=173, Unknown=0, NotChecked=0, Total=240 [2018-09-10 10:15:36,760 INFO L87 Difference]: Start difference. First operand 118 states and 128 transitions. Second operand 16 states. [2018-09-10 10:15:37,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:15:37,178 INFO L93 Difference]: Finished difference Result 128 states and 138 transitions. [2018-09-10 10:15:37,178 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-09-10 10:15:37,178 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 91 [2018-09-10 10:15:37,179 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:15:37,182 INFO L225 Difference]: With dead ends: 128 [2018-09-10 10:15:37,183 INFO L226 Difference]: Without dead ends: 126 [2018-09-10 10:15:37,183 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 387 GetRequests, 339 SyntacticMatches, 32 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 186 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=80, Invalid=226, Unknown=0, NotChecked=0, Total=306 [2018-09-10 10:15:37,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-09-10 10:15:37,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 126. [2018-09-10 10:15:37,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 126 states. [2018-09-10 10:15:37,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 136 transitions. [2018-09-10 10:15:37,293 INFO L78 Accepts]: Start accepts. Automaton has 126 states and 136 transitions. Word has length 91 [2018-09-10 10:15:37,293 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:15:37,294 INFO L480 AbstractCegarLoop]: Abstraction has 126 states and 136 transitions. [2018-09-10 10:15:37,294 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-09-10 10:15:37,294 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 136 transitions. [2018-09-10 10:15:37,294 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-09-10 10:15:37,294 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:15:37,294 INFO L376 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:15:37,295 INFO L423 AbstractCegarLoop]: === Iteration 46 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:15:37,295 INFO L82 PathProgramCache]: Analyzing trace with hash -161069919, now seen corresponding path program 15 times [2018-09-10 10:15:37,295 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:15:37,295 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:37,296 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:15:37,296 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:37,296 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:15:37,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:37,599 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:37,599 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:37,599 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:15:37,609 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:15:37,609 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:15:37,641 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-09-10 10:15:37,642 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:37,644 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:38,015 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:38,015 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:38,655 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:38,674 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:38,675 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 87 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 87 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:15:38,690 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:15:38,690 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:15:38,813 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-09-10 10:15:38,813 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:38,817 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:38,839 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:38,839 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:39,494 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:39,495 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:15:39,496 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 42 [2018-09-10 10:15:39,496 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:15:39,496 INFO L459 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-09-10 10:15:39,496 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-09-10 10:15:39,497 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=353, Invalid=1369, Unknown=0, NotChecked=0, Total=1722 [2018-09-10 10:15:39,497 INFO L87 Difference]: Start difference. First operand 126 states and 136 transitions. Second operand 42 states. [2018-09-10 10:15:40,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:15:40,279 INFO L93 Difference]: Finished difference Result 225 states and 254 transitions. [2018-09-10 10:15:40,279 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-09-10 10:15:40,279 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 99 [2018-09-10 10:15:40,279 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:15:40,280 INFO L225 Difference]: With dead ends: 225 [2018-09-10 10:15:40,280 INFO L226 Difference]: Without dead ends: 180 [2018-09-10 10:15:40,281 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 437 GetRequests, 337 SyntacticMatches, 40 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2292 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=763, Invalid=3019, Unknown=0, NotChecked=0, Total=3782 [2018-09-10 10:15:40,281 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180 states. [2018-09-10 10:15:40,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180 to 128. [2018-09-10 10:15:40,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-09-10 10:15:40,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-09-10 10:15:40,420 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-09-10 10:15:40,420 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:15:40,420 INFO L480 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-09-10 10:15:40,420 INFO L481 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-09-10 10:15:40,420 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-09-10 10:15:40,421 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-09-10 10:15:40,421 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:15:40,421 INFO L376 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 8, 8, 8, 8, 8, 7, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:15:40,421 INFO L423 AbstractCegarLoop]: === Iteration 47 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:15:40,422 INFO L82 PathProgramCache]: Analyzing trace with hash 1635135533, now seen corresponding path program 22 times [2018-09-10 10:15:40,422 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:15:40,422 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:40,422 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:15:40,423 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:40,423 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:15:40,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:40,782 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:40,782 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:40,783 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:15:40,790 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:15:40,790 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:15:40,821 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:15:40,821 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:40,823 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:41,515 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:41,516 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:41,774 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:41,793 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:41,794 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 89 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 89 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:15:41,809 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:15:41,810 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:15:41,886 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:15:41,886 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:41,890 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:41,909 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:41,909 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:42,097 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:42,099 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:15:42,099 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 41 [2018-09-10 10:15:42,099 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:15:42,099 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-09-10 10:15:42,099 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-09-10 10:15:42,100 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=326, Invalid=1314, Unknown=0, NotChecked=0, Total=1640 [2018-09-10 10:15:42,100 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 41 states. [2018-09-10 10:15:43,172 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:15:43,172 INFO L93 Difference]: Finished difference Result 277 states and 316 transitions. [2018-09-10 10:15:43,172 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-09-10 10:15:43,172 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 99 [2018-09-10 10:15:43,173 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:15:43,173 INFO L225 Difference]: With dead ends: 277 [2018-09-10 10:15:43,173 INFO L226 Difference]: Without dead ends: 232 [2018-09-10 10:15:43,174 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 445 GetRequests, 338 SyntacticMatches, 40 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2504 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=903, Invalid=3789, Unknown=0, NotChecked=0, Total=4692 [2018-09-10 10:15:43,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 232 states. [2018-09-10 10:15:43,260 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 232 to 128. [2018-09-10 10:15:43,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-09-10 10:15:43,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-09-10 10:15:43,261 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-09-10 10:15:43,261 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:15:43,261 INFO L480 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-09-10 10:15:43,261 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-09-10 10:15:43,261 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-09-10 10:15:43,262 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-09-10 10:15:43,262 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:15:43,262 INFO L376 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 8, 8, 8, 8, 7, 6, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:15:43,262 INFO L423 AbstractCegarLoop]: === Iteration 48 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:15:43,262 INFO L82 PathProgramCache]: Analyzing trace with hash 1382256313, now seen corresponding path program 23 times [2018-09-10 10:15:43,262 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:15:43,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:43,263 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:15:43,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:43,263 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:15:43,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:43,577 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:43,578 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:43,578 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:15:43,585 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:15:43,585 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:15:43,619 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 9 check-sat command(s) [2018-09-10 10:15:43,619 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:43,622 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:43,960 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:43,960 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:44,126 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:44,145 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:44,145 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 91 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 91 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:15:44,162 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:15:44,163 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:15:44,282 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 9 check-sat command(s) [2018-09-10 10:15:44,282 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:44,286 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:44,303 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:44,304 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:44,537 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:44,538 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:15:44,538 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 40 [2018-09-10 10:15:44,538 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:15:44,538 INFO L459 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-09-10 10:15:44,539 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-09-10 10:15:44,539 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=303, Invalid=1257, Unknown=0, NotChecked=0, Total=1560 [2018-09-10 10:15:44,539 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 40 states. [2018-09-10 10:15:45,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:15:45,738 INFO L93 Difference]: Finished difference Result 327 states and 376 transitions. [2018-09-10 10:15:45,738 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-09-10 10:15:45,738 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 99 [2018-09-10 10:15:45,739 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:15:45,740 INFO L225 Difference]: With dead ends: 327 [2018-09-10 10:15:45,740 INFO L226 Difference]: Without dead ends: 282 [2018-09-10 10:15:45,741 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 451 GetRequests, 339 SyntacticMatches, 40 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2670 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1018, Invalid=4384, Unknown=0, NotChecked=0, Total=5402 [2018-09-10 10:15:45,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282 states. [2018-09-10 10:15:45,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282 to 128. [2018-09-10 10:15:45,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-09-10 10:15:45,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-09-10 10:15:45,833 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-09-10 10:15:45,834 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:15:45,834 INFO L480 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-09-10 10:15:45,834 INFO L481 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-09-10 10:15:45,834 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-09-10 10:15:45,834 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-09-10 10:15:45,834 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:15:45,834 INFO L376 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 8, 8, 8, 8, 6, 5, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:15:45,835 INFO L423 AbstractCegarLoop]: === Iteration 49 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:15:45,835 INFO L82 PathProgramCache]: Analyzing trace with hash 2012160069, now seen corresponding path program 24 times [2018-09-10 10:15:45,835 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:15:45,835 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:45,835 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:15:45,835 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:45,835 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:15:45,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:46,615 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:46,616 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:46,616 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:15:46,624 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:15:46,624 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:15:46,656 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2018-09-10 10:15:46,656 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:46,659 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:46,996 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:46,997 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:47,162 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:47,181 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:47,182 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 93 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 93 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:15:47,197 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:15:47,197 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:15:47,318 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2018-09-10 10:15:47,319 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:47,322 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:47,340 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:47,340 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:48,025 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:48,026 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:15:48,026 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 39 [2018-09-10 10:15:48,026 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:15:48,027 INFO L459 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-09-10 10:15:48,027 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-09-10 10:15:48,027 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=284, Invalid=1198, Unknown=0, NotChecked=0, Total=1482 [2018-09-10 10:15:48,027 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 39 states. [2018-09-10 10:15:49,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:15:49,574 INFO L93 Difference]: Finished difference Result 375 states and 434 transitions. [2018-09-10 10:15:49,574 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-09-10 10:15:49,574 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 99 [2018-09-10 10:15:49,574 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:15:49,576 INFO L225 Difference]: With dead ends: 375 [2018-09-10 10:15:49,576 INFO L226 Difference]: Without dead ends: 330 [2018-09-10 10:15:49,577 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 455 GetRequests, 340 SyntacticMatches, 40 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2758 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=1093, Invalid=4759, Unknown=0, NotChecked=0, Total=5852 [2018-09-10 10:15:49,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 330 states. [2018-09-10 10:15:49,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 330 to 128. [2018-09-10 10:15:49,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-09-10 10:15:49,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-09-10 10:15:49,679 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-09-10 10:15:49,679 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:15:49,679 INFO L480 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-09-10 10:15:49,679 INFO L481 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-09-10 10:15:49,679 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-09-10 10:15:49,680 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-09-10 10:15:49,680 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:15:49,680 INFO L376 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 8, 8, 8, 8, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:15:49,680 INFO L423 AbstractCegarLoop]: === Iteration 50 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:15:49,680 INFO L82 PathProgramCache]: Analyzing trace with hash -1173773103, now seen corresponding path program 25 times [2018-09-10 10:15:49,680 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:15:49,680 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:49,681 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:15:49,681 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:49,681 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:15:49,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:49,906 INFO L134 CoverageAnalysis]: Checked inductivity of 304 backedges. 152 proven. 40 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:49,906 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:49,906 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:15:49,916 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:15:49,916 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:15:49,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:49,947 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:50,303 INFO L134 CoverageAnalysis]: Checked inductivity of 304 backedges. 152 proven. 40 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:50,303 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:50,468 INFO L134 CoverageAnalysis]: Checked inductivity of 304 backedges. 152 proven. 40 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:50,496 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:50,497 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 95 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 95 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:15:50,519 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:15:50,519 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:15:50,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:50,580 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:50,600 INFO L134 CoverageAnalysis]: Checked inductivity of 304 backedges. 152 proven. 40 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:50,600 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:50,797 INFO L134 CoverageAnalysis]: Checked inductivity of 304 backedges. 152 proven. 40 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:50,798 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:15:50,798 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 38 [2018-09-10 10:15:50,798 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:15:50,799 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-09-10 10:15:50,799 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-09-10 10:15:50,799 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=269, Invalid=1137, Unknown=0, NotChecked=0, Total=1406 [2018-09-10 10:15:50,799 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 38 states. [2018-09-10 10:15:52,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:15:52,413 INFO L93 Difference]: Finished difference Result 421 states and 490 transitions. [2018-09-10 10:15:52,413 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-09-10 10:15:52,413 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 99 [2018-09-10 10:15:52,413 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:15:52,415 INFO L225 Difference]: With dead ends: 421 [2018-09-10 10:15:52,415 INFO L226 Difference]: Without dead ends: 376 [2018-09-10 10:15:52,416 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 457 GetRequests, 341 SyntacticMatches, 40 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2748 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1119, Invalid=4887, Unknown=0, NotChecked=0, Total=6006 [2018-09-10 10:15:52,416 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 376 states. [2018-09-10 10:15:52,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 376 to 128. [2018-09-10 10:15:52,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-09-10 10:15:52,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-09-10 10:15:52,530 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-09-10 10:15:52,530 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:15:52,530 INFO L480 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-09-10 10:15:52,530 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-09-10 10:15:52,530 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-09-10 10:15:52,531 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-09-10 10:15:52,531 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:15:52,531 INFO L376 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 8, 8, 8, 8, 6, 5, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:15:52,531 INFO L423 AbstractCegarLoop]: === Iteration 51 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:15:52,531 INFO L82 PathProgramCache]: Analyzing trace with hash -975971235, now seen corresponding path program 26 times [2018-09-10 10:15:52,531 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:15:52,532 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:52,532 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:15:52,532 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:52,532 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:15:52,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:54,830 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:54,830 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:54,830 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 96 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 96 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:15:54,837 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:15:54,837 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:15:54,866 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:15:54,866 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:54,868 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:55,163 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:55,163 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:55,323 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:55,342 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:55,342 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 97 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 97 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:15:55,357 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:15:55,357 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:15:55,421 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:15:55,421 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:55,425 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:55,461 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:55,461 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:55,701 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:55,702 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:15:55,703 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 37 [2018-09-10 10:15:55,703 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:15:55,703 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-09-10 10:15:55,703 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-09-10 10:15:55,704 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=258, Invalid=1074, Unknown=0, NotChecked=0, Total=1332 [2018-09-10 10:15:55,704 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 37 states. [2018-09-10 10:15:57,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:15:57,411 INFO L93 Difference]: Finished difference Result 465 states and 544 transitions. [2018-09-10 10:15:57,413 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-09-10 10:15:57,413 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 99 [2018-09-10 10:15:57,413 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:15:57,415 INFO L225 Difference]: With dead ends: 465 [2018-09-10 10:15:57,415 INFO L226 Difference]: Without dead ends: 420 [2018-09-10 10:15:57,416 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 457 GetRequests, 342 SyntacticMatches, 40 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2631 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=1093, Invalid=4759, Unknown=0, NotChecked=0, Total=5852 [2018-09-10 10:15:57,416 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 420 states. [2018-09-10 10:15:57,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 420 to 128. [2018-09-10 10:15:57,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-09-10 10:15:57,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-09-10 10:15:57,528 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-09-10 10:15:57,528 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:15:57,528 INFO L480 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-09-10 10:15:57,528 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-09-10 10:15:57,528 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-09-10 10:15:57,528 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-09-10 10:15:57,529 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:15:57,529 INFO L376 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 8, 8, 8, 8, 7, 6, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:15:57,529 INFO L423 AbstractCegarLoop]: === Iteration 52 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:15:57,529 INFO L82 PathProgramCache]: Analyzing trace with hash -1717664023, now seen corresponding path program 27 times [2018-09-10 10:15:57,529 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:15:57,530 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:57,530 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:15:57,530 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:15:57,530 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:15:57,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:15:58,292 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:58,292 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:58,292 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 98 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 98 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:15:58,299 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:15:58,299 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:15:58,330 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-09-10 10:15:58,331 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:58,333 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:58,625 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:58,626 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:58,828 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:58,847 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:15:58,848 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 99 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 99 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:15:58,862 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:15:58,862 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:15:59,002 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-09-10 10:15:59,002 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:15:59,006 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:15:59,020 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:59,020 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:15:59,217 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:15:59,218 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:15:59,218 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 36 [2018-09-10 10:15:59,218 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:15:59,219 INFO L459 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-09-10 10:15:59,219 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-09-10 10:15:59,219 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=251, Invalid=1009, Unknown=0, NotChecked=0, Total=1260 [2018-09-10 10:15:59,219 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 36 states. [2018-09-10 10:16:01,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:16:01,015 INFO L93 Difference]: Finished difference Result 507 states and 596 transitions. [2018-09-10 10:16:01,015 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-09-10 10:16:01,016 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 99 [2018-09-10 10:16:01,016 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:16:01,017 INFO L225 Difference]: With dead ends: 507 [2018-09-10 10:16:01,017 INFO L226 Difference]: Without dead ends: 462 [2018-09-10 10:16:01,018 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 455 GetRequests, 343 SyntacticMatches, 40 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2404 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1018, Invalid=4384, Unknown=0, NotChecked=0, Total=5402 [2018-09-10 10:16:01,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 462 states. [2018-09-10 10:16:01,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 462 to 128. [2018-09-10 10:16:01,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-09-10 10:16:01,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-09-10 10:16:01,177 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-09-10 10:16:01,177 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:16:01,177 INFO L480 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-09-10 10:16:01,177 INFO L481 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-09-10 10:16:01,177 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-09-10 10:16:01,178 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-09-10 10:16:01,178 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:16:01,178 INFO L376 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 8, 8, 8, 8, 8, 7, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:16:01,178 INFO L423 AbstractCegarLoop]: === Iteration 53 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:16:01,178 INFO L82 PathProgramCache]: Analyzing trace with hash 283796597, now seen corresponding path program 28 times [2018-09-10 10:16:01,179 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:16:01,179 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:01,179 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:16:01,179 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:01,179 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:16:01,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:16:01,486 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:16:01,487 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:01,487 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 100 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 100 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:16:01,494 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:16:01,494 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:16:01,522 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:16:01,522 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:01,524 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:02,062 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:16:02,063 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:02,220 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:16:02,240 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:02,240 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 101 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 101 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:16:02,255 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:16:02,256 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:16:02,331 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:16:02,332 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:02,336 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:02,356 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:16:02,356 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:02,604 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:16:02,605 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:16:02,605 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 35 [2018-09-10 10:16:02,605 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:16:02,606 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-09-10 10:16:02,606 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-09-10 10:16:02,606 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=248, Invalid=942, Unknown=0, NotChecked=0, Total=1190 [2018-09-10 10:16:02,606 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 35 states. [2018-09-10 10:16:04,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:16:04,227 INFO L93 Difference]: Finished difference Result 547 states and 646 transitions. [2018-09-10 10:16:04,227 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-09-10 10:16:04,227 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 99 [2018-09-10 10:16:04,227 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:16:04,229 INFO L225 Difference]: With dead ends: 547 [2018-09-10 10:16:04,229 INFO L226 Difference]: Without dead ends: 502 [2018-09-10 10:16:04,231 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 451 GetRequests, 344 SyntacticMatches, 40 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2075 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=903, Invalid=3789, Unknown=0, NotChecked=0, Total=4692 [2018-09-10 10:16:04,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 502 states. [2018-09-10 10:16:04,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 502 to 128. [2018-09-10 10:16:04,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-09-10 10:16:04,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-09-10 10:16:04,361 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-09-10 10:16:04,361 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:16:04,361 INFO L480 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-09-10 10:16:04,361 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-09-10 10:16:04,362 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-09-10 10:16:04,362 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-09-10 10:16:04,362 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:16:04,362 INFO L376 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:16:04,362 INFO L423 AbstractCegarLoop]: === Iteration 54 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:16:04,363 INFO L82 PathProgramCache]: Analyzing trace with hash 1885877505, now seen corresponding path program 8 times [2018-09-10 10:16:04,363 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:16:04,363 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:04,363 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:16:04,363 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:04,364 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:16:04,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:16:04,582 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:16:04,582 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:04,582 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 102 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 102 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:16:04,590 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:16:04,590 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:16:04,619 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:16:04,619 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:04,621 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:04,878 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:16:04,878 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:05,036 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:16:05,056 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:05,056 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 103 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 103 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:16:05,070 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:16:05,070 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:16:05,135 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:16:05,136 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:05,141 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:05,159 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:16:05,159 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:05,368 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:16:05,370 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:16:05,370 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 34 [2018-09-10 10:16:05,370 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:16:05,370 INFO L459 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-09-10 10:16:05,371 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-09-10 10:16:05,371 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=249, Invalid=873, Unknown=0, NotChecked=0, Total=1122 [2018-09-10 10:16:05,371 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 34 states. [2018-09-10 10:16:07,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:16:07,078 INFO L93 Difference]: Finished difference Result 590 states and 700 transitions. [2018-09-10 10:16:07,078 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-09-10 10:16:07,079 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 99 [2018-09-10 10:16:07,079 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:16:07,081 INFO L225 Difference]: With dead ends: 590 [2018-09-10 10:16:07,081 INFO L226 Difference]: Without dead ends: 545 [2018-09-10 10:16:07,081 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 445 GetRequests, 345 SyntacticMatches, 40 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1664 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=763, Invalid=3019, Unknown=0, NotChecked=0, Total=3782 [2018-09-10 10:16:07,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 545 states. [2018-09-10 10:16:07,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 545 to 131. [2018-09-10 10:16:07,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2018-09-10 10:16:07,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 142 transitions. [2018-09-10 10:16:07,204 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 142 transitions. Word has length 99 [2018-09-10 10:16:07,204 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:16:07,204 INFO L480 AbstractCegarLoop]: Abstraction has 131 states and 142 transitions. [2018-09-10 10:16:07,204 INFO L481 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-09-10 10:16:07,204 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 142 transitions. [2018-09-10 10:16:07,205 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2018-09-10 10:16:07,205 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:16:07,205 INFO L376 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 9, 9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:16:07,206 INFO L423 AbstractCegarLoop]: === Iteration 55 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:16:07,206 INFO L82 PathProgramCache]: Analyzing trace with hash -1743772005, now seen corresponding path program 16 times [2018-09-10 10:16:07,206 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:16:07,207 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:07,207 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:16:07,207 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:07,207 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:16:07,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:16:07,863 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 105 proven. 158 refuted. 0 times theorem prover too weak. 91 trivial. 0 not checked. [2018-09-10 10:16:07,863 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:07,863 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 104 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 104 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:16:07,871 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:16:07,871 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:16:07,896 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:16:07,896 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:07,898 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:07,929 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 106 proven. 136 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:16:07,929 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:08,040 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 106 proven. 136 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:16:08,060 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:08,060 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 105 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 105 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:16:08,075 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:16:08,075 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:16:08,154 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:16:08,154 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:08,158 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:08,168 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 106 proven. 136 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:16:08,168 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:08,311 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 106 proven. 136 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-10 10:16:08,313 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:16:08,313 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 14, 14, 14, 14] total 17 [2018-09-10 10:16:08,313 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:16:08,313 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-09-10 10:16:08,313 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-09-10 10:16:08,313 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=194, Unknown=0, NotChecked=0, Total=272 [2018-09-10 10:16:08,313 INFO L87 Difference]: Start difference. First operand 131 states and 142 transitions. Second operand 17 states. [2018-09-10 10:16:08,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:16:08,637 INFO L93 Difference]: Finished difference Result 141 states and 152 transitions. [2018-09-10 10:16:08,637 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-09-10 10:16:08,637 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 101 [2018-09-10 10:16:08,637 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:16:08,638 INFO L225 Difference]: With dead ends: 141 [2018-09-10 10:16:08,638 INFO L226 Difference]: Without dead ends: 139 [2018-09-10 10:16:08,638 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 429 GetRequests, 376 SyntacticMatches, 36 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 227 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=91, Invalid=251, Unknown=0, NotChecked=0, Total=342 [2018-09-10 10:16:08,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2018-09-10 10:16:08,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 139. [2018-09-10 10:16:08,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-09-10 10:16:08,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 150 transitions. [2018-09-10 10:16:08,752 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 150 transitions. Word has length 101 [2018-09-10 10:16:08,752 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:16:08,752 INFO L480 AbstractCegarLoop]: Abstraction has 139 states and 150 transitions. [2018-09-10 10:16:08,752 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-09-10 10:16:08,752 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 150 transitions. [2018-09-10 10:16:08,752 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-09-10 10:16:08,752 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:16:08,753 INFO L376 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:16:08,753 INFO L423 AbstractCegarLoop]: === Iteration 56 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:16:08,753 INFO L82 PathProgramCache]: Analyzing trace with hash -860881985, now seen corresponding path program 17 times [2018-09-10 10:16:08,753 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:16:08,753 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:08,753 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:16:08,753 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:08,754 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:16:08,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:16:10,386 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:10,387 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:10,387 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 106 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 106 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:16:10,394 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:16:10,394 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:16:10,431 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-09-10 10:16:10,431 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:10,434 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:10,870 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:10,870 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:11,066 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:11,088 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:11,088 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 107 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 107 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:16:11,103 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:16:11,104 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:16:11,245 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-09-10 10:16:11,246 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:11,250 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:11,271 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:11,271 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:11,496 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:11,498 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:16:11,498 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 46 [2018-09-10 10:16:11,498 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:16:11,499 INFO L459 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-09-10 10:16:11,499 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-09-10 10:16:11,499 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=421, Invalid=1649, Unknown=0, NotChecked=0, Total=2070 [2018-09-10 10:16:11,499 INFO L87 Difference]: Start difference. First operand 139 states and 150 transitions. Second operand 46 states. [2018-09-10 10:16:12,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:16:12,595 INFO L93 Difference]: Finished difference Result 248 states and 280 transitions. [2018-09-10 10:16:12,595 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-09-10 10:16:12,595 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 109 [2018-09-10 10:16:12,595 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:16:12,596 INFO L225 Difference]: With dead ends: 248 [2018-09-10 10:16:12,596 INFO L226 Difference]: Without dead ends: 199 [2018-09-10 10:16:12,597 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 481 GetRequests, 371 SyntacticMatches, 44 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2822 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=905, Invalid=3651, Unknown=0, NotChecked=0, Total=4556 [2018-09-10 10:16:12,597 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 199 states. [2018-09-10 10:16:12,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 199 to 141. [2018-09-10 10:16:12,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-09-10 10:16:12,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-09-10 10:16:12,721 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-09-10 10:16:12,721 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:16:12,721 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-09-10 10:16:12,721 INFO L481 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-09-10 10:16:12,721 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-09-10 10:16:12,722 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-09-10 10:16:12,722 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:16:12,722 INFO L376 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 9, 8, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:16:12,722 INFO L423 AbstractCegarLoop]: === Iteration 57 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:16:12,722 INFO L82 PathProgramCache]: Analyzing trace with hash 1311238219, now seen corresponding path program 29 times [2018-09-10 10:16:12,722 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:16:12,723 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:12,723 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:16:12,723 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:12,723 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:16:12,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:16:13,271 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:13,271 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:13,271 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 108 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 108 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:16:13,279 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:16:13,279 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:16:13,317 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-09-10 10:16:13,317 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:13,319 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:13,731 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:13,731 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:13,952 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:13,972 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:13,972 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 109 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 109 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:16:13,987 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:16:13,987 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:16:14,128 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-09-10 10:16:14,129 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:14,133 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:14,154 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:14,155 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:14,419 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:14,421 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:16:14,421 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 45 [2018-09-10 10:16:14,421 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:16:14,421 INFO L459 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-09-10 10:16:14,422 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-09-10 10:16:14,422 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=391, Invalid=1589, Unknown=0, NotChecked=0, Total=1980 [2018-09-10 10:16:14,422 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 45 states. [2018-09-10 10:16:15,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:16:15,781 INFO L93 Difference]: Finished difference Result 306 states and 349 transitions. [2018-09-10 10:16:15,781 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-09-10 10:16:15,782 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 109 [2018-09-10 10:16:15,782 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:16:15,783 INFO L225 Difference]: With dead ends: 306 [2018-09-10 10:16:15,783 INFO L226 Difference]: Without dead ends: 257 [2018-09-10 10:16:15,784 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 490 GetRequests, 372 SyntacticMatches, 44 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3107 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1081, Invalid=4619, Unknown=0, NotChecked=0, Total=5700 [2018-09-10 10:16:15,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 257 states. [2018-09-10 10:16:15,921 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 257 to 141. [2018-09-10 10:16:15,921 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-09-10 10:16:15,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-09-10 10:16:15,921 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-09-10 10:16:15,921 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:16:15,921 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-09-10 10:16:15,922 INFO L481 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-09-10 10:16:15,922 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-09-10 10:16:15,922 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-09-10 10:16:15,922 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:16:15,922 INFO L376 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 8, 7, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:16:15,922 INFO L423 AbstractCegarLoop]: === Iteration 58 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:16:15,923 INFO L82 PathProgramCache]: Analyzing trace with hash 562661335, now seen corresponding path program 30 times [2018-09-10 10:16:15,923 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:16:15,923 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:15,923 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:16:15,923 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:15,923 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:16:15,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:16:17,385 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:17,386 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:17,386 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 110 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 110 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:16:17,393 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:16:17,393 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:16:17,429 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2018-09-10 10:16:17,430 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:17,432 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:17,823 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:17,824 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:18,019 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:18,038 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:18,039 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 111 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 111 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:16:18,054 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:16:18,054 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:16:18,195 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2018-09-10 10:16:18,196 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:18,200 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:18,221 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:18,221 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:18,460 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:18,461 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:16:18,462 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 44 [2018-09-10 10:16:18,462 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:16:18,462 INFO L459 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-09-10 10:16:18,462 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-09-10 10:16:18,463 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=365, Invalid=1527, Unknown=0, NotChecked=0, Total=1892 [2018-09-10 10:16:18,463 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 44 states. [2018-09-10 10:16:20,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:16:20,137 INFO L93 Difference]: Finished difference Result 362 states and 416 transitions. [2018-09-10 10:16:20,137 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-09-10 10:16:20,137 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 109 [2018-09-10 10:16:20,137 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:16:20,139 INFO L225 Difference]: With dead ends: 362 [2018-09-10 10:16:20,139 INFO L226 Difference]: Without dead ends: 313 [2018-09-10 10:16:20,140 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 497 GetRequests, 373 SyntacticMatches, 44 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3349 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=1234, Invalid=5408, Unknown=0, NotChecked=0, Total=6642 [2018-09-10 10:16:20,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 313 states. [2018-09-10 10:16:20,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 313 to 141. [2018-09-10 10:16:20,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-09-10 10:16:20,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-09-10 10:16:20,299 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-09-10 10:16:20,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:16:20,300 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-09-10 10:16:20,300 INFO L481 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-09-10 10:16:20,300 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-09-10 10:16:20,300 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-09-10 10:16:20,300 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:16:20,301 INFO L376 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 7, 6, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:16:20,301 INFO L423 AbstractCegarLoop]: === Iteration 59 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:16:20,301 INFO L82 PathProgramCache]: Analyzing trace with hash 195402339, now seen corresponding path program 31 times [2018-09-10 10:16:20,301 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:16:20,302 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:20,302 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:16:20,302 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:20,302 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:16:20,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:16:20,579 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:20,580 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:20,580 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 112 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 112 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:16:20,586 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:16:20,587 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:16:20,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:16:20,620 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:20,988 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:20,988 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:21,189 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:21,209 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:21,209 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 113 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 113 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:16:21,223 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:16:21,224 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:16:21,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:16:21,293 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:21,310 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:21,310 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:21,529 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:21,530 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:16:21,530 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 43 [2018-09-10 10:16:21,530 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:16:21,531 INFO L459 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-09-10 10:16:21,531 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-09-10 10:16:21,531 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=343, Invalid=1463, Unknown=0, NotChecked=0, Total=1806 [2018-09-10 10:16:21,531 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 43 states. [2018-09-10 10:16:23,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:16:23,465 INFO L93 Difference]: Finished difference Result 416 states and 481 transitions. [2018-09-10 10:16:23,465 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-09-10 10:16:23,465 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 109 [2018-09-10 10:16:23,465 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:16:23,467 INFO L225 Difference]: With dead ends: 416 [2018-09-10 10:16:23,467 INFO L226 Difference]: Without dead ends: 367 [2018-09-10 10:16:23,467 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 502 GetRequests, 374 SyntacticMatches, 44 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3510 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1346, Invalid=5964, Unknown=0, NotChecked=0, Total=7310 [2018-09-10 10:16:23,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 367 states. [2018-09-10 10:16:23,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 367 to 141. [2018-09-10 10:16:23,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-09-10 10:16:23,636 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-09-10 10:16:23,637 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-09-10 10:16:23,637 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:16:23,637 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-09-10 10:16:23,637 INFO L481 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-09-10 10:16:23,637 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-09-10 10:16:23,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-09-10 10:16:23,638 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:16:23,638 INFO L376 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 6, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:16:23,638 INFO L423 AbstractCegarLoop]: === Iteration 60 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:16:23,638 INFO L82 PathProgramCache]: Analyzing trace with hash 1316806639, now seen corresponding path program 32 times [2018-09-10 10:16:23,639 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:16:23,639 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:23,639 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:16:23,639 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:23,639 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:16:23,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:16:24,597 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:24,598 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:24,598 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 114 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 114 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:16:24,606 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:16:24,606 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:16:24,638 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:16:24,638 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:24,640 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:25,004 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:25,004 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:25,201 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:25,221 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:25,221 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 115 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 115 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:16:25,236 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:16:25,236 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:16:25,308 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:16:25,308 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:25,313 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:25,332 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:25,332 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:25,643 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:25,644 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:16:25,644 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 42 [2018-09-10 10:16:25,644 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:16:25,644 INFO L459 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-09-10 10:16:25,645 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-09-10 10:16:25,645 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=1397, Unknown=0, NotChecked=0, Total=1722 [2018-09-10 10:16:25,645 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 42 states. [2018-09-10 10:16:27,822 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:16:27,823 INFO L93 Difference]: Finished difference Result 468 states and 544 transitions. [2018-09-10 10:16:27,823 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-09-10 10:16:27,823 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 109 [2018-09-10 10:16:27,823 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:16:27,825 INFO L225 Difference]: With dead ends: 468 [2018-09-10 10:16:27,825 INFO L226 Difference]: Without dead ends: 419 [2018-09-10 10:16:27,826 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 505 GetRequests, 375 SyntacticMatches, 44 SemanticMatches, 86 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3564 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=1405, Invalid=6251, Unknown=0, NotChecked=0, Total=7656 [2018-09-10 10:16:27,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 419 states. [2018-09-10 10:16:28,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 419 to 141. [2018-09-10 10:16:28,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-09-10 10:16:28,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-09-10 10:16:28,009 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-09-10 10:16:28,009 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:16:28,009 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-09-10 10:16:28,009 INFO L481 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-09-10 10:16:28,009 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-09-10 10:16:28,010 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-09-10 10:16:28,010 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:16:28,010 INFO L376 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 6, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:16:28,010 INFO L423 AbstractCegarLoop]: === Iteration 61 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:16:28,010 INFO L82 PathProgramCache]: Analyzing trace with hash 893393019, now seen corresponding path program 33 times [2018-09-10 10:16:28,010 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:16:28,011 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:28,011 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:16:28,011 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:28,011 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:16:28,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:16:28,349 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:28,349 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:28,350 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 116 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 116 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:16:28,356 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:16:28,356 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:16:28,396 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-09-10 10:16:28,396 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:28,398 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:28,771 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:28,771 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:29,233 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:29,253 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:29,253 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 117 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 117 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:16:29,268 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:16:29,268 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:16:29,422 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-09-10 10:16:29,422 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:29,426 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:29,446 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:29,446 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:29,654 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:29,655 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:16:29,655 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 41 [2018-09-10 10:16:29,655 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:16:29,656 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-09-10 10:16:29,656 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-09-10 10:16:29,656 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=311, Invalid=1329, Unknown=0, NotChecked=0, Total=1640 [2018-09-10 10:16:29,656 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 41 states. [2018-09-10 10:16:31,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:16:31,770 INFO L93 Difference]: Finished difference Result 518 states and 605 transitions. [2018-09-10 10:16:31,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-09-10 10:16:31,770 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 109 [2018-09-10 10:16:31,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:16:31,772 INFO L225 Difference]: With dead ends: 518 [2018-09-10 10:16:31,773 INFO L226 Difference]: Without dead ends: 469 [2018-09-10 10:16:31,773 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 506 GetRequests, 376 SyntacticMatches, 44 SemanticMatches, 86 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3497 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1405, Invalid=6251, Unknown=0, NotChecked=0, Total=7656 [2018-09-10 10:16:31,774 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 469 states. [2018-09-10 10:16:31,927 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 469 to 141. [2018-09-10 10:16:31,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-09-10 10:16:31,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-09-10 10:16:31,928 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-09-10 10:16:31,928 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:16:31,928 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-09-10 10:16:31,928 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-09-10 10:16:31,928 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-09-10 10:16:31,929 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-09-10 10:16:31,929 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:16:31,929 INFO L376 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 7, 6, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:16:31,929 INFO L423 AbstractCegarLoop]: === Iteration 62 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:16:31,929 INFO L82 PathProgramCache]: Analyzing trace with hash -1605368825, now seen corresponding path program 34 times [2018-09-10 10:16:31,930 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:16:31,930 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:31,930 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:16:31,930 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:31,931 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:16:31,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:16:32,226 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:32,226 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:32,226 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 118 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 118 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:16:32,234 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:16:32,234 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:16:32,265 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:16:32,265 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:32,267 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:32,867 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:32,867 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:33,058 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:33,079 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:33,079 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 119 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 119 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:16:33,093 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:16:33,093 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:16:33,176 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:16:33,177 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:33,181 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:33,198 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:33,198 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:33,487 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:33,488 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:16:33,488 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 40 [2018-09-10 10:16:33,489 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:16:33,489 INFO L459 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-09-10 10:16:33,489 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-09-10 10:16:33,489 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=301, Invalid=1259, Unknown=0, NotChecked=0, Total=1560 [2018-09-10 10:16:33,489 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 40 states. [2018-09-10 10:16:35,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:16:35,778 INFO L93 Difference]: Finished difference Result 566 states and 664 transitions. [2018-09-10 10:16:35,778 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-09-10 10:16:35,778 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 109 [2018-09-10 10:16:35,779 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:16:35,780 INFO L225 Difference]: With dead ends: 566 [2018-09-10 10:16:35,781 INFO L226 Difference]: Without dead ends: 517 [2018-09-10 10:16:35,782 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 505 GetRequests, 377 SyntacticMatches, 44 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3303 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1346, Invalid=5964, Unknown=0, NotChecked=0, Total=7310 [2018-09-10 10:16:35,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 517 states. [2018-09-10 10:16:35,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 517 to 141. [2018-09-10 10:16:35,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-09-10 10:16:35,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-09-10 10:16:35,947 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-09-10 10:16:35,947 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:16:35,947 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-09-10 10:16:35,947 INFO L481 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-09-10 10:16:35,947 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-09-10 10:16:35,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-09-10 10:16:35,948 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:16:35,948 INFO L376 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 8, 7, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:16:35,948 INFO L423 AbstractCegarLoop]: === Iteration 63 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:16:35,948 INFO L82 PathProgramCache]: Analyzing trace with hash -1858248045, now seen corresponding path program 35 times [2018-09-10 10:16:35,948 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:16:35,949 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:35,949 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:16:35,949 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:35,949 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:16:35,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:16:36,815 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:36,815 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:36,815 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 120 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 120 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:16:36,824 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:16:36,825 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:16:36,860 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-09-10 10:16:36,860 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:36,862 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:37,185 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:37,186 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:37,398 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:37,418 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:37,418 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 121 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 121 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:16:37,432 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:16:37,433 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:16:37,568 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-09-10 10:16:37,568 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:37,572 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:37,607 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:37,608 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:37,920 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:37,922 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:16:37,922 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 39 [2018-09-10 10:16:37,922 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:16:37,922 INFO L459 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-09-10 10:16:37,923 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-09-10 10:16:37,923 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=295, Invalid=1187, Unknown=0, NotChecked=0, Total=1482 [2018-09-10 10:16:37,923 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 39 states. [2018-09-10 10:16:40,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:16:40,166 INFO L93 Difference]: Finished difference Result 612 states and 721 transitions. [2018-09-10 10:16:40,166 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-09-10 10:16:40,166 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 109 [2018-09-10 10:16:40,167 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:16:40,169 INFO L225 Difference]: With dead ends: 612 [2018-09-10 10:16:40,169 INFO L226 Difference]: Without dead ends: 563 [2018-09-10 10:16:40,170 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 502 GetRequests, 378 SyntacticMatches, 44 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2984 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1234, Invalid=5408, Unknown=0, NotChecked=0, Total=6642 [2018-09-10 10:16:40,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 563 states. [2018-09-10 10:16:40,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 563 to 141. [2018-09-10 10:16:40,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-09-10 10:16:40,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-09-10 10:16:40,338 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-09-10 10:16:40,338 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:16:40,338 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-09-10 10:16:40,338 INFO L481 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-09-10 10:16:40,338 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-09-10 10:16:40,339 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-09-10 10:16:40,339 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:16:40,339 INFO L376 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 9, 8, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:16:40,339 INFO L423 AbstractCegarLoop]: === Iteration 64 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:16:40,339 INFO L82 PathProgramCache]: Analyzing trace with hash -1228344289, now seen corresponding path program 36 times [2018-09-10 10:16:40,340 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:16:40,340 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:40,340 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:16:40,340 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:40,340 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:16:40,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:16:40,588 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:40,588 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:40,588 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 122 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 122 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:16:40,597 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:16:40,597 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:16:40,633 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2018-09-10 10:16:40,634 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:40,635 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:40,953 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:40,953 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:41,145 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:41,165 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:41,165 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 123 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 123 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:16:41,180 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:16:41,180 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:16:41,322 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2018-09-10 10:16:41,322 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:41,326 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:41,344 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:41,345 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:41,582 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:41,584 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:16:41,584 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 38 [2018-09-10 10:16:41,584 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:16:41,584 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-09-10 10:16:41,584 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-09-10 10:16:41,585 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=293, Invalid=1113, Unknown=0, NotChecked=0, Total=1406 [2018-09-10 10:16:41,585 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 38 states. [2018-09-10 10:16:43,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:16:43,991 INFO L93 Difference]: Finished difference Result 656 states and 776 transitions. [2018-09-10 10:16:43,991 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-09-10 10:16:43,991 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 109 [2018-09-10 10:16:43,992 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:16:43,994 INFO L225 Difference]: With dead ends: 656 [2018-09-10 10:16:43,994 INFO L226 Difference]: Without dead ends: 607 [2018-09-10 10:16:43,995 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 497 GetRequests, 379 SyntacticMatches, 44 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2554 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1081, Invalid=4619, Unknown=0, NotChecked=0, Total=5700 [2018-09-10 10:16:43,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 607 states. [2018-09-10 10:16:44,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 607 to 141. [2018-09-10 10:16:44,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-09-10 10:16:44,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-09-10 10:16:44,163 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-09-10 10:16:44,164 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:16:44,164 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-09-10 10:16:44,164 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-09-10 10:16:44,164 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-09-10 10:16:44,164 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-09-10 10:16:44,165 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:16:44,165 INFO L376 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:16:44,165 INFO L423 AbstractCegarLoop]: === Iteration 65 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:16:44,165 INFO L82 PathProgramCache]: Analyzing trace with hash -119310165, now seen corresponding path program 9 times [2018-09-10 10:16:44,165 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:16:44,166 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:44,166 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:16:44,166 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:44,166 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:16:44,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:16:44,422 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:44,422 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:44,423 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 124 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 124 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:16:44,430 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:16:44,431 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:16:44,465 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-09-10 10:16:44,465 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:44,468 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:44,769 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:44,770 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:44,963 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:44,983 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:44,983 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 125 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 125 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:16:44,997 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:16:44,997 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:16:45,138 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-09-10 10:16:45,138 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:45,142 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:45,160 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:45,160 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:45,387 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:45,388 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:16:45,389 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 37 [2018-09-10 10:16:45,389 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:16:45,389 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-09-10 10:16:45,389 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-09-10 10:16:45,389 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=295, Invalid=1037, Unknown=0, NotChecked=0, Total=1332 [2018-09-10 10:16:45,390 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 37 states. [2018-09-10 10:16:47,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:16:47,620 INFO L93 Difference]: Finished difference Result 703 states and 835 transitions. [2018-09-10 10:16:47,621 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-09-10 10:16:47,621 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 109 [2018-09-10 10:16:47,621 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:16:47,624 INFO L225 Difference]: With dead ends: 703 [2018-09-10 10:16:47,624 INFO L226 Difference]: Without dead ends: 654 [2018-09-10 10:16:47,625 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 490 GetRequests, 380 SyntacticMatches, 44 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2039 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=905, Invalid=3651, Unknown=0, NotChecked=0, Total=4556 [2018-09-10 10:16:47,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 654 states. [2018-09-10 10:16:47,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 654 to 144. [2018-09-10 10:16:47,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-09-10 10:16:47,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 156 transitions. [2018-09-10 10:16:47,804 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 156 transitions. Word has length 109 [2018-09-10 10:16:47,804 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:16:47,804 INFO L480 AbstractCegarLoop]: Abstraction has 144 states and 156 transitions. [2018-09-10 10:16:47,804 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-09-10 10:16:47,804 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 156 transitions. [2018-09-10 10:16:47,804 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-09-10 10:16:47,804 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:16:47,805 INFO L376 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:16:47,805 INFO L423 AbstractCegarLoop]: === Iteration 66 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:16:47,805 INFO L82 PathProgramCache]: Analyzing trace with hash -1752486599, now seen corresponding path program 18 times [2018-09-10 10:16:47,805 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:16:47,805 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:47,806 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:16:47,806 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:47,806 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:16:47,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:16:48,014 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 127 proven. 196 refuted. 0 times theorem prover too weak. 120 trivial. 0 not checked. [2018-09-10 10:16:48,015 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:48,015 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 126 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 126 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:16:48,022 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:16:48,022 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:16:48,060 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2018-09-10 10:16:48,060 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:48,062 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:48,122 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 128 proven. 171 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:48,123 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:48,236 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 128 proven. 171 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:48,256 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:48,256 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 127 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 127 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:16:48,272 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:16:48,272 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:16:48,424 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2018-09-10 10:16:48,424 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:48,429 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:48,439 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 128 proven. 171 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:48,440 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:48,587 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 128 proven. 171 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-10 10:16:48,588 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:16:48,588 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 15, 15, 15, 15] total 18 [2018-09-10 10:16:48,588 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:16:48,588 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-09-10 10:16:48,589 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-09-10 10:16:48,589 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=90, Invalid=216, Unknown=0, NotChecked=0, Total=306 [2018-09-10 10:16:48,589 INFO L87 Difference]: Start difference. First operand 144 states and 156 transitions. Second operand 18 states. [2018-09-10 10:16:49,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:16:49,048 INFO L93 Difference]: Finished difference Result 154 states and 166 transitions. [2018-09-10 10:16:49,049 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-09-10 10:16:49,049 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 111 [2018-09-10 10:16:49,049 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:16:49,051 INFO L225 Difference]: With dead ends: 154 [2018-09-10 10:16:49,051 INFO L226 Difference]: Without dead ends: 152 [2018-09-10 10:16:49,051 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 471 GetRequests, 413 SyntacticMatches, 40 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 272 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=103, Invalid=277, Unknown=0, NotChecked=0, Total=380 [2018-09-10 10:16:49,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-09-10 10:16:49,242 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 152. [2018-09-10 10:16:49,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 152 states. [2018-09-10 10:16:49,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152 states to 152 states and 164 transitions. [2018-09-10 10:16:49,243 INFO L78 Accepts]: Start accepts. Automaton has 152 states and 164 transitions. Word has length 111 [2018-09-10 10:16:49,243 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:16:49,243 INFO L480 AbstractCegarLoop]: Abstraction has 152 states and 164 transitions. [2018-09-10 10:16:49,243 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-09-10 10:16:49,243 INFO L276 IsEmpty]: Start isEmpty. Operand 152 states and 164 transitions. [2018-09-10 10:16:49,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-10 10:16:49,244 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:16:49,244 INFO L376 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 11, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:16:49,244 INFO L423 AbstractCegarLoop]: === Iteration 67 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:16:49,244 INFO L82 PathProgramCache]: Analyzing trace with hash 1040286813, now seen corresponding path program 19 times [2018-09-10 10:16:49,244 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:16:49,245 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:49,245 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:16:49,245 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:49,245 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:16:49,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:16:49,545 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:16:49,545 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:49,545 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 128 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 128 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:16:49,553 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:16:49,553 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:16:49,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:16:49,590 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:50,112 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:16:50,112 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:50,346 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:16:50,367 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:50,367 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 129 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 129 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:16:50,383 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:16:50,383 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:16:50,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:16:50,461 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:50,483 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:16:50,484 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:50,744 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:16:50,745 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:16:50,745 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 50 [2018-09-10 10:16:50,746 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:16:50,746 INFO L459 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-09-10 10:16:50,746 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-09-10 10:16:50,747 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=495, Invalid=1955, Unknown=0, NotChecked=0, Total=2450 [2018-09-10 10:16:50,747 INFO L87 Difference]: Start difference. First operand 152 states and 164 transitions. Second operand 50 states. [2018-09-10 10:16:52,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:16:52,038 INFO L93 Difference]: Finished difference Result 271 states and 306 transitions. [2018-09-10 10:16:52,038 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-09-10 10:16:52,038 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 119 [2018-09-10 10:16:52,039 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:16:52,039 INFO L225 Difference]: With dead ends: 271 [2018-09-10 10:16:52,040 INFO L226 Difference]: Without dead ends: 218 [2018-09-10 10:16:52,040 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 525 GetRequests, 405 SyntacticMatches, 48 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3407 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1059, Invalid=4343, Unknown=0, NotChecked=0, Total=5402 [2018-09-10 10:16:52,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 218 states. [2018-09-10 10:16:52,228 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 218 to 154. [2018-09-10 10:16:52,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-09-10 10:16:52,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-09-10 10:16:52,229 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-09-10 10:16:52,229 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:16:52,229 INFO L480 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-09-10 10:16:52,229 INFO L481 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-09-10 10:16:52,229 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-09-10 10:16:52,230 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-10 10:16:52,230 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:16:52,230 INFO L376 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 10, 9, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:16:52,230 INFO L423 AbstractCegarLoop]: === Iteration 68 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:16:52,231 INFO L82 PathProgramCache]: Analyzing trace with hash -661376535, now seen corresponding path program 37 times [2018-09-10 10:16:52,231 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:16:52,231 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:52,231 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:16:52,232 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:52,232 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:16:52,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:16:52,518 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:16:52,518 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:52,518 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 130 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 130 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:16:52,525 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:16:52,526 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:16:52,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:16:52,560 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:53,338 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:16:53,339 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:53,575 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:16:53,595 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:53,595 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 131 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 131 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:16:53,611 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:16:53,611 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:16:53,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:16:53,689 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:53,712 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:16:53,712 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:53,966 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:16:53,967 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:16:53,967 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 49 [2018-09-10 10:16:53,967 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:16:53,967 INFO L459 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-09-10 10:16:53,968 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-09-10 10:16:53,968 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=462, Invalid=1890, Unknown=0, NotChecked=0, Total=2352 [2018-09-10 10:16:53,968 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 49 states. [2018-09-10 10:16:55,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:16:55,815 INFO L93 Difference]: Finished difference Result 335 states and 382 transitions. [2018-09-10 10:16:55,815 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-09-10 10:16:55,815 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 119 [2018-09-10 10:16:55,815 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:16:55,816 INFO L225 Difference]: With dead ends: 335 [2018-09-10 10:16:55,816 INFO L226 Difference]: Without dead ends: 282 [2018-09-10 10:16:55,817 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 535 GetRequests, 406 SyntacticMatches, 48 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3775 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1275, Invalid=5531, Unknown=0, NotChecked=0, Total=6806 [2018-09-10 10:16:55,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282 states. [2018-09-10 10:16:56,044 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282 to 154. [2018-09-10 10:16:56,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-09-10 10:16:56,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-09-10 10:16:56,045 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-09-10 10:16:56,045 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:16:56,045 INFO L480 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-09-10 10:16:56,045 INFO L481 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-09-10 10:16:56,045 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-09-10 10:16:56,046 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-10 10:16:56,046 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:16:56,046 INFO L376 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 9, 8, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:16:56,046 INFO L423 AbstractCegarLoop]: === Iteration 69 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:16:56,046 INFO L82 PathProgramCache]: Analyzing trace with hash 516739701, now seen corresponding path program 38 times [2018-09-10 10:16:56,046 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:16:56,047 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:56,047 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:16:56,047 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:16:56,047 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:16:56,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:16:56,347 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:16:56,347 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:56,347 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 132 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 132 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:16:56,356 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:16:56,357 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:16:56,391 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:16:56,391 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:56,393 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:56,888 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:16:56,889 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:57,183 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:16:57,203 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:16:57,203 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 133 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 133 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:16:57,218 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:16:57,218 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:16:57,297 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:16:57,297 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:16:57,301 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:16:57,328 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:16:57,329 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:16:57,583 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:16:57,584 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:16:57,585 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 48 [2018-09-10 10:16:57,585 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:16:57,585 INFO L459 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-09-10 10:16:57,585 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-09-10 10:16:57,585 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=433, Invalid=1823, Unknown=0, NotChecked=0, Total=2256 [2018-09-10 10:16:57,586 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 48 states. [2018-09-10 10:16:59,941 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:16:59,941 INFO L93 Difference]: Finished difference Result 397 states and 456 transitions. [2018-09-10 10:16:59,942 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-09-10 10:16:59,942 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 119 [2018-09-10 10:16:59,942 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:16:59,943 INFO L225 Difference]: With dead ends: 397 [2018-09-10 10:16:59,943 INFO L226 Difference]: Without dead ends: 344 [2018-09-10 10:16:59,944 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 543 GetRequests, 407 SyntacticMatches, 48 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4105 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1471, Invalid=6539, Unknown=0, NotChecked=0, Total=8010 [2018-09-10 10:16:59,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 344 states. [2018-09-10 10:17:00,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 344 to 154. [2018-09-10 10:17:00,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-09-10 10:17:00,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-09-10 10:17:00,154 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-09-10 10:17:00,154 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:17:00,154 INFO L480 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-09-10 10:17:00,154 INFO L481 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-09-10 10:17:00,154 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-09-10 10:17:00,155 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-10 10:17:00,155 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:00,155 INFO L376 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 8, 7, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:00,155 INFO L423 AbstractCegarLoop]: === Iteration 70 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:00,155 INFO L82 PathProgramCache]: Analyzing trace with hash -1752422911, now seen corresponding path program 39 times [2018-09-10 10:17:00,155 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:00,156 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:00,156 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:17:00,156 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:00,156 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:00,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:00,469 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:00,469 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:00,469 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 134 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 134 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:17:00,490 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:17:00,491 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:17:00,533 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-09-10 10:17:00,533 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:00,535 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:00,991 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:00,991 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:01,213 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:01,234 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:01,234 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 135 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 135 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:17:01,248 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:17:01,248 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:17:01,423 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-09-10 10:17:01,423 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:01,427 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:01,450 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:01,450 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:01,700 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:01,701 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:17:01,701 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 47 [2018-09-10 10:17:01,701 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:17:01,702 INFO L459 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-09-10 10:17:01,702 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-09-10 10:17:01,702 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=408, Invalid=1754, Unknown=0, NotChecked=0, Total=2162 [2018-09-10 10:17:01,702 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 47 states. [2018-09-10 10:17:04,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:17:04,164 INFO L93 Difference]: Finished difference Result 457 states and 528 transitions. [2018-09-10 10:17:04,165 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-09-10 10:17:04,165 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 119 [2018-09-10 10:17:04,165 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:17:04,166 INFO L225 Difference]: With dead ends: 457 [2018-09-10 10:17:04,166 INFO L226 Difference]: Without dead ends: 404 [2018-09-10 10:17:04,168 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 549 GetRequests, 408 SyntacticMatches, 48 SemanticMatches, 93 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4353 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1626, Invalid=7304, Unknown=0, NotChecked=0, Total=8930 [2018-09-10 10:17:04,168 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 404 states. [2018-09-10 10:17:04,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 404 to 154. [2018-09-10 10:17:04,396 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-09-10 10:17:04,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-09-10 10:17:04,397 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-09-10 10:17:04,397 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:17:04,397 INFO L480 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-09-10 10:17:04,397 INFO L481 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-09-10 10:17:04,397 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-09-10 10:17:04,397 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-10 10:17:04,397 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:04,398 INFO L376 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 7, 6, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:04,398 INFO L423 AbstractCegarLoop]: === Iteration 71 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:04,398 INFO L82 PathProgramCache]: Analyzing trace with hash -1964839795, now seen corresponding path program 40 times [2018-09-10 10:17:04,398 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:04,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:04,399 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:17:04,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:04,399 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:04,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:04,689 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:04,689 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:04,689 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 136 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 136 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:17:04,696 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:17:04,696 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:17:04,732 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:17:04,732 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:04,734 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:05,182 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:05,183 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:05,409 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:05,429 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:05,430 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 137 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 137 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:17:05,444 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:17:05,444 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:17:05,535 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:17:05,536 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:05,540 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:05,563 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:05,563 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:05,807 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:05,809 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:17:05,809 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 46 [2018-09-10 10:17:05,809 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:17:05,809 INFO L459 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-09-10 10:17:05,810 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-09-10 10:17:05,810 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=387, Invalid=1683, Unknown=0, NotChecked=0, Total=2070 [2018-09-10 10:17:05,810 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 46 states. [2018-09-10 10:17:08,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:17:08,675 INFO L93 Difference]: Finished difference Result 515 states and 598 transitions. [2018-09-10 10:17:08,676 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-09-10 10:17:08,676 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 119 [2018-09-10 10:17:08,676 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:17:08,678 INFO L225 Difference]: With dead ends: 515 [2018-09-10 10:17:08,678 INFO L226 Difference]: Without dead ends: 462 [2018-09-10 10:17:08,679 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 553 GetRequests, 409 SyntacticMatches, 48 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4487 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1725, Invalid=7781, Unknown=0, NotChecked=0, Total=9506 [2018-09-10 10:17:08,680 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 462 states. [2018-09-10 10:17:08,897 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 462 to 154. [2018-09-10 10:17:08,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-09-10 10:17:08,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-09-10 10:17:08,898 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-09-10 10:17:08,898 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:17:08,898 INFO L480 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-09-10 10:17:08,898 INFO L481 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-09-10 10:17:08,898 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-09-10 10:17:08,899 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-10 10:17:08,899 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:08,899 INFO L376 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 6, 6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:08,899 INFO L423 AbstractCegarLoop]: === Iteration 72 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:08,900 INFO L82 PathProgramCache]: Analyzing trace with hash -1911429607, now seen corresponding path program 41 times [2018-09-10 10:17:08,900 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:08,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:08,900 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:17:08,901 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:08,901 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:08,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:09,208 INFO L134 CoverageAnalysis]: Checked inductivity of 470 backedges. 230 proven. 60 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:09,208 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:09,208 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 138 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 138 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:17:09,217 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:17:09,217 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:17:09,258 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 11 check-sat command(s) [2018-09-10 10:17:09,259 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:09,261 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:09,677 INFO L134 CoverageAnalysis]: Checked inductivity of 470 backedges. 230 proven. 60 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:09,677 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:09,898 INFO L134 CoverageAnalysis]: Checked inductivity of 470 backedges. 230 proven. 60 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:09,918 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:09,918 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 139 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 139 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:17:09,934 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:17:09,935 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:17:10,091 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 11 check-sat command(s) [2018-09-10 10:17:10,091 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:10,096 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:10,117 INFO L134 CoverageAnalysis]: Checked inductivity of 470 backedges. 230 proven. 60 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:10,117 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:10,353 INFO L134 CoverageAnalysis]: Checked inductivity of 470 backedges. 230 proven. 60 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:10,354 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:17:10,354 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 45 [2018-09-10 10:17:10,355 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:17:10,355 INFO L459 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-09-10 10:17:10,355 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-09-10 10:17:10,355 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=370, Invalid=1610, Unknown=0, NotChecked=0, Total=1980 [2018-09-10 10:17:10,356 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 45 states. [2018-09-10 10:17:13,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:17:13,213 INFO L93 Difference]: Finished difference Result 571 states and 666 transitions. [2018-09-10 10:17:13,214 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-09-10 10:17:13,214 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 119 [2018-09-10 10:17:13,214 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:17:13,217 INFO L225 Difference]: With dead ends: 571 [2018-09-10 10:17:13,217 INFO L226 Difference]: Without dead ends: 518 [2018-09-10 10:17:13,218 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 555 GetRequests, 410 SyntacticMatches, 48 SemanticMatches, 97 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4487 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1759, Invalid=7943, Unknown=0, NotChecked=0, Total=9702 [2018-09-10 10:17:13,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518 states. [2018-09-10 10:17:13,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518 to 154. [2018-09-10 10:17:13,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-09-10 10:17:13,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-09-10 10:17:13,452 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-09-10 10:17:13,453 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:17:13,453 INFO L480 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-09-10 10:17:13,453 INFO L481 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-09-10 10:17:13,453 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-09-10 10:17:13,453 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-10 10:17:13,454 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:13,454 INFO L376 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 7, 6, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:13,454 INFO L423 AbstractCegarLoop]: === Iteration 73 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:13,454 INFO L82 PathProgramCache]: Analyzing trace with hash 260690597, now seen corresponding path program 42 times [2018-09-10 10:17:13,454 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:13,454 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:13,455 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:17:13,455 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:13,455 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:13,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:13,859 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:13,859 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:13,859 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 140 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 140 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:17:13,867 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:17:13,867 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:17:13,909 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2018-09-10 10:17:13,909 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:13,911 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:14,326 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:14,327 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:14,561 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:14,582 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:14,582 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 141 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 141 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:17:14,597 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:17:14,597 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:17:14,761 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2018-09-10 10:17:14,761 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:14,765 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:14,786 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:14,786 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:15,025 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:15,027 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:17:15,027 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 44 [2018-09-10 10:17:15,027 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:17:15,027 INFO L459 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-09-10 10:17:15,027 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-09-10 10:17:15,028 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=357, Invalid=1535, Unknown=0, NotChecked=0, Total=1892 [2018-09-10 10:17:15,028 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 44 states. [2018-09-10 10:17:18,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:17:18,081 INFO L93 Difference]: Finished difference Result 625 states and 732 transitions. [2018-09-10 10:17:18,081 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-09-10 10:17:18,082 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 119 [2018-09-10 10:17:18,082 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:17:18,084 INFO L225 Difference]: With dead ends: 625 [2018-09-10 10:17:18,084 INFO L226 Difference]: Without dead ends: 572 [2018-09-10 10:17:18,084 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 555 GetRequests, 411 SyntacticMatches, 48 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4344 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1725, Invalid=7781, Unknown=0, NotChecked=0, Total=9506 [2018-09-10 10:17:18,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 572 states. [2018-09-10 10:17:18,324 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 572 to 154. [2018-09-10 10:17:18,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-09-10 10:17:18,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-09-10 10:17:18,324 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-09-10 10:17:18,324 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:17:18,324 INFO L480 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-09-10 10:17:18,324 INFO L481 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-09-10 10:17:18,325 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-09-10 10:17:18,325 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-10 10:17:18,325 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:18,325 INFO L376 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 8, 7, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:18,326 INFO L423 AbstractCegarLoop]: === Iteration 74 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:18,326 INFO L82 PathProgramCache]: Analyzing trace with hash -487886287, now seen corresponding path program 43 times [2018-09-10 10:17:18,326 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:18,327 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:18,328 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:17:18,328 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:18,328 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:18,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:18,847 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:18,847 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:18,847 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 142 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 142 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:17:18,854 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:17:18,854 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:17:18,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:18,891 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:19,258 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:19,258 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:19,478 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:19,498 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:19,498 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 143 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 143 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:17:19,513 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:17:19,513 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:17:19,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:19,590 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:19,612 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:19,612 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:19,857 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:19,858 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:17:19,859 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 43 [2018-09-10 10:17:19,859 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:17:19,859 INFO L459 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-09-10 10:17:19,859 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-09-10 10:17:19,859 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=348, Invalid=1458, Unknown=0, NotChecked=0, Total=1806 [2018-09-10 10:17:19,860 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 43 states. [2018-09-10 10:17:23,112 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:17:23,112 INFO L93 Difference]: Finished difference Result 677 states and 796 transitions. [2018-09-10 10:17:23,112 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-09-10 10:17:23,113 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 119 [2018-09-10 10:17:23,113 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:17:23,115 INFO L225 Difference]: With dead ends: 677 [2018-09-10 10:17:23,115 INFO L226 Difference]: Without dead ends: 624 [2018-09-10 10:17:23,116 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 553 GetRequests, 412 SyntacticMatches, 48 SemanticMatches, 93 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4055 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1626, Invalid=7304, Unknown=0, NotChecked=0, Total=8930 [2018-09-10 10:17:23,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 624 states. [2018-09-10 10:17:23,365 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 624 to 154. [2018-09-10 10:17:23,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-09-10 10:17:23,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-09-10 10:17:23,365 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-09-10 10:17:23,365 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:17:23,366 INFO L480 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-09-10 10:17:23,366 INFO L481 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-09-10 10:17:23,366 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-09-10 10:17:23,366 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-10 10:17:23,366 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:23,367 INFO L376 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 9, 8, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:23,367 INFO L423 AbstractCegarLoop]: === Iteration 75 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:23,367 INFO L82 PathProgramCache]: Analyzing trace with hash -855145283, now seen corresponding path program 44 times [2018-09-10 10:17:23,367 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:23,368 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:23,368 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:17:23,368 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:23,368 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:23,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:23,899 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:23,899 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:23,899 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 144 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 144 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:17:23,907 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:17:23,908 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:17:23,942 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:17:23,942 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:23,944 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:24,321 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:24,322 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:24,539 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:24,559 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:24,559 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 145 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 145 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:17:24,573 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:17:24,573 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:17:24,647 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:17:24,648 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:24,651 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:24,670 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:24,670 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:24,918 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:24,920 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:17:24,920 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 42 [2018-09-10 10:17:24,920 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:17:24,920 INFO L459 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-09-10 10:17:24,920 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-09-10 10:17:24,921 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=343, Invalid=1379, Unknown=0, NotChecked=0, Total=1722 [2018-09-10 10:17:24,921 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 42 states. [2018-09-10 10:17:28,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:17:28,056 INFO L93 Difference]: Finished difference Result 727 states and 858 transitions. [2018-09-10 10:17:28,057 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-09-10 10:17:28,057 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 119 [2018-09-10 10:17:28,057 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:17:28,060 INFO L225 Difference]: With dead ends: 727 [2018-09-10 10:17:28,060 INFO L226 Difference]: Without dead ends: 674 [2018-09-10 10:17:28,061 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 549 GetRequests, 413 SyntacticMatches, 48 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3628 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1471, Invalid=6539, Unknown=0, NotChecked=0, Total=8010 [2018-09-10 10:17:28,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 674 states. [2018-09-10 10:17:28,301 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 674 to 154. [2018-09-10 10:17:28,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-09-10 10:17:28,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-09-10 10:17:28,302 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-09-10 10:17:28,302 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:17:28,302 INFO L480 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-09-10 10:17:28,302 INFO L481 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-09-10 10:17:28,302 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-09-10 10:17:28,303 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-10 10:17:28,303 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:28,303 INFO L376 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 10, 9, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:28,303 INFO L423 AbstractCegarLoop]: === Iteration 76 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:28,303 INFO L82 PathProgramCache]: Analyzing trace with hash 266259017, now seen corresponding path program 45 times [2018-09-10 10:17:28,303 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:28,304 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:28,304 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:17:28,304 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:28,304 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:28,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:28,571 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:28,572 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:28,572 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 146 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 146 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:17:28,578 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:17:28,579 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:17:28,622 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-09-10 10:17:28,623 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:28,625 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:29,200 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:29,200 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:29,440 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:29,460 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:29,460 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 147 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 147 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:17:29,475 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:17:29,475 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:17:29,643 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-09-10 10:17:29,644 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:29,648 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:29,669 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:29,670 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:29,916 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:29,918 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:17:29,918 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 41 [2018-09-10 10:17:29,918 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:17:29,918 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-09-10 10:17:29,919 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-09-10 10:17:29,919 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=342, Invalid=1298, Unknown=0, NotChecked=0, Total=1640 [2018-09-10 10:17:29,919 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 41 states. [2018-09-10 10:17:33,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:17:33,211 INFO L93 Difference]: Finished difference Result 775 states and 918 transitions. [2018-09-10 10:17:33,211 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-09-10 10:17:33,211 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 119 [2018-09-10 10:17:33,211 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:17:33,214 INFO L225 Difference]: With dead ends: 775 [2018-09-10 10:17:33,214 INFO L226 Difference]: Without dead ends: 722 [2018-09-10 10:17:33,214 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 543 GetRequests, 414 SyntacticMatches, 48 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3083 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1275, Invalid=5531, Unknown=0, NotChecked=0, Total=6806 [2018-09-10 10:17:33,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 722 states. [2018-09-10 10:17:33,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 722 to 154. [2018-09-10 10:17:33,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-09-10 10:17:33,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-09-10 10:17:33,480 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-09-10 10:17:33,481 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:17:33,481 INFO L480 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-09-10 10:17:33,481 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-09-10 10:17:33,481 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-09-10 10:17:33,481 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-10 10:17:33,481 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:33,481 INFO L376 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 11, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:33,482 INFO L423 AbstractCegarLoop]: === Iteration 77 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:33,482 INFO L82 PathProgramCache]: Analyzing trace with hash -157154603, now seen corresponding path program 10 times [2018-09-10 10:17:33,482 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:33,482 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:33,482 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:17:33,482 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:33,482 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:33,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:34,043 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:34,043 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:34,043 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 148 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 148 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:17:34,050 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:17:34,050 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:17:34,086 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:17:34,086 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:34,088 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:34,423 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:34,424 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:34,653 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:34,673 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:34,673 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 149 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 149 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:17:34,688 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:17:34,688 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:17:34,779 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:17:34,779 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:34,783 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:34,805 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:34,805 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:35,050 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:35,052 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:17:35,052 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 40 [2018-09-10 10:17:35,052 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:17:35,052 INFO L459 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-09-10 10:17:35,053 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-09-10 10:17:35,053 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=345, Invalid=1215, Unknown=0, NotChecked=0, Total=1560 [2018-09-10 10:17:35,053 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 40 states. [2018-09-10 10:17:38,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:17:38,188 INFO L93 Difference]: Finished difference Result 826 states and 982 transitions. [2018-09-10 10:17:38,188 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-09-10 10:17:38,188 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 119 [2018-09-10 10:17:38,188 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:17:38,191 INFO L225 Difference]: With dead ends: 826 [2018-09-10 10:17:38,191 INFO L226 Difference]: Without dead ends: 773 [2018-09-10 10:17:38,191 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 535 GetRequests, 415 SyntacticMatches, 48 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2452 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1059, Invalid=4343, Unknown=0, NotChecked=0, Total=5402 [2018-09-10 10:17:38,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 773 states. [2018-09-10 10:17:38,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 773 to 157. [2018-09-10 10:17:38,449 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 157 states. [2018-09-10 10:17:38,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 170 transitions. [2018-09-10 10:17:38,449 INFO L78 Accepts]: Start accepts. Automaton has 157 states and 170 transitions. Word has length 119 [2018-09-10 10:17:38,449 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:17:38,449 INFO L480 AbstractCegarLoop]: Abstraction has 157 states and 170 transitions. [2018-09-10 10:17:38,449 INFO L481 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-09-10 10:17:38,450 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 170 transitions. [2018-09-10 10:17:38,450 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 122 [2018-09-10 10:17:38,450 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:38,450 INFO L376 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 11, 11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:38,450 INFO L423 AbstractCegarLoop]: === Iteration 78 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:38,450 INFO L82 PathProgramCache]: Analyzing trace with hash 777037143, now seen corresponding path program 20 times [2018-09-10 10:17:38,451 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:38,451 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:38,451 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:17:38,451 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:38,451 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:38,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:38,622 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 151 proven. 238 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-10 10:17:38,622 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:38,622 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 150 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 150 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:17:38,629 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:17:38,629 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:17:38,665 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:17:38,665 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:38,667 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:38,702 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 152 proven. 210 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:38,702 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:38,974 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 152 proven. 210 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:38,995 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:38,995 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 151 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 151 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:17:39,009 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:17:39,010 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:17:39,092 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:17:39,092 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:39,096 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:39,109 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 152 proven. 210 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:39,109 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:39,342 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 152 proven. 210 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-10 10:17:39,343 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:17:39,344 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 16, 16, 16, 16] total 19 [2018-09-10 10:17:39,344 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:17:39,344 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-09-10 10:17:39,344 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-09-10 10:17:39,344 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=103, Invalid=239, Unknown=0, NotChecked=0, Total=342 [2018-09-10 10:17:39,345 INFO L87 Difference]: Start difference. First operand 157 states and 170 transitions. Second operand 19 states. [2018-09-10 10:17:39,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:17:39,909 INFO L93 Difference]: Finished difference Result 167 states and 180 transitions. [2018-09-10 10:17:39,909 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-09-10 10:17:39,910 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 121 [2018-09-10 10:17:39,910 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:17:39,911 INFO L225 Difference]: With dead ends: 167 [2018-09-10 10:17:39,911 INFO L226 Difference]: Without dead ends: 165 [2018-09-10 10:17:39,911 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 513 GetRequests, 450 SyntacticMatches, 44 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 321 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=116, Invalid=304, Unknown=0, NotChecked=0, Total=420 [2018-09-10 10:17:39,912 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165 states. [2018-09-10 10:17:40,168 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165 to 165. [2018-09-10 10:17:40,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-09-10 10:17:40,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 178 transitions. [2018-09-10 10:17:40,169 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 178 transitions. Word has length 121 [2018-09-10 10:17:40,169 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:17:40,169 INFO L480 AbstractCegarLoop]: Abstraction has 165 states and 178 transitions. [2018-09-10 10:17:40,169 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-09-10 10:17:40,169 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 178 transitions. [2018-09-10 10:17:40,170 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-09-10 10:17:40,170 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:40,170 INFO L376 BasicCegarLoop]: trace histogram [12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:40,170 INFO L423 AbstractCegarLoop]: === Iteration 79 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:40,170 INFO L82 PathProgramCache]: Analyzing trace with hash -1277952389, now seen corresponding path program 21 times [2018-09-10 10:17:40,170 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:40,171 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:40,171 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:17:40,171 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:40,171 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:40,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:40,632 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:17:40,632 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:40,632 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 152 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 152 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:17:40,640 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:17:40,640 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:17:40,682 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-09-10 10:17:40,683 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:40,685 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:41,249 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:17:41,249 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:41,531 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:17:41,550 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:41,551 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 153 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 153 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:17:41,565 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:17:41,565 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:17:41,754 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-09-10 10:17:41,754 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:41,759 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:41,786 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:17:41,786 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:42,103 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:17:42,105 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:17:42,105 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 54 [2018-09-10 10:17:42,105 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:17:42,105 INFO L459 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-09-10 10:17:42,105 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-09-10 10:17:42,106 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=575, Invalid=2287, Unknown=0, NotChecked=0, Total=2862 [2018-09-10 10:17:42,106 INFO L87 Difference]: Start difference. First operand 165 states and 178 transitions. Second operand 54 states. [2018-09-10 10:17:43,940 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:17:43,940 INFO L93 Difference]: Finished difference Result 294 states and 332 transitions. [2018-09-10 10:17:43,941 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-09-10 10:17:43,941 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 129 [2018-09-10 10:17:43,941 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:17:43,942 INFO L225 Difference]: With dead ends: 294 [2018-09-10 10:17:43,942 INFO L226 Difference]: Without dead ends: 237 [2018-09-10 10:17:43,943 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 569 GetRequests, 439 SyntacticMatches, 52 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4047 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1225, Invalid=5095, Unknown=0, NotChecked=0, Total=6320 [2018-09-10 10:17:43,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 237 states. [2018-09-10 10:17:44,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 237 to 167. [2018-09-10 10:17:44,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-09-10 10:17:44,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 180 transitions. [2018-09-10 10:17:44,234 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 180 transitions. Word has length 129 [2018-09-10 10:17:44,234 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:17:44,234 INFO L480 AbstractCegarLoop]: Abstraction has 167 states and 180 transitions. [2018-09-10 10:17:44,234 INFO L481 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-09-10 10:17:44,234 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 180 transitions. [2018-09-10 10:17:44,235 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-09-10 10:17:44,235 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:44,235 INFO L376 BasicCegarLoop]: trace histogram [12, 12, 12, 12, 11, 11, 11, 11, 11, 10, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:44,235 INFO L423 AbstractCegarLoop]: === Iteration 80 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:44,236 INFO L82 PathProgramCache]: Analyzing trace with hash -1178325753, now seen corresponding path program 46 times [2018-09-10 10:17:44,236 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:44,236 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:44,236 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:17:44,236 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:44,236 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:44,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:44,625 INFO L134 CoverageAnalysis]: Checked inductivity of 607 backedges. 275 proven. 112 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:17:44,625 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:44,625 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 154 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 154 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:17:44,633 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:17:44,633 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:17:44,671 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:17:44,671 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:44,673 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:45,223 INFO L134 CoverageAnalysis]: Checked inductivity of 607 backedges. 275 proven. 112 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:17:45,223 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:45,542 INFO L134 CoverageAnalysis]: Checked inductivity of 607 backedges. 275 proven. 112 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:17:45,562 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:45,562 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 155 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 155 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:17:45,577 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-10 10:17:45,577 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-10 10:17:45,677 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-10 10:17:45,678 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:45,682 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:45,710 INFO L134 CoverageAnalysis]: Checked inductivity of 607 backedges. 275 proven. 112 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:17:45,710 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:46,003 INFO L134 CoverageAnalysis]: Checked inductivity of 607 backedges. 275 proven. 112 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:17:46,004 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:17:46,004 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 53 [2018-09-10 10:17:46,004 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:17:46,005 INFO L459 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-09-10 10:17:46,005 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-09-10 10:17:46,005 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=539, Invalid=2217, Unknown=0, NotChecked=0, Total=2756 [2018-09-10 10:17:46,005 INFO L87 Difference]: Start difference. First operand 167 states and 180 transitions. Second operand 53 states. [2018-09-10 10:17:48,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:17:48,351 INFO L93 Difference]: Finished difference Result 364 states and 415 transitions. [2018-09-10 10:17:48,351 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-09-10 10:17:48,351 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 129 [2018-09-10 10:17:48,351 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:17:48,352 INFO L225 Difference]: With dead ends: 364 [2018-09-10 10:17:48,352 INFO L226 Difference]: Without dead ends: 307 [2018-09-10 10:17:48,353 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 580 GetRequests, 440 SyntacticMatches, 52 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4508 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1485, Invalid=6525, Unknown=0, NotChecked=0, Total=8010 [2018-09-10 10:17:48,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 307 states. [2018-09-10 10:17:48,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 307 to 167. [2018-09-10 10:17:48,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-09-10 10:17:48,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 180 transitions. [2018-09-10 10:17:48,642 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 180 transitions. Word has length 129 [2018-09-10 10:17:48,643 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:17:48,643 INFO L480 AbstractCegarLoop]: Abstraction has 167 states and 180 transitions. [2018-09-10 10:17:48,643 INFO L481 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-09-10 10:17:48,643 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 180 transitions. [2018-09-10 10:17:48,643 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-09-10 10:17:48,643 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:48,643 INFO L376 BasicCegarLoop]: trace histogram [12, 12, 12, 12, 11, 11, 11, 11, 10, 9, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:48,644 INFO L423 AbstractCegarLoop]: === Iteration 81 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:48,644 INFO L82 PathProgramCache]: Analyzing trace with hash -154759533, now seen corresponding path program 47 times [2018-09-10 10:17:48,644 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:48,644 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:48,644 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:17:48,644 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:48,645 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:48,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:49,220 INFO L134 CoverageAnalysis]: Checked inductivity of 591 backedges. 275 proven. 96 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:17:49,220 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:49,220 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 156 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 156 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:17:49,227 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:17:49,227 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:17:49,274 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2018-09-10 10:17:49,275 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:49,277 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:49,962 INFO L134 CoverageAnalysis]: Checked inductivity of 591 backedges. 275 proven. 96 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:17:49,963 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:50,225 INFO L134 CoverageAnalysis]: Checked inductivity of 591 backedges. 275 proven. 96 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:17:50,245 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:50,245 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 157 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 157 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:17:50,259 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-10 10:17:50,259 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:17:50,437 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2018-09-10 10:17:50,437 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:50,441 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:50,469 INFO L134 CoverageAnalysis]: Checked inductivity of 591 backedges. 275 proven. 96 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:17:50,469 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:50,762 INFO L134 CoverageAnalysis]: Checked inductivity of 591 backedges. 275 proven. 96 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:17:50,763 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:17:50,763 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 52 [2018-09-10 10:17:50,763 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:17:50,764 INFO L459 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-09-10 10:17:50,764 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-09-10 10:17:50,764 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=507, Invalid=2145, Unknown=0, NotChecked=0, Total=2652 [2018-09-10 10:17:50,764 INFO L87 Difference]: Start difference. First operand 167 states and 180 transitions. Second operand 52 states. [2018-09-10 10:17:53,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:17:53,738 INFO L93 Difference]: Finished difference Result 432 states and 496 transitions. [2018-09-10 10:17:53,738 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-09-10 10:17:53,738 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 129 [2018-09-10 10:17:53,738 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:17:53,740 INFO L225 Difference]: With dead ends: 432 [2018-09-10 10:17:53,740 INFO L226 Difference]: Without dead ends: 375 [2018-09-10 10:17:53,740 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 589 GetRequests, 441 SyntacticMatches, 52 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4938 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=1729, Invalid=7777, Unknown=0, NotChecked=0, Total=9506 [2018-09-10 10:17:53,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 375 states. [2018-09-10 10:17:54,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 375 to 167. [2018-09-10 10:17:54,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-09-10 10:17:54,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 180 transitions. [2018-09-10 10:17:54,047 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 180 transitions. Word has length 129 [2018-09-10 10:17:54,047 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:17:54,047 INFO L480 AbstractCegarLoop]: Abstraction has 167 states and 180 transitions. [2018-09-10 10:17:54,047 INFO L481 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-09-10 10:17:54,047 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 180 transitions. [2018-09-10 10:17:54,047 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-09-10 10:17:54,047 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:54,048 INFO L376 BasicCegarLoop]: trace histogram [12, 12, 12, 12, 11, 11, 11, 11, 9, 8, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:54,048 INFO L423 AbstractCegarLoop]: === Iteration 82 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:54,048 INFO L82 PathProgramCache]: Analyzing trace with hash 1607197471, now seen corresponding path program 48 times [2018-09-10 10:17:54,048 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:54,049 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:54,049 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:17:54,049 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:54,049 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:54,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:17:54,675 INFO L134 CoverageAnalysis]: Checked inductivity of 579 backedges. 275 proven. 84 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:17:54,675 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:54,675 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 158 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 158 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:17:54,682 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:17:54,682 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:17:54,743 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 12 check-sat command(s) [2018-09-10 10:17:54,744 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:54,746 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:55,296 INFO L134 CoverageAnalysis]: Checked inductivity of 579 backedges. 275 proven. 84 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:17:55,297 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:55,572 INFO L134 CoverageAnalysis]: Checked inductivity of 579 backedges. 275 proven. 84 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:17:55,592 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:17:55,592 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 159 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 159 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:17:55,606 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-10 10:17:55,607 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-10 10:17:55,806 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 12 check-sat command(s) [2018-09-10 10:17:55,807 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:17:55,811 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:17:55,838 INFO L134 CoverageAnalysis]: Checked inductivity of 579 backedges. 275 proven. 84 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:17:55,838 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:17:56,124 INFO L134 CoverageAnalysis]: Checked inductivity of 579 backedges. 275 proven. 84 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:17:56,125 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:17:56,126 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 51 [2018-09-10 10:17:56,126 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:17:56,126 INFO L459 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-09-10 10:17:56,126 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-09-10 10:17:56,126 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=479, Invalid=2071, Unknown=0, NotChecked=0, Total=2550 [2018-09-10 10:17:56,127 INFO L87 Difference]: Start difference. First operand 167 states and 180 transitions. Second operand 51 states. [2018-09-10 10:17:59,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:17:59,505 INFO L93 Difference]: Finished difference Result 498 states and 575 transitions. [2018-09-10 10:17:59,506 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-09-10 10:17:59,506 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 129 [2018-09-10 10:17:59,506 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:17:59,507 INFO L225 Difference]: With dead ends: 498 [2018-09-10 10:17:59,508 INFO L226 Difference]: Without dead ends: 441 [2018-09-10 10:17:59,508 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 596 GetRequests, 442 SyntacticMatches, 52 SemanticMatches, 102 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5287 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=1933, Invalid=8779, Unknown=0, NotChecked=0, Total=10712 [2018-09-10 10:17:59,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 441 states. [2018-09-10 10:17:59,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 441 to 167. [2018-09-10 10:17:59,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-09-10 10:17:59,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 180 transitions. [2018-09-10 10:17:59,822 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 180 transitions. Word has length 129 [2018-09-10 10:17:59,822 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:17:59,822 INFO L480 AbstractCegarLoop]: Abstraction has 167 states and 180 transitions. [2018-09-10 10:17:59,822 INFO L481 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-09-10 10:17:59,822 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 180 transitions. [2018-09-10 10:17:59,823 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-09-10 10:17:59,823 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:17:59,823 INFO L376 BasicCegarLoop]: trace histogram [12, 12, 12, 12, 11, 11, 11, 11, 8, 7, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:17:59,823 INFO L423 AbstractCegarLoop]: === Iteration 83 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:17:59,823 INFO L82 PathProgramCache]: Analyzing trace with hash -285939029, now seen corresponding path program 49 times [2018-09-10 10:17:59,823 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:17:59,824 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:59,824 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:17:59,824 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:17:59,824 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:17:59,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:00,136 INFO L134 CoverageAnalysis]: Checked inductivity of 571 backedges. 275 proven. 76 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:18:00,136 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:00,137 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 160 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 160 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:00,144 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:18:00,144 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:18:00,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:00,182 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:00,730 INFO L134 CoverageAnalysis]: Checked inductivity of 571 backedges. 275 proven. 76 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:18:00,730 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:01,003 INFO L134 CoverageAnalysis]: Checked inductivity of 571 backedges. 275 proven. 76 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:18:01,023 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:01,023 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 161 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 161 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:01,038 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:18:01,038 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-10 10:18:01,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:01,120 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:01,145 INFO L134 CoverageAnalysis]: Checked inductivity of 571 backedges. 275 proven. 76 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:18:01,146 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:01,433 INFO L134 CoverageAnalysis]: Checked inductivity of 571 backedges. 275 proven. 76 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:18:01,434 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:01,434 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 50 [2018-09-10 10:18:01,434 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:01,435 INFO L459 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-09-10 10:18:01,435 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-09-10 10:18:01,435 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=455, Invalid=1995, Unknown=0, NotChecked=0, Total=2450 [2018-09-10 10:18:01,435 INFO L87 Difference]: Start difference. First operand 167 states and 180 transitions. Second operand 50 states. [2018-09-10 10:18:05,228 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:05,228 INFO L93 Difference]: Finished difference Result 562 states and 652 transitions. [2018-09-10 10:18:05,229 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-09-10 10:18:05,229 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 129 [2018-09-10 10:18:05,229 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:05,231 INFO L225 Difference]: With dead ends: 562 [2018-09-10 10:18:05,231 INFO L226 Difference]: Without dead ends: 505 [2018-09-10 10:18:05,232 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 601 GetRequests, 443 SyntacticMatches, 52 SemanticMatches, 106 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5517 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=2079, Invalid=9477, Unknown=0, NotChecked=0, Total=11556 [2018-09-10 10:18:05,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 505 states. [2018-09-10 10:18:05,553 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 505 to 167. [2018-09-10 10:18:05,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-09-10 10:18:05,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 180 transitions. [2018-09-10 10:18:05,554 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 180 transitions. Word has length 129 [2018-09-10 10:18:05,554 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:05,554 INFO L480 AbstractCegarLoop]: Abstraction has 167 states and 180 transitions. [2018-09-10 10:18:05,554 INFO L481 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-09-10 10:18:05,554 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 180 transitions. [2018-09-10 10:18:05,555 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-09-10 10:18:05,555 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:05,555 INFO L376 BasicCegarLoop]: trace histogram [12, 12, 12, 12, 11, 11, 11, 11, 7, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:05,556 INFO L423 AbstractCegarLoop]: === Iteration 84 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:05,556 INFO L82 PathProgramCache]: Analyzing trace with hash 798123319, now seen corresponding path program 50 times [2018-09-10 10:18:05,556 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:05,556 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:05,556 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-10 10:18:05,556 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:05,556 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:05,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:05,889 INFO L134 CoverageAnalysis]: Checked inductivity of 567 backedges. 275 proven. 72 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:18:05,889 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:05,889 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 162 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 162 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:05,896 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:18:05,896 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:18:05,934 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:18:05,935 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:05,936 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:06,425 INFO L134 CoverageAnalysis]: Checked inductivity of 567 backedges. 275 proven. 72 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:18:06,425 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:06,703 INFO L134 CoverageAnalysis]: Checked inductivity of 567 backedges. 275 proven. 72 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:18:06,723 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:06,723 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 163 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 163 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:06,738 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-10 10:18:06,738 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-10 10:18:06,825 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-10 10:18:06,825 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:06,829 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:06,852 INFO L134 CoverageAnalysis]: Checked inductivity of 567 backedges. 275 proven. 72 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:18:06,852 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:07,136 INFO L134 CoverageAnalysis]: Checked inductivity of 567 backedges. 275 proven. 72 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:18:07,137 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:07,137 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 49 [2018-09-10 10:18:07,138 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:07,138 INFO L459 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-09-10 10:18:07,138 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-09-10 10:18:07,138 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=1917, Unknown=0, NotChecked=0, Total=2352 [2018-09-10 10:18:07,139 INFO L87 Difference]: Start difference. First operand 167 states and 180 transitions. Second operand 49 states. [2018-09-10 10:18:11,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-10 10:18:11,263 INFO L93 Difference]: Finished difference Result 624 states and 727 transitions. [2018-09-10 10:18:11,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-09-10 10:18:11,263 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 129 [2018-09-10 10:18:11,263 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-10 10:18:11,265 INFO L225 Difference]: With dead ends: 624 [2018-09-10 10:18:11,265 INFO L226 Difference]: Without dead ends: 567 [2018-09-10 10:18:11,266 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 604 GetRequests, 444 SyntacticMatches, 52 SemanticMatches, 108 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5602 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=2155, Invalid=9835, Unknown=0, NotChecked=0, Total=11990 [2018-09-10 10:18:11,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 567 states. [2018-09-10 10:18:11,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 567 to 167. [2018-09-10 10:18:11,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-09-10 10:18:11,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 180 transitions. [2018-09-10 10:18:11,848 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 180 transitions. Word has length 129 [2018-09-10 10:18:11,848 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-10 10:18:11,848 INFO L480 AbstractCegarLoop]: Abstraction has 167 states and 180 transitions. [2018-09-10 10:18:11,848 INFO L481 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-09-10 10:18:11,849 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 180 transitions. [2018-09-10 10:18:11,849 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-09-10 10:18:11,849 INFO L368 BasicCegarLoop]: Found error trace [2018-09-10 10:18:11,850 INFO L376 BasicCegarLoop]: trace histogram [12, 12, 12, 12, 11, 11, 11, 11, 7, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-10 10:18:11,850 INFO L423 AbstractCegarLoop]: === Iteration 85 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_seq_true_unreach_call_true_termination_i____VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-10 10:18:11,850 INFO L82 PathProgramCache]: Analyzing trace with hash -903540029, now seen corresponding path program 51 times [2018-09-10 10:18:11,850 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-10 10:18:11,851 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:11,851 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-10 10:18:11,851 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-10 10:18:11,851 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-10 10:18:11,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-10 10:18:12,486 INFO L134 CoverageAnalysis]: Checked inductivity of 567 backedges. 275 proven. 72 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:18:12,486 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:12,486 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 164 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 164 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-10 10:18:12,494 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:18:12,494 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:18:12,541 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-09-10 10:18:12,541 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:12,543 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:13,005 INFO L134 CoverageAnalysis]: Checked inductivity of 567 backedges. 275 proven. 72 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:18:13,005 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:13,312 INFO L134 CoverageAnalysis]: Checked inductivity of 567 backedges. 275 proven. 72 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:18:13,333 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-10 10:18:13,333 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 165 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 165 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-10 10:18:13,359 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-10 10:18:13,359 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-10 10:18:13,561 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-09-10 10:18:13,561 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-10 10:18:13,566 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-10 10:18:13,602 INFO L134 CoverageAnalysis]: Checked inductivity of 567 backedges. 275 proven. 72 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:18:13,602 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-10 10:18:13,983 INFO L134 CoverageAnalysis]: Checked inductivity of 567 backedges. 275 proven. 72 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-10 10:18:13,984 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-10 10:18:13,984 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 48 [2018-09-10 10:18:13,984 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-10 10:18:13,985 INFO L459 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-09-10 10:18:13,985 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-09-10 10:18:13,985 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=419, Invalid=1837, Unknown=0, NotChecked=0, Total=2256 [2018-09-10 10:18:13,985 INFO L87 Difference]: Start difference. First operand 167 states and 180 transitions. Second operand 48 states. Received shutdown request... [2018-09-10 10:18:16,942 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2018-09-10 10:18:16,942 WARN L549 AbstractCegarLoop]: Verification canceled [2018-09-10 10:18:16,946 WARN L206 ceAbstractionStarter]: Timeout [2018-09-10 10:18:16,946 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 10.09 10:18:16 BoogieIcfgContainer [2018-09-10 10:18:16,947 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-09-10 10:18:16,947 INFO L168 Benchmark]: Toolchain (without parser) took 236181.55 ms. Allocated memory was 1.5 GB in the beginning and 2.1 GB in the end (delta: 602.4 MB). Free memory was 1.4 GB in the beginning and 1.8 GB in the end (delta: -439.7 MB). Peak memory consumption was 162.7 MB. Max. memory is 7.1 GB. [2018-09-10 10:18:16,948 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-09-10 10:18:16,948 INFO L168 Benchmark]: CACSL2BoogieTranslator took 306.47 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. [2018-09-10 10:18:16,948 INFO L168 Benchmark]: Boogie Procedure Inliner took 22.53 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-09-10 10:18:16,948 INFO L168 Benchmark]: Boogie Preprocessor took 22.14 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-09-10 10:18:16,948 INFO L168 Benchmark]: RCFGBuilder took 498.55 ms. Allocated memory was 1.5 GB in the beginning and 2.2 GB in the end (delta: 699.4 MB). Free memory was 1.4 GB in the beginning and 2.1 GB in the end (delta: -750.9 MB). Peak memory consumption was 26.7 MB. Max. memory is 7.1 GB. [2018-09-10 10:18:16,949 INFO L168 Benchmark]: TraceAbstraction took 235325.53 ms. Allocated memory was 2.2 GB in the beginning and 2.1 GB in the end (delta: -97.0 MB). Free memory was 2.1 GB in the beginning and 1.8 GB in the end (delta: 300.6 MB). Peak memory consumption was 203.6 MB. Max. memory is 7.1 GB. [2018-09-10 10:18:16,951 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 306.47 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 22.53 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Preprocessor took 22.14 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * RCFGBuilder took 498.55 ms. Allocated memory was 1.5 GB in the beginning and 2.2 GB in the end (delta: 699.4 MB). Free memory was 1.4 GB in the beginning and 2.1 GB in the end (delta: -750.9 MB). Peak memory consumption was 26.7 MB. Max. memory is 7.1 GB. * TraceAbstraction took 235325.53 ms. Allocated memory was 2.2 GB in the beginning and 2.1 GB in the end (delta: -97.0 MB). Free memory was 2.1 GB in the beginning and 1.8 GB in the end (delta: 300.6 MB). Peak memory consumption was 203.6 MB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 5]: Timeout (TraceAbstraction) Unable to prove that call of __VERIFIER_error() unreachable (line 5). Cancelled while BasicCegarLoop was constructing difference of abstraction (167states) and FLOYD_HOARE automaton (currently 61 states, 48 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 100 known predicates. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 27 locations, 1 error locations. TIMEOUT Result, 235.2s OverallTime, 85 OverallIterations, 12 TraceHistogramMax, 113.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 3985 SDtfs, 10399 SDslu, 34847 SDs, 0 SdLazy, 31593 SolverSat, 6751 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 29.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 32995 GetRequests, 25340 SyntacticMatches, 2904 SemanticMatches, 4750 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 167563 ImplicationChecksByTransitivity, 123.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=167occurred in iteration=79, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 9.5s AutomataMinimizationTime, 84 MinimizatonAttempts, 14482 StatesRemovedByMinimization, 73 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.8s SsaConstructionTime, 9.4s SatisfiabilityAnalysisTime, 97.1s InterpolantComputationTime, 21951 NumberOfCodeBlocks, 21951 NumberOfCodeBlocksAsserted, 875 NumberOfCheckSat, 36134 ConstructedInterpolants, 0 QuantifiedInterpolants, 14393820 SizeOfPredicates, 1048 NumberOfNonLiveVariables, 31524 ConjunctsInSsa, 3312 ConjunctsInUnsatCore, 413 InterpolantComputations, 3 PerfectInterpolantSequences, 94282/116072 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/seq_true-unreach-call_true-termination.i_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-Benchmark-0-2018-09-10_10-18-16-958.csv Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/seq_true-unreach-call_true-termination.i_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-TraceAbstractionBenchmarks-0-2018-09-10_10-18-16-958.csv Completed graceful shutdown