java -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data --generate-csv --csv-dir csv -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml -s ../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf -i ../../../trunk/examples/svcomp/loop-acceleration/array_true-unreach-call2_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-dace188-m [2018-09-14 15:46:12,826 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-09-14 15:46:12,828 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-09-14 15:46:12,843 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-09-14 15:46:12,843 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-09-14 15:46:12,844 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-09-14 15:46:12,846 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-09-14 15:46:12,848 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-09-14 15:46:12,850 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-09-14 15:46:12,851 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-09-14 15:46:12,852 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-09-14 15:46:12,852 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-09-14 15:46:12,853 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-09-14 15:46:12,854 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-09-14 15:46:12,857 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-09-14 15:46:12,858 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-09-14 15:46:12,862 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-09-14 15:46:12,864 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-09-14 15:46:12,870 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-09-14 15:46:12,872 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-09-14 15:46:12,875 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-09-14 15:46:12,879 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-09-14 15:46:12,884 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2018-09-14 15:46:12,899 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf [2018-09-14 15:46:12,925 INFO L110 SettingsManager]: Loading preferences was successful [2018-09-14 15:46:12,927 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-09-14 15:46:12,928 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-09-14 15:46:12,928 INFO L133 SettingsManager]: * User list type=DISABLED [2018-09-14 15:46:12,928 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-09-14 15:46:12,928 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-09-14 15:46:12,929 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-09-14 15:46:12,929 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-09-14 15:46:12,929 INFO L133 SettingsManager]: * Log string format=TERM [2018-09-14 15:46:12,929 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-09-14 15:46:12,929 INFO L133 SettingsManager]: * Interval Domain=false [2018-09-14 15:46:12,930 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-09-14 15:46:12,930 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-09-14 15:46:12,932 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-09-14 15:46:12,932 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-09-14 15:46:12,932 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-09-14 15:46:12,932 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-09-14 15:46:12,932 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-09-14 15:46:12,932 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-09-14 15:46:12,933 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-09-14 15:46:12,933 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-09-14 15:46:12,933 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-09-14 15:46:12,933 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-09-14 15:46:12,934 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-09-14 15:46:12,934 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-09-14 15:46:12,934 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-09-14 15:46:12,934 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-09-14 15:46:12,934 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-09-14 15:46:12,935 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-09-14 15:46:12,935 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-09-14 15:46:12,935 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-09-14 15:46:12,935 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-09-14 15:46:12,935 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-09-14 15:46:12,998 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-09-14 15:46:13,011 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-09-14 15:46:13,015 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-09-14 15:46:13,016 INFO L271 PluginConnector]: Initializing CDTParser... [2018-09-14 15:46:13,017 INFO L276 PluginConnector]: CDTParser initialized [2018-09-14 15:46:13,018 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-acceleration/array_true-unreach-call2_true-termination.i [2018-09-14 15:46:13,371 INFO L221 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5ec083bfc/3b8e546035cf4b1691b38e86348a97f4/FLAG576f66b4b [2018-09-14 15:46:13,484 INFO L277 CDTParser]: Found 1 translation units. [2018-09-14 15:46:13,485 INFO L159 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-acceleration/array_true-unreach-call2_true-termination.i [2018-09-14 15:46:13,490 INFO L325 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5ec083bfc/3b8e546035cf4b1691b38e86348a97f4/FLAG576f66b4b [2018-09-14 15:46:13,504 INFO L333 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5ec083bfc/3b8e546035cf4b1691b38e86348a97f4 [2018-09-14 15:46:13,515 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-09-14 15:46:13,518 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-09-14 15:46:13,519 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-09-14 15:46:13,520 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-09-14 15:46:13,526 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-09-14 15:46:13,527 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.09 03:46:13" (1/1) ... [2018-09-14 15:46:13,530 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@37de77e5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:46:13, skipping insertion in model container [2018-09-14 15:46:13,531 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.09 03:46:13" (1/1) ... [2018-09-14 15:46:13,543 INFO L160 ieTranslatorObserver]: Starting translation in SV-COMP mode [2018-09-14 15:46:13,757 INFO L170 PostProcessor]: Settings: Checked method=main [2018-09-14 15:46:13,777 INFO L424 MainDispatcher]: Starting main dispatcher in SV-COMP mode [2018-09-14 15:46:13,782 INFO L170 PostProcessor]: Settings: Checked method=main [2018-09-14 15:46:13,793 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:46:13 WrapperNode [2018-09-14 15:46:13,793 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-09-14 15:46:13,794 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-09-14 15:46:13,794 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-09-14 15:46:13,794 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-09-14 15:46:13,802 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:46:13" (1/1) ... [2018-09-14 15:46:13,809 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:46:13" (1/1) ... [2018-09-14 15:46:13,815 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-09-14 15:46:13,815 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-09-14 15:46:13,815 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-09-14 15:46:13,816 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-09-14 15:46:13,826 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:46:13" (1/1) ... [2018-09-14 15:46:13,826 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:46:13" (1/1) ... [2018-09-14 15:46:13,827 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:46:13" (1/1) ... [2018-09-14 15:46:13,827 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:46:13" (1/1) ... [2018-09-14 15:46:13,829 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:46:13" (1/1) ... [2018-09-14 15:46:13,834 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:46:13" (1/1) ... [2018-09-14 15:46:13,835 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:46:13" (1/1) ... [2018-09-14 15:46:13,837 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-09-14 15:46:13,837 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-09-14 15:46:13,837 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-09-14 15:46:13,838 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-09-14 15:46:13,839 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:46:13" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-09-14 15:46:13,903 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-09-14 15:46:13,904 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-09-14 15:46:13,904 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-09-14 15:46:13,904 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-09-14 15:46:13,904 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-09-14 15:46:13,904 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-09-14 15:46:13,904 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-09-14 15:46:13,905 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-09-14 15:46:14,166 INFO L353 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-09-14 15:46:14,167 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.09 03:46:14 BoogieIcfgContainer [2018-09-14 15:46:14,167 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-09-14 15:46:14,168 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-09-14 15:46:14,168 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-09-14 15:46:14,171 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-09-14 15:46:14,172 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 14.09 03:46:13" (1/3) ... [2018-09-14 15:46:14,172 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3b668537 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.09 03:46:14, skipping insertion in model container [2018-09-14 15:46:14,173 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:46:13" (2/3) ... [2018-09-14 15:46:14,173 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3b668537 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.09 03:46:14, skipping insertion in model container [2018-09-14 15:46:14,173 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.09 03:46:14" (3/3) ... [2018-09-14 15:46:14,175 INFO L112 eAbstractionObserver]: Analyzing ICFG array_true-unreach-call2_true-termination.i [2018-09-14 15:46:14,185 INFO L137 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-09-14 15:46:14,193 INFO L149 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-09-14 15:46:14,245 INFO L130 ementStrategyFactory]: Using default assertion order modulation [2018-09-14 15:46:14,246 INFO L381 AbstractCegarLoop]: Interprodecural is true [2018-09-14 15:46:14,246 INFO L382 AbstractCegarLoop]: Hoare is true [2018-09-14 15:46:14,246 INFO L383 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-09-14 15:46:14,246 INFO L384 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-09-14 15:46:14,246 INFO L385 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-09-14 15:46:14,247 INFO L386 AbstractCegarLoop]: Difference is false [2018-09-14 15:46:14,247 INFO L387 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-09-14 15:46:14,247 INFO L392 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-09-14 15:46:14,264 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states. [2018-09-14 15:46:14,271 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2018-09-14 15:46:14,271 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:14,272 INFO L376 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:14,273 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:14,278 INFO L82 PathProgramCache]: Analyzing trace with hash -1870586046, now seen corresponding path program 1 times [2018-09-14 15:46:14,281 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:14,332 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:14,332 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:46:14,332 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:14,332 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:14,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:14,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:14,391 INFO L313 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-09-14 15:46:14,392 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-09-14 15:46:14,392 INFO L265 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-09-14 15:46:14,396 INFO L459 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-09-14 15:46:14,411 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-09-14 15:46:14,412 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-09-14 15:46:14,414 INFO L87 Difference]: Start difference. First operand 19 states. Second operand 2 states. [2018-09-14 15:46:14,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:14,436 INFO L93 Difference]: Finished difference Result 30 states and 33 transitions. [2018-09-14 15:46:14,436 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-09-14 15:46:14,437 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 10 [2018-09-14 15:46:14,438 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:14,447 INFO L225 Difference]: With dead ends: 30 [2018-09-14 15:46:14,447 INFO L226 Difference]: Without dead ends: 13 [2018-09-14 15:46:14,451 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-09-14 15:46:14,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states. [2018-09-14 15:46:14,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 13. [2018-09-14 15:46:14,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13 states. [2018-09-14 15:46:14,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 13 transitions. [2018-09-14 15:46:14,491 INFO L78 Accepts]: Start accepts. Automaton has 13 states and 13 transitions. Word has length 10 [2018-09-14 15:46:14,491 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:14,492 INFO L480 AbstractCegarLoop]: Abstraction has 13 states and 13 transitions. [2018-09-14 15:46:14,492 INFO L481 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-09-14 15:46:14,492 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 13 transitions. [2018-09-14 15:46:14,492 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-09-14 15:46:14,493 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:14,493 INFO L376 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:14,493 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:14,494 INFO L82 PathProgramCache]: Analyzing trace with hash 1861068280, now seen corresponding path program 1 times [2018-09-14 15:46:14,494 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:14,495 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:14,495 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:46:14,496 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:14,496 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:14,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:14,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:14,579 INFO L313 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-09-14 15:46:14,580 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-09-14 15:46:14,580 INFO L265 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-09-14 15:46:14,581 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-09-14 15:46:14,582 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-09-14 15:46:14,582 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-09-14 15:46:14,583 INFO L87 Difference]: Start difference. First operand 13 states and 13 transitions. Second operand 3 states. [2018-09-14 15:46:14,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:14,748 INFO L93 Difference]: Finished difference Result 21 states and 21 transitions. [2018-09-14 15:46:14,749 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-09-14 15:46:14,749 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-09-14 15:46:14,750 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:14,750 INFO L225 Difference]: With dead ends: 21 [2018-09-14 15:46:14,751 INFO L226 Difference]: Without dead ends: 16 [2018-09-14 15:46:14,752 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-09-14 15:46:14,753 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2018-09-14 15:46:14,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 15. [2018-09-14 15:46:14,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2018-09-14 15:46:14,761 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 15 transitions. [2018-09-14 15:46:14,762 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 15 transitions. Word has length 11 [2018-09-14 15:46:14,762 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:14,763 INFO L480 AbstractCegarLoop]: Abstraction has 15 states and 15 transitions. [2018-09-14 15:46:14,763 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-09-14 15:46:14,763 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 15 transitions. [2018-09-14 15:46:14,764 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-09-14 15:46:14,764 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:14,764 INFO L376 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:14,764 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:14,765 INFO L82 PathProgramCache]: Analyzing trace with hash 996352094, now seen corresponding path program 1 times [2018-09-14 15:46:14,765 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:14,767 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:14,767 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:46:14,767 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:14,767 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:14,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:14,945 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:14,945 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:14,945 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:14,958 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:46:14,958 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:46:14,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:14,991 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:15,013 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:15,013 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:15,098 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:15,122 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:15,122 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:15,139 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:46:15,140 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:46:15,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:15,157 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:15,162 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:15,162 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:15,179 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:15,183 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:46:15,184 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 6 [2018-09-14 15:46:15,184 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:46:15,184 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-09-14 15:46:15,185 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-09-14 15:46:15,185 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-09-14 15:46:15,186 INFO L87 Difference]: Start difference. First operand 15 states and 15 transitions. Second operand 4 states. [2018-09-14 15:46:15,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:15,261 INFO L93 Difference]: Finished difference Result 24 states and 24 transitions. [2018-09-14 15:46:15,262 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-09-14 15:46:15,263 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 14 [2018-09-14 15:46:15,263 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:15,264 INFO L225 Difference]: With dead ends: 24 [2018-09-14 15:46:15,264 INFO L226 Difference]: Without dead ends: 19 [2018-09-14 15:46:15,266 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 54 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-09-14 15:46:15,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2018-09-14 15:46:15,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 18. [2018-09-14 15:46:15,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2018-09-14 15:46:15,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 18 transitions. [2018-09-14 15:46:15,273 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 18 transitions. Word has length 14 [2018-09-14 15:46:15,274 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:15,275 INFO L480 AbstractCegarLoop]: Abstraction has 18 states and 18 transitions. [2018-09-14 15:46:15,275 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-09-14 15:46:15,275 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 18 transitions. [2018-09-14 15:46:15,276 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-09-14 15:46:15,276 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:15,276 INFO L376 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:15,277 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:15,277 INFO L82 PathProgramCache]: Analyzing trace with hash 1450296376, now seen corresponding path program 2 times [2018-09-14 15:46:15,277 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:15,279 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:15,279 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:46:15,279 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:15,280 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:15,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:15,372 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:15,373 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:15,373 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:15,388 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:46:15,388 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:46:15,428 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:46:15,428 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:15,430 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:15,436 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:15,437 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:15,723 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:15,745 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:15,746 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:15,761 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:46:15,761 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:46:15,782 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:46:15,783 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:15,787 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:15,792 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:15,793 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:15,825 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:15,828 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:46:15,828 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 8 [2018-09-14 15:46:15,828 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:46:15,829 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-09-14 15:46:15,829 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-09-14 15:46:15,830 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-09-14 15:46:15,831 INFO L87 Difference]: Start difference. First operand 18 states and 18 transitions. Second operand 5 states. [2018-09-14 15:46:15,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:15,871 INFO L93 Difference]: Finished difference Result 27 states and 27 transitions. [2018-09-14 15:46:15,873 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-09-14 15:46:15,873 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-09-14 15:46:15,873 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:15,874 INFO L225 Difference]: With dead ends: 27 [2018-09-14 15:46:15,874 INFO L226 Difference]: Without dead ends: 22 [2018-09-14 15:46:15,876 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 71 GetRequests, 65 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-09-14 15:46:15,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2018-09-14 15:46:15,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 21. [2018-09-14 15:46:15,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2018-09-14 15:46:15,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 21 transitions. [2018-09-14 15:46:15,882 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 21 transitions. Word has length 17 [2018-09-14 15:46:15,882 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:15,882 INFO L480 AbstractCegarLoop]: Abstraction has 21 states and 21 transitions. [2018-09-14 15:46:15,882 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-09-14 15:46:15,883 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 21 transitions. [2018-09-14 15:46:15,883 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-09-14 15:46:15,883 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:15,884 INFO L376 BasicCegarLoop]: trace histogram [4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:15,884 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:15,884 INFO L82 PathProgramCache]: Analyzing trace with hash 52386334, now seen corresponding path program 3 times [2018-09-14 15:46:15,884 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:15,885 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:15,885 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:46:15,886 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:15,886 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:15,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:15,978 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:15,978 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:15,979 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:15,992 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:46:15,992 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:46:16,039 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-09-14 15:46:16,040 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:16,042 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:16,048 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:16,048 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:16,250 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:16,271 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:16,271 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:16,287 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:46:16,287 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:46:16,317 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-09-14 15:46:16,317 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:16,321 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:16,327 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:16,328 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:16,348 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:16,351 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:46:16,352 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 10 [2018-09-14 15:46:16,352 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:46:16,353 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-09-14 15:46:16,353 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-09-14 15:46:16,353 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-09-14 15:46:16,354 INFO L87 Difference]: Start difference. First operand 21 states and 21 transitions. Second operand 6 states. [2018-09-14 15:46:16,397 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:16,398 INFO L93 Difference]: Finished difference Result 30 states and 30 transitions. [2018-09-14 15:46:16,398 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-09-14 15:46:16,399 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 20 [2018-09-14 15:46:16,399 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:16,400 INFO L225 Difference]: With dead ends: 30 [2018-09-14 15:46:16,400 INFO L226 Difference]: Without dead ends: 25 [2018-09-14 15:46:16,401 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 76 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-09-14 15:46:16,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2018-09-14 15:46:16,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 24. [2018-09-14 15:46:16,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-09-14 15:46:16,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 24 transitions. [2018-09-14 15:46:16,406 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 24 transitions. Word has length 20 [2018-09-14 15:46:16,406 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:16,407 INFO L480 AbstractCegarLoop]: Abstraction has 24 states and 24 transitions. [2018-09-14 15:46:16,407 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-09-14 15:46:16,407 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 24 transitions. [2018-09-14 15:46:16,408 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-09-14 15:46:16,408 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:16,408 INFO L376 BasicCegarLoop]: trace histogram [5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:16,408 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:16,409 INFO L82 PathProgramCache]: Analyzing trace with hash -1082772872, now seen corresponding path program 4 times [2018-09-14 15:46:16,409 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:16,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:16,410 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:46:16,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:16,410 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:16,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:16,514 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:16,515 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:16,515 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:16,523 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:46:16,523 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:46:16,536 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:46:16,536 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:16,538 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:16,544 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:16,544 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:16,991 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:17,012 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:17,012 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:17,029 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:46:17,029 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:46:17,051 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:46:17,051 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:17,056 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:17,062 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:17,063 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:17,081 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:17,084 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:46:17,085 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 12 [2018-09-14 15:46:17,085 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:46:17,086 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-09-14 15:46:17,086 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-09-14 15:46:17,087 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-09-14 15:46:17,088 INFO L87 Difference]: Start difference. First operand 24 states and 24 transitions. Second operand 7 states. [2018-09-14 15:46:17,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:17,133 INFO L93 Difference]: Finished difference Result 33 states and 33 transitions. [2018-09-14 15:46:17,134 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-09-14 15:46:17,134 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 23 [2018-09-14 15:46:17,134 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:17,135 INFO L225 Difference]: With dead ends: 33 [2018-09-14 15:46:17,135 INFO L226 Difference]: Without dead ends: 28 [2018-09-14 15:46:17,135 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 97 GetRequests, 87 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-09-14 15:46:17,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2018-09-14 15:46:17,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 27. [2018-09-14 15:46:17,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27 states. [2018-09-14 15:46:17,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 27 transitions. [2018-09-14 15:46:17,140 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 27 transitions. Word has length 23 [2018-09-14 15:46:17,141 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:17,141 INFO L480 AbstractCegarLoop]: Abstraction has 27 states and 27 transitions. [2018-09-14 15:46:17,141 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-09-14 15:46:17,141 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 27 transitions. [2018-09-14 15:46:17,142 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-09-14 15:46:17,142 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:17,142 INFO L376 BasicCegarLoop]: trace histogram [6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:17,143 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:17,143 INFO L82 PathProgramCache]: Analyzing trace with hash -38190114, now seen corresponding path program 5 times [2018-09-14 15:46:17,143 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:17,144 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:17,144 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:46:17,144 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:17,144 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:17,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:17,259 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:17,259 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:17,260 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:17,277 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:46:17,277 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:46:17,329 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-09-14 15:46:17,329 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:17,332 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:17,339 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:17,339 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:17,549 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:17,571 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:17,571 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:17,586 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:46:17,587 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:46:17,626 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-09-14 15:46:17,626 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:17,630 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:17,637 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:17,637 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:17,653 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:17,654 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:46:17,655 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 14 [2018-09-14 15:46:17,655 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:46:17,656 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-09-14 15:46:17,656 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-09-14 15:46:17,657 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-09-14 15:46:17,657 INFO L87 Difference]: Start difference. First operand 27 states and 27 transitions. Second operand 8 states. [2018-09-14 15:46:17,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:17,724 INFO L93 Difference]: Finished difference Result 36 states and 36 transitions. [2018-09-14 15:46:17,727 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-09-14 15:46:17,727 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 26 [2018-09-14 15:46:17,727 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:17,728 INFO L225 Difference]: With dead ends: 36 [2018-09-14 15:46:17,728 INFO L226 Difference]: Without dead ends: 31 [2018-09-14 15:46:17,729 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 110 GetRequests, 98 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-09-14 15:46:17,729 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2018-09-14 15:46:17,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 30. [2018-09-14 15:46:17,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-09-14 15:46:17,734 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 30 transitions. [2018-09-14 15:46:17,734 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 30 transitions. Word has length 26 [2018-09-14 15:46:17,735 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:17,735 INFO L480 AbstractCegarLoop]: Abstraction has 30 states and 30 transitions. [2018-09-14 15:46:17,735 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-09-14 15:46:17,735 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 30 transitions. [2018-09-14 15:46:17,736 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-09-14 15:46:17,736 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:17,736 INFO L376 BasicCegarLoop]: trace histogram [7, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:17,736 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:17,736 INFO L82 PathProgramCache]: Analyzing trace with hash 2088693944, now seen corresponding path program 6 times [2018-09-14 15:46:17,736 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:17,737 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:17,737 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:46:17,737 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:17,738 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:17,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:17,901 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:17,901 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:17,901 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:17,911 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:46:17,912 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:46:17,964 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-09-14 15:46:17,965 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:17,967 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:17,975 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:17,975 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:18,342 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:18,364 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:18,364 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:18,380 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:46:18,380 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:46:18,449 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-09-14 15:46:18,449 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:18,453 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:18,461 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:18,461 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:18,480 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:18,482 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:46:18,482 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 16 [2018-09-14 15:46:18,483 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:46:18,483 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-09-14 15:46:18,484 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-09-14 15:46:18,484 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-09-14 15:46:18,485 INFO L87 Difference]: Start difference. First operand 30 states and 30 transitions. Second operand 9 states. [2018-09-14 15:46:18,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:18,543 INFO L93 Difference]: Finished difference Result 39 states and 39 transitions. [2018-09-14 15:46:18,547 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-09-14 15:46:18,547 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 29 [2018-09-14 15:46:18,547 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:18,548 INFO L225 Difference]: With dead ends: 39 [2018-09-14 15:46:18,548 INFO L226 Difference]: Without dead ends: 34 [2018-09-14 15:46:18,548 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 123 GetRequests, 109 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-09-14 15:46:18,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-09-14 15:46:18,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 33. [2018-09-14 15:46:18,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33 states. [2018-09-14 15:46:18,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 33 transitions. [2018-09-14 15:46:18,553 INFO L78 Accepts]: Start accepts. Automaton has 33 states and 33 transitions. Word has length 29 [2018-09-14 15:46:18,554 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:18,554 INFO L480 AbstractCegarLoop]: Abstraction has 33 states and 33 transitions. [2018-09-14 15:46:18,554 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-09-14 15:46:18,554 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 33 transitions. [2018-09-14 15:46:18,555 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-09-14 15:46:18,555 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:18,555 INFO L376 BasicCegarLoop]: trace histogram [8, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:18,556 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:18,556 INFO L82 PathProgramCache]: Analyzing trace with hash 439147934, now seen corresponding path program 7 times [2018-09-14 15:46:18,556 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:18,557 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:18,557 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:46:18,557 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:18,557 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:18,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:18,822 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:18,823 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:18,823 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:18,831 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:46:18,831 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:46:18,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:18,857 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:18,865 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:18,865 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:19,052 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:19,073 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:19,073 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:19,092 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:46:19,092 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:46:19,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:19,117 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:19,125 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:19,125 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:19,149 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:19,152 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:46:19,153 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 18 [2018-09-14 15:46:19,153 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:46:19,154 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-09-14 15:46:19,154 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-09-14 15:46:19,154 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-09-14 15:46:19,155 INFO L87 Difference]: Start difference. First operand 33 states and 33 transitions. Second operand 10 states. [2018-09-14 15:46:19,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:19,234 INFO L93 Difference]: Finished difference Result 42 states and 42 transitions. [2018-09-14 15:46:19,242 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-09-14 15:46:19,242 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 32 [2018-09-14 15:46:19,242 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:19,243 INFO L225 Difference]: With dead ends: 42 [2018-09-14 15:46:19,243 INFO L226 Difference]: Without dead ends: 37 [2018-09-14 15:46:19,244 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 120 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-09-14 15:46:19,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2018-09-14 15:46:19,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 36. [2018-09-14 15:46:19,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2018-09-14 15:46:19,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 36 transitions. [2018-09-14 15:46:19,248 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 36 transitions. Word has length 32 [2018-09-14 15:46:19,248 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:19,249 INFO L480 AbstractCegarLoop]: Abstraction has 36 states and 36 transitions. [2018-09-14 15:46:19,249 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-09-14 15:46:19,249 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 36 transitions. [2018-09-14 15:46:19,250 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-09-14 15:46:19,250 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:19,250 INFO L376 BasicCegarLoop]: trace histogram [9, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:19,250 INFO L423 AbstractCegarLoop]: === Iteration 10 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:19,251 INFO L82 PathProgramCache]: Analyzing trace with hash 1829764856, now seen corresponding path program 8 times [2018-09-14 15:46:19,251 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:19,251 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:19,252 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:46:19,252 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:19,252 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:19,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:19,395 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:19,396 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:19,396 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:19,404 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:46:19,405 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:46:19,430 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:46:19,430 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:19,432 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:19,440 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:19,441 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:19,733 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:19,755 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:19,755 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:19,771 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:46:19,771 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:46:19,804 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:46:19,804 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:19,807 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:19,815 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:19,816 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:19,835 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:19,837 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:46:19,838 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 20 [2018-09-14 15:46:19,838 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:46:19,838 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-09-14 15:46:19,839 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-09-14 15:46:19,839 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-09-14 15:46:19,839 INFO L87 Difference]: Start difference. First operand 36 states and 36 transitions. Second operand 11 states. [2018-09-14 15:46:20,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:20,017 INFO L93 Difference]: Finished difference Result 45 states and 45 transitions. [2018-09-14 15:46:20,022 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-09-14 15:46:20,022 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 35 [2018-09-14 15:46:20,022 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:20,023 INFO L225 Difference]: With dead ends: 45 [2018-09-14 15:46:20,023 INFO L226 Difference]: Without dead ends: 40 [2018-09-14 15:46:20,024 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 149 GetRequests, 131 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-09-14 15:46:20,024 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-09-14 15:46:20,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 39. [2018-09-14 15:46:20,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2018-09-14 15:46:20,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 39 transitions. [2018-09-14 15:46:20,028 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 39 transitions. Word has length 35 [2018-09-14 15:46:20,028 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:20,029 INFO L480 AbstractCegarLoop]: Abstraction has 39 states and 39 transitions. [2018-09-14 15:46:20,029 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-09-14 15:46:20,029 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 39 transitions. [2018-09-14 15:46:20,030 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-09-14 15:46:20,030 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:20,030 INFO L376 BasicCegarLoop]: trace histogram [10, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:20,030 INFO L423 AbstractCegarLoop]: === Iteration 11 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:20,031 INFO L82 PathProgramCache]: Analyzing trace with hash 443950942, now seen corresponding path program 9 times [2018-09-14 15:46:20,031 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:20,031 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:20,032 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:46:20,032 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:20,032 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:20,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:20,256 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:20,257 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:20,257 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:20,266 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:46:20,267 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:46:20,301 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-09-14 15:46:20,301 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:20,304 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:20,313 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:20,313 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:20,541 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:20,563 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:20,563 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:20,578 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:46:20,578 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:46:20,769 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-09-14 15:46:20,769 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:20,774 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:20,782 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:20,782 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:20,849 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:20,853 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:46:20,853 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 22 [2018-09-14 15:46:20,853 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:46:20,854 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-09-14 15:46:20,854 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-09-14 15:46:20,855 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-09-14 15:46:20,855 INFO L87 Difference]: Start difference. First operand 39 states and 39 transitions. Second operand 12 states. [2018-09-14 15:46:20,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:20,959 INFO L93 Difference]: Finished difference Result 48 states and 48 transitions. [2018-09-14 15:46:20,959 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-09-14 15:46:20,959 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 38 [2018-09-14 15:46:20,960 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:20,961 INFO L225 Difference]: With dead ends: 48 [2018-09-14 15:46:20,961 INFO L226 Difference]: Without dead ends: 43 [2018-09-14 15:46:20,962 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 162 GetRequests, 142 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-09-14 15:46:20,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2018-09-14 15:46:20,965 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 42. [2018-09-14 15:46:20,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2018-09-14 15:46:20,966 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 42 transitions. [2018-09-14 15:46:20,966 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 42 transitions. Word has length 38 [2018-09-14 15:46:20,967 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:20,967 INFO L480 AbstractCegarLoop]: Abstraction has 42 states and 42 transitions. [2018-09-14 15:46:20,967 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-09-14 15:46:20,967 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 42 transitions. [2018-09-14 15:46:20,967 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-09-14 15:46:20,968 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:20,968 INFO L376 BasicCegarLoop]: trace histogram [11, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:20,968 INFO L423 AbstractCegarLoop]: === Iteration 12 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:20,968 INFO L82 PathProgramCache]: Analyzing trace with hash -1112711880, now seen corresponding path program 10 times [2018-09-14 15:46:20,969 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:20,969 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:20,969 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:46:20,970 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:20,970 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:20,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:21,232 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:21,233 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:21,233 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:21,241 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:46:21,241 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:46:21,269 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:46:21,270 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:21,271 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:21,279 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:21,280 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:21,817 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:21,838 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:21,838 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:21,870 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:46:21,871 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:46:21,903 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:46:21,904 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:21,907 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:21,916 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:21,917 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:21,973 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:21,975 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:46:21,976 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 24 [2018-09-14 15:46:21,976 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:46:21,976 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-09-14 15:46:21,977 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-09-14 15:46:21,977 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-09-14 15:46:21,977 INFO L87 Difference]: Start difference. First operand 42 states and 42 transitions. Second operand 13 states. [2018-09-14 15:46:22,271 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:22,271 INFO L93 Difference]: Finished difference Result 51 states and 51 transitions. [2018-09-14 15:46:22,271 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-09-14 15:46:22,272 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 41 [2018-09-14 15:46:22,272 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:22,272 INFO L225 Difference]: With dead ends: 51 [2018-09-14 15:46:22,273 INFO L226 Difference]: Without dead ends: 46 [2018-09-14 15:46:22,273 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 175 GetRequests, 153 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-09-14 15:46:22,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states. [2018-09-14 15:46:22,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 45. [2018-09-14 15:46:22,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-09-14 15:46:22,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 45 transitions. [2018-09-14 15:46:22,278 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 45 transitions. Word has length 41 [2018-09-14 15:46:22,278 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:22,278 INFO L480 AbstractCegarLoop]: Abstraction has 45 states and 45 transitions. [2018-09-14 15:46:22,278 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-09-14 15:46:22,279 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 45 transitions. [2018-09-14 15:46:22,279 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-09-14 15:46:22,279 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:22,280 INFO L376 BasicCegarLoop]: trace histogram [12, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:22,280 INFO L423 AbstractCegarLoop]: === Iteration 13 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:22,280 INFO L82 PathProgramCache]: Analyzing trace with hash 1402020126, now seen corresponding path program 11 times [2018-09-14 15:46:22,280 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:22,281 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:22,281 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:46:22,281 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:22,281 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:22,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:22,489 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:22,490 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:22,490 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:22,497 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:46:22,497 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:46:22,525 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2018-09-14 15:46:22,525 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:22,528 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:22,536 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:22,536 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:23,083 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:23,104 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:23,104 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:23,119 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:46:23,119 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:46:23,250 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2018-09-14 15:46:23,250 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:23,254 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:23,261 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:23,261 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:23,323 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:23,325 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:46:23,325 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 26 [2018-09-14 15:46:23,325 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:46:23,325 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-09-14 15:46:23,326 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-09-14 15:46:23,326 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-09-14 15:46:23,326 INFO L87 Difference]: Start difference. First operand 45 states and 45 transitions. Second operand 14 states. [2018-09-14 15:46:23,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:23,413 INFO L93 Difference]: Finished difference Result 54 states and 54 transitions. [2018-09-14 15:46:23,414 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-09-14 15:46:23,415 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 44 [2018-09-14 15:46:23,415 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:23,416 INFO L225 Difference]: With dead ends: 54 [2018-09-14 15:46:23,416 INFO L226 Difference]: Without dead ends: 49 [2018-09-14 15:46:23,416 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 188 GetRequests, 164 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-09-14 15:46:23,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-09-14 15:46:23,420 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 48. [2018-09-14 15:46:23,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-09-14 15:46:23,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 48 transitions. [2018-09-14 15:46:23,421 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 48 transitions. Word has length 44 [2018-09-14 15:46:23,421 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:23,421 INFO L480 AbstractCegarLoop]: Abstraction has 48 states and 48 transitions. [2018-09-14 15:46:23,422 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-09-14 15:46:23,422 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 48 transitions. [2018-09-14 15:46:23,422 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-09-14 15:46:23,423 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:23,423 INFO L376 BasicCegarLoop]: trace histogram [13, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:23,423 INFO L423 AbstractCegarLoop]: === Iteration 14 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:23,423 INFO L82 PathProgramCache]: Analyzing trace with hash 668666744, now seen corresponding path program 12 times [2018-09-14 15:46:23,423 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:23,424 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:23,424 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:46:23,424 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:23,424 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:23,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:23,616 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:23,617 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:23,617 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:23,624 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:46:23,625 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:46:23,661 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2018-09-14 15:46:23,661 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:23,662 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:23,670 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:23,671 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:23,939 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:23,958 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:23,958 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:23,974 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:46:23,975 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:46:24,317 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2018-09-14 15:46:24,317 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:24,321 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:24,329 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:24,329 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:24,388 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:24,390 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:46:24,390 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 28 [2018-09-14 15:46:24,390 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:46:24,390 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-09-14 15:46:24,391 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-09-14 15:46:24,391 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-09-14 15:46:24,391 INFO L87 Difference]: Start difference. First operand 48 states and 48 transitions. Second operand 15 states. [2018-09-14 15:46:24,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:24,476 INFO L93 Difference]: Finished difference Result 57 states and 57 transitions. [2018-09-14 15:46:24,476 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-09-14 15:46:24,476 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 47 [2018-09-14 15:46:24,476 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:24,477 INFO L225 Difference]: With dead ends: 57 [2018-09-14 15:46:24,477 INFO L226 Difference]: Without dead ends: 52 [2018-09-14 15:46:24,477 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 201 GetRequests, 175 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-09-14 15:46:24,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2018-09-14 15:46:24,481 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 51. [2018-09-14 15:46:24,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-09-14 15:46:24,481 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 51 transitions. [2018-09-14 15:46:24,482 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 51 transitions. Word has length 47 [2018-09-14 15:46:24,482 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:24,482 INFO L480 AbstractCegarLoop]: Abstraction has 51 states and 51 transitions. [2018-09-14 15:46:24,482 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-09-14 15:46:24,482 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 51 transitions. [2018-09-14 15:46:24,483 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-09-14 15:46:24,483 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:24,483 INFO L376 BasicCegarLoop]: trace histogram [14, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:24,483 INFO L423 AbstractCegarLoop]: === Iteration 15 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:24,484 INFO L82 PathProgramCache]: Analyzing trace with hash 1836698334, now seen corresponding path program 13 times [2018-09-14 15:46:24,484 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:24,485 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:24,485 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:46:24,485 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:24,485 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:24,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:24,669 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:24,670 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:24,670 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:24,678 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:46:24,678 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:46:24,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:24,707 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:24,715 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:24,715 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:25,064 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:25,089 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:25,090 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:25,104 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:46:25,105 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:46:25,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:25,155 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:25,166 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:25,166 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:25,225 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:25,226 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:46:25,227 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 30 [2018-09-14 15:46:25,227 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:46:25,227 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-09-14 15:46:25,227 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-09-14 15:46:25,228 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-09-14 15:46:25,228 INFO L87 Difference]: Start difference. First operand 51 states and 51 transitions. Second operand 16 states. [2018-09-14 15:46:25,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:25,387 INFO L93 Difference]: Finished difference Result 60 states and 60 transitions. [2018-09-14 15:46:25,387 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-09-14 15:46:25,387 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 50 [2018-09-14 15:46:25,388 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:25,389 INFO L225 Difference]: With dead ends: 60 [2018-09-14 15:46:25,389 INFO L226 Difference]: Without dead ends: 55 [2018-09-14 15:46:25,389 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 214 GetRequests, 186 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-09-14 15:46:25,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states. [2018-09-14 15:46:25,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 54. [2018-09-14 15:46:25,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-09-14 15:46:25,394 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 54 transitions. [2018-09-14 15:46:25,394 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 54 transitions. Word has length 50 [2018-09-14 15:46:25,395 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:25,395 INFO L480 AbstractCegarLoop]: Abstraction has 54 states and 54 transitions. [2018-09-14 15:46:25,395 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-09-14 15:46:25,395 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 54 transitions. [2018-09-14 15:46:25,396 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-09-14 15:46:25,396 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:25,396 INFO L376 BasicCegarLoop]: trace histogram [15, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:25,396 INFO L423 AbstractCegarLoop]: === Iteration 16 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:25,397 INFO L82 PathProgramCache]: Analyzing trace with hash 840763832, now seen corresponding path program 14 times [2018-09-14 15:46:25,397 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:25,398 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:25,398 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:46:25,398 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:25,398 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:25,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:25,588 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:25,588 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:25,588 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:25,597 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:46:25,597 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:46:25,612 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:46:25,612 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:25,615 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:25,621 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:25,621 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:25,947 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:25,968 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:25,969 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:25,983 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:46:25,983 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:46:26,025 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:46:26,026 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:26,029 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:26,037 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:26,037 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:26,081 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:26,082 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:46:26,082 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 32 [2018-09-14 15:46:26,082 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:46:26,082 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-09-14 15:46:26,083 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-09-14 15:46:26,083 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-09-14 15:46:26,083 INFO L87 Difference]: Start difference. First operand 54 states and 54 transitions. Second operand 17 states. [2018-09-14 15:46:26,203 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:26,203 INFO L93 Difference]: Finished difference Result 63 states and 63 transitions. [2018-09-14 15:46:26,204 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-09-14 15:46:26,204 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 53 [2018-09-14 15:46:26,204 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:26,205 INFO L225 Difference]: With dead ends: 63 [2018-09-14 15:46:26,205 INFO L226 Difference]: Without dead ends: 58 [2018-09-14 15:46:26,206 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 227 GetRequests, 197 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-09-14 15:46:26,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2018-09-14 15:46:26,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 57. [2018-09-14 15:46:26,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 57 states. [2018-09-14 15:46:26,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 57 transitions. [2018-09-14 15:46:26,212 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 57 transitions. Word has length 53 [2018-09-14 15:46:26,212 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:26,212 INFO L480 AbstractCegarLoop]: Abstraction has 57 states and 57 transitions. [2018-09-14 15:46:26,212 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-09-14 15:46:26,212 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 57 transitions. [2018-09-14 15:46:26,216 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-09-14 15:46:26,216 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:26,216 INFO L376 BasicCegarLoop]: trace histogram [16, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:26,216 INFO L423 AbstractCegarLoop]: === Iteration 17 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:26,216 INFO L82 PathProgramCache]: Analyzing trace with hash 590095518, now seen corresponding path program 15 times [2018-09-14 15:46:26,217 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:26,217 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:26,218 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:46:26,218 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:26,218 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:26,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:26,447 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:26,448 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:26,448 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:26,456 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:46:26,457 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:46:26,500 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-09-14 15:46:26,500 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:26,502 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:26,512 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:26,512 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:27,018 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:27,040 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:27,040 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:27,056 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:46:27,057 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:46:27,534 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-09-14 15:46:27,535 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:27,539 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:27,548 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:27,549 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:27,564 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:27,566 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:46:27,566 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 34 [2018-09-14 15:46:27,566 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:46:27,566 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-09-14 15:46:27,567 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-09-14 15:46:27,567 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-09-14 15:46:27,567 INFO L87 Difference]: Start difference. First operand 57 states and 57 transitions. Second operand 18 states. [2018-09-14 15:46:27,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:27,634 INFO L93 Difference]: Finished difference Result 66 states and 66 transitions. [2018-09-14 15:46:27,634 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-09-14 15:46:27,634 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 56 [2018-09-14 15:46:27,634 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:27,635 INFO L225 Difference]: With dead ends: 66 [2018-09-14 15:46:27,635 INFO L226 Difference]: Without dead ends: 61 [2018-09-14 15:46:27,636 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 240 GetRequests, 208 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-09-14 15:46:27,636 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2018-09-14 15:46:27,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 60. [2018-09-14 15:46:27,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-09-14 15:46:27,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 60 transitions. [2018-09-14 15:46:27,641 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 60 transitions. Word has length 56 [2018-09-14 15:46:27,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:27,642 INFO L480 AbstractCegarLoop]: Abstraction has 60 states and 60 transitions. [2018-09-14 15:46:27,642 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-09-14 15:46:27,642 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 60 transitions. [2018-09-14 15:46:27,643 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-09-14 15:46:27,643 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:27,643 INFO L376 BasicCegarLoop]: trace histogram [17, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:27,643 INFO L423 AbstractCegarLoop]: === Iteration 18 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:27,643 INFO L82 PathProgramCache]: Analyzing trace with hash 1878480888, now seen corresponding path program 16 times [2018-09-14 15:46:27,643 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:27,644 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:27,644 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:46:27,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:27,645 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:27,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:28,691 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:28,692 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:28,692 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:28,709 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:46:28,710 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:46:28,731 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:46:28,731 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:28,733 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:28,741 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:28,741 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:29,309 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:29,332 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:29,332 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:29,346 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:46:29,347 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:46:29,389 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:46:29,389 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:29,392 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:29,400 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:29,400 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:29,447 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:29,448 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:46:29,448 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 36 [2018-09-14 15:46:29,449 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:46:29,449 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-09-14 15:46:29,449 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-09-14 15:46:29,450 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-09-14 15:46:29,450 INFO L87 Difference]: Start difference. First operand 60 states and 60 transitions. Second operand 19 states. [2018-09-14 15:46:29,524 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:29,524 INFO L93 Difference]: Finished difference Result 69 states and 69 transitions. [2018-09-14 15:46:29,530 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-09-14 15:46:29,531 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 59 [2018-09-14 15:46:29,531 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:29,532 INFO L225 Difference]: With dead ends: 69 [2018-09-14 15:46:29,532 INFO L226 Difference]: Without dead ends: 64 [2018-09-14 15:46:29,533 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 253 GetRequests, 219 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-09-14 15:46:29,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2018-09-14 15:46:29,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 63. [2018-09-14 15:46:29,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-09-14 15:46:29,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 63 transitions. [2018-09-14 15:46:29,546 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 63 transitions. Word has length 59 [2018-09-14 15:46:29,546 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:29,546 INFO L480 AbstractCegarLoop]: Abstraction has 63 states and 63 transitions. [2018-09-14 15:46:29,546 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-09-14 15:46:29,547 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 63 transitions. [2018-09-14 15:46:29,547 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-09-14 15:46:29,547 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:29,548 INFO L376 BasicCegarLoop]: trace histogram [18, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:29,548 INFO L423 AbstractCegarLoop]: === Iteration 19 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:29,548 INFO L82 PathProgramCache]: Analyzing trace with hash 44314206, now seen corresponding path program 17 times [2018-09-14 15:46:29,548 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:29,552 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:29,552 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:46:29,552 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:29,553 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:29,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:29,959 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:29,959 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:29,959 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:29,969 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:46:29,969 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:46:30,019 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2018-09-14 15:46:30,019 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:30,022 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:30,030 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:30,030 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:30,712 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:30,732 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:30,732 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:30,747 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:46:30,747 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:46:31,112 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2018-09-14 15:46:31,112 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:31,116 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:31,126 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:31,126 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:31,187 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:31,190 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:46:31,190 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 38 [2018-09-14 15:46:31,190 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:46:31,191 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-09-14 15:46:31,191 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-09-14 15:46:31,192 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-09-14 15:46:31,192 INFO L87 Difference]: Start difference. First operand 63 states and 63 transitions. Second operand 20 states. [2018-09-14 15:46:31,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:31,700 INFO L93 Difference]: Finished difference Result 72 states and 72 transitions. [2018-09-14 15:46:31,700 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-09-14 15:46:31,701 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 62 [2018-09-14 15:46:31,701 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:31,701 INFO L225 Difference]: With dead ends: 72 [2018-09-14 15:46:31,702 INFO L226 Difference]: Without dead ends: 67 [2018-09-14 15:46:31,702 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 266 GetRequests, 230 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-09-14 15:46:31,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2018-09-14 15:46:31,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 66. [2018-09-14 15:46:31,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-09-14 15:46:31,706 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 66 transitions. [2018-09-14 15:46:31,706 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 66 transitions. Word has length 62 [2018-09-14 15:46:31,707 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:31,707 INFO L480 AbstractCegarLoop]: Abstraction has 66 states and 66 transitions. [2018-09-14 15:46:31,707 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-09-14 15:46:31,707 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 66 transitions. [2018-09-14 15:46:31,707 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-09-14 15:46:31,707 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:31,708 INFO L376 BasicCegarLoop]: trace histogram [19, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:31,708 INFO L423 AbstractCegarLoop]: === Iteration 20 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:31,708 INFO L82 PathProgramCache]: Analyzing trace with hash -1041369544, now seen corresponding path program 18 times [2018-09-14 15:46:31,708 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:31,709 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:31,709 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:46:31,709 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:31,709 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:31,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:33,294 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:33,295 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:33,295 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:33,302 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:46:33,302 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:46:33,353 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2018-09-14 15:46:33,353 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:33,355 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:33,363 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:33,364 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:33,867 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:33,887 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:33,887 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:33,905 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:46:33,906 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:46:36,472 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2018-09-14 15:46:36,472 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:36,477 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:36,486 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:36,486 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:36,516 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:36,518 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:46:36,518 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 40 [2018-09-14 15:46:36,519 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:46:36,519 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-09-14 15:46:36,519 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-09-14 15:46:36,520 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-09-14 15:46:36,520 INFO L87 Difference]: Start difference. First operand 66 states and 66 transitions. Second operand 21 states. [2018-09-14 15:46:36,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:36,600 INFO L93 Difference]: Finished difference Result 75 states and 75 transitions. [2018-09-14 15:46:36,600 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-09-14 15:46:36,600 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 65 [2018-09-14 15:46:36,600 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:36,601 INFO L225 Difference]: With dead ends: 75 [2018-09-14 15:46:36,601 INFO L226 Difference]: Without dead ends: 70 [2018-09-14 15:46:36,602 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 279 GetRequests, 241 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-09-14 15:46:36,603 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states. [2018-09-14 15:46:36,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 69. [2018-09-14 15:46:36,606 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2018-09-14 15:46:36,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 69 transitions. [2018-09-14 15:46:36,607 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 69 transitions. Word has length 65 [2018-09-14 15:46:36,611 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:36,611 INFO L480 AbstractCegarLoop]: Abstraction has 69 states and 69 transitions. [2018-09-14 15:46:36,611 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-09-14 15:46:36,611 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 69 transitions. [2018-09-14 15:46:36,611 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-09-14 15:46:36,611 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:36,612 INFO L376 BasicCegarLoop]: trace histogram [20, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:36,612 INFO L423 AbstractCegarLoop]: === Iteration 21 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:36,612 INFO L82 PathProgramCache]: Analyzing trace with hash 752740382, now seen corresponding path program 19 times [2018-09-14 15:46:36,612 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:36,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:36,614 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:46:36,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:36,614 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:36,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:36,872 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:36,872 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:36,872 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:36,879 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:46:36,880 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:46:36,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:36,905 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:36,916 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:36,916 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:37,441 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:37,462 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:37,462 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:37,477 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:46:37,477 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:46:37,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:37,526 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:37,534 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:37,534 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:37,552 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:37,553 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:46:37,553 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22, 22, 22] total 42 [2018-09-14 15:46:37,553 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:46:37,554 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-09-14 15:46:37,554 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-09-14 15:46:37,555 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-09-14 15:46:37,555 INFO L87 Difference]: Start difference. First operand 69 states and 69 transitions. Second operand 22 states. [2018-09-14 15:46:37,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:37,656 INFO L93 Difference]: Finished difference Result 78 states and 78 transitions. [2018-09-14 15:46:37,656 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-09-14 15:46:37,656 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 68 [2018-09-14 15:46:37,657 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:37,657 INFO L225 Difference]: With dead ends: 78 [2018-09-14 15:46:37,658 INFO L226 Difference]: Without dead ends: 73 [2018-09-14 15:46:37,659 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 292 GetRequests, 252 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-09-14 15:46:37,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2018-09-14 15:46:37,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 72. [2018-09-14 15:46:37,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-09-14 15:46:37,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 72 transitions. [2018-09-14 15:46:37,664 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 72 transitions. Word has length 68 [2018-09-14 15:46:37,664 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:37,664 INFO L480 AbstractCegarLoop]: Abstraction has 72 states and 72 transitions. [2018-09-14 15:46:37,664 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-09-14 15:46:37,664 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 72 transitions. [2018-09-14 15:46:37,665 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-09-14 15:46:37,665 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:37,665 INFO L376 BasicCegarLoop]: trace histogram [21, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:37,666 INFO L423 AbstractCegarLoop]: === Iteration 22 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:37,666 INFO L82 PathProgramCache]: Analyzing trace with hash -1786452872, now seen corresponding path program 20 times [2018-09-14 15:46:37,666 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:37,667 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:37,667 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:46:37,667 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:37,667 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:37,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:38,360 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:38,360 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:38,360 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:38,369 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:46:38,369 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:46:38,396 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:46:38,396 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:38,398 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:38,410 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:38,410 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:39,055 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:39,075 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:39,075 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:39,090 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:46:39,090 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:46:39,141 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:46:39,141 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:39,145 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:39,153 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:39,153 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:39,170 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:39,171 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:46:39,171 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 44 [2018-09-14 15:46:39,171 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:46:39,172 INFO L459 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-09-14 15:46:39,172 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-09-14 15:46:39,173 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-09-14 15:46:39,173 INFO L87 Difference]: Start difference. First operand 72 states and 72 transitions. Second operand 23 states. [2018-09-14 15:46:39,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:39,254 INFO L93 Difference]: Finished difference Result 81 states and 81 transitions. [2018-09-14 15:46:39,256 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-09-14 15:46:39,256 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 71 [2018-09-14 15:46:39,257 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:39,257 INFO L225 Difference]: With dead ends: 81 [2018-09-14 15:46:39,257 INFO L226 Difference]: Without dead ends: 76 [2018-09-14 15:46:39,258 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 305 GetRequests, 263 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-09-14 15:46:39,258 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states. [2018-09-14 15:46:39,260 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 75. [2018-09-14 15:46:39,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 75 states. [2018-09-14 15:46:39,260 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 75 transitions. [2018-09-14 15:46:39,261 INFO L78 Accepts]: Start accepts. Automaton has 75 states and 75 transitions. Word has length 71 [2018-09-14 15:46:39,261 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:39,261 INFO L480 AbstractCegarLoop]: Abstraction has 75 states and 75 transitions. [2018-09-14 15:46:39,261 INFO L481 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-09-14 15:46:39,261 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 75 transitions. [2018-09-14 15:46:39,262 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-09-14 15:46:39,262 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:39,262 INFO L376 BasicCegarLoop]: trace histogram [22, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:39,262 INFO L423 AbstractCegarLoop]: === Iteration 23 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:39,263 INFO L82 PathProgramCache]: Analyzing trace with hash 366301662, now seen corresponding path program 21 times [2018-09-14 15:46:39,263 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:39,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:39,263 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:46:39,264 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:39,264 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:39,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:39,632 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:39,632 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:39,632 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:39,641 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:46:39,641 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:46:39,703 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2018-09-14 15:46:39,703 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:39,705 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:39,715 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:39,715 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:40,248 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:40,269 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:40,270 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:40,285 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:46:40,285 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:46:41,566 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2018-09-14 15:46:41,566 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:41,570 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:41,580 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:41,581 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:41,602 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:41,603 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:46:41,604 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 46 [2018-09-14 15:46:41,604 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:46:41,604 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-09-14 15:46:41,605 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-09-14 15:46:41,606 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-09-14 15:46:41,606 INFO L87 Difference]: Start difference. First operand 75 states and 75 transitions. Second operand 24 states. [2018-09-14 15:46:41,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:41,695 INFO L93 Difference]: Finished difference Result 84 states and 84 transitions. [2018-09-14 15:46:41,696 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-09-14 15:46:41,696 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 74 [2018-09-14 15:46:41,697 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:41,697 INFO L225 Difference]: With dead ends: 84 [2018-09-14 15:46:41,698 INFO L226 Difference]: Without dead ends: 79 [2018-09-14 15:46:41,699 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 318 GetRequests, 274 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-09-14 15:46:41,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states. [2018-09-14 15:46:41,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 78. [2018-09-14 15:46:41,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-09-14 15:46:41,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 78 transitions. [2018-09-14 15:46:41,702 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 78 transitions. Word has length 74 [2018-09-14 15:46:41,702 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:41,702 INFO L480 AbstractCegarLoop]: Abstraction has 78 states and 78 transitions. [2018-09-14 15:46:41,702 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-09-14 15:46:41,702 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 78 transitions. [2018-09-14 15:46:41,703 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-09-14 15:46:41,703 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:41,703 INFO L376 BasicCegarLoop]: trace histogram [23, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:41,703 INFO L423 AbstractCegarLoop]: === Iteration 24 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:41,703 INFO L82 PathProgramCache]: Analyzing trace with hash 624960184, now seen corresponding path program 22 times [2018-09-14 15:46:41,704 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:41,704 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:41,704 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:46:41,704 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:41,705 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:41,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:42,014 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:42,015 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:42,015 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:42,022 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:46:42,022 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:46:42,049 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:46:42,049 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:42,050 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:42,062 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:42,062 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:42,640 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:42,660 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:42,660 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:42,674 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:46:42,675 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:46:42,732 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:46:42,732 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:42,736 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:42,746 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:42,746 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:42,801 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:42,803 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:46:42,803 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 48 [2018-09-14 15:46:42,803 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:46:42,804 INFO L459 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-09-14 15:46:42,804 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-09-14 15:46:42,805 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-09-14 15:46:42,805 INFO L87 Difference]: Start difference. First operand 78 states and 78 transitions. Second operand 25 states. [2018-09-14 15:46:43,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:43,013 INFO L93 Difference]: Finished difference Result 87 states and 87 transitions. [2018-09-14 15:46:43,020 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-09-14 15:46:43,021 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 77 [2018-09-14 15:46:43,021 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:43,021 INFO L225 Difference]: With dead ends: 87 [2018-09-14 15:46:43,022 INFO L226 Difference]: Without dead ends: 82 [2018-09-14 15:46:43,023 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 331 GetRequests, 285 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-09-14 15:46:43,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2018-09-14 15:46:43,025 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 81. [2018-09-14 15:46:43,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-09-14 15:46:43,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 81 transitions. [2018-09-14 15:46:43,026 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 81 transitions. Word has length 77 [2018-09-14 15:46:43,026 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:43,026 INFO L480 AbstractCegarLoop]: Abstraction has 81 states and 81 transitions. [2018-09-14 15:46:43,026 INFO L481 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-09-14 15:46:43,026 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 81 transitions. [2018-09-14 15:46:43,027 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-09-14 15:46:43,027 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:43,027 INFO L376 BasicCegarLoop]: trace histogram [24, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:43,027 INFO L423 AbstractCegarLoop]: === Iteration 25 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:43,028 INFO L82 PathProgramCache]: Analyzing trace with hash 1149660062, now seen corresponding path program 23 times [2018-09-14 15:46:43,028 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:43,028 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:43,028 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:46:43,029 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:43,029 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:43,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:43,659 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:43,659 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:43,659 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:43,666 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:46:43,666 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:46:43,764 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2018-09-14 15:46:43,764 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:43,766 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:43,775 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:43,775 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:44,447 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:44,468 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:44,468 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:44,482 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:46:44,483 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:46:45,289 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2018-09-14 15:46:45,290 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:45,294 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:45,306 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:45,306 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:45,319 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:45,320 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:46:45,320 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 50 [2018-09-14 15:46:45,321 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:46:45,321 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-09-14 15:46:45,321 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-09-14 15:46:45,322 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-09-14 15:46:45,322 INFO L87 Difference]: Start difference. First operand 81 states and 81 transitions. Second operand 26 states. [2018-09-14 15:46:45,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:46:45,412 INFO L93 Difference]: Finished difference Result 90 states and 90 transitions. [2018-09-14 15:46:45,412 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-09-14 15:46:45,412 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 80 [2018-09-14 15:46:45,413 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:46:45,413 INFO L225 Difference]: With dead ends: 90 [2018-09-14 15:46:45,413 INFO L226 Difference]: Without dead ends: 85 [2018-09-14 15:46:45,415 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 344 GetRequests, 296 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-09-14 15:46:45,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-09-14 15:46:45,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 84. [2018-09-14 15:46:45,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-09-14 15:46:45,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 84 transitions. [2018-09-14 15:46:45,418 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 84 transitions. Word has length 80 [2018-09-14 15:46:45,418 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:46:45,418 INFO L480 AbstractCegarLoop]: Abstraction has 84 states and 84 transitions. [2018-09-14 15:46:45,418 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-09-14 15:46:45,418 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 84 transitions. [2018-09-14 15:46:45,419 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-09-14 15:46:45,419 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:46:45,419 INFO L376 BasicCegarLoop]: trace histogram [25, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:46:45,419 INFO L423 AbstractCegarLoop]: === Iteration 26 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:46:45,419 INFO L82 PathProgramCache]: Analyzing trace with hash -1197231880, now seen corresponding path program 24 times [2018-09-14 15:46:45,419 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:46:45,420 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:45,420 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:46:45,420 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:46:45,420 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:46:45,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:46:45,786 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:45,786 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:45,786 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:46:45,794 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:46:45,794 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:46:45,864 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) [2018-09-14 15:46:45,864 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:46:45,866 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:46:45,880 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:45,880 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:46:46,719 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:46:46,741 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:46:46,741 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:46:46,755 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:46:46,755 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:47:30,479 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) [2018-09-14 15:47:30,479 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:47:30,485 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:47:30,498 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:30,498 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:47:30,521 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:30,523 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:47:30,523 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 52 [2018-09-14 15:47:30,523 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:47:30,524 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-09-14 15:47:30,524 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-09-14 15:47:30,525 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:47:30,526 INFO L87 Difference]: Start difference. First operand 84 states and 84 transitions. Second operand 27 states. [2018-09-14 15:47:30,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:47:30,612 INFO L93 Difference]: Finished difference Result 93 states and 93 transitions. [2018-09-14 15:47:30,613 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-09-14 15:47:30,613 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 83 [2018-09-14 15:47:30,613 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:47:30,614 INFO L225 Difference]: With dead ends: 93 [2018-09-14 15:47:30,614 INFO L226 Difference]: Without dead ends: 88 [2018-09-14 15:47:30,616 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 357 GetRequests, 307 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:47:30,616 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states. [2018-09-14 15:47:30,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 87. [2018-09-14 15:47:30,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2018-09-14 15:47:30,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 87 transitions. [2018-09-14 15:47:30,618 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 87 transitions. Word has length 83 [2018-09-14 15:47:30,618 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:47:30,618 INFO L480 AbstractCegarLoop]: Abstraction has 87 states and 87 transitions. [2018-09-14 15:47:30,618 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-09-14 15:47:30,619 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 87 transitions. [2018-09-14 15:47:30,619 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-09-14 15:47:30,619 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:47:30,619 INFO L376 BasicCegarLoop]: trace histogram [26, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:47:30,620 INFO L423 AbstractCegarLoop]: === Iteration 27 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:47:30,620 INFO L82 PathProgramCache]: Analyzing trace with hash 317535582, now seen corresponding path program 25 times [2018-09-14 15:47:30,620 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:47:30,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:47:30,620 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:47:30,621 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:47:30,621 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:47:30,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:47:32,059 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:32,060 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:47:32,060 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:47:32,068 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:47:32,068 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:47:32,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:47:32,099 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:47:32,108 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:32,108 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:47:32,848 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:32,868 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:47:32,868 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:47:32,883 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:47:32,883 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:47:32,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:47:32,948 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:47:32,961 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:32,961 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:47:32,987 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:32,988 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:47:32,988 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28, 28, 28] total 54 [2018-09-14 15:47:32,988 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:47:32,989 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-09-14 15:47:32,989 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-09-14 15:47:32,990 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1431, Invalid=1431, Unknown=0, NotChecked=0, Total=2862 [2018-09-14 15:47:32,990 INFO L87 Difference]: Start difference. First operand 87 states and 87 transitions. Second operand 28 states. [2018-09-14 15:47:33,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:47:33,082 INFO L93 Difference]: Finished difference Result 96 states and 96 transitions. [2018-09-14 15:47:33,085 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-09-14 15:47:33,085 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 86 [2018-09-14 15:47:33,085 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:47:33,086 INFO L225 Difference]: With dead ends: 96 [2018-09-14 15:47:33,086 INFO L226 Difference]: Without dead ends: 91 [2018-09-14 15:47:33,087 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 370 GetRequests, 318 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1431, Invalid=1431, Unknown=0, NotChecked=0, Total=2862 [2018-09-14 15:47:33,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states. [2018-09-14 15:47:33,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 90. [2018-09-14 15:47:33,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. [2018-09-14 15:47:33,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 90 transitions. [2018-09-14 15:47:33,090 INFO L78 Accepts]: Start accepts. Automaton has 90 states and 90 transitions. Word has length 86 [2018-09-14 15:47:33,090 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:47:33,090 INFO L480 AbstractCegarLoop]: Abstraction has 90 states and 90 transitions. [2018-09-14 15:47:33,090 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-09-14 15:47:33,090 INFO L276 IsEmpty]: Start isEmpty. Operand 90 states and 90 transitions. [2018-09-14 15:47:33,091 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-09-14 15:47:33,091 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:47:33,091 INFO L376 BasicCegarLoop]: trace histogram [27, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:47:33,091 INFO L423 AbstractCegarLoop]: === Iteration 28 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:47:33,091 INFO L82 PathProgramCache]: Analyzing trace with hash -466383048, now seen corresponding path program 26 times [2018-09-14 15:47:33,092 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:47:33,092 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:47:33,092 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:47:33,092 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:47:33,092 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:47:33,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:47:33,728 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:33,729 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:47:33,729 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:47:33,737 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:47:33,737 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:47:33,777 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:47:33,777 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:47:33,779 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:47:33,799 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:33,799 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:47:34,711 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:34,732 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:47:34,732 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:47:34,746 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:47:34,746 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:47:34,813 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:47:34,813 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:47:34,817 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:47:34,830 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:34,830 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:47:34,894 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:34,896 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:47:34,896 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 56 [2018-09-14 15:47:34,896 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:47:34,896 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-09-14 15:47:34,897 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-09-14 15:47:34,898 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-09-14 15:47:34,898 INFO L87 Difference]: Start difference. First operand 90 states and 90 transitions. Second operand 29 states. [2018-09-14 15:47:35,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:47:35,073 INFO L93 Difference]: Finished difference Result 99 states and 99 transitions. [2018-09-14 15:47:35,074 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-09-14 15:47:35,074 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 89 [2018-09-14 15:47:35,074 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:47:35,075 INFO L225 Difference]: With dead ends: 99 [2018-09-14 15:47:35,075 INFO L226 Difference]: Without dead ends: 94 [2018-09-14 15:47:35,077 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 383 GetRequests, 329 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-09-14 15:47:35,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-09-14 15:47:35,079 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 93. [2018-09-14 15:47:35,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93 states. [2018-09-14 15:47:35,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 93 transitions. [2018-09-14 15:47:35,079 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 93 transitions. Word has length 89 [2018-09-14 15:47:35,079 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:47:35,080 INFO L480 AbstractCegarLoop]: Abstraction has 93 states and 93 transitions. [2018-09-14 15:47:35,080 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-09-14 15:47:35,080 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 93 transitions. [2018-09-14 15:47:35,080 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-09-14 15:47:35,080 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:47:35,080 INFO L376 BasicCegarLoop]: trace histogram [28, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:47:35,080 INFO L423 AbstractCegarLoop]: === Iteration 29 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:47:35,081 INFO L82 PathProgramCache]: Analyzing trace with hash 1845866270, now seen corresponding path program 27 times [2018-09-14 15:47:35,081 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:47:35,081 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:47:35,081 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:47:35,081 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:47:35,081 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:47:35,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:47:36,142 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:36,142 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:47:36,143 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:47:36,149 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:47:36,149 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:47:36,247 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2018-09-14 15:47:36,247 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:47:36,249 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:47:36,263 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:36,263 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:47:37,342 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:37,362 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:47:37,362 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:47:37,378 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:47:37,378 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:47:40,296 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2018-09-14 15:47:40,296 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:47:40,301 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:47:40,315 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:40,316 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:47:40,373 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:40,375 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:47:40,375 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 30, 30] total 58 [2018-09-14 15:47:40,375 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:47:40,376 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-09-14 15:47:40,376 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-09-14 15:47:40,377 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-09-14 15:47:40,377 INFO L87 Difference]: Start difference. First operand 93 states and 93 transitions. Second operand 30 states. [2018-09-14 15:47:40,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:47:40,498 INFO L93 Difference]: Finished difference Result 102 states and 102 transitions. [2018-09-14 15:47:40,499 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-09-14 15:47:40,499 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 92 [2018-09-14 15:47:40,499 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:47:40,500 INFO L225 Difference]: With dead ends: 102 [2018-09-14 15:47:40,500 INFO L226 Difference]: Without dead ends: 97 [2018-09-14 15:47:40,502 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 396 GetRequests, 340 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-09-14 15:47:40,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states. [2018-09-14 15:47:40,504 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 96. [2018-09-14 15:47:40,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 96 states. [2018-09-14 15:47:40,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96 states to 96 states and 96 transitions. [2018-09-14 15:47:40,505 INFO L78 Accepts]: Start accepts. Automaton has 96 states and 96 transitions. Word has length 92 [2018-09-14 15:47:40,505 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:47:40,505 INFO L480 AbstractCegarLoop]: Abstraction has 96 states and 96 transitions. [2018-09-14 15:47:40,505 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-09-14 15:47:40,505 INFO L276 IsEmpty]: Start isEmpty. Operand 96 states and 96 transitions. [2018-09-14 15:47:40,506 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-09-14 15:47:40,506 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:47:40,506 INFO L376 BasicCegarLoop]: trace histogram [29, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:47:40,506 INFO L423 AbstractCegarLoop]: === Iteration 30 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:47:40,506 INFO L82 PathProgramCache]: Analyzing trace with hash -915161736, now seen corresponding path program 28 times [2018-09-14 15:47:40,506 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:47:40,507 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:47:40,507 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:47:40,507 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:47:40,507 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:47:40,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:47:41,171 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:41,171 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:47:41,171 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:47:41,179 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:47:41,179 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:47:41,204 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:47:41,205 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:47:41,207 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:47:41,222 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:41,222 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:47:43,774 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:43,804 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:47:43,805 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:47:43,841 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:47:43,841 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:47:43,909 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:47:43,909 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:47:43,914 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:47:43,928 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:43,929 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:47:43,949 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:43,950 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:47:43,950 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31, 31, 31, 31] total 60 [2018-09-14 15:47:43,950 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:47:43,951 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-09-14 15:47:43,951 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-09-14 15:47:43,951 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1770, Invalid=1770, Unknown=0, NotChecked=0, Total=3540 [2018-09-14 15:47:43,952 INFO L87 Difference]: Start difference. First operand 96 states and 96 transitions. Second operand 31 states. [2018-09-14 15:47:44,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:47:44,085 INFO L93 Difference]: Finished difference Result 105 states and 105 transitions. [2018-09-14 15:47:44,085 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-09-14 15:47:44,086 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 95 [2018-09-14 15:47:44,086 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:47:44,087 INFO L225 Difference]: With dead ends: 105 [2018-09-14 15:47:44,087 INFO L226 Difference]: Without dead ends: 100 [2018-09-14 15:47:44,088 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 409 GetRequests, 351 SyntacticMatches, 0 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=1770, Invalid=1770, Unknown=0, NotChecked=0, Total=3540 [2018-09-14 15:47:44,088 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states. [2018-09-14 15:47:44,091 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 99. [2018-09-14 15:47:44,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2018-09-14 15:47:44,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 99 transitions. [2018-09-14 15:47:44,092 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 99 transitions. Word has length 95 [2018-09-14 15:47:44,092 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:47:44,093 INFO L480 AbstractCegarLoop]: Abstraction has 99 states and 99 transitions. [2018-09-14 15:47:44,093 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-09-14 15:47:44,093 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 99 transitions. [2018-09-14 15:47:44,093 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-09-14 15:47:44,093 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:47:44,093 INFO L376 BasicCegarLoop]: trace histogram [30, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:47:44,093 INFO L423 AbstractCegarLoop]: === Iteration 31 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:47:44,094 INFO L82 PathProgramCache]: Analyzing trace with hash -1781802786, now seen corresponding path program 29 times [2018-09-14 15:47:44,094 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:47:44,094 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:47:44,094 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:47:44,094 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:47:44,094 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:47:44,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:47:44,793 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:44,793 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:47:44,793 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:47:44,800 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:47:44,800 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:47:44,970 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 30 check-sat command(s) [2018-09-14 15:47:44,971 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:47:44,973 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:47:44,985 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:44,985 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:47:45,978 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:45,999 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:47:45,999 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:47:46,014 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:47:46,014 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:47:47,686 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 30 check-sat command(s) [2018-09-14 15:47:47,686 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:47:47,691 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:47:47,706 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:47,706 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:47:47,772 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:47,774 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:47:47,774 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32, 32, 32, 32] total 62 [2018-09-14 15:47:47,774 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:47:47,775 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-09-14 15:47:47,775 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-09-14 15:47:47,776 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-09-14 15:47:47,776 INFO L87 Difference]: Start difference. First operand 99 states and 99 transitions. Second operand 32 states. [2018-09-14 15:47:48,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:47:48,002 INFO L93 Difference]: Finished difference Result 108 states and 108 transitions. [2018-09-14 15:47:48,003 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-09-14 15:47:48,003 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 98 [2018-09-14 15:47:48,003 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:47:48,004 INFO L225 Difference]: With dead ends: 108 [2018-09-14 15:47:48,004 INFO L226 Difference]: Without dead ends: 103 [2018-09-14 15:47:48,005 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 422 GetRequests, 362 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-09-14 15:47:48,006 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states. [2018-09-14 15:47:48,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 102. [2018-09-14 15:47:48,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-09-14 15:47:48,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 102 transitions. [2018-09-14 15:47:48,009 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 102 transitions. Word has length 98 [2018-09-14 15:47:48,009 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:47:48,009 INFO L480 AbstractCegarLoop]: Abstraction has 102 states and 102 transitions. [2018-09-14 15:47:48,009 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-09-14 15:47:48,009 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 102 transitions. [2018-09-14 15:47:48,010 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2018-09-14 15:47:48,010 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:47:48,010 INFO L376 BasicCegarLoop]: trace histogram [31, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:47:48,010 INFO L423 AbstractCegarLoop]: === Iteration 32 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:47:48,010 INFO L82 PathProgramCache]: Analyzing trace with hash 1458060216, now seen corresponding path program 30 times [2018-09-14 15:47:48,011 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:47:48,011 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:47:48,011 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:47:48,011 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:47:48,012 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:47:48,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:47:48,514 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:48,515 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:47:48,515 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:47:48,522 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:47:48,522 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:47:48,641 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 31 check-sat command(s) [2018-09-14 15:47:48,641 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:47:48,644 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:47:48,656 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:48,656 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:47:49,788 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:47:49,809 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:47:49,809 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:47:49,825 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:47:49,825 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:49:36,781 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 31 check-sat command(s) [2018-09-14 15:49:36,781 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:49:36,787 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:49:36,803 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:36,803 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:49:36,828 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:36,830 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:49:36,830 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33, 33, 33, 33] total 64 [2018-09-14 15:49:36,830 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:49:36,831 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-09-14 15:49:36,831 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-09-14 15:49:36,831 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-09-14 15:49:36,831 INFO L87 Difference]: Start difference. First operand 102 states and 102 transitions. Second operand 33 states. [2018-09-14 15:49:36,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:49:36,995 INFO L93 Difference]: Finished difference Result 111 states and 111 transitions. [2018-09-14 15:49:36,996 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-09-14 15:49:36,996 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 101 [2018-09-14 15:49:36,996 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:49:36,997 INFO L225 Difference]: With dead ends: 111 [2018-09-14 15:49:36,997 INFO L226 Difference]: Without dead ends: 106 [2018-09-14 15:49:36,998 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 435 GetRequests, 373 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-09-14 15:49:36,999 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2018-09-14 15:49:37,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 105. [2018-09-14 15:49:37,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-09-14 15:49:37,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 105 transitions. [2018-09-14 15:49:37,002 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 105 transitions. Word has length 101 [2018-09-14 15:49:37,002 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:49:37,002 INFO L480 AbstractCegarLoop]: Abstraction has 105 states and 105 transitions. [2018-09-14 15:49:37,002 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-09-14 15:49:37,002 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 105 transitions. [2018-09-14 15:49:37,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-09-14 15:49:37,003 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:49:37,003 INFO L376 BasicCegarLoop]: trace histogram [32, 31, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:49:37,003 INFO L423 AbstractCegarLoop]: === Iteration 33 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:49:37,004 INFO L82 PathProgramCache]: Analyzing trace with hash -583290210, now seen corresponding path program 31 times [2018-09-14 15:49:37,004 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:49:37,004 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:49:37,004 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:49:37,004 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:49:37,005 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:49:37,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:49:37,645 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:37,646 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:49:37,646 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:49:37,655 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:49:37,656 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:49:37,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:49:37,701 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:49:37,717 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:37,717 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:49:38,865 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:38,885 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:49:38,885 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:49:38,900 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:49:38,900 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:49:38,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:49:38,974 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:49:38,990 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:38,990 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:49:39,009 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:39,011 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:49:39,011 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34, 34, 34, 34] total 66 [2018-09-14 15:49:39,011 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:49:39,011 INFO L459 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-09-14 15:49:39,012 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-09-14 15:49:39,012 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=2145, Invalid=2145, Unknown=0, NotChecked=0, Total=4290 [2018-09-14 15:49:39,012 INFO L87 Difference]: Start difference. First operand 105 states and 105 transitions. Second operand 34 states. [2018-09-14 15:49:39,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:49:39,151 INFO L93 Difference]: Finished difference Result 114 states and 114 transitions. [2018-09-14 15:49:39,151 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-09-14 15:49:39,151 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 104 [2018-09-14 15:49:39,152 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:49:39,153 INFO L225 Difference]: With dead ends: 114 [2018-09-14 15:49:39,153 INFO L226 Difference]: Without dead ends: 109 [2018-09-14 15:49:39,154 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 448 GetRequests, 384 SyntacticMatches, 0 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=2145, Invalid=2145, Unknown=0, NotChecked=0, Total=4290 [2018-09-14 15:49:39,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109 states. [2018-09-14 15:49:39,157 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109 to 108. [2018-09-14 15:49:39,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108 states. [2018-09-14 15:49:39,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 108 transitions. [2018-09-14 15:49:39,158 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 108 transitions. Word has length 104 [2018-09-14 15:49:39,158 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:49:39,158 INFO L480 AbstractCegarLoop]: Abstraction has 108 states and 108 transitions. [2018-09-14 15:49:39,159 INFO L481 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-09-14 15:49:39,159 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 108 transitions. [2018-09-14 15:49:39,159 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-09-14 15:49:39,159 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:49:39,159 INFO L376 BasicCegarLoop]: trace histogram [33, 32, 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:49:39,160 INFO L423 AbstractCegarLoop]: === Iteration 34 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:49:39,160 INFO L82 PathProgramCache]: Analyzing trace with hash -2011887112, now seen corresponding path program 32 times [2018-09-14 15:49:39,160 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:49:39,161 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:49:39,161 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:49:39,161 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:49:39,161 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:49:39,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:49:39,676 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:39,676 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:49:39,677 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:49:39,684 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:49:39,684 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:49:39,718 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:49:39,718 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:49:39,720 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:49:39,736 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:39,736 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:49:40,890 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:40,910 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:49:40,910 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:49:40,925 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:49:40,926 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:49:40,997 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:49:40,997 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:49:41,001 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:49:41,018 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:41,018 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:49:41,078 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:41,079 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:49:41,079 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35, 35, 35, 35] total 68 [2018-09-14 15:49:41,079 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:49:41,080 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-09-14 15:49:41,080 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-09-14 15:49:41,081 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=2278, Invalid=2278, Unknown=0, NotChecked=0, Total=4556 [2018-09-14 15:49:41,081 INFO L87 Difference]: Start difference. First operand 108 states and 108 transitions. Second operand 35 states. [2018-09-14 15:49:41,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:49:41,208 INFO L93 Difference]: Finished difference Result 117 states and 117 transitions. [2018-09-14 15:49:41,209 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-09-14 15:49:41,209 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 107 [2018-09-14 15:49:41,209 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:49:41,210 INFO L225 Difference]: With dead ends: 117 [2018-09-14 15:49:41,210 INFO L226 Difference]: Without dead ends: 112 [2018-09-14 15:49:41,211 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 461 GetRequests, 395 SyntacticMatches, 0 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=2278, Invalid=2278, Unknown=0, NotChecked=0, Total=4556 [2018-09-14 15:49:41,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-09-14 15:49:41,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 111. [2018-09-14 15:49:41,214 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-09-14 15:49:41,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 111 transitions. [2018-09-14 15:49:41,215 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 111 transitions. Word has length 107 [2018-09-14 15:49:41,215 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:49:41,215 INFO L480 AbstractCegarLoop]: Abstraction has 111 states and 111 transitions. [2018-09-14 15:49:41,215 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-09-14 15:49:41,216 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 111 transitions. [2018-09-14 15:49:41,216 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-09-14 15:49:41,216 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:49:41,216 INFO L376 BasicCegarLoop]: trace histogram [34, 33, 33, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:49:41,217 INFO L423 AbstractCegarLoop]: === Iteration 35 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:49:41,217 INFO L82 PathProgramCache]: Analyzing trace with hash 1783708766, now seen corresponding path program 33 times [2018-09-14 15:49:41,217 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:49:41,217 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:49:41,218 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:49:41,218 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:49:41,218 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:49:41,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:49:41,713 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:41,713 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:49:41,713 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:49:41,721 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:49:41,722 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:49:41,876 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 34 check-sat command(s) [2018-09-14 15:49:41,876 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:49:41,880 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:49:41,898 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:41,898 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:49:43,411 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:43,432 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:49:43,432 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:49:43,446 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:49:43,446 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:49:49,653 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 34 check-sat command(s) [2018-09-14 15:49:49,653 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:49:49,659 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:49:49,675 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:49,675 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:49:49,699 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:49,700 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:49:49,701 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36, 36, 36, 36] total 70 [2018-09-14 15:49:49,701 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:49:49,701 INFO L459 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-09-14 15:49:49,701 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-09-14 15:49:49,702 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=2415, Invalid=2415, Unknown=0, NotChecked=0, Total=4830 [2018-09-14 15:49:49,702 INFO L87 Difference]: Start difference. First operand 111 states and 111 transitions. Second operand 36 states. [2018-09-14 15:49:49,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:49:49,884 INFO L93 Difference]: Finished difference Result 120 states and 120 transitions. [2018-09-14 15:49:49,885 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-09-14 15:49:49,885 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 110 [2018-09-14 15:49:49,885 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:49:49,886 INFO L225 Difference]: With dead ends: 120 [2018-09-14 15:49:49,886 INFO L226 Difference]: Without dead ends: 115 [2018-09-14 15:49:49,888 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 474 GetRequests, 406 SyntacticMatches, 0 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=2415, Invalid=2415, Unknown=0, NotChecked=0, Total=4830 [2018-09-14 15:49:49,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-09-14 15:49:49,891 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 114. [2018-09-14 15:49:49,891 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-09-14 15:49:49,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 114 transitions. [2018-09-14 15:49:49,892 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 114 transitions. Word has length 110 [2018-09-14 15:49:49,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:49:49,892 INFO L480 AbstractCegarLoop]: Abstraction has 114 states and 114 transitions. [2018-09-14 15:49:49,892 INFO L481 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-09-14 15:49:49,892 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 114 transitions. [2018-09-14 15:49:49,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-09-14 15:49:49,893 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:49:49,893 INFO L376 BasicCegarLoop]: trace histogram [35, 34, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:49:49,893 INFO L423 AbstractCegarLoop]: === Iteration 36 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:49:49,894 INFO L82 PathProgramCache]: Analyzing trace with hash -1518458824, now seen corresponding path program 34 times [2018-09-14 15:49:49,894 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:49:49,894 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:49:49,894 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:49:49,895 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:49:49,895 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:49:49,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:49:50,424 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:50,425 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:49:50,425 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:49:50,431 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:49:50,432 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:49:50,468 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:49:50,468 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:49:50,470 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:49:50,505 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:50,505 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:49:52,036 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:52,056 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:49:52,056 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 69 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:49:52,071 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:49:52,072 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:49:52,151 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:49:52,151 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:49:52,156 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:49:52,174 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:52,174 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:49:52,229 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:52,230 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:49:52,230 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37, 37, 37, 37] total 72 [2018-09-14 15:49:52,230 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:49:52,231 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-09-14 15:49:52,231 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-09-14 15:49:52,231 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=2556, Invalid=2556, Unknown=0, NotChecked=0, Total=5112 [2018-09-14 15:49:52,231 INFO L87 Difference]: Start difference. First operand 114 states and 114 transitions. Second operand 37 states. [2018-09-14 15:49:52,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:49:52,355 INFO L93 Difference]: Finished difference Result 123 states and 123 transitions. [2018-09-14 15:49:52,355 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-09-14 15:49:52,356 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 113 [2018-09-14 15:49:52,356 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:49:52,357 INFO L225 Difference]: With dead ends: 123 [2018-09-14 15:49:52,357 INFO L226 Difference]: Without dead ends: 118 [2018-09-14 15:49:52,358 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 487 GetRequests, 417 SyntacticMatches, 0 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=2556, Invalid=2556, Unknown=0, NotChecked=0, Total=5112 [2018-09-14 15:49:52,358 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states. [2018-09-14 15:49:52,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 117. [2018-09-14 15:49:52,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-09-14 15:49:52,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 117 transitions. [2018-09-14 15:49:52,362 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 117 transitions. Word has length 113 [2018-09-14 15:49:52,362 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:49:52,362 INFO L480 AbstractCegarLoop]: Abstraction has 117 states and 117 transitions. [2018-09-14 15:49:52,362 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-09-14 15:49:52,362 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 117 transitions. [2018-09-14 15:49:52,363 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-09-14 15:49:52,363 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:49:52,363 INFO L376 BasicCegarLoop]: trace histogram [36, 35, 35, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:49:52,363 INFO L423 AbstractCegarLoop]: === Iteration 37 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:49:52,363 INFO L82 PathProgramCache]: Analyzing trace with hash -167217634, now seen corresponding path program 35 times [2018-09-14 15:49:52,363 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:49:52,364 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:49:52,364 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:49:52,364 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:49:52,364 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:49:52,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:49:53,265 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:53,265 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:49:53,265 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:49:53,272 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:49:53,273 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:49:53,612 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 36 check-sat command(s) [2018-09-14 15:49:53,613 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:49:53,616 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:49:53,630 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:53,630 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:49:54,993 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:55,014 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:49:55,014 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:49:55,029 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:49:55,029 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:49:58,210 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 36 check-sat command(s) [2018-09-14 15:49:58,211 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:49:58,217 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:49:58,235 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:58,236 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:49:58,280 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:58,282 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:49:58,282 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38, 38, 38, 38] total 74 [2018-09-14 15:49:58,282 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:49:58,283 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-09-14 15:49:58,283 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-09-14 15:49:58,283 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=2701, Invalid=2701, Unknown=0, NotChecked=0, Total=5402 [2018-09-14 15:49:58,283 INFO L87 Difference]: Start difference. First operand 117 states and 117 transitions. Second operand 38 states. [2018-09-14 15:49:58,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:49:58,404 INFO L93 Difference]: Finished difference Result 126 states and 126 transitions. [2018-09-14 15:49:58,406 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-09-14 15:49:58,406 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 116 [2018-09-14 15:49:58,406 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:49:58,407 INFO L225 Difference]: With dead ends: 126 [2018-09-14 15:49:58,407 INFO L226 Difference]: Without dead ends: 121 [2018-09-14 15:49:58,407 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 500 GetRequests, 428 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=2701, Invalid=2701, Unknown=0, NotChecked=0, Total=5402 [2018-09-14 15:49:58,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2018-09-14 15:49:58,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 120. [2018-09-14 15:49:58,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 120 states. [2018-09-14 15:49:58,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 120 transitions. [2018-09-14 15:49:58,410 INFO L78 Accepts]: Start accepts. Automaton has 120 states and 120 transitions. Word has length 116 [2018-09-14 15:49:58,410 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:49:58,410 INFO L480 AbstractCegarLoop]: Abstraction has 120 states and 120 transitions. [2018-09-14 15:49:58,410 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-09-14 15:49:58,410 INFO L276 IsEmpty]: Start isEmpty. Operand 120 states and 120 transitions. [2018-09-14 15:49:58,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-14 15:49:58,411 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:49:58,411 INFO L376 BasicCegarLoop]: trace histogram [37, 36, 36, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:49:58,411 INFO L423 AbstractCegarLoop]: === Iteration 38 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:49:58,411 INFO L82 PathProgramCache]: Analyzing trace with hash -2069391752, now seen corresponding path program 36 times [2018-09-14 15:49:58,412 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:49:58,412 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:49:58,412 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:49:58,412 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:49:58,412 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:49:58,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:49:59,120 INFO L134 CoverageAnalysis]: Checked inductivity of 1962 backedges. 0 proven. 1962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:59,120 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:49:59,120 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:49:59,127 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:49:59,127 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:49:59,317 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 37 check-sat command(s) [2018-09-14 15:49:59,318 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:49:59,321 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:49:59,341 INFO L134 CoverageAnalysis]: Checked inductivity of 1962 backedges. 0 proven. 1962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:49:59,342 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:50:00,781 INFO L134 CoverageAnalysis]: Checked inductivity of 1962 backedges. 0 proven. 1962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:00,801 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:50:00,801 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:50:00,816 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:50:00,816 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) Received shutdown request... Cannot interrupt operation gracefully because timeout expired. Forcing shutdown