java -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data --generate-csv --csv-dir csv -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml -s ../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf -i ../../../trunk/examples/svcomp/loop-lit/gj2007_true-unreach-call_true-termination.c.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-dace188-m [2018-09-14 15:51:57,772 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-09-14 15:51:57,774 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-09-14 15:51:57,788 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-09-14 15:51:57,789 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-09-14 15:51:57,790 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-09-14 15:51:57,791 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-09-14 15:51:57,793 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-09-14 15:51:57,795 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-09-14 15:51:57,796 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-09-14 15:51:57,796 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-09-14 15:51:57,797 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-09-14 15:51:57,798 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-09-14 15:51:57,799 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-09-14 15:51:57,800 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-09-14 15:51:57,801 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-09-14 15:51:57,801 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-09-14 15:51:57,803 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-09-14 15:51:57,805 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-09-14 15:51:57,807 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-09-14 15:51:57,808 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-09-14 15:51:57,809 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-09-14 15:51:57,811 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2018-09-14 15:51:57,820 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf [2018-09-14 15:51:57,835 INFO L110 SettingsManager]: Loading preferences was successful [2018-09-14 15:51:57,836 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-09-14 15:51:57,836 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-09-14 15:51:57,837 INFO L133 SettingsManager]: * User list type=DISABLED [2018-09-14 15:51:57,837 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-09-14 15:51:57,837 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-09-14 15:51:57,837 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-09-14 15:51:57,837 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-09-14 15:51:57,838 INFO L133 SettingsManager]: * Log string format=TERM [2018-09-14 15:51:57,838 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-09-14 15:51:57,838 INFO L133 SettingsManager]: * Interval Domain=false [2018-09-14 15:51:57,839 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-09-14 15:51:57,839 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-09-14 15:51:57,839 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-09-14 15:51:57,839 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-09-14 15:51:57,839 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-09-14 15:51:57,840 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-09-14 15:51:57,840 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-09-14 15:51:57,840 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-09-14 15:51:57,840 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-09-14 15:51:57,840 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-09-14 15:51:57,840 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-09-14 15:51:57,841 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-09-14 15:51:57,841 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-09-14 15:51:57,841 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-09-14 15:51:57,841 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-09-14 15:51:57,841 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-09-14 15:51:57,842 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-09-14 15:51:57,842 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-09-14 15:51:57,842 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-09-14 15:51:57,842 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-09-14 15:51:57,842 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-09-14 15:51:57,843 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-09-14 15:51:57,889 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-09-14 15:51:57,902 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-09-14 15:51:57,905 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-09-14 15:51:57,907 INFO L271 PluginConnector]: Initializing CDTParser... [2018-09-14 15:51:57,907 INFO L276 PluginConnector]: CDTParser initialized [2018-09-14 15:51:57,908 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-lit/gj2007_true-unreach-call_true-termination.c.i [2018-09-14 15:51:58,276 INFO L221 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/dd5a7fd49/9ad349f1936d4df0a303d9a8716e372e/FLAG2e4fc9e84 [2018-09-14 15:51:58,439 INFO L277 CDTParser]: Found 1 translation units. [2018-09-14 15:51:58,439 INFO L159 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-lit/gj2007_true-unreach-call_true-termination.c.i [2018-09-14 15:51:58,446 INFO L325 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/dd5a7fd49/9ad349f1936d4df0a303d9a8716e372e/FLAG2e4fc9e84 [2018-09-14 15:51:58,462 INFO L333 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/dd5a7fd49/9ad349f1936d4df0a303d9a8716e372e [2018-09-14 15:51:58,474 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-09-14 15:51:58,477 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-09-14 15:51:58,478 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-09-14 15:51:58,479 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-09-14 15:51:58,485 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-09-14 15:51:58,486 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.09 03:51:58" (1/1) ... [2018-09-14 15:51:58,489 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6beab7ee and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:58, skipping insertion in model container [2018-09-14 15:51:58,489 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.09 03:51:58" (1/1) ... [2018-09-14 15:51:58,501 INFO L160 ieTranslatorObserver]: Starting translation in SV-COMP mode [2018-09-14 15:51:58,697 INFO L170 PostProcessor]: Settings: Checked method=main [2018-09-14 15:51:58,716 INFO L424 MainDispatcher]: Starting main dispatcher in SV-COMP mode [2018-09-14 15:51:58,720 INFO L170 PostProcessor]: Settings: Checked method=main [2018-09-14 15:51:58,733 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:58 WrapperNode [2018-09-14 15:51:58,733 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-09-14 15:51:58,734 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-09-14 15:51:58,734 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-09-14 15:51:58,734 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-09-14 15:51:58,744 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:58" (1/1) ... [2018-09-14 15:51:58,750 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:58" (1/1) ... [2018-09-14 15:51:58,756 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-09-14 15:51:58,757 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-09-14 15:51:58,757 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-09-14 15:51:58,757 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-09-14 15:51:58,768 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:58" (1/1) ... [2018-09-14 15:51:58,768 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:58" (1/1) ... [2018-09-14 15:51:58,769 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:58" (1/1) ... [2018-09-14 15:51:58,769 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:58" (1/1) ... [2018-09-14 15:51:58,770 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:58" (1/1) ... [2018-09-14 15:51:58,776 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:58" (1/1) ... [2018-09-14 15:51:58,777 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:58" (1/1) ... [2018-09-14 15:51:58,778 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-09-14 15:51:58,779 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-09-14 15:51:58,779 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-09-14 15:51:58,779 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-09-14 15:51:58,780 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:58" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-09-14 15:51:58,857 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-09-14 15:51:58,857 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-09-14 15:51:58,858 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-09-14 15:51:58,858 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-09-14 15:51:58,858 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-09-14 15:51:58,858 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-09-14 15:51:58,858 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-09-14 15:51:58,859 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-09-14 15:51:59,187 INFO L353 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-09-14 15:51:59,188 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.09 03:51:59 BoogieIcfgContainer [2018-09-14 15:51:59,188 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-09-14 15:51:59,189 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-09-14 15:51:59,189 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-09-14 15:51:59,192 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-09-14 15:51:59,193 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 14.09 03:51:58" (1/3) ... [2018-09-14 15:51:59,194 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@36297c9b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.09 03:51:59, skipping insertion in model container [2018-09-14 15:51:59,194 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:58" (2/3) ... [2018-09-14 15:51:59,194 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@36297c9b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.09 03:51:59, skipping insertion in model container [2018-09-14 15:51:59,194 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.09 03:51:59" (3/3) ... [2018-09-14 15:51:59,196 INFO L112 eAbstractionObserver]: Analyzing ICFG gj2007_true-unreach-call_true-termination.c.i [2018-09-14 15:51:59,206 INFO L137 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-09-14 15:51:59,213 INFO L149 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-09-14 15:51:59,264 INFO L130 ementStrategyFactory]: Using default assertion order modulation [2018-09-14 15:51:59,264 INFO L381 AbstractCegarLoop]: Interprodecural is true [2018-09-14 15:51:59,265 INFO L382 AbstractCegarLoop]: Hoare is true [2018-09-14 15:51:59,265 INFO L383 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-09-14 15:51:59,265 INFO L384 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-09-14 15:51:59,265 INFO L385 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-09-14 15:51:59,265 INFO L386 AbstractCegarLoop]: Difference is false [2018-09-14 15:51:59,265 INFO L387 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-09-14 15:51:59,265 INFO L392 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-09-14 15:51:59,289 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states. [2018-09-14 15:51:59,294 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2018-09-14 15:51:59,295 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:59,296 INFO L376 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:59,297 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:59,302 INFO L82 PathProgramCache]: Analyzing trace with hash -147882559, now seen corresponding path program 1 times [2018-09-14 15:51:59,305 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:59,356 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:59,357 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:59,357 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:59,357 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:59,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:59,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:59,413 INFO L313 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-09-14 15:51:59,413 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-09-14 15:51:59,414 INFO L265 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-09-14 15:51:59,418 INFO L459 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-09-14 15:51:59,434 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-09-14 15:51:59,435 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-09-14 15:51:59,437 INFO L87 Difference]: Start difference. First operand 20 states. Second operand 2 states. [2018-09-14 15:51:59,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:59,461 INFO L93 Difference]: Finished difference Result 32 states and 36 transitions. [2018-09-14 15:51:59,461 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-09-14 15:51:59,462 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 10 [2018-09-14 15:51:59,463 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:59,473 INFO L225 Difference]: With dead ends: 32 [2018-09-14 15:51:59,473 INFO L226 Difference]: Without dead ends: 13 [2018-09-14 15:51:59,477 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-09-14 15:51:59,497 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states. [2018-09-14 15:51:59,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 13. [2018-09-14 15:51:59,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13 states. [2018-09-14 15:51:59,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 14 transitions. [2018-09-14 15:51:59,519 INFO L78 Accepts]: Start accepts. Automaton has 13 states and 14 transitions. Word has length 10 [2018-09-14 15:51:59,519 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:59,520 INFO L480 AbstractCegarLoop]: Abstraction has 13 states and 14 transitions. [2018-09-14 15:51:59,520 INFO L481 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-09-14 15:51:59,520 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 14 transitions. [2018-09-14 15:51:59,521 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-09-14 15:51:59,521 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:59,521 INFO L376 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:59,521 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:59,522 INFO L82 PathProgramCache]: Analyzing trace with hash -717461825, now seen corresponding path program 1 times [2018-09-14 15:51:59,522 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:59,523 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:59,523 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:59,523 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:59,524 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:59,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:59,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:59,600 INFO L313 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-09-14 15:51:59,601 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-09-14 15:51:59,601 INFO L265 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-09-14 15:51:59,603 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-09-14 15:51:59,604 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-09-14 15:51:59,604 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-09-14 15:51:59,605 INFO L87 Difference]: Start difference. First operand 13 states and 14 transitions. Second operand 3 states. [2018-09-14 15:51:59,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:59,707 INFO L93 Difference]: Finished difference Result 24 states and 28 transitions. [2018-09-14 15:51:59,708 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-09-14 15:51:59,708 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-09-14 15:51:59,709 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:59,709 INFO L225 Difference]: With dead ends: 24 [2018-09-14 15:51:59,709 INFO L226 Difference]: Without dead ends: 16 [2018-09-14 15:51:59,711 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-09-14 15:51:59,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2018-09-14 15:51:59,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 16. [2018-09-14 15:51:59,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2018-09-14 15:51:59,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 17 transitions. [2018-09-14 15:51:59,716 INFO L78 Accepts]: Start accepts. Automaton has 16 states and 17 transitions. Word has length 11 [2018-09-14 15:51:59,716 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:59,716 INFO L480 AbstractCegarLoop]: Abstraction has 16 states and 17 transitions. [2018-09-14 15:51:59,716 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-09-14 15:51:59,716 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 17 transitions. [2018-09-14 15:51:59,717 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-09-14 15:51:59,717 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:59,717 INFO L376 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:59,717 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:59,718 INFO L82 PathProgramCache]: Analyzing trace with hash 64649018, now seen corresponding path program 1 times [2018-09-14 15:51:59,718 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:59,719 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:59,719 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:59,720 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:59,720 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:59,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:59,820 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:59,820 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:59,820 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-09-14 15:51:59,836 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:59,837 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:59,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:59,878 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:59,920 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:59,921 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:59,972 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:59,997 INFO L313 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-09-14 15:51:59,997 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 3] imperfect sequences [4] total 6 [2018-09-14 15:51:59,997 INFO L265 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-09-14 15:51:59,998 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-09-14 15:51:59,998 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-09-14 15:51:59,998 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-09-14 15:51:59,999 INFO L87 Difference]: Start difference. First operand 16 states and 17 transitions. Second operand 3 states. [2018-09-14 15:52:00,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:00,043 INFO L93 Difference]: Finished difference Result 24 states and 26 transitions. [2018-09-14 15:52:00,044 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-09-14 15:52:00,045 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 14 [2018-09-14 15:52:00,045 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:00,046 INFO L225 Difference]: With dead ends: 24 [2018-09-14 15:52:00,047 INFO L226 Difference]: Without dead ends: 19 [2018-09-14 15:52:00,048 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 27 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-09-14 15:52:00,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2018-09-14 15:52:00,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 18. [2018-09-14 15:52:00,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2018-09-14 15:52:00,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 19 transitions. [2018-09-14 15:52:00,057 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 19 transitions. Word has length 14 [2018-09-14 15:52:00,057 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:00,057 INFO L480 AbstractCegarLoop]: Abstraction has 18 states and 19 transitions. [2018-09-14 15:52:00,057 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-09-14 15:52:00,057 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 19 transitions. [2018-09-14 15:52:00,058 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-09-14 15:52:00,058 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:00,058 INFO L376 BasicCegarLoop]: trace histogram [3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:00,059 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:00,059 INFO L82 PathProgramCache]: Analyzing trace with hash 1506199393, now seen corresponding path program 1 times [2018-09-14 15:52:00,059 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:00,061 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:00,062 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:00,062 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:00,063 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:00,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:00,141 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:00,141 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:00,142 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:00,152 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:00,152 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:00,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:00,178 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:00,183 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:00,183 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:00,301 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:00,330 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:00,331 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:00,361 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:00,361 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:00,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:00,389 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:00,402 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:00,402 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:00,429 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:00,430 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:00,431 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 6 [2018-09-14 15:52:00,431 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:00,431 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-09-14 15:52:00,432 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-09-14 15:52:00,432 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-09-14 15:52:00,432 INFO L87 Difference]: Start difference. First operand 18 states and 19 transitions. Second operand 4 states. [2018-09-14 15:52:00,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:00,540 INFO L93 Difference]: Finished difference Result 31 states and 34 transitions. [2018-09-14 15:52:00,540 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-09-14 15:52:00,540 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 17 [2018-09-14 15:52:00,541 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:00,541 INFO L225 Difference]: With dead ends: 31 [2018-09-14 15:52:00,541 INFO L226 Difference]: Without dead ends: 21 [2018-09-14 15:52:00,542 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 70 GetRequests, 66 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-09-14 15:52:00,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2018-09-14 15:52:00,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2018-09-14 15:52:00,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2018-09-14 15:52:00,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 22 transitions. [2018-09-14 15:52:00,547 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 22 transitions. Word has length 17 [2018-09-14 15:52:00,547 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:00,547 INFO L480 AbstractCegarLoop]: Abstraction has 21 states and 22 transitions. [2018-09-14 15:52:00,547 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-09-14 15:52:00,548 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 22 transitions. [2018-09-14 15:52:00,548 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-09-14 15:52:00,548 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:00,549 INFO L376 BasicCegarLoop]: trace histogram [4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:00,549 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:00,549 INFO L82 PathProgramCache]: Analyzing trace with hash 1748455324, now seen corresponding path program 2 times [2018-09-14 15:52:00,549 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:00,551 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:00,551 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:00,551 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:00,551 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:00,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:00,653 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:00,654 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:00,654 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:00,662 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:00,662 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:00,675 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:00,675 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:00,678 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:00,684 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:00,684 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:00,752 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:00,774 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:00,774 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:00,790 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:00,790 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:00,807 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:00,808 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:00,811 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:00,817 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:00,817 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:00,860 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:00,864 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:00,864 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 8 [2018-09-14 15:52:00,864 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:00,865 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-09-14 15:52:00,865 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-09-14 15:52:00,866 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-09-14 15:52:00,866 INFO L87 Difference]: Start difference. First operand 21 states and 22 transitions. Second operand 5 states. [2018-09-14 15:52:00,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:00,918 INFO L93 Difference]: Finished difference Result 34 states and 37 transitions. [2018-09-14 15:52:00,919 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-09-14 15:52:00,919 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 20 [2018-09-14 15:52:00,920 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:00,921 INFO L225 Difference]: With dead ends: 34 [2018-09-14 15:52:00,921 INFO L226 Difference]: Without dead ends: 24 [2018-09-14 15:52:00,921 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 83 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-09-14 15:52:00,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states. [2018-09-14 15:52:00,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 24. [2018-09-14 15:52:00,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-09-14 15:52:00,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 25 transitions. [2018-09-14 15:52:00,927 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 25 transitions. Word has length 20 [2018-09-14 15:52:00,927 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:00,927 INFO L480 AbstractCegarLoop]: Abstraction has 24 states and 25 transitions. [2018-09-14 15:52:00,927 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-09-14 15:52:00,927 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 25 transitions. [2018-09-14 15:52:00,929 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-09-14 15:52:00,929 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:00,929 INFO L376 BasicCegarLoop]: trace histogram [5, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:00,929 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:00,930 INFO L82 PathProgramCache]: Analyzing trace with hash -1045128831, now seen corresponding path program 3 times [2018-09-14 15:52:00,930 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:00,931 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:00,931 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:00,931 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:00,931 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:00,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:01,085 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 8 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:01,086 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:01,086 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:01,101 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:01,101 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:01,124 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-09-14 15:52:01,125 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:01,127 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:01,161 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 15 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-09-14 15:52:01,162 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:01,225 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 15 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-09-14 15:52:01,253 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:01,253 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:01,269 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:01,269 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:01,289 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-09-14 15:52:01,289 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:01,292 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:01,297 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 15 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-09-14 15:52:01,297 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:01,316 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 15 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-09-14 15:52:01,318 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:01,318 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 4, 4, 4, 4] total 10 [2018-09-14 15:52:01,318 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:01,319 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-09-14 15:52:01,319 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-09-14 15:52:01,320 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-09-14 15:52:01,320 INFO L87 Difference]: Start difference. First operand 24 states and 25 transitions. Second operand 8 states. [2018-09-14 15:52:01,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:01,375 INFO L93 Difference]: Finished difference Result 41 states and 47 transitions. [2018-09-14 15:52:01,376 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-09-14 15:52:01,376 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 23 [2018-09-14 15:52:01,376 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:01,379 INFO L225 Difference]: With dead ends: 41 [2018-09-14 15:52:01,379 INFO L226 Difference]: Without dead ends: 31 [2018-09-14 15:52:01,380 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 96 GetRequests, 88 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-09-14 15:52:01,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2018-09-14 15:52:01,385 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 30. [2018-09-14 15:52:01,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-09-14 15:52:01,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 32 transitions. [2018-09-14 15:52:01,387 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 32 transitions. Word has length 23 [2018-09-14 15:52:01,387 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:01,387 INFO L480 AbstractCegarLoop]: Abstraction has 30 states and 32 transitions. [2018-09-14 15:52:01,387 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-09-14 15:52:01,387 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 32 transitions. [2018-09-14 15:52:01,388 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-09-14 15:52:01,388 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:01,389 INFO L376 BasicCegarLoop]: trace histogram [7, 6, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:01,389 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:01,389 INFO L82 PathProgramCache]: Analyzing trace with hash 634861023, now seen corresponding path program 4 times [2018-09-14 15:52:01,389 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:01,390 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:01,390 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:01,391 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:01,391 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:01,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:01,572 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 25 proven. 30 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-09-14 15:52:01,573 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:01,573 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:01,585 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:01,585 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:01,622 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:01,623 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:01,626 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:01,633 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 25 proven. 30 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-09-14 15:52:01,633 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:01,945 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 25 proven. 30 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-09-14 15:52:01,969 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:01,969 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:01,985 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:01,985 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:02,004 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:02,004 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:02,008 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:02,015 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 25 proven. 30 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-09-14 15:52:02,015 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:02,036 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 25 proven. 30 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-09-14 15:52:02,037 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:02,037 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 12 [2018-09-14 15:52:02,038 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:02,038 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-09-14 15:52:02,038 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-09-14 15:52:02,039 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-09-14 15:52:02,039 INFO L87 Difference]: Start difference. First operand 30 states and 32 transitions. Second operand 7 states. [2018-09-14 15:52:02,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:02,089 INFO L93 Difference]: Finished difference Result 46 states and 51 transitions. [2018-09-14 15:52:02,090 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-09-14 15:52:02,090 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 29 [2018-09-14 15:52:02,090 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:02,091 INFO L225 Difference]: With dead ends: 46 [2018-09-14 15:52:02,091 INFO L226 Difference]: Without dead ends: 33 [2018-09-14 15:52:02,092 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 121 GetRequests, 111 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-09-14 15:52:02,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33 states. [2018-09-14 15:52:02,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33 to 33. [2018-09-14 15:52:02,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33 states. [2018-09-14 15:52:02,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 35 transitions. [2018-09-14 15:52:02,097 INFO L78 Accepts]: Start accepts. Automaton has 33 states and 35 transitions. Word has length 29 [2018-09-14 15:52:02,097 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:02,098 INFO L480 AbstractCegarLoop]: Abstraction has 33 states and 35 transitions. [2018-09-14 15:52:02,098 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-09-14 15:52:02,098 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 35 transitions. [2018-09-14 15:52:02,099 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-09-14 15:52:02,099 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:02,099 INFO L376 BasicCegarLoop]: trace histogram [8, 7, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:02,099 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:02,100 INFO L82 PathProgramCache]: Analyzing trace with hash -1611776614, now seen corresponding path program 5 times [2018-09-14 15:52:02,100 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:02,101 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:02,101 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:02,101 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:02,101 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:02,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:02,209 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 30 proven. 45 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-09-14 15:52:02,210 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:02,210 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:02,221 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:02,221 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:02,241 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2018-09-14 15:52:02,242 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:02,245 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:02,253 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 30 proven. 45 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-09-14 15:52:02,253 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:02,439 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 30 proven. 45 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-09-14 15:52:02,459 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:02,460 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:02,474 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:02,475 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:02,513 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2018-09-14 15:52:02,514 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:02,518 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:02,526 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 30 proven. 45 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-09-14 15:52:02,526 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:02,545 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 30 proven. 45 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-09-14 15:52:02,548 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:02,549 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 14 [2018-09-14 15:52:02,549 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:02,549 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-09-14 15:52:02,550 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-09-14 15:52:02,550 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-09-14 15:52:02,550 INFO L87 Difference]: Start difference. First operand 33 states and 35 transitions. Second operand 8 states. [2018-09-14 15:52:02,658 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:02,658 INFO L93 Difference]: Finished difference Result 49 states and 54 transitions. [2018-09-14 15:52:02,659 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-09-14 15:52:02,659 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 32 [2018-09-14 15:52:02,659 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:02,660 INFO L225 Difference]: With dead ends: 49 [2018-09-14 15:52:02,660 INFO L226 Difference]: Without dead ends: 36 [2018-09-14 15:52:02,661 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 134 GetRequests, 122 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-09-14 15:52:02,661 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2018-09-14 15:52:02,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2018-09-14 15:52:02,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2018-09-14 15:52:02,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 38 transitions. [2018-09-14 15:52:02,666 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 38 transitions. Word has length 32 [2018-09-14 15:52:02,666 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:02,667 INFO L480 AbstractCegarLoop]: Abstraction has 36 states and 38 transitions. [2018-09-14 15:52:02,667 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-09-14 15:52:02,667 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 38 transitions. [2018-09-14 15:52:02,668 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-09-14 15:52:02,668 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:02,668 INFO L376 BasicCegarLoop]: trace histogram [9, 8, 6, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:02,668 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:02,669 INFO L82 PathProgramCache]: Analyzing trace with hash 1576720383, now seen corresponding path program 6 times [2018-09-14 15:52:02,669 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:02,669 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:02,670 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:02,670 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:02,670 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:02,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:02,909 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 35 proven. 63 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-09-14 15:52:02,910 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:02,910 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:02,919 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:02,919 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:02,937 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2018-09-14 15:52:02,937 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:02,940 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:03,187 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 23 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:03,188 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:03,428 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 23 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:03,449 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:03,449 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 14 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:03,465 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:03,465 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:03,516 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2018-09-14 15:52:03,516 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:03,520 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:03,538 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 23 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:03,539 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:03,560 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 23 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:03,562 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:03,562 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 10, 10, 10, 10] total 25 [2018-09-14 15:52:03,562 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:03,562 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-09-14 15:52:03,563 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-09-14 15:52:03,563 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2018-09-14 15:52:03,563 INFO L87 Difference]: Start difference. First operand 36 states and 38 transitions. Second operand 17 states. [2018-09-14 15:52:03,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:03,824 INFO L93 Difference]: Finished difference Result 71 states and 89 transitions. [2018-09-14 15:52:03,824 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-09-14 15:52:03,824 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 35 [2018-09-14 15:52:03,825 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:03,825 INFO L225 Difference]: With dead ends: 71 [2018-09-14 15:52:03,825 INFO L226 Difference]: Without dead ends: 58 [2018-09-14 15:52:03,826 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 147 GetRequests, 124 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2018-09-14 15:52:03,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2018-09-14 15:52:03,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 57. [2018-09-14 15:52:03,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 57 states. [2018-09-14 15:52:03,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 65 transitions. [2018-09-14 15:52:03,833 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 65 transitions. Word has length 35 [2018-09-14 15:52:03,834 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:03,834 INFO L480 AbstractCegarLoop]: Abstraction has 57 states and 65 transitions. [2018-09-14 15:52:03,834 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-09-14 15:52:03,834 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 65 transitions. [2018-09-14 15:52:03,836 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-09-14 15:52:03,836 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:03,836 INFO L376 BasicCegarLoop]: trace histogram [16, 15, 8, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:03,836 INFO L423 AbstractCegarLoop]: === Iteration 10 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:03,837 INFO L82 PathProgramCache]: Analyzing trace with hash 1775771482, now seen corresponding path program 7 times [2018-09-14 15:52:03,837 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:03,838 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:03,838 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:03,838 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:03,838 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:03,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:03,961 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 184 proven. 84 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-09-14 15:52:03,961 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:03,961 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:03,968 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:03,968 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:03,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:03,990 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:04,009 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 184 proven. 84 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-09-14 15:52:04,010 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:04,198 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 184 proven. 84 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-09-14 15:52:04,221 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:04,221 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 16 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:04,236 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:04,236 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:04,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:04,277 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:04,297 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 184 proven. 84 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-09-14 15:52:04,297 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:04,363 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 184 proven. 84 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-09-14 15:52:04,364 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:04,364 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 18 [2018-09-14 15:52:04,365 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:04,366 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-09-14 15:52:04,366 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-09-14 15:52:04,366 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-09-14 15:52:04,367 INFO L87 Difference]: Start difference. First operand 57 states and 65 transitions. Second operand 10 states. [2018-09-14 15:52:04,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:04,443 INFO L93 Difference]: Finished difference Result 91 states and 108 transitions. [2018-09-14 15:52:04,444 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-09-14 15:52:04,444 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 56 [2018-09-14 15:52:04,444 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:04,445 INFO L225 Difference]: With dead ends: 91 [2018-09-14 15:52:04,445 INFO L226 Difference]: Without dead ends: 60 [2018-09-14 15:52:04,446 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 232 GetRequests, 216 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-09-14 15:52:04,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2018-09-14 15:52:04,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 60. [2018-09-14 15:52:04,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-09-14 15:52:04,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 68 transitions. [2018-09-14 15:52:04,453 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 68 transitions. Word has length 56 [2018-09-14 15:52:04,454 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:04,454 INFO L480 AbstractCegarLoop]: Abstraction has 60 states and 68 transitions. [2018-09-14 15:52:04,454 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-09-14 15:52:04,454 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 68 transitions. [2018-09-14 15:52:04,455 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-09-14 15:52:04,455 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:04,455 INFO L376 BasicCegarLoop]: trace histogram [17, 16, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:04,456 INFO L423 AbstractCegarLoop]: === Iteration 11 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:04,456 INFO L82 PathProgramCache]: Analyzing trace with hash -112911681, now seen corresponding path program 8 times [2018-09-14 15:52:04,456 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:04,457 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:04,457 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:04,457 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:04,458 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:04,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:04,594 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 207 proven. 108 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-09-14 15:52:04,594 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:04,594 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:04,602 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:04,602 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:04,633 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:04,633 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:04,636 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:04,645 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 207 proven. 108 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-09-14 15:52:04,645 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:04,851 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 207 proven. 108 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-09-14 15:52:04,872 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:04,872 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 18 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:04,889 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:04,889 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:04,925 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:04,925 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:04,929 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:04,938 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 207 proven. 108 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-09-14 15:52:04,939 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:04,981 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 207 proven. 108 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-09-14 15:52:04,984 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:04,985 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 20 [2018-09-14 15:52:04,985 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:04,985 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-09-14 15:52:04,986 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-09-14 15:52:04,986 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-09-14 15:52:04,986 INFO L87 Difference]: Start difference. First operand 60 states and 68 transitions. Second operand 11 states. [2018-09-14 15:52:05,104 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:05,105 INFO L93 Difference]: Finished difference Result 94 states and 111 transitions. [2018-09-14 15:52:05,109 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-09-14 15:52:05,110 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 59 [2018-09-14 15:52:05,110 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:05,111 INFO L225 Difference]: With dead ends: 94 [2018-09-14 15:52:05,111 INFO L226 Difference]: Without dead ends: 63 [2018-09-14 15:52:05,112 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 245 GetRequests, 227 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-09-14 15:52:05,112 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2018-09-14 15:52:05,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 63. [2018-09-14 15:52:05,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-09-14 15:52:05,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 71 transitions. [2018-09-14 15:52:05,119 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 71 transitions. Word has length 59 [2018-09-14 15:52:05,119 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:05,119 INFO L480 AbstractCegarLoop]: Abstraction has 63 states and 71 transitions. [2018-09-14 15:52:05,119 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-09-14 15:52:05,119 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 71 transitions. [2018-09-14 15:52:05,120 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-09-14 15:52:05,121 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:05,121 INFO L376 BasicCegarLoop]: trace histogram [18, 17, 9, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:05,121 INFO L423 AbstractCegarLoop]: === Iteration 12 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:05,121 INFO L82 PathProgramCache]: Analyzing trace with hash -1801443014, now seen corresponding path program 9 times [2018-09-14 15:52:05,121 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:05,122 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:05,122 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:05,123 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:05,123 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:05,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:05,410 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 230 proven. 135 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-09-14 15:52:05,410 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:05,410 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:05,418 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:05,418 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:05,442 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 14 check-sat command(s) [2018-09-14 15:52:05,443 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:05,446 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:06,113 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 234 proven. 100 refuted. 0 times theorem prover too weak. 108 trivial. 0 not checked. [2018-09-14 15:52:06,114 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:06,406 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 234 proven. 100 refuted. 0 times theorem prover too weak. 108 trivial. 0 not checked. [2018-09-14 15:52:06,426 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:06,427 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 20 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:06,442 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:06,442 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:06,532 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 14 check-sat command(s) [2018-09-14 15:52:06,532 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:06,536 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:06,543 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 234 proven. 100 refuted. 0 times theorem prover too weak. 108 trivial. 0 not checked. [2018-09-14 15:52:06,543 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:06,601 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 234 proven. 100 refuted. 0 times theorem prover too weak. 108 trivial. 0 not checked. [2018-09-14 15:52:06,605 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:06,605 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11, 11, 11, 11] total 30 [2018-09-14 15:52:06,606 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:06,606 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-09-14 15:52:06,606 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-09-14 15:52:06,607 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-09-14 15:52:06,607 INFO L87 Difference]: Start difference. First operand 63 states and 71 transitions. Second operand 21 states. [2018-09-14 15:52:06,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:06,811 INFO L93 Difference]: Finished difference Result 101 states and 121 transitions. [2018-09-14 15:52:06,811 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-09-14 15:52:06,811 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 62 [2018-09-14 15:52:06,812 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:06,812 INFO L225 Difference]: With dead ends: 101 [2018-09-14 15:52:06,812 INFO L226 Difference]: Without dead ends: 70 [2018-09-14 15:52:06,813 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 258 GetRequests, 230 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-09-14 15:52:06,814 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states. [2018-09-14 15:52:06,819 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 69. [2018-09-14 15:52:06,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2018-09-14 15:52:06,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 78 transitions. [2018-09-14 15:52:06,820 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 78 transitions. Word has length 62 [2018-09-14 15:52:06,820 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:06,820 INFO L480 AbstractCegarLoop]: Abstraction has 69 states and 78 transitions. [2018-09-14 15:52:06,820 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-09-14 15:52:06,820 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 78 transitions. [2018-09-14 15:52:06,821 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-09-14 15:52:06,821 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:06,822 INFO L376 BasicCegarLoop]: trace histogram [20, 19, 10, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:06,822 INFO L423 AbstractCegarLoop]: === Iteration 13 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:06,822 INFO L82 PathProgramCache]: Analyzing trace with hash 348314524, now seen corresponding path program 10 times [2018-09-14 15:52:06,822 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:06,823 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:06,823 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:06,823 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:06,823 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:06,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:06,970 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 286 proven. 165 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:06,970 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:06,970 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:06,979 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:06,979 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:06,998 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:06,999 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:07,002 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:07,014 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 286 proven. 165 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:07,014 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:07,231 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 286 proven. 165 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:07,251 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:07,251 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 22 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:07,267 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:07,267 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:07,308 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:07,308 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:07,312 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:07,321 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 286 proven. 165 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:07,321 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:07,376 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 286 proven. 165 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:07,379 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:07,379 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 24 [2018-09-14 15:52:07,379 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:07,380 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-09-14 15:52:07,380 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-09-14 15:52:07,381 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-09-14 15:52:07,381 INFO L87 Difference]: Start difference. First operand 69 states and 78 transitions. Second operand 13 states. [2018-09-14 15:52:07,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:07,643 INFO L93 Difference]: Finished difference Result 106 states and 125 transitions. [2018-09-14 15:52:07,644 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-09-14 15:52:07,645 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 68 [2018-09-14 15:52:07,645 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:07,646 INFO L225 Difference]: With dead ends: 106 [2018-09-14 15:52:07,646 INFO L226 Difference]: Without dead ends: 72 [2018-09-14 15:52:07,647 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 283 GetRequests, 261 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-09-14 15:52:07,647 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states. [2018-09-14 15:52:07,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 72. [2018-09-14 15:52:07,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-09-14 15:52:07,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 81 transitions. [2018-09-14 15:52:07,655 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 81 transitions. Word has length 68 [2018-09-14 15:52:07,656 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:07,656 INFO L480 AbstractCegarLoop]: Abstraction has 72 states and 81 transitions. [2018-09-14 15:52:07,656 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-09-14 15:52:07,656 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 81 transitions. [2018-09-14 15:52:07,657 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-09-14 15:52:07,658 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:07,658 INFO L376 BasicCegarLoop]: trace histogram [21, 20, 11, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:07,658 INFO L423 AbstractCegarLoop]: === Iteration 14 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:07,659 INFO L82 PathProgramCache]: Analyzing trace with hash 1933633409, now seen corresponding path program 11 times [2018-09-14 15:52:07,659 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:07,662 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:07,662 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:07,662 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:07,662 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:07,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:07,807 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 312 proven. 198 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:07,807 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:07,807 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:07,818 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:07,818 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:07,877 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 21 check-sat command(s) [2018-09-14 15:52:07,878 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:07,880 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:07,893 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 312 proven. 198 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:07,893 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:08,179 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 312 proven. 198 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:08,199 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:08,199 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 24 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:08,214 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:08,214 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:08,383 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 21 check-sat command(s) [2018-09-14 15:52:08,383 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:08,387 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:08,397 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 312 proven. 198 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:08,397 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:08,463 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 312 proven. 198 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:08,466 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:08,467 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 26 [2018-09-14 15:52:08,467 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:08,467 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-09-14 15:52:08,468 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-09-14 15:52:08,468 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-09-14 15:52:08,468 INFO L87 Difference]: Start difference. First operand 72 states and 81 transitions. Second operand 14 states. [2018-09-14 15:52:08,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:08,598 INFO L93 Difference]: Finished difference Result 109 states and 128 transitions. [2018-09-14 15:52:08,598 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-09-14 15:52:08,598 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 71 [2018-09-14 15:52:08,599 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:08,599 INFO L225 Difference]: With dead ends: 109 [2018-09-14 15:52:08,600 INFO L226 Difference]: Without dead ends: 75 [2018-09-14 15:52:08,601 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 296 GetRequests, 272 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-09-14 15:52:08,601 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states. [2018-09-14 15:52:08,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 75. [2018-09-14 15:52:08,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 75 states. [2018-09-14 15:52:08,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 84 transitions. [2018-09-14 15:52:08,608 INFO L78 Accepts]: Start accepts. Automaton has 75 states and 84 transitions. Word has length 71 [2018-09-14 15:52:08,608 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:08,608 INFO L480 AbstractCegarLoop]: Abstraction has 75 states and 84 transitions. [2018-09-14 15:52:08,608 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-09-14 15:52:08,608 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 84 transitions. [2018-09-14 15:52:08,609 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-09-14 15:52:08,609 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:08,610 INFO L376 BasicCegarLoop]: trace histogram [22, 21, 12, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:08,610 INFO L423 AbstractCegarLoop]: === Iteration 15 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:08,610 INFO L82 PathProgramCache]: Analyzing trace with hash -1586817668, now seen corresponding path program 12 times [2018-09-14 15:52:08,610 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:08,611 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:08,611 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:08,611 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:08,611 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:08,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:08,846 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 338 proven. 234 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:08,846 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:08,846 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:08,854 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:08,854 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:08,881 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 20 check-sat command(s) [2018-09-14 15:52:08,881 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:08,883 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:08,895 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 338 proven. 234 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:08,895 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:09,165 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 338 proven. 234 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:09,190 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:09,190 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 26 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:09,205 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:09,206 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:09,344 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 20 check-sat command(s) [2018-09-14 15:52:09,344 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:09,348 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:09,360 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 338 proven. 234 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:09,361 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:09,408 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 338 proven. 234 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:09,409 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:09,409 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 28 [2018-09-14 15:52:09,410 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:09,410 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-09-14 15:52:09,410 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-09-14 15:52:09,411 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-09-14 15:52:09,411 INFO L87 Difference]: Start difference. First operand 75 states and 84 transitions. Second operand 15 states. [2018-09-14 15:52:09,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:09,481 INFO L93 Difference]: Finished difference Result 112 states and 131 transitions. [2018-09-14 15:52:09,481 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-09-14 15:52:09,481 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 74 [2018-09-14 15:52:09,481 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:09,482 INFO L225 Difference]: With dead ends: 112 [2018-09-14 15:52:09,482 INFO L226 Difference]: Without dead ends: 78 [2018-09-14 15:52:09,483 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 309 GetRequests, 283 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-09-14 15:52:09,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states. [2018-09-14 15:52:09,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 78. [2018-09-14 15:52:09,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-09-14 15:52:09,489 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 87 transitions. [2018-09-14 15:52:09,489 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 87 transitions. Word has length 74 [2018-09-14 15:52:09,489 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:09,489 INFO L480 AbstractCegarLoop]: Abstraction has 78 states and 87 transitions. [2018-09-14 15:52:09,490 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-09-14 15:52:09,490 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 87 transitions. [2018-09-14 15:52:09,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-09-14 15:52:09,491 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:09,491 INFO L376 BasicCegarLoop]: trace histogram [23, 22, 13, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:09,491 INFO L423 AbstractCegarLoop]: === Iteration 16 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:09,491 INFO L82 PathProgramCache]: Analyzing trace with hash -538451551, now seen corresponding path program 13 times [2018-09-14 15:52:09,491 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:09,492 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:09,492 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:09,492 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:09,493 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:09,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:09,714 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 364 proven. 273 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:09,715 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:09,715 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:09,723 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:09,723 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:09,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:09,739 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:09,750 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 364 proven. 273 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:09,750 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:10,028 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 364 proven. 273 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:10,051 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:10,051 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 28 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:10,067 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:10,068 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:10,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:10,116 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:10,125 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 364 proven. 273 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:10,125 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:10,157 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 364 proven. 273 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:10,158 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:10,158 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 30 [2018-09-14 15:52:10,158 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:10,159 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-09-14 15:52:10,159 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-09-14 15:52:10,159 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-09-14 15:52:10,160 INFO L87 Difference]: Start difference. First operand 78 states and 87 transitions. Second operand 16 states. [2018-09-14 15:52:10,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:10,253 INFO L93 Difference]: Finished difference Result 115 states and 134 transitions. [2018-09-14 15:52:10,254 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-09-14 15:52:10,255 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 77 [2018-09-14 15:52:10,255 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:10,255 INFO L225 Difference]: With dead ends: 115 [2018-09-14 15:52:10,256 INFO L226 Difference]: Without dead ends: 81 [2018-09-14 15:52:10,256 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 322 GetRequests, 294 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-09-14 15:52:10,256 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states. [2018-09-14 15:52:10,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 81. [2018-09-14 15:52:10,261 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-09-14 15:52:10,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 90 transitions. [2018-09-14 15:52:10,262 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 90 transitions. Word has length 77 [2018-09-14 15:52:10,263 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:10,263 INFO L480 AbstractCegarLoop]: Abstraction has 81 states and 90 transitions. [2018-09-14 15:52:10,263 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-09-14 15:52:10,263 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 90 transitions. [2018-09-14 15:52:10,264 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-09-14 15:52:10,264 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:10,264 INFO L376 BasicCegarLoop]: trace histogram [24, 23, 14, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:10,264 INFO L423 AbstractCegarLoop]: === Iteration 17 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:10,265 INFO L82 PathProgramCache]: Analyzing trace with hash -1665636516, now seen corresponding path program 14 times [2018-09-14 15:52:10,265 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:10,265 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:10,266 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:10,266 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:10,266 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:10,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:10,489 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 390 proven. 315 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:10,490 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:10,490 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:10,497 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:10,497 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:10,517 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:10,517 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:10,519 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:10,532 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 390 proven. 315 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:10,532 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:11,286 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 390 proven. 315 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:11,307 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:11,307 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 30 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:11,321 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:11,322 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:11,364 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:11,365 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:11,368 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:11,379 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 390 proven. 315 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:11,379 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:11,413 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 390 proven. 315 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:11,414 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:11,414 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 32 [2018-09-14 15:52:11,414 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:11,414 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-09-14 15:52:11,414 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-09-14 15:52:11,415 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-09-14 15:52:11,415 INFO L87 Difference]: Start difference. First operand 81 states and 90 transitions. Second operand 17 states. [2018-09-14 15:52:11,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:11,564 INFO L93 Difference]: Finished difference Result 118 states and 137 transitions. [2018-09-14 15:52:11,564 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-09-14 15:52:11,564 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 80 [2018-09-14 15:52:11,564 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:11,565 INFO L225 Difference]: With dead ends: 118 [2018-09-14 15:52:11,565 INFO L226 Difference]: Without dead ends: 84 [2018-09-14 15:52:11,566 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 335 GetRequests, 305 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-09-14 15:52:11,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2018-09-14 15:52:11,570 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 84. [2018-09-14 15:52:11,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-09-14 15:52:11,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 93 transitions. [2018-09-14 15:52:11,571 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 93 transitions. Word has length 80 [2018-09-14 15:52:11,571 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:11,572 INFO L480 AbstractCegarLoop]: Abstraction has 84 states and 93 transitions. [2018-09-14 15:52:11,572 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-09-14 15:52:11,572 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 93 transitions. [2018-09-14 15:52:11,572 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-09-14 15:52:11,573 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:11,573 INFO L376 BasicCegarLoop]: trace histogram [25, 24, 15, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:11,573 INFO L423 AbstractCegarLoop]: === Iteration 18 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:11,573 INFO L82 PathProgramCache]: Analyzing trace with hash 716358593, now seen corresponding path program 15 times [2018-09-14 15:52:11,573 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:11,574 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:11,574 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:11,574 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:11,574 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:11,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:11,745 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 416 proven. 360 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-09-14 15:52:11,746 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:11,746 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:11,757 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:11,757 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:11,782 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2018-09-14 15:52:11,783 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:11,785 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:12,462 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 435 proven. 126 refuted. 0 times theorem prover too weak. 315 trivial. 0 not checked. [2018-09-14 15:52:12,463 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:13,120 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 435 proven. 126 refuted. 0 times theorem prover too weak. 315 trivial. 0 not checked. [2018-09-14 15:52:13,139 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:13,139 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 32 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:13,154 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:13,154 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:13,247 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2018-09-14 15:52:13,248 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:13,251 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:13,260 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 435 proven. 126 refuted. 0 times theorem prover too weak. 315 trivial. 0 not checked. [2018-09-14 15:52:13,261 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:13,308 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 435 proven. 126 refuted. 0 times theorem prover too weak. 315 trivial. 0 not checked. [2018-09-14 15:52:13,310 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:13,310 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 12, 12, 12, 12] total 38 [2018-09-14 15:52:13,310 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:13,311 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-09-14 15:52:13,311 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-09-14 15:52:13,312 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-09-14 15:52:13,312 INFO L87 Difference]: Start difference. First operand 84 states and 93 transitions. Second operand 28 states. [2018-09-14 15:52:13,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:13,688 INFO L93 Difference]: Finished difference Result 125 states and 147 transitions. [2018-09-14 15:52:13,692 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-09-14 15:52:13,692 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 83 [2018-09-14 15:52:13,692 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:13,693 INFO L225 Difference]: With dead ends: 125 [2018-09-14 15:52:13,693 INFO L226 Difference]: Without dead ends: 91 [2018-09-14 15:52:13,694 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 348 GetRequests, 312 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-09-14 15:52:13,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states. [2018-09-14 15:52:13,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 90. [2018-09-14 15:52:13,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. [2018-09-14 15:52:13,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 100 transitions. [2018-09-14 15:52:13,702 INFO L78 Accepts]: Start accepts. Automaton has 90 states and 100 transitions. Word has length 83 [2018-09-14 15:52:13,702 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:13,702 INFO L480 AbstractCegarLoop]: Abstraction has 90 states and 100 transitions. [2018-09-14 15:52:13,702 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-09-14 15:52:13,703 INFO L276 IsEmpty]: Start isEmpty. Operand 90 states and 100 transitions. [2018-09-14 15:52:13,703 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-09-14 15:52:13,703 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:13,704 INFO L376 BasicCegarLoop]: trace histogram [27, 26, 16, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:13,704 INFO L423 AbstractCegarLoop]: === Iteration 19 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:13,704 INFO L82 PathProgramCache]: Analyzing trace with hash 223548959, now seen corresponding path program 16 times [2018-09-14 15:52:13,704 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:13,705 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:13,705 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:13,705 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:13,705 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:13,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:13,959 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 493 proven. 408 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:13,959 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:13,959 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:13,967 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:13,967 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:13,990 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:13,990 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:13,991 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:14,002 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 493 proven. 408 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:14,002 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:14,903 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 493 proven. 408 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:14,923 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:14,924 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 34 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:14,938 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:14,938 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:14,987 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:14,988 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:14,992 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:15,004 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 493 proven. 408 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:15,004 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:15,059 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 493 proven. 408 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:15,060 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:15,060 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 36 [2018-09-14 15:52:15,061 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:15,061 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-09-14 15:52:15,061 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-09-14 15:52:15,062 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-09-14 15:52:15,062 INFO L87 Difference]: Start difference. First operand 90 states and 100 transitions. Second operand 19 states. [2018-09-14 15:52:15,120 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:15,120 INFO L93 Difference]: Finished difference Result 130 states and 151 transitions. [2018-09-14 15:52:15,120 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-09-14 15:52:15,120 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 89 [2018-09-14 15:52:15,121 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:15,122 INFO L225 Difference]: With dead ends: 130 [2018-09-14 15:52:15,122 INFO L226 Difference]: Without dead ends: 93 [2018-09-14 15:52:15,123 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 373 GetRequests, 339 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-09-14 15:52:15,123 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2018-09-14 15:52:15,126 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 93. [2018-09-14 15:52:15,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93 states. [2018-09-14 15:52:15,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 103 transitions. [2018-09-14 15:52:15,126 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 103 transitions. Word has length 89 [2018-09-14 15:52:15,127 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:15,127 INFO L480 AbstractCegarLoop]: Abstraction has 93 states and 103 transitions. [2018-09-14 15:52:15,127 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-09-14 15:52:15,127 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 103 transitions. [2018-09-14 15:52:15,128 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-09-14 15:52:15,128 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:15,128 INFO L376 BasicCegarLoop]: trace histogram [28, 27, 17, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:15,128 INFO L423 AbstractCegarLoop]: === Iteration 20 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:15,129 INFO L82 PathProgramCache]: Analyzing trace with hash 1580850010, now seen corresponding path program 17 times [2018-09-14 15:52:15,129 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:15,129 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:15,130 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:15,130 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:15,130 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:15,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:16,191 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 522 proven. 459 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:16,192 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:16,192 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:16,201 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:16,201 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:16,242 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2018-09-14 15:52:16,242 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:16,244 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:16,256 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 522 proven. 459 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:16,256 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:16,667 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 522 proven. 459 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:16,689 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:16,689 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 36 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:16,704 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:16,704 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:16,886 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2018-09-14 15:52:16,886 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:16,890 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:16,902 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 522 proven. 459 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:16,902 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:16,938 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 522 proven. 459 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:16,939 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:16,940 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 38 [2018-09-14 15:52:16,940 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:16,940 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-09-14 15:52:16,940 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-09-14 15:52:16,941 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-09-14 15:52:16,941 INFO L87 Difference]: Start difference. First operand 93 states and 103 transitions. Second operand 20 states. [2018-09-14 15:52:17,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:17,051 INFO L93 Difference]: Finished difference Result 133 states and 154 transitions. [2018-09-14 15:52:17,052 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-09-14 15:52:17,052 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 92 [2018-09-14 15:52:17,052 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:17,053 INFO L225 Difference]: With dead ends: 133 [2018-09-14 15:52:17,053 INFO L226 Difference]: Without dead ends: 96 [2018-09-14 15:52:17,055 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 386 GetRequests, 350 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-09-14 15:52:17,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-09-14 15:52:17,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 96. [2018-09-14 15:52:17,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 96 states. [2018-09-14 15:52:17,060 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96 states to 96 states and 106 transitions. [2018-09-14 15:52:17,060 INFO L78 Accepts]: Start accepts. Automaton has 96 states and 106 transitions. Word has length 92 [2018-09-14 15:52:17,060 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:17,060 INFO L480 AbstractCegarLoop]: Abstraction has 96 states and 106 transitions. [2018-09-14 15:52:17,060 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-09-14 15:52:17,061 INFO L276 IsEmpty]: Start isEmpty. Operand 96 states and 106 transitions. [2018-09-14 15:52:17,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-09-14 15:52:17,062 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:17,062 INFO L376 BasicCegarLoop]: trace histogram [29, 28, 18, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:17,062 INFO L423 AbstractCegarLoop]: === Iteration 21 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:17,062 INFO L82 PathProgramCache]: Analyzing trace with hash -180631489, now seen corresponding path program 18 times [2018-09-14 15:52:17,062 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:17,063 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:17,063 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:17,064 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:17,064 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:17,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:17,482 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 551 proven. 513 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:17,482 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:17,483 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:17,491 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:17,491 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:17,539 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 29 check-sat command(s) [2018-09-14 15:52:17,540 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:17,543 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:17,563 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 551 proven. 513 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:17,563 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:18,562 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 551 proven. 513 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:18,582 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:18,582 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 38 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:18,597 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:18,597 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:18,819 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 29 check-sat command(s) [2018-09-14 15:52:18,819 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:18,822 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:18,835 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 551 proven. 513 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:18,835 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:18,850 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 551 proven. 513 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:18,852 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:18,852 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 40 [2018-09-14 15:52:18,852 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:18,853 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-09-14 15:52:18,853 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-09-14 15:52:18,854 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-09-14 15:52:18,854 INFO L87 Difference]: Start difference. First operand 96 states and 106 transitions. Second operand 21 states. [2018-09-14 15:52:18,944 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:18,944 INFO L93 Difference]: Finished difference Result 136 states and 157 transitions. [2018-09-14 15:52:18,944 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-09-14 15:52:18,945 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 95 [2018-09-14 15:52:18,945 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:18,945 INFO L225 Difference]: With dead ends: 136 [2018-09-14 15:52:18,946 INFO L226 Difference]: Without dead ends: 99 [2018-09-14 15:52:18,946 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 399 GetRequests, 361 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-09-14 15:52:18,947 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states. [2018-09-14 15:52:18,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 99. [2018-09-14 15:52:18,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2018-09-14 15:52:18,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 109 transitions. [2018-09-14 15:52:18,951 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 109 transitions. Word has length 95 [2018-09-14 15:52:18,951 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:18,951 INFO L480 AbstractCegarLoop]: Abstraction has 99 states and 109 transitions. [2018-09-14 15:52:18,951 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-09-14 15:52:18,951 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 109 transitions. [2018-09-14 15:52:18,952 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-09-14 15:52:18,952 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:18,952 INFO L376 BasicCegarLoop]: trace histogram [30, 29, 19, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:18,952 INFO L423 AbstractCegarLoop]: === Iteration 22 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:18,952 INFO L82 PathProgramCache]: Analyzing trace with hash -565545670, now seen corresponding path program 19 times [2018-09-14 15:52:18,952 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:18,953 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:18,953 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:18,953 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:18,953 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:18,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:19,238 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 580 proven. 570 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:19,239 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:19,239 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:19,246 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:19,246 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:19,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:19,271 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:19,283 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 580 proven. 570 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:19,283 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:19,730 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 580 proven. 570 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:19,751 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:19,751 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 40 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:19,766 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:19,766 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:19,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:19,815 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:19,826 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 580 proven. 570 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:19,827 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:19,846 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 580 proven. 570 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:19,847 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:19,847 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22, 22, 22] total 42 [2018-09-14 15:52:19,847 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:19,847 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-09-14 15:52:19,847 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-09-14 15:52:19,848 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-09-14 15:52:19,848 INFO L87 Difference]: Start difference. First operand 99 states and 109 transitions. Second operand 22 states. [2018-09-14 15:52:19,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:19,933 INFO L93 Difference]: Finished difference Result 139 states and 160 transitions. [2018-09-14 15:52:19,936 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-09-14 15:52:19,936 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 98 [2018-09-14 15:52:19,936 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:19,937 INFO L225 Difference]: With dead ends: 139 [2018-09-14 15:52:19,937 INFO L226 Difference]: Without dead ends: 102 [2018-09-14 15:52:19,938 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 412 GetRequests, 372 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-09-14 15:52:19,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states. [2018-09-14 15:52:19,941 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 102. [2018-09-14 15:52:19,941 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-09-14 15:52:19,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 112 transitions. [2018-09-14 15:52:19,942 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 112 transitions. Word has length 98 [2018-09-14 15:52:19,942 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:19,942 INFO L480 AbstractCegarLoop]: Abstraction has 102 states and 112 transitions. [2018-09-14 15:52:19,942 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-09-14 15:52:19,942 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 112 transitions. [2018-09-14 15:52:19,943 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2018-09-14 15:52:19,943 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:19,944 INFO L376 BasicCegarLoop]: trace histogram [31, 30, 20, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:19,944 INFO L423 AbstractCegarLoop]: === Iteration 23 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:19,944 INFO L82 PathProgramCache]: Analyzing trace with hash 18768479, now seen corresponding path program 20 times [2018-09-14 15:52:19,944 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:19,945 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:19,945 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:19,945 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:19,945 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:19,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:20,261 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 609 proven. 630 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:20,261 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:20,261 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:20,274 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:20,274 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:20,298 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:20,299 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:20,300 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:20,314 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 609 proven. 630 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:20,314 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:20,904 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 609 proven. 630 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:20,926 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:20,926 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 42 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:20,941 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:20,942 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:20,994 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:20,994 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:20,998 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:21,011 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 609 proven. 630 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:21,011 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:21,037 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 609 proven. 630 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:21,038 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:21,039 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 44 [2018-09-14 15:52:21,039 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:21,039 INFO L459 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-09-14 15:52:21,040 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-09-14 15:52:21,040 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-09-14 15:52:21,040 INFO L87 Difference]: Start difference. First operand 102 states and 112 transitions. Second operand 23 states. [2018-09-14 15:52:21,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:21,148 INFO L93 Difference]: Finished difference Result 142 states and 163 transitions. [2018-09-14 15:52:21,148 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-09-14 15:52:21,148 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 101 [2018-09-14 15:52:21,148 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:21,149 INFO L225 Difference]: With dead ends: 142 [2018-09-14 15:52:21,150 INFO L226 Difference]: Without dead ends: 105 [2018-09-14 15:52:21,151 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 425 GetRequests, 383 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-09-14 15:52:21,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2018-09-14 15:52:21,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 105. [2018-09-14 15:52:21,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-09-14 15:52:21,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 115 transitions. [2018-09-14 15:52:21,155 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 115 transitions. Word has length 101 [2018-09-14 15:52:21,155 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:21,155 INFO L480 AbstractCegarLoop]: Abstraction has 105 states and 115 transitions. [2018-09-14 15:52:21,156 INFO L481 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-09-14 15:52:21,156 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 115 transitions. [2018-09-14 15:52:21,156 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-09-14 15:52:21,157 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:21,157 INFO L376 BasicCegarLoop]: trace histogram [32, 31, 21, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:21,157 INFO L423 AbstractCegarLoop]: === Iteration 24 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:21,157 INFO L82 PathProgramCache]: Analyzing trace with hash -180869350, now seen corresponding path program 21 times [2018-09-14 15:52:21,157 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:21,158 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:21,158 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:21,158 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:21,158 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:21,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:21,581 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 638 proven. 693 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-09-14 15:52:21,581 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:21,581 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:21,590 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:21,590 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:21,617 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 17 check-sat command(s) [2018-09-14 15:52:21,617 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:21,619 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:21,875 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 672 proven. 155 refuted. 0 times theorem prover too weak. 630 trivial. 0 not checked. [2018-09-14 15:52:21,875 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:22,240 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 672 proven. 155 refuted. 0 times theorem prover too weak. 630 trivial. 0 not checked. [2018-09-14 15:52:22,260 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:22,260 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 44 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:22,275 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:22,275 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:22,386 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 17 check-sat command(s) [2018-09-14 15:52:22,386 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:22,389 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:22,399 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 672 proven. 155 refuted. 0 times theorem prover too weak. 630 trivial. 0 not checked. [2018-09-14 15:52:22,399 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:22,467 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 672 proven. 155 refuted. 0 times theorem prover too weak. 630 trivial. 0 not checked. [2018-09-14 15:52:22,468 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:22,469 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 13, 13, 13, 13] total 46 [2018-09-14 15:52:22,469 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:22,469 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-09-14 15:52:22,470 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-09-14 15:52:22,470 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-09-14 15:52:22,471 INFO L87 Difference]: Start difference. First operand 105 states and 115 transitions. Second operand 35 states. [2018-09-14 15:52:22,706 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:22,706 INFO L93 Difference]: Finished difference Result 149 states and 173 transitions. [2018-09-14 15:52:22,707 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-09-14 15:52:22,707 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 104 [2018-09-14 15:52:22,707 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:22,708 INFO L225 Difference]: With dead ends: 149 [2018-09-14 15:52:22,708 INFO L226 Difference]: Without dead ends: 112 [2018-09-14 15:52:22,710 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 438 GetRequests, 394 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-09-14 15:52:22,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-09-14 15:52:22,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 111. [2018-09-14 15:52:22,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-09-14 15:52:22,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 122 transitions. [2018-09-14 15:52:22,715 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 122 transitions. Word has length 104 [2018-09-14 15:52:22,715 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:22,715 INFO L480 AbstractCegarLoop]: Abstraction has 111 states and 122 transitions. [2018-09-14 15:52:22,715 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-09-14 15:52:22,715 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 122 transitions. [2018-09-14 15:52:22,716 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-09-14 15:52:22,716 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:22,716 INFO L376 BasicCegarLoop]: trace histogram [34, 33, 22, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:22,716 INFO L423 AbstractCegarLoop]: === Iteration 25 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:22,716 INFO L82 PathProgramCache]: Analyzing trace with hash 102799356, now seen corresponding path program 22 times [2018-09-14 15:52:22,717 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:22,717 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:22,717 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:22,717 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:22,718 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:22,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:23,094 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 736 proven. 759 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-09-14 15:52:23,095 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:23,095 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:23,102 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:23,103 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:23,129 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:23,129 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:23,131 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:23,146 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 736 proven. 759 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-09-14 15:52:23,146 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:24,212 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 736 proven. 759 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-09-14 15:52:24,232 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:24,232 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 46 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:24,247 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:24,248 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:24,302 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:24,303 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:24,307 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:24,321 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 736 proven. 759 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-09-14 15:52:24,322 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:24,366 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 736 proven. 759 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-09-14 15:52:24,367 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:24,368 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 48 [2018-09-14 15:52:24,368 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:24,368 INFO L459 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-09-14 15:52:24,368 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-09-14 15:52:24,369 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-09-14 15:52:24,369 INFO L87 Difference]: Start difference. First operand 111 states and 122 transitions. Second operand 25 states. [2018-09-14 15:52:24,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:24,464 INFO L93 Difference]: Finished difference Result 154 states and 177 transitions. [2018-09-14 15:52:24,465 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-09-14 15:52:24,466 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 110 [2018-09-14 15:52:24,466 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:24,467 INFO L225 Difference]: With dead ends: 154 [2018-09-14 15:52:24,467 INFO L226 Difference]: Without dead ends: 114 [2018-09-14 15:52:24,468 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 463 GetRequests, 417 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-09-14 15:52:24,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-09-14 15:52:24,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 114. [2018-09-14 15:52:24,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-09-14 15:52:24,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 125 transitions. [2018-09-14 15:52:24,472 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 125 transitions. Word has length 110 [2018-09-14 15:52:24,472 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:24,472 INFO L480 AbstractCegarLoop]: Abstraction has 114 states and 125 transitions. [2018-09-14 15:52:24,472 INFO L481 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-09-14 15:52:24,472 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 125 transitions. [2018-09-14 15:52:24,473 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-09-14 15:52:24,473 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:24,473 INFO L376 BasicCegarLoop]: trace histogram [35, 34, 23, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:24,474 INFO L423 AbstractCegarLoop]: === Iteration 26 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:24,474 INFO L82 PathProgramCache]: Analyzing trace with hash 1248392609, now seen corresponding path program 23 times [2018-09-14 15:52:24,474 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:24,474 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:24,475 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:24,475 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:24,475 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:24,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:25,078 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 768 proven. 828 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-09-14 15:52:25,078 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:25,078 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:25,088 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:25,088 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:25,145 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 35 check-sat command(s) [2018-09-14 15:52:25,145 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:25,149 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:25,165 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 768 proven. 828 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-09-14 15:52:25,165 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:25,914 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 768 proven. 828 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-09-14 15:52:25,933 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:25,934 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 48 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:25,952 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:25,952 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:26,200 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 35 check-sat command(s) [2018-09-14 15:52:26,200 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:26,204 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:26,216 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 768 proven. 828 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-09-14 15:52:26,216 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:26,234 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 768 proven. 828 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-09-14 15:52:26,235 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:26,235 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 50 [2018-09-14 15:52:26,235 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:26,236 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-09-14 15:52:26,236 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-09-14 15:52:26,237 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-09-14 15:52:26,237 INFO L87 Difference]: Start difference. First operand 114 states and 125 transitions. Second operand 26 states. [2018-09-14 15:52:26,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:26,453 INFO L93 Difference]: Finished difference Result 157 states and 180 transitions. [2018-09-14 15:52:26,453 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-09-14 15:52:26,453 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 113 [2018-09-14 15:52:26,453 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:26,454 INFO L225 Difference]: With dead ends: 157 [2018-09-14 15:52:26,454 INFO L226 Difference]: Without dead ends: 117 [2018-09-14 15:52:26,455 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 476 GetRequests, 428 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-09-14 15:52:26,455 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states. [2018-09-14 15:52:26,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2018-09-14 15:52:26,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-09-14 15:52:26,458 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 128 transitions. [2018-09-14 15:52:26,458 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 128 transitions. Word has length 113 [2018-09-14 15:52:26,458 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:26,458 INFO L480 AbstractCegarLoop]: Abstraction has 117 states and 128 transitions. [2018-09-14 15:52:26,458 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-09-14 15:52:26,458 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 128 transitions. [2018-09-14 15:52:26,459 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-09-14 15:52:26,459 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:26,459 INFO L376 BasicCegarLoop]: trace histogram [36, 35, 24, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:26,459 INFO L423 AbstractCegarLoop]: === Iteration 27 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:26,459 INFO L82 PathProgramCache]: Analyzing trace with hash 1806858716, now seen corresponding path program 24 times [2018-09-14 15:52:26,460 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:26,460 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:26,460 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:26,460 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:26,460 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:26,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:26,909 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 800 proven. 900 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-09-14 15:52:26,910 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:26,910 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:26,918 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:26,918 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:27,008 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 35 check-sat command(s) [2018-09-14 15:52:27,008 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:27,013 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:28,673 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 852 proven. 805 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-09-14 15:52:28,674 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:29,684 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 852 proven. 805 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-09-14 15:52:29,704 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:29,704 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 50 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:29,720 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:29,720 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:30,142 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 35 check-sat command(s) [2018-09-14 15:52:30,142 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:30,147 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:30,163 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 884 proven. 737 refuted. 0 times theorem prover too weak. 234 trivial. 0 not checked. [2018-09-14 15:52:30,163 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:30,229 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 884 proven. 737 refuted. 0 times theorem prover too weak. 234 trivial. 0 not checked. [2018-09-14 15:52:30,230 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:30,231 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 26, 26, 25, 25] total 75 [2018-09-14 15:52:30,231 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:30,231 INFO L459 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-09-14 15:52:30,232 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-09-14 15:52:30,234 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=2775, Invalid=2775, Unknown=0, NotChecked=0, Total=5550 [2018-09-14 15:52:30,234 INFO L87 Difference]: Start difference. First operand 117 states and 128 transitions. Second operand 51 states. [2018-09-14 15:52:30,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:30,652 INFO L93 Difference]: Finished difference Result 200 states and 250 transitions. [2018-09-14 15:52:30,652 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-09-14 15:52:30,653 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 116 [2018-09-14 15:52:30,653 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:30,654 INFO L225 Difference]: With dead ends: 200 [2018-09-14 15:52:30,654 INFO L226 Difference]: Without dead ends: 160 [2018-09-14 15:52:30,657 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 489 GetRequests, 416 SyntacticMatches, 0 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=2775, Invalid=2775, Unknown=0, NotChecked=0, Total=5550 [2018-09-14 15:52:30,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states. [2018-09-14 15:52:30,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 159. [2018-09-14 15:52:30,662 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159 states. [2018-09-14 15:52:30,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 183 transitions. [2018-09-14 15:52:30,663 INFO L78 Accepts]: Start accepts. Automaton has 159 states and 183 transitions. Word has length 116 [2018-09-14 15:52:30,663 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:30,663 INFO L480 AbstractCegarLoop]: Abstraction has 159 states and 183 transitions. [2018-09-14 15:52:30,663 INFO L481 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-09-14 15:52:30,663 INFO L276 IsEmpty]: Start isEmpty. Operand 159 states and 183 transitions. [2018-09-14 15:52:30,664 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 159 [2018-09-14 15:52:30,664 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:30,664 INFO L376 BasicCegarLoop]: trace histogram [50, 49, 25, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:30,664 INFO L423 AbstractCegarLoop]: === Iteration 28 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:30,665 INFO L82 PathProgramCache]: Analyzing trace with hash -1028485830, now seen corresponding path program 25 times [2018-09-14 15:52:30,665 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:30,665 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:30,666 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:30,666 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:30,666 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:30,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:31,117 INFO L134 CoverageAnalysis]: Checked inductivity of 3626 backedges. 1846 proven. 975 refuted. 0 times theorem prover too weak. 805 trivial. 0 not checked. [2018-09-14 15:52:31,118 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:31,118 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:31,126 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:31,126 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:31,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:31,170 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:31,189 INFO L134 CoverageAnalysis]: Checked inductivity of 3626 backedges. 1846 proven. 975 refuted. 0 times theorem prover too weak. 805 trivial. 0 not checked. [2018-09-14 15:52:31,189 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:32,489 INFO L134 CoverageAnalysis]: Checked inductivity of 3626 backedges. 1846 proven. 975 refuted. 0 times theorem prover too weak. 805 trivial. 0 not checked. [2018-09-14 15:52:32,525 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:32,526 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 52 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:32,554 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:32,554 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:32,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:32,641 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:32,678 INFO L134 CoverageAnalysis]: Checked inductivity of 3626 backedges. 1846 proven. 975 refuted. 0 times theorem prover too weak. 805 trivial. 0 not checked. [2018-09-14 15:52:32,678 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:32,879 INFO L134 CoverageAnalysis]: Checked inductivity of 3626 backedges. 1846 proven. 975 refuted. 0 times theorem prover too weak. 805 trivial. 0 not checked. [2018-09-14 15:52:32,881 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:32,881 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28, 28, 28] total 52 [2018-09-14 15:52:32,881 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:32,881 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-09-14 15:52:32,881 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-09-14 15:52:32,882 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:52:32,882 INFO L87 Difference]: Start difference. First operand 159 states and 183 transitions. Second operand 28 states. [2018-09-14 15:52:32,979 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:32,979 INFO L93 Difference]: Finished difference Result 241 states and 290 transitions. [2018-09-14 15:52:32,980 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-09-14 15:52:32,980 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 158 [2018-09-14 15:52:32,980 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:32,981 INFO L225 Difference]: With dead ends: 241 [2018-09-14 15:52:32,981 INFO L226 Difference]: Without dead ends: 162 [2018-09-14 15:52:32,983 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 658 GetRequests, 604 SyntacticMatches, 4 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 98 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:52:32,984 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2018-09-14 15:52:32,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 162. [2018-09-14 15:52:32,988 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-09-14 15:52:32,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 186 transitions. [2018-09-14 15:52:32,989 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 186 transitions. Word has length 158 [2018-09-14 15:52:32,989 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:32,989 INFO L480 AbstractCegarLoop]: Abstraction has 162 states and 186 transitions. [2018-09-14 15:52:32,990 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-09-14 15:52:32,990 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 186 transitions. [2018-09-14 15:52:32,990 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 162 [2018-09-14 15:52:32,991 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:32,991 INFO L376 BasicCegarLoop]: trace histogram [51, 50, 26, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:32,991 INFO L423 AbstractCegarLoop]: === Iteration 29 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:32,991 INFO L82 PathProgramCache]: Analyzing trace with hash 127741151, now seen corresponding path program 26 times [2018-09-14 15:52:32,991 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:32,992 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:32,992 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:32,992 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:32,992 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:33,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:33,672 INFO L134 CoverageAnalysis]: Checked inductivity of 3775 backedges. 1917 proven. 1053 refuted. 0 times theorem prover too weak. 805 trivial. 0 not checked. [2018-09-14 15:52:33,673 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:33,673 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:33,680 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:33,680 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:33,729 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:33,729 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:33,731 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:33,754 INFO L134 CoverageAnalysis]: Checked inductivity of 3775 backedges. 1917 proven. 1053 refuted. 0 times theorem prover too weak. 805 trivial. 0 not checked. [2018-09-14 15:52:33,754 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:34,694 INFO L134 CoverageAnalysis]: Checked inductivity of 3775 backedges. 1917 proven. 1053 refuted. 0 times theorem prover too weak. 805 trivial. 0 not checked. [2018-09-14 15:52:34,713 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:34,714 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 54 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:34,728 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:34,728 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:34,813 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:34,813 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:34,818 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:34,842 INFO L134 CoverageAnalysis]: Checked inductivity of 3775 backedges. 1917 proven. 1053 refuted. 0 times theorem prover too weak. 805 trivial. 0 not checked. [2018-09-14 15:52:34,842 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:35,021 INFO L134 CoverageAnalysis]: Checked inductivity of 3775 backedges. 1917 proven. 1053 refuted. 0 times theorem prover too weak. 805 trivial. 0 not checked. [2018-09-14 15:52:35,022 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:35,022 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 52 [2018-09-14 15:52:35,022 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:35,023 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-09-14 15:52:35,023 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-09-14 15:52:35,024 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:52:35,024 INFO L87 Difference]: Start difference. First operand 162 states and 186 transitions. Second operand 29 states. [2018-09-14 15:52:35,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:35,145 INFO L93 Difference]: Finished difference Result 244 states and 293 transitions. [2018-09-14 15:52:35,146 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-09-14 15:52:35,146 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 161 [2018-09-14 15:52:35,146 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:35,147 INFO L225 Difference]: With dead ends: 244 [2018-09-14 15:52:35,147 INFO L226 Difference]: Without dead ends: 165 [2018-09-14 15:52:35,148 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 671 GetRequests, 613 SyntacticMatches, 8 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 196 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:52:35,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165 states. [2018-09-14 15:52:35,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165 to 165. [2018-09-14 15:52:35,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-09-14 15:52:35,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 189 transitions. [2018-09-14 15:52:35,154 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 189 transitions. Word has length 161 [2018-09-14 15:52:35,154 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:35,155 INFO L480 AbstractCegarLoop]: Abstraction has 165 states and 189 transitions. [2018-09-14 15:52:35,155 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-09-14 15:52:35,155 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 189 transitions. [2018-09-14 15:52:35,155 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 165 [2018-09-14 15:52:35,156 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:35,156 INFO L376 BasicCegarLoop]: trace histogram [52, 51, 27, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:35,156 INFO L423 AbstractCegarLoop]: === Iteration 30 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:35,156 INFO L82 PathProgramCache]: Analyzing trace with hash -351981798, now seen corresponding path program 27 times [2018-09-14 15:52:35,156 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:35,157 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:35,157 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:35,157 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:35,157 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:35,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:35,563 INFO L134 CoverageAnalysis]: Checked inductivity of 3927 backedges. 1988 proven. 1134 refuted. 0 times theorem prover too weak. 805 trivial. 0 not checked. [2018-09-14 15:52:35,563 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:35,563 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:35,575 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:35,576 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:35,642 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 38 check-sat command(s) [2018-09-14 15:52:35,643 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:35,647 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:36,863 INFO L134 CoverageAnalysis]: Checked inductivity of 3927 backedges. 1998 proven. 876 refuted. 0 times theorem prover too weak. 1053 trivial. 0 not checked. [2018-09-14 15:52:36,864 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:38,356 INFO L134 CoverageAnalysis]: Checked inductivity of 3927 backedges. 1998 proven. 876 refuted. 0 times theorem prover too weak. 1053 trivial. 0 not checked. [2018-09-14 15:52:38,383 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:38,383 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 56 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:38,398 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:38,398 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:38,780 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 38 check-sat command(s) [2018-09-14 15:52:38,781 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:38,785 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:38,808 INFO L134 CoverageAnalysis]: Checked inductivity of 3927 backedges. 1998 proven. 876 refuted. 0 times theorem prover too weak. 1053 trivial. 0 not checked. [2018-09-14 15:52:38,809 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:38,881 INFO L134 CoverageAnalysis]: Checked inductivity of 3927 backedges. 1998 proven. 876 refuted. 0 times theorem prover too weak. 1053 trivial. 0 not checked. [2018-09-14 15:52:38,882 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:38,882 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 27, 27, 27, 27] total 80 [2018-09-14 15:52:38,882 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:38,883 INFO L459 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-09-14 15:52:38,883 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-09-14 15:52:38,884 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=3160, Invalid=3160, Unknown=0, NotChecked=0, Total=6320 [2018-09-14 15:52:38,884 INFO L87 Difference]: Start difference. First operand 165 states and 189 transitions. Second operand 55 states. [2018-09-14 15:52:40,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:40,284 INFO L93 Difference]: Finished difference Result 251 states and 303 transitions. [2018-09-14 15:52:40,284 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-09-14 15:52:40,285 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 164 [2018-09-14 15:52:40,285 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:40,286 INFO L225 Difference]: With dead ends: 251 [2018-09-14 15:52:40,286 INFO L226 Difference]: Without dead ends: 172 [2018-09-14 15:52:40,287 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 684 GetRequests, 606 SyntacticMatches, 0 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=3160, Invalid=3160, Unknown=0, NotChecked=0, Total=6320 [2018-09-14 15:52:40,287 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states. [2018-09-14 15:52:40,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 171. [2018-09-14 15:52:40,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 171 states. [2018-09-14 15:52:40,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 196 transitions. [2018-09-14 15:52:40,292 INFO L78 Accepts]: Start accepts. Automaton has 171 states and 196 transitions. Word has length 164 [2018-09-14 15:52:40,293 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:40,293 INFO L480 AbstractCegarLoop]: Abstraction has 171 states and 196 transitions. [2018-09-14 15:52:40,293 INFO L481 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-09-14 15:52:40,293 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states and 196 transitions. [2018-09-14 15:52:40,294 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 171 [2018-09-14 15:52:40,294 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:40,294 INFO L376 BasicCegarLoop]: trace histogram [54, 53, 28, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:40,294 INFO L423 AbstractCegarLoop]: === Iteration 31 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:40,295 INFO L82 PathProgramCache]: Analyzing trace with hash 820030844, now seen corresponding path program 28 times [2018-09-14 15:52:40,295 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:40,295 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:40,295 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:40,296 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:40,296 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:40,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:40,782 INFO L134 CoverageAnalysis]: Checked inductivity of 4240 backedges. 2146 proven. 1218 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:40,783 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:40,783 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:40,791 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:40,791 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:40,834 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:40,835 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:40,837 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:40,856 INFO L134 CoverageAnalysis]: Checked inductivity of 4240 backedges. 2146 proven. 1218 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:40,856 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:41,928 INFO L134 CoverageAnalysis]: Checked inductivity of 4240 backedges. 2146 proven. 1218 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:41,948 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:41,948 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 58 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:41,963 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:41,963 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:42,055 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:42,056 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:42,061 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:42,086 INFO L134 CoverageAnalysis]: Checked inductivity of 4240 backedges. 2146 proven. 1218 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:42,087 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:42,458 INFO L134 CoverageAnalysis]: Checked inductivity of 4240 backedges. 2146 proven. 1218 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:42,459 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:42,459 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31, 31, 31, 31] total 52 [2018-09-14 15:52:42,459 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:42,460 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-09-14 15:52:42,460 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-09-14 15:52:42,460 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:52:42,461 INFO L87 Difference]: Start difference. First operand 171 states and 196 transitions. Second operand 31 states. [2018-09-14 15:52:42,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:42,561 INFO L93 Difference]: Finished difference Result 256 states and 307 transitions. [2018-09-14 15:52:42,562 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-09-14 15:52:42,562 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 170 [2018-09-14 15:52:42,562 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:42,563 INFO L225 Difference]: With dead ends: 256 [2018-09-14 15:52:42,563 INFO L226 Difference]: Without dead ends: 174 [2018-09-14 15:52:42,564 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 709 GetRequests, 643 SyntacticMatches, 16 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 392 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:52:42,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states. [2018-09-14 15:52:42,568 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 174. [2018-09-14 15:52:42,568 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-09-14 15:52:42,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 199 transitions. [2018-09-14 15:52:42,569 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 199 transitions. Word has length 170 [2018-09-14 15:52:42,569 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:42,569 INFO L480 AbstractCegarLoop]: Abstraction has 174 states and 199 transitions. [2018-09-14 15:52:42,569 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-09-14 15:52:42,570 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 199 transitions. [2018-09-14 15:52:42,570 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2018-09-14 15:52:42,571 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:42,571 INFO L376 BasicCegarLoop]: trace histogram [55, 54, 29, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:42,571 INFO L423 AbstractCegarLoop]: === Iteration 32 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:42,571 INFO L82 PathProgramCache]: Analyzing trace with hash -2109211231, now seen corresponding path program 29 times [2018-09-14 15:52:42,571 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:42,572 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:42,572 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:42,572 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:42,572 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:42,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:43,063 INFO L134 CoverageAnalysis]: Checked inductivity of 4401 backedges. 2220 proven. 1305 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:43,063 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:43,064 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:43,073 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:43,073 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:43,157 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 55 check-sat command(s) [2018-09-14 15:52:43,157 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:43,160 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:43,180 INFO L134 CoverageAnalysis]: Checked inductivity of 4401 backedges. 2220 proven. 1305 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:43,180 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:44,003 INFO L134 CoverageAnalysis]: Checked inductivity of 4401 backedges. 2220 proven. 1305 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:44,023 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:44,023 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 60 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:44,038 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:44,038 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:44,616 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 55 check-sat command(s) [2018-09-14 15:52:44,616 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:44,622 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:44,648 INFO L134 CoverageAnalysis]: Checked inductivity of 4401 backedges. 2220 proven. 1305 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:44,648 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:45,035 INFO L134 CoverageAnalysis]: Checked inductivity of 4401 backedges. 2220 proven. 1305 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:45,036 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:45,036 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32, 32, 32, 32] total 52 [2018-09-14 15:52:45,036 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:45,037 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-09-14 15:52:45,037 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-09-14 15:52:45,037 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:52:45,037 INFO L87 Difference]: Start difference. First operand 174 states and 199 transitions. Second operand 32 states. [2018-09-14 15:52:45,224 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:45,224 INFO L93 Difference]: Finished difference Result 259 states and 310 transitions. [2018-09-14 15:52:45,224 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-09-14 15:52:45,225 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 173 [2018-09-14 15:52:45,225 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:45,226 INFO L225 Difference]: With dead ends: 259 [2018-09-14 15:52:45,226 INFO L226 Difference]: Without dead ends: 177 [2018-09-14 15:52:45,227 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 722 GetRequests, 652 SyntacticMatches, 20 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 490 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:52:45,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states. [2018-09-14 15:52:45,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 177. [2018-09-14 15:52:45,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 177 states. [2018-09-14 15:52:45,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177 states to 177 states and 202 transitions. [2018-09-14 15:52:45,233 INFO L78 Accepts]: Start accepts. Automaton has 177 states and 202 transitions. Word has length 173 [2018-09-14 15:52:45,233 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:45,234 INFO L480 AbstractCegarLoop]: Abstraction has 177 states and 202 transitions. [2018-09-14 15:52:45,234 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-09-14 15:52:45,234 INFO L276 IsEmpty]: Start isEmpty. Operand 177 states and 202 transitions. [2018-09-14 15:52:45,235 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2018-09-14 15:52:45,235 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:45,235 INFO L376 BasicCegarLoop]: trace histogram [56, 55, 30, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:45,235 INFO L423 AbstractCegarLoop]: === Iteration 33 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:45,236 INFO L82 PathProgramCache]: Analyzing trace with hash -2014347428, now seen corresponding path program 30 times [2018-09-14 15:52:45,236 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:45,236 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:45,236 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:45,237 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:45,237 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:45,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:45,895 INFO L134 CoverageAnalysis]: Checked inductivity of 4565 backedges. 2294 proven. 1395 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:45,895 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:45,895 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:45,904 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:45,904 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:46,020 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 55 check-sat command(s) [2018-09-14 15:52:46,021 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:46,024 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:46,055 INFO L134 CoverageAnalysis]: Checked inductivity of 4565 backedges. 2294 proven. 1395 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:46,055 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:47,556 INFO L134 CoverageAnalysis]: Checked inductivity of 4565 backedges. 2294 proven. 1395 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:47,576 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:47,576 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 62 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:47,596 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:47,596 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:48,227 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 55 check-sat command(s) [2018-09-14 15:52:48,228 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:48,233 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:48,255 INFO L134 CoverageAnalysis]: Checked inductivity of 4565 backedges. 2294 proven. 1395 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:48,255 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:48,560 INFO L134 CoverageAnalysis]: Checked inductivity of 4565 backedges. 2294 proven. 1395 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:48,561 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:48,562 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33, 33, 33, 33] total 52 [2018-09-14 15:52:48,562 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:48,563 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-09-14 15:52:48,563 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-09-14 15:52:48,564 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:52:48,564 INFO L87 Difference]: Start difference. First operand 177 states and 202 transitions. Second operand 33 states. [2018-09-14 15:52:48,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:48,789 INFO L93 Difference]: Finished difference Result 262 states and 313 transitions. [2018-09-14 15:52:48,790 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-09-14 15:52:48,790 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 176 [2018-09-14 15:52:48,791 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:48,792 INFO L225 Difference]: With dead ends: 262 [2018-09-14 15:52:48,792 INFO L226 Difference]: Without dead ends: 180 [2018-09-14 15:52:48,792 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 735 GetRequests, 661 SyntacticMatches, 24 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 588 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:52:48,793 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180 states. [2018-09-14 15:52:48,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180 to 180. [2018-09-14 15:52:48,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 180 states. [2018-09-14 15:52:48,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 205 transitions. [2018-09-14 15:52:48,798 INFO L78 Accepts]: Start accepts. Automaton has 180 states and 205 transitions. Word has length 176 [2018-09-14 15:52:48,799 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:48,799 INFO L480 AbstractCegarLoop]: Abstraction has 180 states and 205 transitions. [2018-09-14 15:52:48,799 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-09-14 15:52:48,799 INFO L276 IsEmpty]: Start isEmpty. Operand 180 states and 205 transitions. [2018-09-14 15:52:48,800 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2018-09-14 15:52:48,800 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:48,800 INFO L376 BasicCegarLoop]: trace histogram [57, 56, 31, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:48,801 INFO L423 AbstractCegarLoop]: === Iteration 34 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:48,801 INFO L82 PathProgramCache]: Analyzing trace with hash -2015273023, now seen corresponding path program 31 times [2018-09-14 15:52:48,801 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:48,802 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:48,802 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:48,802 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:48,802 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:48,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:49,575 INFO L134 CoverageAnalysis]: Checked inductivity of 4732 backedges. 2368 proven. 1488 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:49,576 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:49,576 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:49,584 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:49,584 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:49,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:49,627 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:49,656 INFO L134 CoverageAnalysis]: Checked inductivity of 4732 backedges. 2368 proven. 1488 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:49,656 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:50,757 INFO L134 CoverageAnalysis]: Checked inductivity of 4732 backedges. 2368 proven. 1488 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:50,778 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:50,778 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 64 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:50,793 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:50,793 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:50,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:50,886 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:50,905 INFO L134 CoverageAnalysis]: Checked inductivity of 4732 backedges. 2368 proven. 1488 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:50,905 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:51,241 INFO L134 CoverageAnalysis]: Checked inductivity of 4732 backedges. 2368 proven. 1488 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:51,242 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:51,242 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34, 34, 34, 34] total 52 [2018-09-14 15:52:51,242 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:51,243 INFO L459 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-09-14 15:52:51,243 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-09-14 15:52:51,243 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:52:51,243 INFO L87 Difference]: Start difference. First operand 180 states and 205 transitions. Second operand 34 states. [2018-09-14 15:52:51,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:51,380 INFO L93 Difference]: Finished difference Result 265 states and 316 transitions. [2018-09-14 15:52:51,380 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-09-14 15:52:51,380 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 179 [2018-09-14 15:52:51,380 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:51,381 INFO L225 Difference]: With dead ends: 265 [2018-09-14 15:52:51,381 INFO L226 Difference]: Without dead ends: 183 [2018-09-14 15:52:51,382 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 748 GetRequests, 670 SyntacticMatches, 28 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 686 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:52:51,382 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 183 states. [2018-09-14 15:52:51,387 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 183 to 183. [2018-09-14 15:52:51,388 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 183 states. [2018-09-14 15:52:51,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 183 states to 183 states and 208 transitions. [2018-09-14 15:52:51,389 INFO L78 Accepts]: Start accepts. Automaton has 183 states and 208 transitions. Word has length 179 [2018-09-14 15:52:51,389 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:51,389 INFO L480 AbstractCegarLoop]: Abstraction has 183 states and 208 transitions. [2018-09-14 15:52:51,389 INFO L481 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-09-14 15:52:51,389 INFO L276 IsEmpty]: Start isEmpty. Operand 183 states and 208 transitions. [2018-09-14 15:52:51,390 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2018-09-14 15:52:51,390 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:51,390 INFO L376 BasicCegarLoop]: trace histogram [58, 57, 32, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:51,391 INFO L423 AbstractCegarLoop]: === Iteration 35 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:51,391 INFO L82 PathProgramCache]: Analyzing trace with hash 475097404, now seen corresponding path program 32 times [2018-09-14 15:52:51,391 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:51,392 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:51,392 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:51,392 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:51,392 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:51,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:52,387 INFO L134 CoverageAnalysis]: Checked inductivity of 4902 backedges. 2442 proven. 1584 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:52,388 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:52,388 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:52,397 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:52,397 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:52,438 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:52,439 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:52,441 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:52,470 INFO L134 CoverageAnalysis]: Checked inductivity of 4902 backedges. 2442 proven. 1584 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:52,470 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:53,709 INFO L134 CoverageAnalysis]: Checked inductivity of 4902 backedges. 2442 proven. 1584 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:53,729 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:53,729 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 66 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:53,744 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:53,744 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:53,830 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:53,830 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:53,835 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:53,866 INFO L134 CoverageAnalysis]: Checked inductivity of 4902 backedges. 2442 proven. 1584 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:53,866 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:54,279 INFO L134 CoverageAnalysis]: Checked inductivity of 4902 backedges. 2442 proven. 1584 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:54,281 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:54,281 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35, 35, 35, 35] total 52 [2018-09-14 15:52:54,281 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:54,281 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-09-14 15:52:54,282 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-09-14 15:52:54,282 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:52:54,282 INFO L87 Difference]: Start difference. First operand 183 states and 208 transitions. Second operand 35 states. [2018-09-14 15:52:54,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:54,409 INFO L93 Difference]: Finished difference Result 268 states and 319 transitions. [2018-09-14 15:52:54,409 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-09-14 15:52:54,409 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 182 [2018-09-14 15:52:54,410 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:54,411 INFO L225 Difference]: With dead ends: 268 [2018-09-14 15:52:54,411 INFO L226 Difference]: Without dead ends: 186 [2018-09-14 15:52:54,412 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 761 GetRequests, 679 SyntacticMatches, 32 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 784 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:52:54,412 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states. [2018-09-14 15:52:54,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 186. [2018-09-14 15:52:54,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-09-14 15:52:54,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 211 transitions. [2018-09-14 15:52:54,418 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 211 transitions. Word has length 182 [2018-09-14 15:52:54,419 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:54,419 INFO L480 AbstractCegarLoop]: Abstraction has 186 states and 211 transitions. [2018-09-14 15:52:54,419 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-09-14 15:52:54,419 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 211 transitions. [2018-09-14 15:52:54,420 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2018-09-14 15:52:54,420 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:54,420 INFO L376 BasicCegarLoop]: trace histogram [59, 58, 33, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:54,420 INFO L423 AbstractCegarLoop]: === Iteration 36 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:54,421 INFO L82 PathProgramCache]: Analyzing trace with hash -164582943, now seen corresponding path program 33 times [2018-09-14 15:52:54,421 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:54,421 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:54,421 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:54,422 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:54,422 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:54,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:55,104 INFO L134 CoverageAnalysis]: Checked inductivity of 5075 backedges. 2516 proven. 1683 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-09-14 15:52:55,104 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:55,104 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:55,112 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:55,112 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:55,175 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 39 check-sat command(s) [2018-09-14 15:52:55,176 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:55,178 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:56,030 INFO L134 CoverageAnalysis]: Checked inductivity of 5075 backedges. 2541 proven. 950 refuted. 0 times theorem prover too weak. 1584 trivial. 0 not checked. [2018-09-14 15:52:56,030 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:57,650 INFO L134 CoverageAnalysis]: Checked inductivity of 5075 backedges. 2541 proven. 950 refuted. 0 times theorem prover too weak. 1584 trivial. 0 not checked. [2018-09-14 15:52:57,669 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:57,669 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 68 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:57,696 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:57,696 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:58,088 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 39 check-sat command(s) [2018-09-14 15:52:58,089 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:58,093 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:58,119 INFO L134 CoverageAnalysis]: Checked inductivity of 5075 backedges. 2541 proven. 950 refuted. 0 times theorem prover too weak. 1584 trivial. 0 not checked. [2018-09-14 15:52:58,119 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:58,339 INFO L134 CoverageAnalysis]: Checked inductivity of 5075 backedges. 2541 proven. 950 refuted. 0 times theorem prover too weak. 1584 trivial. 0 not checked. [2018-09-14 15:52:58,340 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:58,341 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 28, 28, 28, 28] total 86 [2018-09-14 15:52:58,341 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:58,341 INFO L459 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-09-14 15:52:58,342 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-09-14 15:52:58,343 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=3655, Invalid=3655, Unknown=0, NotChecked=0, Total=7310 [2018-09-14 15:52:58,343 INFO L87 Difference]: Start difference. First operand 186 states and 211 transitions. Second operand 62 states. [2018-09-14 15:52:58,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:58,854 INFO L93 Difference]: Finished difference Result 275 states and 329 transitions. [2018-09-14 15:52:58,854 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-09-14 15:52:58,854 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 185 [2018-09-14 15:52:58,855 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:58,856 INFO L225 Difference]: With dead ends: 275 [2018-09-14 15:52:58,856 INFO L226 Difference]: Without dead ends: 193 [2018-09-14 15:52:58,856 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 774 GetRequests, 686 SyntacticMatches, 4 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 98 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=3655, Invalid=3655, Unknown=0, NotChecked=0, Total=7310 [2018-09-14 15:52:58,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 193 states. [2018-09-14 15:52:58,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 193 to 192. [2018-09-14 15:52:58,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 192 states. [2018-09-14 15:52:58,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192 states to 192 states and 218 transitions. [2018-09-14 15:52:58,862 INFO L78 Accepts]: Start accepts. Automaton has 192 states and 218 transitions. Word has length 185 [2018-09-14 15:52:58,863 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:58,863 INFO L480 AbstractCegarLoop]: Abstraction has 192 states and 218 transitions. [2018-09-14 15:52:58,863 INFO L481 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-09-14 15:52:58,863 INFO L276 IsEmpty]: Start isEmpty. Operand 192 states and 218 transitions. [2018-09-14 15:52:58,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 192 [2018-09-14 15:52:58,864 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:58,864 INFO L376 BasicCegarLoop]: trace histogram [61, 60, 34, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:58,865 INFO L423 AbstractCegarLoop]: === Iteration 37 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:58,865 INFO L82 PathProgramCache]: Analyzing trace with hash -1265979329, now seen corresponding path program 34 times [2018-09-14 15:52:58,865 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:58,866 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:58,866 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:58,866 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:58,866 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:58,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:00,219 INFO L134 CoverageAnalysis]: Checked inductivity of 5430 backedges. 2695 proven. 1785 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:00,219 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:00,219 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:00,226 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:53:00,226 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:53:00,279 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:53:00,279 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:00,282 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:00,312 INFO L134 CoverageAnalysis]: Checked inductivity of 5430 backedges. 2695 proven. 1785 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:00,312 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:01,351 INFO L134 CoverageAnalysis]: Checked inductivity of 5430 backedges. 2695 proven. 1785 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:01,372 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:01,372 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 70 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:01,387 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:53:01,387 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:53:01,484 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:53:01,484 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:01,489 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:01,510 INFO L134 CoverageAnalysis]: Checked inductivity of 5430 backedges. 2695 proven. 1785 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:01,510 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:01,921 INFO L134 CoverageAnalysis]: Checked inductivity of 5430 backedges. 2695 proven. 1785 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:01,922 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:01,922 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37, 37, 37, 37] total 52 [2018-09-14 15:53:01,922 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:01,923 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-09-14 15:53:01,923 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-09-14 15:53:01,923 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:01,923 INFO L87 Difference]: Start difference. First operand 192 states and 218 transitions. Second operand 37 states. [2018-09-14 15:53:02,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:02,087 INFO L93 Difference]: Finished difference Result 280 states and 333 transitions. [2018-09-14 15:53:02,089 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-09-14 15:53:02,089 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 191 [2018-09-14 15:53:02,089 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:02,090 INFO L225 Difference]: With dead ends: 280 [2018-09-14 15:53:02,090 INFO L226 Difference]: Without dead ends: 195 [2018-09-14 15:53:02,091 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 799 GetRequests, 709 SyntacticMatches, 40 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 980 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:02,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states. [2018-09-14 15:53:02,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 195. [2018-09-14 15:53:02,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 195 states. [2018-09-14 15:53:02,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 221 transitions. [2018-09-14 15:53:02,095 INFO L78 Accepts]: Start accepts. Automaton has 195 states and 221 transitions. Word has length 191 [2018-09-14 15:53:02,095 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:02,095 INFO L480 AbstractCegarLoop]: Abstraction has 195 states and 221 transitions. [2018-09-14 15:53:02,096 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-09-14 15:53:02,096 INFO L276 IsEmpty]: Start isEmpty. Operand 195 states and 221 transitions. [2018-09-14 15:53:02,097 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 195 [2018-09-14 15:53:02,097 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:02,097 INFO L376 BasicCegarLoop]: trace histogram [62, 61, 35, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:02,097 INFO L423 AbstractCegarLoop]: === Iteration 38 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:02,097 INFO L82 PathProgramCache]: Analyzing trace with hash 1428773178, now seen corresponding path program 35 times [2018-09-14 15:53:02,097 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:02,098 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:02,098 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:02,098 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:02,098 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:02,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:02,750 INFO L134 CoverageAnalysis]: Checked inductivity of 5612 backedges. 2772 proven. 1890 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:02,750 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:02,751 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:02,757 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:53:02,758 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:02,862 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 62 check-sat command(s) [2018-09-14 15:53:02,862 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:02,866 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:02,905 INFO L134 CoverageAnalysis]: Checked inductivity of 5612 backedges. 2772 proven. 1890 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:02,905 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:03,766 INFO L134 CoverageAnalysis]: Checked inductivity of 5612 backedges. 2772 proven. 1890 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:03,786 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:03,787 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 72 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:03,802 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:53:03,802 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:04,505 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 62 check-sat command(s) [2018-09-14 15:53:04,505 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:04,510 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:04,540 INFO L134 CoverageAnalysis]: Checked inductivity of 5612 backedges. 2772 proven. 1890 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:04,541 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:04,964 INFO L134 CoverageAnalysis]: Checked inductivity of 5612 backedges. 2772 proven. 1890 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:04,965 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:04,965 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38, 38, 38, 38] total 52 [2018-09-14 15:53:04,965 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:04,966 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-09-14 15:53:04,966 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-09-14 15:53:04,966 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:04,967 INFO L87 Difference]: Start difference. First operand 195 states and 221 transitions. Second operand 38 states. [2018-09-14 15:53:05,118 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:05,118 INFO L93 Difference]: Finished difference Result 283 states and 336 transitions. [2018-09-14 15:53:05,119 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-09-14 15:53:05,119 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 194 [2018-09-14 15:53:05,120 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:05,121 INFO L225 Difference]: With dead ends: 283 [2018-09-14 15:53:05,121 INFO L226 Difference]: Without dead ends: 198 [2018-09-14 15:53:05,122 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 812 GetRequests, 718 SyntacticMatches, 44 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1078 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:05,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states. [2018-09-14 15:53:05,127 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 198. [2018-09-14 15:53:05,127 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 198 states. [2018-09-14 15:53:05,128 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198 states to 198 states and 224 transitions. [2018-09-14 15:53:05,128 INFO L78 Accepts]: Start accepts. Automaton has 198 states and 224 transitions. Word has length 194 [2018-09-14 15:53:05,129 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:05,129 INFO L480 AbstractCegarLoop]: Abstraction has 198 states and 224 transitions. [2018-09-14 15:53:05,129 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-09-14 15:53:05,129 INFO L276 IsEmpty]: Start isEmpty. Operand 198 states and 224 transitions. [2018-09-14 15:53:05,130 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 198 [2018-09-14 15:53:05,130 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:05,130 INFO L376 BasicCegarLoop]: trace histogram [63, 62, 36, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:05,130 INFO L423 AbstractCegarLoop]: === Iteration 39 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:05,131 INFO L82 PathProgramCache]: Analyzing trace with hash -727987617, now seen corresponding path program 36 times [2018-09-14 15:53:05,131 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:05,131 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:05,132 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:05,132 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:05,132 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:05,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:06,067 INFO L134 CoverageAnalysis]: Checked inductivity of 5797 backedges. 2849 proven. 1998 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:06,067 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:06,067 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:06,074 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:53:06,074 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:53:06,175 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 61 check-sat command(s) [2018-09-14 15:53:06,176 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:06,179 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:06,213 INFO L134 CoverageAnalysis]: Checked inductivity of 5797 backedges. 2849 proven. 1998 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:06,214 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:07,131 INFO L134 CoverageAnalysis]: Checked inductivity of 5797 backedges. 2849 proven. 1998 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:07,151 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:07,151 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 74 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:07,165 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:53:07,165 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:53:07,915 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 61 check-sat command(s) [2018-09-14 15:53:07,915 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:07,920 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:07,968 INFO L134 CoverageAnalysis]: Checked inductivity of 5797 backedges. 2849 proven. 1998 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:07,968 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:08,424 INFO L134 CoverageAnalysis]: Checked inductivity of 5797 backedges. 2849 proven. 1998 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:08,426 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:08,426 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39, 39, 39, 39] total 52 [2018-09-14 15:53:08,426 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:08,427 INFO L459 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-09-14 15:53:08,427 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-09-14 15:53:08,427 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:08,428 INFO L87 Difference]: Start difference. First operand 198 states and 224 transitions. Second operand 39 states. [2018-09-14 15:53:08,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:08,594 INFO L93 Difference]: Finished difference Result 286 states and 339 transitions. [2018-09-14 15:53:08,594 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-09-14 15:53:08,594 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 197 [2018-09-14 15:53:08,595 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:08,596 INFO L225 Difference]: With dead ends: 286 [2018-09-14 15:53:08,596 INFO L226 Difference]: Without dead ends: 201 [2018-09-14 15:53:08,597 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 825 GetRequests, 727 SyntacticMatches, 48 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1176 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:08,597 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states. [2018-09-14 15:53:08,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 201. [2018-09-14 15:53:08,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 201 states. [2018-09-14 15:53:08,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 227 transitions. [2018-09-14 15:53:08,602 INFO L78 Accepts]: Start accepts. Automaton has 201 states and 227 transitions. Word has length 197 [2018-09-14 15:53:08,603 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:08,603 INFO L480 AbstractCegarLoop]: Abstraction has 201 states and 227 transitions. [2018-09-14 15:53:08,603 INFO L481 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-09-14 15:53:08,603 INFO L276 IsEmpty]: Start isEmpty. Operand 201 states and 227 transitions. [2018-09-14 15:53:08,603 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 201 [2018-09-14 15:53:08,604 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:08,604 INFO L376 BasicCegarLoop]: trace histogram [64, 63, 37, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:08,604 INFO L423 AbstractCegarLoop]: === Iteration 40 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:08,604 INFO L82 PathProgramCache]: Analyzing trace with hash -78083302, now seen corresponding path program 37 times [2018-09-14 15:53:08,604 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:08,605 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:08,605 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:08,605 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:08,605 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:08,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:11,250 INFO L134 CoverageAnalysis]: Checked inductivity of 5985 backedges. 2926 proven. 2109 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:11,250 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:11,250 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:11,259 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:53:11,259 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:53:11,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:11,308 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:11,333 INFO L134 CoverageAnalysis]: Checked inductivity of 5985 backedges. 2926 proven. 2109 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:11,334 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:12,254 INFO L134 CoverageAnalysis]: Checked inductivity of 5985 backedges. 2926 proven. 2109 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:12,274 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:12,275 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 76 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:12,289 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:53:12,289 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:53:12,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:12,389 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:12,411 INFO L134 CoverageAnalysis]: Checked inductivity of 5985 backedges. 2926 proven. 2109 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:12,411 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:13,107 INFO L134 CoverageAnalysis]: Checked inductivity of 5985 backedges. 2926 proven. 2109 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:13,108 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:13,109 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40, 40, 40, 40] total 52 [2018-09-14 15:53:13,109 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:13,109 INFO L459 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-09-14 15:53:13,109 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-09-14 15:53:13,110 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:13,110 INFO L87 Difference]: Start difference. First operand 201 states and 227 transitions. Second operand 40 states. [2018-09-14 15:53:13,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:13,222 INFO L93 Difference]: Finished difference Result 289 states and 342 transitions. [2018-09-14 15:53:13,222 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-09-14 15:53:13,223 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 200 [2018-09-14 15:53:13,223 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:13,224 INFO L225 Difference]: With dead ends: 289 [2018-09-14 15:53:13,224 INFO L226 Difference]: Without dead ends: 204 [2018-09-14 15:53:13,224 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 838 GetRequests, 736 SyntacticMatches, 52 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1274 ImplicationChecksByTransitivity, 4.1s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:13,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 204 states. [2018-09-14 15:53:13,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 204 to 204. [2018-09-14 15:53:13,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 204 states. [2018-09-14 15:53:13,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 230 transitions. [2018-09-14 15:53:13,230 INFO L78 Accepts]: Start accepts. Automaton has 204 states and 230 transitions. Word has length 200 [2018-09-14 15:53:13,230 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:13,231 INFO L480 AbstractCegarLoop]: Abstraction has 204 states and 230 transitions. [2018-09-14 15:53:13,231 INFO L481 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-09-14 15:53:13,231 INFO L276 IsEmpty]: Start isEmpty. Operand 204 states and 230 transitions. [2018-09-14 15:53:13,232 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 204 [2018-09-14 15:53:13,232 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:13,232 INFO L376 BasicCegarLoop]: trace histogram [65, 64, 38, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:13,232 INFO L423 AbstractCegarLoop]: === Iteration 41 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:13,233 INFO L82 PathProgramCache]: Analyzing trace with hash -491205505, now seen corresponding path program 38 times [2018-09-14 15:53:13,233 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:13,233 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:13,233 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:53:13,233 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:13,234 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:13,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:14,795 INFO L134 CoverageAnalysis]: Checked inductivity of 6176 backedges. 3003 proven. 2223 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:14,795 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:14,795 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:14,803 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:53:14,803 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:14,852 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:53:14,852 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:14,854 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:14,880 INFO L134 CoverageAnalysis]: Checked inductivity of 6176 backedges. 3003 proven. 2223 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:14,880 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:15,796 INFO L134 CoverageAnalysis]: Checked inductivity of 6176 backedges. 3003 proven. 2223 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:15,816 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:15,816 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 78 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:15,830 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:53:15,830 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:15,935 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:53:15,935 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:15,942 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:15,971 INFO L134 CoverageAnalysis]: Checked inductivity of 6176 backedges. 3003 proven. 2223 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:15,971 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:16,496 INFO L134 CoverageAnalysis]: Checked inductivity of 6176 backedges. 3003 proven. 2223 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:16,497 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:16,498 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41, 41, 41, 41] total 52 [2018-09-14 15:53:16,498 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:16,498 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-09-14 15:53:16,499 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-09-14 15:53:16,499 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:16,499 INFO L87 Difference]: Start difference. First operand 204 states and 230 transitions. Second operand 41 states. [2018-09-14 15:53:16,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:16,659 INFO L93 Difference]: Finished difference Result 292 states and 345 transitions. [2018-09-14 15:53:16,666 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-09-14 15:53:16,667 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 203 [2018-09-14 15:53:16,667 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:16,668 INFO L225 Difference]: With dead ends: 292 [2018-09-14 15:53:16,668 INFO L226 Difference]: Without dead ends: 207 [2018-09-14 15:53:16,669 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 851 GetRequests, 745 SyntacticMatches, 56 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1372 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:16,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 207 states. [2018-09-14 15:53:16,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 207 to 207. [2018-09-14 15:53:16,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2018-09-14 15:53:16,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 233 transitions. [2018-09-14 15:53:16,674 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 233 transitions. Word has length 203 [2018-09-14 15:53:16,674 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:16,674 INFO L480 AbstractCegarLoop]: Abstraction has 207 states and 233 transitions. [2018-09-14 15:53:16,674 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-09-14 15:53:16,674 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 233 transitions. [2018-09-14 15:53:16,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 207 [2018-09-14 15:53:16,676 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:16,676 INFO L376 BasicCegarLoop]: trace histogram [66, 65, 39, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:16,676 INFO L423 AbstractCegarLoop]: === Iteration 42 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:16,676 INFO L82 PathProgramCache]: Analyzing trace with hash 1561515258, now seen corresponding path program 39 times [2018-09-14 15:53:16,676 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:16,677 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:16,677 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:16,677 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:16,677 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:16,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:17,949 INFO L134 CoverageAnalysis]: Checked inductivity of 6370 backedges. 3080 proven. 2340 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-09-14 15:53:17,950 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:17,950 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:17,957 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:53:17,957 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:53:18,023 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 41 check-sat command(s) [2018-09-14 15:53:18,023 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:18,026 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:19,125 INFO L134 CoverageAnalysis]: Checked inductivity of 6370 backedges. 3120 proven. 1027 refuted. 0 times theorem prover too weak. 2223 trivial. 0 not checked. [2018-09-14 15:53:19,125 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:20,553 INFO L134 CoverageAnalysis]: Checked inductivity of 6370 backedges. 3120 proven. 1027 refuted. 0 times theorem prover too weak. 2223 trivial. 0 not checked. [2018-09-14 15:53:20,573 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:20,573 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 80 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:20,588 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:53:20,588 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:53:21,020 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 41 check-sat command(s) [2018-09-14 15:53:21,020 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:21,025 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:21,049 INFO L134 CoverageAnalysis]: Checked inductivity of 6370 backedges. 3120 proven. 1027 refuted. 0 times theorem prover too weak. 2223 trivial. 0 not checked. [2018-09-14 15:53:21,049 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:21,316 INFO L134 CoverageAnalysis]: Checked inductivity of 6370 backedges. 3120 proven. 1027 refuted. 0 times theorem prover too weak. 2223 trivial. 0 not checked. [2018-09-14 15:53:21,317 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:21,317 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 29, 29, 29, 29] total 92 [2018-09-14 15:53:21,317 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:21,318 INFO L459 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-09-14 15:53:21,318 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-09-14 15:53:21,319 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=4186, Invalid=4186, Unknown=0, NotChecked=0, Total=8372 [2018-09-14 15:53:21,319 INFO L87 Difference]: Start difference. First operand 207 states and 233 transitions. Second operand 69 states. [2018-09-14 15:53:21,940 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:21,941 INFO L93 Difference]: Finished difference Result 299 states and 355 transitions. [2018-09-14 15:53:21,941 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-09-14 15:53:21,941 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 206 [2018-09-14 15:53:21,941 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:21,942 INFO L225 Difference]: With dead ends: 299 [2018-09-14 15:53:21,942 INFO L226 Difference]: Without dead ends: 214 [2018-09-14 15:53:21,943 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 864 GetRequests, 766 SyntacticMatches, 8 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 196 ImplicationChecksByTransitivity, 3.9s TimeCoverageRelationStatistics Valid=4186, Invalid=4186, Unknown=0, NotChecked=0, Total=8372 [2018-09-14 15:53:21,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 214 states. [2018-09-14 15:53:21,948 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 214 to 213. [2018-09-14 15:53:21,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 213 states. [2018-09-14 15:53:21,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 213 states to 213 states and 240 transitions. [2018-09-14 15:53:21,949 INFO L78 Accepts]: Start accepts. Automaton has 213 states and 240 transitions. Word has length 206 [2018-09-14 15:53:21,949 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:21,949 INFO L480 AbstractCegarLoop]: Abstraction has 213 states and 240 transitions. [2018-09-14 15:53:21,949 INFO L481 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-09-14 15:53:21,950 INFO L276 IsEmpty]: Start isEmpty. Operand 213 states and 240 transitions. [2018-09-14 15:53:21,951 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 213 [2018-09-14 15:53:21,951 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:21,951 INFO L376 BasicCegarLoop]: trace histogram [68, 67, 40, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:21,951 INFO L423 AbstractCegarLoop]: === Iteration 43 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:21,951 INFO L82 PathProgramCache]: Analyzing trace with hash 1803489756, now seen corresponding path program 40 times [2018-09-14 15:53:21,951 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:21,952 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:21,952 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:21,952 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:21,952 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:21,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:23,064 INFO L134 CoverageAnalysis]: Checked inductivity of 6767 backedges. 3280 proven. 2460 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:23,065 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:23,065 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:23,072 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:53:23,072 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:53:23,119 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:53:23,120 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:23,122 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:23,150 INFO L134 CoverageAnalysis]: Checked inductivity of 6767 backedges. 3280 proven. 2460 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:23,150 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:24,106 INFO L134 CoverageAnalysis]: Checked inductivity of 6767 backedges. 3280 proven. 2460 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:24,125 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:24,126 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 82 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 82 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:24,140 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:53:24,141 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:53:24,246 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:53:24,246 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:24,252 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:24,283 INFO L134 CoverageAnalysis]: Checked inductivity of 6767 backedges. 3280 proven. 2460 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:24,283 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:24,892 INFO L134 CoverageAnalysis]: Checked inductivity of 6767 backedges. 3280 proven. 2460 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:24,893 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:24,893 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43, 43, 43, 43] total 52 [2018-09-14 15:53:24,893 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:24,894 INFO L459 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-09-14 15:53:24,894 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-09-14 15:53:24,894 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:24,894 INFO L87 Difference]: Start difference. First operand 213 states and 240 transitions. Second operand 43 states. [2018-09-14 15:53:25,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:25,046 INFO L93 Difference]: Finished difference Result 304 states and 359 transitions. [2018-09-14 15:53:25,048 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-09-14 15:53:25,049 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 212 [2018-09-14 15:53:25,049 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:25,050 INFO L225 Difference]: With dead ends: 304 [2018-09-14 15:53:25,051 INFO L226 Difference]: Without dead ends: 216 [2018-09-14 15:53:25,052 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 889 GetRequests, 775 SyntacticMatches, 64 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1568 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:25,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216 states. [2018-09-14 15:53:25,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216 to 216. [2018-09-14 15:53:25,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 216 states. [2018-09-14 15:53:25,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 216 states to 216 states and 243 transitions. [2018-09-14 15:53:25,058 INFO L78 Accepts]: Start accepts. Automaton has 216 states and 243 transitions. Word has length 212 [2018-09-14 15:53:25,059 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:25,059 INFO L480 AbstractCegarLoop]: Abstraction has 216 states and 243 transitions. [2018-09-14 15:53:25,059 INFO L481 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-09-14 15:53:25,059 INFO L276 IsEmpty]: Start isEmpty. Operand 216 states and 243 transitions. [2018-09-14 15:53:25,060 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 216 [2018-09-14 15:53:25,060 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:25,060 INFO L376 BasicCegarLoop]: trace histogram [69, 68, 41, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:25,060 INFO L423 AbstractCegarLoop]: === Iteration 44 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:25,061 INFO L82 PathProgramCache]: Analyzing trace with hash -1590205503, now seen corresponding path program 41 times [2018-09-14 15:53:25,061 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:25,061 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:25,062 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:25,062 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:25,062 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:25,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:25,834 INFO L134 CoverageAnalysis]: Checked inductivity of 6970 backedges. 3360 proven. 2583 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:25,834 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:25,834 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 83 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 83 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:25,842 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:53:25,842 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:25,960 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 69 check-sat command(s) [2018-09-14 15:53:25,961 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:25,964 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:25,993 INFO L134 CoverageAnalysis]: Checked inductivity of 6970 backedges. 3360 proven. 2583 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:25,993 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:26,894 INFO L134 CoverageAnalysis]: Checked inductivity of 6970 backedges. 3360 proven. 2583 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:26,915 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:26,915 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 84 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 84 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:26,932 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:53:26,932 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:27,758 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 69 check-sat command(s) [2018-09-14 15:53:27,759 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:27,764 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:27,796 INFO L134 CoverageAnalysis]: Checked inductivity of 6970 backedges. 3360 proven. 2583 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:27,796 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:28,606 INFO L134 CoverageAnalysis]: Checked inductivity of 6970 backedges. 3360 proven. 2583 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:28,607 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:28,607 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44, 44, 44, 44] total 52 [2018-09-14 15:53:28,607 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:28,608 INFO L459 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-09-14 15:53:28,608 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-09-14 15:53:28,608 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:28,608 INFO L87 Difference]: Start difference. First operand 216 states and 243 transitions. Second operand 44 states. [2018-09-14 15:53:28,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:28,732 INFO L93 Difference]: Finished difference Result 307 states and 362 transitions. [2018-09-14 15:53:28,732 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-09-14 15:53:28,732 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 215 [2018-09-14 15:53:28,733 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:28,734 INFO L225 Difference]: With dead ends: 307 [2018-09-14 15:53:28,734 INFO L226 Difference]: Without dead ends: 219 [2018-09-14 15:53:28,735 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 902 GetRequests, 784 SyntacticMatches, 68 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1666 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:28,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219 states. [2018-09-14 15:53:28,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219 to 219. [2018-09-14 15:53:28,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 219 states. [2018-09-14 15:53:28,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 219 states to 219 states and 246 transitions. [2018-09-14 15:53:28,742 INFO L78 Accepts]: Start accepts. Automaton has 219 states and 246 transitions. Word has length 215 [2018-09-14 15:53:28,742 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:28,742 INFO L480 AbstractCegarLoop]: Abstraction has 219 states and 246 transitions. [2018-09-14 15:53:28,742 INFO L481 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-09-14 15:53:28,742 INFO L276 IsEmpty]: Start isEmpty. Operand 219 states and 246 transitions. [2018-09-14 15:53:28,743 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 219 [2018-09-14 15:53:28,743 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:28,744 INFO L376 BasicCegarLoop]: trace histogram [70, 69, 42, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:28,744 INFO L423 AbstractCegarLoop]: === Iteration 45 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:28,744 INFO L82 PathProgramCache]: Analyzing trace with hash 364481468, now seen corresponding path program 42 times [2018-09-14 15:53:28,744 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:28,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:28,745 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:28,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:28,745 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:28,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:29,530 INFO L134 CoverageAnalysis]: Checked inductivity of 7176 backedges. 3440 proven. 2709 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:29,530 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:29,530 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 85 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 85 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:29,541 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:53:29,541 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:53:29,654 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 68 check-sat command(s) [2018-09-14 15:53:29,654 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:29,657 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:29,699 INFO L134 CoverageAnalysis]: Checked inductivity of 7176 backedges. 3440 proven. 2709 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:29,700 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:30,663 INFO L134 CoverageAnalysis]: Checked inductivity of 7176 backedges. 3440 proven. 2709 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:30,683 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:30,683 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 86 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 86 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:30,699 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:53:30,699 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:53:31,613 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 68 check-sat command(s) [2018-09-14 15:53:31,614 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:31,619 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:31,648 INFO L134 CoverageAnalysis]: Checked inductivity of 7176 backedges. 3440 proven. 2709 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:31,649 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:32,329 INFO L134 CoverageAnalysis]: Checked inductivity of 7176 backedges. 3440 proven. 2709 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:32,330 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:32,330 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45, 45, 45, 45] total 52 [2018-09-14 15:53:32,330 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:32,331 INFO L459 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-09-14 15:53:32,331 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-09-14 15:53:32,331 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:32,332 INFO L87 Difference]: Start difference. First operand 219 states and 246 transitions. Second operand 45 states. [2018-09-14 15:53:32,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:32,463 INFO L93 Difference]: Finished difference Result 310 states and 365 transitions. [2018-09-14 15:53:32,463 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-09-14 15:53:32,463 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 218 [2018-09-14 15:53:32,463 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:32,464 INFO L225 Difference]: With dead ends: 310 [2018-09-14 15:53:32,465 INFO L226 Difference]: Without dead ends: 222 [2018-09-14 15:53:32,465 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 915 GetRequests, 793 SyntacticMatches, 72 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1764 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:32,465 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 222 states. [2018-09-14 15:53:32,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 222 to 222. [2018-09-14 15:53:32,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 222 states. [2018-09-14 15:53:32,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 222 states to 222 states and 249 transitions. [2018-09-14 15:53:32,471 INFO L78 Accepts]: Start accepts. Automaton has 222 states and 249 transitions. Word has length 218 [2018-09-14 15:53:32,471 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:32,471 INFO L480 AbstractCegarLoop]: Abstraction has 222 states and 249 transitions. [2018-09-14 15:53:32,471 INFO L481 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-09-14 15:53:32,471 INFO L276 IsEmpty]: Start isEmpty. Operand 222 states and 249 transitions. [2018-09-14 15:53:32,472 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 222 [2018-09-14 15:53:32,472 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:32,473 INFO L376 BasicCegarLoop]: trace histogram [71, 70, 43, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:32,473 INFO L423 AbstractCegarLoop]: === Iteration 46 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:32,473 INFO L82 PathProgramCache]: Analyzing trace with hash 1277435361, now seen corresponding path program 43 times [2018-09-14 15:53:32,473 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:32,474 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:32,474 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:32,474 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:32,474 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:32,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:33,664 INFO L134 CoverageAnalysis]: Checked inductivity of 7385 backedges. 3520 proven. 2838 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:33,664 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:33,664 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 87 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 87 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:33,674 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:53:33,674 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:53:33,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:33,725 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:33,756 INFO L134 CoverageAnalysis]: Checked inductivity of 7385 backedges. 3520 proven. 2838 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:33,756 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:34,662 INFO L134 CoverageAnalysis]: Checked inductivity of 7385 backedges. 3520 proven. 2838 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:34,683 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:34,683 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 88 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 88 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:34,698 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:53:34,698 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:53:34,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:34,809 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:34,840 INFO L134 CoverageAnalysis]: Checked inductivity of 7385 backedges. 3520 proven. 2838 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:34,840 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:35,598 INFO L134 CoverageAnalysis]: Checked inductivity of 7385 backedges. 3520 proven. 2838 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:35,599 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:35,599 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46, 46, 46, 46] total 52 [2018-09-14 15:53:35,600 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:35,600 INFO L459 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-09-14 15:53:35,600 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-09-14 15:53:35,600 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:35,601 INFO L87 Difference]: Start difference. First operand 222 states and 249 transitions. Second operand 46 states. [2018-09-14 15:53:35,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:35,736 INFO L93 Difference]: Finished difference Result 313 states and 368 transitions. [2018-09-14 15:53:35,736 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-09-14 15:53:35,736 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 221 [2018-09-14 15:53:35,737 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:35,738 INFO L225 Difference]: With dead ends: 313 [2018-09-14 15:53:35,739 INFO L226 Difference]: Without dead ends: 225 [2018-09-14 15:53:35,739 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 928 GetRequests, 802 SyntacticMatches, 76 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1862 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:35,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225 states. [2018-09-14 15:53:35,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225 to 225. [2018-09-14 15:53:35,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 225 states. [2018-09-14 15:53:35,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225 states to 225 states and 252 transitions. [2018-09-14 15:53:35,745 INFO L78 Accepts]: Start accepts. Automaton has 225 states and 252 transitions. Word has length 221 [2018-09-14 15:53:35,746 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:35,746 INFO L480 AbstractCegarLoop]: Abstraction has 225 states and 252 transitions. [2018-09-14 15:53:35,746 INFO L481 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-09-14 15:53:35,746 INFO L276 IsEmpty]: Start isEmpty. Operand 225 states and 252 transitions. [2018-09-14 15:53:35,747 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 225 [2018-09-14 15:53:35,747 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:35,747 INFO L376 BasicCegarLoop]: trace histogram [72, 71, 44, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:35,748 INFO L423 AbstractCegarLoop]: === Iteration 47 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:35,748 INFO L82 PathProgramCache]: Analyzing trace with hash -941023844, now seen corresponding path program 44 times [2018-09-14 15:53:35,748 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:35,749 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:35,749 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:53:35,749 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:35,749 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:35,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:36,726 INFO L134 CoverageAnalysis]: Checked inductivity of 7597 backedges. 3600 proven. 2970 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:36,726 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:36,727 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 89 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 89 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:36,734 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:53:36,734 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:36,788 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:53:36,788 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:36,791 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:36,823 INFO L134 CoverageAnalysis]: Checked inductivity of 7597 backedges. 3600 proven. 2970 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:36,823 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:37,765 INFO L134 CoverageAnalysis]: Checked inductivity of 7597 backedges. 3600 proven. 2970 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:37,786 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:37,786 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 90 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 90 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:37,802 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:53:37,802 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:37,916 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:53:37,916 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:37,922 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:37,950 INFO L134 CoverageAnalysis]: Checked inductivity of 7597 backedges. 3600 proven. 2970 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:37,951 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:38,876 INFO L134 CoverageAnalysis]: Checked inductivity of 7597 backedges. 3600 proven. 2970 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:38,877 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:38,878 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47, 47, 47, 47] total 52 [2018-09-14 15:53:38,878 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:38,878 INFO L459 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-09-14 15:53:38,878 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-09-14 15:53:38,879 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:38,879 INFO L87 Difference]: Start difference. First operand 225 states and 252 transitions. Second operand 47 states. [2018-09-14 15:53:39,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:39,023 INFO L93 Difference]: Finished difference Result 316 states and 371 transitions. [2018-09-14 15:53:39,024 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-09-14 15:53:39,024 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 224 [2018-09-14 15:53:39,025 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:39,026 INFO L225 Difference]: With dead ends: 316 [2018-09-14 15:53:39,026 INFO L226 Difference]: Without dead ends: 228 [2018-09-14 15:53:39,027 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 941 GetRequests, 811 SyntacticMatches, 80 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1960 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:39,027 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228 states. [2018-09-14 15:53:39,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228 to 228. [2018-09-14 15:53:39,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2018-09-14 15:53:39,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 255 transitions. [2018-09-14 15:53:39,033 INFO L78 Accepts]: Start accepts. Automaton has 228 states and 255 transitions. Word has length 224 [2018-09-14 15:53:39,033 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:39,033 INFO L480 AbstractCegarLoop]: Abstraction has 228 states and 255 transitions. [2018-09-14 15:53:39,034 INFO L481 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-09-14 15:53:39,034 INFO L276 IsEmpty]: Start isEmpty. Operand 228 states and 255 transitions. [2018-09-14 15:53:39,035 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 228 [2018-09-14 15:53:39,035 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:39,035 INFO L376 BasicCegarLoop]: trace histogram [73, 72, 45, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:39,035 INFO L423 AbstractCegarLoop]: === Iteration 48 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:39,036 INFO L82 PathProgramCache]: Analyzing trace with hash -102449151, now seen corresponding path program 45 times [2018-09-14 15:53:39,036 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:39,036 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:39,036 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:39,037 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:39,037 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:39,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:40,604 INFO L134 CoverageAnalysis]: Checked inductivity of 7812 backedges. 3680 proven. 3105 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-09-14 15:53:40,605 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:40,605 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 91 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 91 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:40,614 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:53:40,615 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:53:40,683 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 42 check-sat command(s) [2018-09-14 15:53:40,683 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:40,687 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:41,963 INFO L134 CoverageAnalysis]: Checked inductivity of 7812 backedges. 3735 proven. 1107 refuted. 0 times theorem prover too weak. 2970 trivial. 0 not checked. [2018-09-14 15:53:41,963 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:43,833 INFO L134 CoverageAnalysis]: Checked inductivity of 7812 backedges. 3735 proven. 1107 refuted. 0 times theorem prover too weak. 2970 trivial. 0 not checked. [2018-09-14 15:53:43,853 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:43,853 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 92 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 92 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:43,867 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:53:43,867 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:53:44,325 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 42 check-sat command(s) [2018-09-14 15:53:44,325 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:44,331 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:44,360 INFO L134 CoverageAnalysis]: Checked inductivity of 7812 backedges. 3735 proven. 1107 refuted. 0 times theorem prover too weak. 2970 trivial. 0 not checked. [2018-09-14 15:53:44,361 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:44,693 INFO L134 CoverageAnalysis]: Checked inductivity of 7812 backedges. 3735 proven. 1107 refuted. 0 times theorem prover too weak. 2970 trivial. 0 not checked. [2018-09-14 15:53:44,694 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:44,694 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 30, 30, 30, 30] total 98 [2018-09-14 15:53:44,694 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:44,695 INFO L459 AbstractCegarLoop]: Interpolant automaton has 76 states [2018-09-14 15:53:44,695 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2018-09-14 15:53:44,696 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=4753, Invalid=4753, Unknown=0, NotChecked=0, Total=9506 [2018-09-14 15:53:44,696 INFO L87 Difference]: Start difference. First operand 228 states and 255 transitions. Second operand 76 states. [2018-09-14 15:53:45,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:45,287 INFO L93 Difference]: Finished difference Result 323 states and 381 transitions. [2018-09-14 15:53:45,287 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2018-09-14 15:53:45,287 INFO L78 Accepts]: Start accepts. Automaton has 76 states. Word has length 227 [2018-09-14 15:53:45,287 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:45,288 INFO L225 Difference]: With dead ends: 323 [2018-09-14 15:53:45,288 INFO L226 Difference]: Without dead ends: 235 [2018-09-14 15:53:45,289 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 954 GetRequests, 846 SyntacticMatches, 12 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 294 ImplicationChecksByTransitivity, 4.8s TimeCoverageRelationStatistics Valid=4753, Invalid=4753, Unknown=0, NotChecked=0, Total=9506 [2018-09-14 15:53:45,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 235 states. [2018-09-14 15:53:45,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 235 to 234. [2018-09-14 15:53:45,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 234 states. [2018-09-14 15:53:45,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 234 states to 234 states and 262 transitions. [2018-09-14 15:53:45,295 INFO L78 Accepts]: Start accepts. Automaton has 234 states and 262 transitions. Word has length 227 [2018-09-14 15:53:45,296 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:45,296 INFO L480 AbstractCegarLoop]: Abstraction has 234 states and 262 transitions. [2018-09-14 15:53:45,296 INFO L481 AbstractCegarLoop]: Interpolant automaton has 76 states. [2018-09-14 15:53:45,296 INFO L276 IsEmpty]: Start isEmpty. Operand 234 states and 262 transitions. [2018-09-14 15:53:45,297 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 234 [2018-09-14 15:53:45,297 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:45,297 INFO L376 BasicCegarLoop]: trace histogram [75, 74, 46, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:45,298 INFO L423 AbstractCegarLoop]: === Iteration 49 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:45,298 INFO L82 PathProgramCache]: Analyzing trace with hash 1788966879, now seen corresponding path program 46 times [2018-09-14 15:53:45,298 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:45,299 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:45,299 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:45,299 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:45,299 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:45,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:46,506 INFO L134 CoverageAnalysis]: Checked inductivity of 8251 backedges. 3901 proven. 3243 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-09-14 15:53:46,507 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:46,507 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 93 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 93 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:46,515 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:53:46,515 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:53:46,567 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:53:46,567 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:46,570 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:46,603 INFO L134 CoverageAnalysis]: Checked inductivity of 8251 backedges. 3901 proven. 3243 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-09-14 15:53:46,603 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:47,537 INFO L134 CoverageAnalysis]: Checked inductivity of 8251 backedges. 3901 proven. 3243 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-09-14 15:53:47,557 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:47,557 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 94 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 94 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:47,572 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:53:47,572 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:53:47,683 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:53:47,684 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:47,690 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:47,724 INFO L134 CoverageAnalysis]: Checked inductivity of 8251 backedges. 3901 proven. 3243 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-09-14 15:53:47,724 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:48,862 INFO L134 CoverageAnalysis]: Checked inductivity of 8251 backedges. 3901 proven. 3243 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-09-14 15:53:48,863 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:48,864 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49, 49, 49, 49] total 52 [2018-09-14 15:53:48,864 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:48,864 INFO L459 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-09-14 15:53:48,865 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-09-14 15:53:48,865 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:48,865 INFO L87 Difference]: Start difference. First operand 234 states and 262 transitions. Second operand 49 states. [2018-09-14 15:53:49,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:49,012 INFO L93 Difference]: Finished difference Result 328 states and 385 transitions. [2018-09-14 15:53:49,012 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-09-14 15:53:49,013 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 233 [2018-09-14 15:53:49,013 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:49,014 INFO L225 Difference]: With dead ends: 328 [2018-09-14 15:53:49,014 INFO L226 Difference]: Without dead ends: 237 [2018-09-14 15:53:49,015 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 979 GetRequests, 841 SyntacticMatches, 88 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2156 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:49,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 237 states. [2018-09-14 15:53:49,020 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 237 to 237. [2018-09-14 15:53:49,020 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 237 states. [2018-09-14 15:53:49,021 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 237 states to 237 states and 265 transitions. [2018-09-14 15:53:49,021 INFO L78 Accepts]: Start accepts. Automaton has 237 states and 265 transitions. Word has length 233 [2018-09-14 15:53:49,021 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:49,021 INFO L480 AbstractCegarLoop]: Abstraction has 237 states and 265 transitions. [2018-09-14 15:53:49,021 INFO L481 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-09-14 15:53:49,021 INFO L276 IsEmpty]: Start isEmpty. Operand 237 states and 265 transitions. [2018-09-14 15:53:49,023 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 237 [2018-09-14 15:53:49,023 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:49,023 INFO L376 BasicCegarLoop]: trace histogram [76, 75, 47, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:49,023 INFO L423 AbstractCegarLoop]: === Iteration 50 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:49,023 INFO L82 PathProgramCache]: Analyzing trace with hash 496351002, now seen corresponding path program 47 times [2018-09-14 15:53:49,024 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:49,024 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:49,024 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:49,024 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:49,024 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:49,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:49,991 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 3984 proven. 3384 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-09-14 15:53:49,992 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:49,992 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 95 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 95 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:50,001 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:53:50,002 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:50,128 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 76 check-sat command(s) [2018-09-14 15:53:50,128 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:50,131 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:50,167 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 3984 proven. 3384 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-09-14 15:53:50,167 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:51,109 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 3984 proven. 3384 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-09-14 15:53:51,129 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:51,130 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 96 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 96 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:51,144 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:53:51,144 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:52,131 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 76 check-sat command(s) [2018-09-14 15:53:52,131 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:52,137 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:52,172 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 3984 proven. 3384 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-09-14 15:53:52,172 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:53,033 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 3984 proven. 3384 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-09-14 15:53:53,034 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:53,034 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50, 50, 50, 50] total 52 [2018-09-14 15:53:53,034 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:53,035 INFO L459 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-09-14 15:53:53,035 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-09-14 15:53:53,035 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:53,036 INFO L87 Difference]: Start difference. First operand 237 states and 265 transitions. Second operand 50 states. [2018-09-14 15:53:53,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:53,280 INFO L93 Difference]: Finished difference Result 331 states and 388 transitions. [2018-09-14 15:53:53,281 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-09-14 15:53:53,281 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 236 [2018-09-14 15:53:53,281 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:53,282 INFO L225 Difference]: With dead ends: 331 [2018-09-14 15:53:53,282 INFO L226 Difference]: Without dead ends: 240 [2018-09-14 15:53:53,282 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 992 GetRequests, 850 SyntacticMatches, 92 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2254 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:53,283 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 240 states. [2018-09-14 15:53:53,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 240 to 240. [2018-09-14 15:53:53,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 240 states. [2018-09-14 15:53:53,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 240 states to 240 states and 268 transitions. [2018-09-14 15:53:53,288 INFO L78 Accepts]: Start accepts. Automaton has 240 states and 268 transitions. Word has length 236 [2018-09-14 15:53:53,288 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:53,288 INFO L480 AbstractCegarLoop]: Abstraction has 240 states and 268 transitions. [2018-09-14 15:53:53,288 INFO L481 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-09-14 15:53:53,289 INFO L276 IsEmpty]: Start isEmpty. Operand 240 states and 268 transitions. [2018-09-14 15:53:53,290 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 240 [2018-09-14 15:53:53,290 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:53,290 INFO L376 BasicCegarLoop]: trace histogram [77, 76, 48, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:53,290 INFO L423 AbstractCegarLoop]: === Iteration 51 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:53,290 INFO L82 PathProgramCache]: Analyzing trace with hash 853535231, now seen corresponding path program 48 times [2018-09-14 15:53:53,291 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:53,291 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:53,291 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:53,291 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:53,291 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:53,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:54,346 INFO L134 CoverageAnalysis]: Checked inductivity of 8702 backedges. 4067 proven. 3528 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-09-14 15:53:54,346 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:54,347 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 97 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 97 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:54,355 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:53:54,355 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:53:54,596 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 76 check-sat command(s) [2018-09-14 15:53:54,596 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:54,600 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:54,637 INFO L134 CoverageAnalysis]: Checked inductivity of 8702 backedges. 4067 proven. 3528 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-09-14 15:53:54,637 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:55,580 INFO L134 CoverageAnalysis]: Checked inductivity of 8702 backedges. 4067 proven. 3528 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-09-14 15:53:55,600 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:55,600 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 98 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 98 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:55,614 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:53:55,614 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:53:56,725 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 76 check-sat command(s) [2018-09-14 15:53:56,725 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:56,731 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:56,767 INFO L134 CoverageAnalysis]: Checked inductivity of 8702 backedges. 4067 proven. 3528 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-09-14 15:53:56,767 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:57,679 INFO L134 CoverageAnalysis]: Checked inductivity of 8702 backedges. 4067 proven. 3528 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-09-14 15:53:57,680 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:57,681 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 51, 51, 51, 51] total 52 [2018-09-14 15:53:57,681 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:57,681 INFO L459 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-09-14 15:53:57,682 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-09-14 15:53:57,682 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:57,682 INFO L87 Difference]: Start difference. First operand 240 states and 268 transitions. Second operand 51 states. [2018-09-14 15:53:57,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:57,883 INFO L93 Difference]: Finished difference Result 334 states and 391 transitions. [2018-09-14 15:53:57,883 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-09-14 15:53:57,883 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 239 [2018-09-14 15:53:57,884 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:57,885 INFO L225 Difference]: With dead ends: 334 [2018-09-14 15:53:57,886 INFO L226 Difference]: Without dead ends: 243 [2018-09-14 15:53:57,886 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1005 GetRequests, 859 SyntacticMatches, 96 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2352 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:57,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 243 states. [2018-09-14 15:53:57,891 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 243 to 243. [2018-09-14 15:53:57,891 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 243 states. [2018-09-14 15:53:57,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 243 states to 243 states and 271 transitions. [2018-09-14 15:53:57,892 INFO L78 Accepts]: Start accepts. Automaton has 243 states and 271 transitions. Word has length 239 [2018-09-14 15:53:57,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:57,892 INFO L480 AbstractCegarLoop]: Abstraction has 243 states and 271 transitions. [2018-09-14 15:53:57,892 INFO L481 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-09-14 15:53:57,893 INFO L276 IsEmpty]: Start isEmpty. Operand 243 states and 271 transitions. [2018-09-14 15:53:57,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 243 [2018-09-14 15:53:57,894 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:57,894 INFO L376 BasicCegarLoop]: trace histogram [78, 77, 49, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:57,894 INFO L423 AbstractCegarLoop]: === Iteration 52 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:57,895 INFO L82 PathProgramCache]: Analyzing trace with hash -1200058118, now seen corresponding path program 49 times [2018-09-14 15:53:57,895 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:57,895 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:57,895 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:57,895 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:57,896 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:57,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:59,339 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 4150 proven. 3675 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-09-14 15:53:59,339 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:59,339 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 99 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 99 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:59,346 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:53:59,346 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:53:59,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:59,404 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:59,441 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 4150 proven. 3675 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-09-14 15:53:59,442 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:00,383 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 4150 proven. 3675 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-09-14 15:54:00,403 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:00,403 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 100 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 100 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:00,417 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:54:00,418 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:54:00,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:00,540 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:00,577 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 4150 proven. 3675 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-09-14 15:54:00,577 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:01,507 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 4150 proven. 3675 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-09-14 15:54:01,509 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:01,509 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 52, 52, 52, 52] total 52 [2018-09-14 15:54:01,509 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:01,509 INFO L459 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-09-14 15:54:01,510 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-09-14 15:54:01,510 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:01,510 INFO L87 Difference]: Start difference. First operand 243 states and 271 transitions. Second operand 52 states. [2018-09-14 15:54:01,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:01,662 INFO L93 Difference]: Finished difference Result 337 states and 394 transitions. [2018-09-14 15:54:01,662 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-09-14 15:54:01,663 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 242 [2018-09-14 15:54:01,663 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:01,664 INFO L225 Difference]: With dead ends: 337 [2018-09-14 15:54:01,664 INFO L226 Difference]: Without dead ends: 246 [2018-09-14 15:54:01,665 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1018 GetRequests, 868 SyntacticMatches, 100 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2450 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:01,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 246 states. [2018-09-14 15:54:01,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 246 to 246. [2018-09-14 15:54:01,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 246 states. [2018-09-14 15:54:01,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 246 states to 246 states and 274 transitions. [2018-09-14 15:54:01,670 INFO L78 Accepts]: Start accepts. Automaton has 246 states and 274 transitions. Word has length 242 [2018-09-14 15:54:01,671 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:01,671 INFO L480 AbstractCegarLoop]: Abstraction has 246 states and 274 transitions. [2018-09-14 15:54:01,671 INFO L481 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-09-14 15:54:01,671 INFO L276 IsEmpty]: Start isEmpty. Operand 246 states and 274 transitions. [2018-09-14 15:54:01,672 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 246 [2018-09-14 15:54:01,672 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:01,672 INFO L376 BasicCegarLoop]: trace histogram [79, 78, 50, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:01,673 INFO L423 AbstractCegarLoop]: === Iteration 53 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:01,673 INFO L82 PathProgramCache]: Analyzing trace with hash 2009613343, now seen corresponding path program 50 times [2018-09-14 15:54:01,673 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:01,673 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:01,673 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:54:01,674 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:01,674 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:01,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:02,448 INFO L134 CoverageAnalysis]: Checked inductivity of 9165 backedges. 4416 proven. 1365 refuted. 0 times theorem prover too weak. 3384 trivial. 0 not checked. [2018-09-14 15:54:02,448 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:02,448 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 101 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 101 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:02,455 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:54:02,456 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:54:02,512 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:54:02,512 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:02,515 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:04,438 INFO L134 CoverageAnalysis]: Checked inductivity of 9165 backedges. 0 proven. 9165 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:54:04,438 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:07,639 INFO L134 CoverageAnalysis]: Checked inductivity of 9165 backedges. 0 proven. 9165 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:54:07,659 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:07,659 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 102 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 102 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:07,673 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:54:07,674 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:54:07,799 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:54:07,799 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:07,805 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:07,853 INFO L134 CoverageAnalysis]: Checked inductivity of 9165 backedges. 0 proven. 9165 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:54:07,853 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:09,329 INFO L134 CoverageAnalysis]: Checked inductivity of 9165 backedges. 0 proven. 9165 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:54:09,331 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:09,331 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 81, 81, 81, 81] total 102 [2018-09-14 15:54:09,331 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:09,331 INFO L459 AbstractCegarLoop]: Interpolant automaton has 83 states [2018-09-14 15:54:09,332 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2018-09-14 15:54:09,332 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=5151, Invalid=5151, Unknown=0, NotChecked=0, Total=10302 [2018-09-14 15:54:09,332 INFO L87 Difference]: Start difference. First operand 246 states and 274 transitions. Second operand 83 states. [2018-09-14 15:54:11,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:11,215 INFO L93 Difference]: Finished difference Result 261 states and 295 transitions. [2018-09-14 15:54:11,215 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2018-09-14 15:54:11,215 INFO L78 Accepts]: Start accepts. Automaton has 83 states. Word has length 245 [2018-09-14 15:54:11,215 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:11,216 INFO L225 Difference]: With dead ends: 261 [2018-09-14 15:54:11,216 INFO L226 Difference]: Without dead ends: 256 [2018-09-14 15:54:11,217 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1011 GetRequests, 791 SyntacticMatches, 120 SemanticMatches, 100 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19604 ImplicationChecksByTransitivity, 7.1s TimeCoverageRelationStatistics Valid=5151, Invalid=5151, Unknown=0, NotChecked=0, Total=10302 [2018-09-14 15:54:11,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states. [2018-09-14 15:54:11,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 255. [2018-09-14 15:54:11,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 255 states. [2018-09-14 15:54:11,221 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 255 states to 255 states and 286 transitions. [2018-09-14 15:54:11,222 INFO L78 Accepts]: Start accepts. Automaton has 255 states and 286 transitions. Word has length 245 [2018-09-14 15:54:11,222 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:11,222 INFO L480 AbstractCegarLoop]: Abstraction has 255 states and 286 transitions. [2018-09-14 15:54:11,222 INFO L481 AbstractCegarLoop]: Interpolant automaton has 83 states. [2018-09-14 15:54:11,222 INFO L276 IsEmpty]: Start isEmpty. Operand 255 states and 286 transitions. [2018-09-14 15:54:11,224 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 255 [2018-09-14 15:54:11,224 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:11,224 INFO L376 BasicCegarLoop]: trace histogram [82, 81, 50, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:11,225 INFO L423 AbstractCegarLoop]: === Iteration 54 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:11,225 INFO L82 PathProgramCache]: Analyzing trace with hash 970419580, now seen corresponding path program 51 times [2018-09-14 15:54:11,225 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:11,226 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:11,226 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:11,226 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:11,226 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:11,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:11,830 INFO L134 CoverageAnalysis]: Checked inductivity of 9882 backedges. 4848 proven. 1650 refuted. 0 times theorem prover too weak. 3384 trivial. 0 not checked. [2018-09-14 15:54:11,830 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:11,830 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 103 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 103 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:11,838 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:54:11,838 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:54:11,924 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 48 check-sat command(s) [2018-09-14 15:54:11,924 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:11,927 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:11,971 INFO L134 CoverageAnalysis]: Checked inductivity of 9882 backedges. 4750 proven. 1457 refuted. 0 times theorem prover too weak. 3675 trivial. 0 not checked. [2018-09-14 15:54:11,971 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:12,791 INFO L134 CoverageAnalysis]: Checked inductivity of 9882 backedges. 4750 proven. 1457 refuted. 0 times theorem prover too weak. 3675 trivial. 0 not checked. [2018-09-14 15:54:12,811 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:12,812 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 104 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 104 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:12,826 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:54:12,826 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:54:13,437 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 48 check-sat command(s) [2018-09-14 15:54:13,437 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:13,443 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:13,476 INFO L134 CoverageAnalysis]: Checked inductivity of 9882 backedges. 4750 proven. 1457 refuted. 0 times theorem prover too weak. 3675 trivial. 0 not checked. [2018-09-14 15:54:13,477 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:14,117 INFO L134 CoverageAnalysis]: Checked inductivity of 9882 backedges. 4750 proven. 1457 refuted. 0 times theorem prover too weak. 3675 trivial. 0 not checked. [2018-09-14 15:54:14,118 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:14,119 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 34, 34, 34, 34] total 52 [2018-09-14 15:54:14,119 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:14,119 INFO L459 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-09-14 15:54:14,120 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-09-14 15:54:14,120 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:14,120 INFO L87 Difference]: Start difference. First operand 255 states and 286 transitions. Second operand 36 states. [2018-09-14 15:54:14,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:14,301 INFO L93 Difference]: Finished difference Result 270 states and 307 transitions. [2018-09-14 15:54:14,302 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-09-14 15:54:14,302 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 254 [2018-09-14 15:54:14,302 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:14,303 INFO L225 Difference]: With dead ends: 270 [2018-09-14 15:54:14,303 INFO L226 Difference]: Without dead ends: 265 [2018-09-14 15:54:14,304 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1050 GetRequests, 968 SyntacticMatches, 32 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 752 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:14,304 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 265 states. [2018-09-14 15:54:14,308 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 265 to 264. [2018-09-14 15:54:14,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 264 states. [2018-09-14 15:54:14,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 264 states to 264 states and 298 transitions. [2018-09-14 15:54:14,309 INFO L78 Accepts]: Start accepts. Automaton has 264 states and 298 transitions. Word has length 254 [2018-09-14 15:54:14,309 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:14,309 INFO L480 AbstractCegarLoop]: Abstraction has 264 states and 298 transitions. [2018-09-14 15:54:14,310 INFO L481 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-09-14 15:54:14,310 INFO L276 IsEmpty]: Start isEmpty. Operand 264 states and 298 transitions. [2018-09-14 15:54:14,311 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 264 [2018-09-14 15:54:14,311 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:14,311 INFO L376 BasicCegarLoop]: trace histogram [85, 84, 50, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:14,312 INFO L423 AbstractCegarLoop]: === Iteration 55 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:14,312 INFO L82 PathProgramCache]: Analyzing trace with hash -629900097, now seen corresponding path program 52 times [2018-09-14 15:54:14,312 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:14,313 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:14,313 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:14,313 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:14,313 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:14,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:15,169 INFO L134 CoverageAnalysis]: Checked inductivity of 10626 backedges. 5280 proven. 1962 refuted. 0 times theorem prover too weak. 3384 trivial. 0 not checked. [2018-09-14 15:54:15,169 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:15,169 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 105 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 105 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:15,177 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:54:15,177 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:54:15,237 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:54:15,237 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:15,240 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:16,313 INFO L134 CoverageAnalysis]: Checked inductivity of 10626 backedges. 0 proven. 10626 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:54:16,313 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:18,218 INFO L134 CoverageAnalysis]: Checked inductivity of 10626 backedges. 0 proven. 10626 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:54:18,240 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:18,240 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 106 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 106 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:18,254 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:54:18,255 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:54:18,391 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:54:18,391 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:18,397 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:18,468 INFO L134 CoverageAnalysis]: Checked inductivity of 10626 backedges. 0 proven. 10626 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:54:18,468 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:20,184 INFO L134 CoverageAnalysis]: Checked inductivity of 10626 backedges. 0 proven. 10626 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:54:20,185 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:20,186 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 87, 87, 87, 87] total 102 [2018-09-14 15:54:20,186 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:20,187 INFO L459 AbstractCegarLoop]: Interpolant automaton has 89 states [2018-09-14 15:54:20,188 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 89 interpolants. [2018-09-14 15:54:20,188 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=5151, Invalid=5151, Unknown=0, NotChecked=0, Total=10302 [2018-09-14 15:54:20,188 INFO L87 Difference]: Start difference. First operand 264 states and 298 transitions. Second operand 89 states. [2018-09-14 15:54:21,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:21,074 INFO L93 Difference]: Finished difference Result 279 states and 319 transitions. [2018-09-14 15:54:21,074 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-09-14 15:54:21,074 INFO L78 Accepts]: Start accepts. Automaton has 89 states. Word has length 263 [2018-09-14 15:54:21,075 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:21,076 INFO L225 Difference]: With dead ends: 279 [2018-09-14 15:54:21,076 INFO L226 Difference]: Without dead ends: 274 [2018-09-14 15:54:21,076 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1089 GetRequests, 845 SyntacticMatches, 144 SemanticMatches, 100 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22544 ImplicationChecksByTransitivity, 5.2s TimeCoverageRelationStatistics Valid=5151, Invalid=5151, Unknown=0, NotChecked=0, Total=10302 [2018-09-14 15:54:21,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 274 states. [2018-09-14 15:54:21,081 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 274 to 273. [2018-09-14 15:54:21,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 273 states. [2018-09-14 15:54:21,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 273 states to 273 states and 310 transitions. [2018-09-14 15:54:21,082 INFO L78 Accepts]: Start accepts. Automaton has 273 states and 310 transitions. Word has length 263 [2018-09-14 15:54:21,083 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:21,083 INFO L480 AbstractCegarLoop]: Abstraction has 273 states and 310 transitions. [2018-09-14 15:54:21,083 INFO L481 AbstractCegarLoop]: Interpolant automaton has 89 states. [2018-09-14 15:54:21,083 INFO L276 IsEmpty]: Start isEmpty. Operand 273 states and 310 transitions. [2018-09-14 15:54:21,084 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 273 [2018-09-14 15:54:21,084 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:21,085 INFO L376 BasicCegarLoop]: trace histogram [88, 87, 50, 37, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:21,085 INFO L423 AbstractCegarLoop]: === Iteration 56 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:21,085 INFO L82 PathProgramCache]: Analyzing trace with hash -682563364, now seen corresponding path program 53 times [2018-09-14 15:54:21,085 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:21,086 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:21,086 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:21,086 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:21,086 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:21,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:21,817 INFO L134 CoverageAnalysis]: Checked inductivity of 11397 backedges. 5712 proven. 2301 refuted. 0 times theorem prover too weak. 3384 trivial. 0 not checked. [2018-09-14 15:54:21,817 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:21,818 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 107 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 107 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:21,825 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:54:21,825 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:54:21,986 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 88 check-sat command(s) [2018-09-14 15:54:21,986 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:21,990 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:22,385 INFO L134 CoverageAnalysis]: Checked inductivity of 11397 backedges. 5662 proven. 3626 refuted. 0 times theorem prover too weak. 2109 trivial. 0 not checked. [2018-09-14 15:54:22,385 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:23,341 INFO L134 CoverageAnalysis]: Checked inductivity of 11397 backedges. 5662 proven. 3626 refuted. 0 times theorem prover too weak. 2109 trivial. 0 not checked. [2018-09-14 15:54:23,361 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:23,362 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 108 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 108 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:23,376 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:54:23,377 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:54:24,692 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 88 check-sat command(s) [2018-09-14 15:54:24,693 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:24,699 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:24,738 INFO L134 CoverageAnalysis]: Checked inductivity of 11397 backedges. 5650 proven. 2072 refuted. 0 times theorem prover too weak. 3675 trivial. 0 not checked. [2018-09-14 15:54:24,738 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:25,611 INFO L134 CoverageAnalysis]: Checked inductivity of 11397 backedges. 5650 proven. 2072 refuted. 0 times theorem prover too weak. 3675 trivial. 0 not checked. [2018-09-14 15:54:25,613 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:25,613 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 52, 52, 40, 40] total 52 [2018-09-14 15:54:25,613 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:25,614 INFO L459 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-09-14 15:54:25,614 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-09-14 15:54:25,615 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:25,615 INFO L87 Difference]: Start difference. First operand 273 states and 310 transitions. Second operand 52 states. [2018-09-14 15:54:25,970 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:25,971 INFO L93 Difference]: Finished difference Result 317 states and 379 transitions. [2018-09-14 15:54:25,971 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-09-14 15:54:25,971 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 272 [2018-09-14 15:54:25,972 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:25,973 INFO L225 Difference]: With dead ends: 317 [2018-09-14 15:54:25,974 INFO L226 Difference]: Without dead ends: 312 [2018-09-14 15:54:25,974 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1128 GetRequests, 990 SyntacticMatches, 88 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1928 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:25,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312 states. [2018-09-14 15:54:25,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 312 to 312. [2018-09-14 15:54:25,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 312 states. [2018-09-14 15:54:25,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 312 states to 312 states and 362 transitions. [2018-09-14 15:54:25,978 INFO L78 Accepts]: Start accepts. Automaton has 312 states and 362 transitions. Word has length 272 [2018-09-14 15:54:25,979 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:25,979 INFO L480 AbstractCegarLoop]: Abstraction has 312 states and 362 transitions. [2018-09-14 15:54:25,979 INFO L481 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-09-14 15:54:25,979 INFO L276 IsEmpty]: Start isEmpty. Operand 312 states and 362 transitions. [2018-09-14 15:54:25,981 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 312 [2018-09-14 15:54:25,981 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:25,981 INFO L376 BasicCegarLoop]: trace histogram [101, 100, 50, 50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:25,981 INFO L423 AbstractCegarLoop]: === Iteration 57 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:25,982 INFO L82 PathProgramCache]: Analyzing trace with hash -1819528257, now seen corresponding path program 54 times [2018-09-14 15:54:25,982 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:25,982 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:25,982 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:25,982 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:25,983 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:26,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:28,443 INFO L134 CoverageAnalysis]: Checked inductivity of 15050 backedges. 0 proven. 11225 refuted. 0 times theorem prover too weak. 3825 trivial. 0 not checked. [2018-09-14 15:54:28,443 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:28,443 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 109 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 109 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:28,452 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:54:28,453 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:54:28,653 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 101 check-sat command(s) [2018-09-14 15:54:28,653 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:28,659 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:29,026 INFO L134 CoverageAnalysis]: Checked inductivity of 15050 backedges. 0 proven. 11225 refuted. 0 times theorem prover too weak. 3825 trivial. 0 not checked. [2018-09-14 15:54:29,026 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:29,618 INFO L134 CoverageAnalysis]: Checked inductivity of 15050 backedges. 0 proven. 11225 refuted. 0 times theorem prover too weak. 3825 trivial. 0 not checked. [2018-09-14 15:54:29,639 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:29,639 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 110 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 110 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:29,653 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:54:29,654 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:54:31,663 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 101 check-sat command(s) [2018-09-14 15:54:31,663 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:31,673 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:32,142 INFO L134 CoverageAnalysis]: Checked inductivity of 15050 backedges. 0 proven. 11225 refuted. 0 times theorem prover too weak. 3825 trivial. 0 not checked. [2018-09-14 15:54:32,142 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:32,503 INFO L134 CoverageAnalysis]: Checked inductivity of 15050 backedges. 0 proven. 11225 refuted. 0 times theorem prover too weak. 3825 trivial. 0 not checked. [2018-09-14 15:54:32,504 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:32,505 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [55, 55, 55, 55, 55] total 57 [2018-09-14 15:54:32,505 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:32,505 INFO L459 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-09-14 15:54:32,505 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-09-14 15:54:32,505 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=113, Invalid=3079, Unknown=0, NotChecked=0, Total=3192 [2018-09-14 15:54:32,505 INFO L87 Difference]: Start difference. First operand 312 states and 362 transitions. Second operand 55 states. [2018-09-14 15:54:34,786 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:34,786 INFO L93 Difference]: Finished difference Result 4294 states and 5669 transitions. [2018-09-14 15:54:34,786 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-09-14 15:54:34,786 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 311 [2018-09-14 15:54:34,787 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:34,806 INFO L225 Difference]: With dead ends: 4294 [2018-09-14 15:54:34,806 INFO L226 Difference]: Without dead ends: 4289 [2018-09-14 15:54:34,808 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1298 GetRequests, 1232 SyntacticMatches, 10 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=119, Invalid=3187, Unknown=0, NotChecked=0, Total=3306 [2018-09-14 15:54:34,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4289 states. [2018-09-14 15:54:34,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4289 to 315. [2018-09-14 15:54:34,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 315 states. [2018-09-14 15:54:34,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 315 states to 315 states and 366 transitions. [2018-09-14 15:54:34,878 INFO L78 Accepts]: Start accepts. Automaton has 315 states and 366 transitions. Word has length 311 [2018-09-14 15:54:34,878 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:34,879 INFO L480 AbstractCegarLoop]: Abstraction has 315 states and 366 transitions. [2018-09-14 15:54:34,879 INFO L481 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-09-14 15:54:34,879 INFO L276 IsEmpty]: Start isEmpty. Operand 315 states and 366 transitions. [2018-09-14 15:54:34,880 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 315 [2018-09-14 15:54:34,881 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:34,881 INFO L376 BasicCegarLoop]: trace histogram [102, 101, 51, 50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:34,881 INFO L423 AbstractCegarLoop]: === Iteration 58 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:34,881 INFO L82 PathProgramCache]: Analyzing trace with hash 908591292, now seen corresponding path program 55 times [2018-09-14 15:54:34,882 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:34,882 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:34,882 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:34,883 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:34,883 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:34,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:36,087 INFO L134 CoverageAnalysis]: Checked inductivity of 15352 backedges. 11527 proven. 0 refuted. 0 times theorem prover too weak. 3825 trivial. 0 not checked. [2018-09-14 15:54:36,088 INFO L313 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-09-14 15:54:36,088 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [52] imperfect sequences [] total 52 [2018-09-14 15:54:36,088 INFO L265 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-09-14 15:54:36,088 INFO L459 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-09-14 15:54:36,089 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-09-14 15:54:36,089 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:36,089 INFO L87 Difference]: Start difference. First operand 315 states and 366 transitions. Second operand 52 states. [2018-09-14 15:54:36,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:36,405 INFO L93 Difference]: Finished difference Result 464 states and 564 transitions. [2018-09-14 15:54:36,405 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-09-14 15:54:36,406 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 314 [2018-09-14 15:54:36,406 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:36,407 INFO L225 Difference]: With dead ends: 464 [2018-09-14 15:54:36,407 INFO L226 Difference]: Without dead ends: 0 [2018-09-14 15:54:36,408 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:36,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 0 states. [2018-09-14 15:54:36,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 0 to 0. [2018-09-14 15:54:36,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 0 states. [2018-09-14 15:54:36,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 0 states to 0 states and 0 transitions. [2018-09-14 15:54:36,410 INFO L78 Accepts]: Start accepts. Automaton has 0 states and 0 transitions. Word has length 314 [2018-09-14 15:54:36,410 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:36,410 INFO L480 AbstractCegarLoop]: Abstraction has 0 states and 0 transitions. [2018-09-14 15:54:36,410 INFO L481 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-09-14 15:54:36,410 INFO L276 IsEmpty]: Start isEmpty. Operand 0 states and 0 transitions. [2018-09-14 15:54:36,410 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-09-14 15:54:36,415 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends 0 states and 0 transitions. [2018-09-14 15:54:37,255 WARN L178 SmtUtils]: Spent 821.00 ms on a formula simplification. DAG size of input: 1832 DAG size of output: 407 [2018-09-14 15:54:40,479 WARN L178 SmtUtils]: Spent 3.17 s on a formula simplification. DAG size of input: 407 DAG size of output: 357 [2018-09-14 15:54:40,490 INFO L429 ceAbstractionStarter]: At program point ULTIMATE.initFINAL(line -1) the Hoare annotation is: true [2018-09-14 15:54:40,490 INFO L426 ceAbstractionStarter]: For program point ULTIMATE.initEXIT(line -1) no Hoare annotation was computed. [2018-09-14 15:54:40,490 INFO L426 ceAbstractionStarter]: For program point ULTIMATE.startEXIT(line -1) no Hoare annotation was computed. [2018-09-14 15:54:40,490 INFO L429 ceAbstractionStarter]: At program point L-1(line -1) the Hoare annotation is: true [2018-09-14 15:54:40,490 INFO L429 ceAbstractionStarter]: At program point ULTIMATE.startENTRY(line -1) the Hoare annotation is: true [2018-09-14 15:54:40,491 INFO L426 ceAbstractionStarter]: For program point ULTIMATE.startFINAL(line -1) no Hoare annotation was computed. [2018-09-14 15:54:40,491 INFO L429 ceAbstractionStarter]: At program point mainENTRY(lines 10 23) the Hoare annotation is: true [2018-09-14 15:54:40,491 INFO L426 ceAbstractionStarter]: For program point mainEXIT(lines 10 23) no Hoare annotation was computed. [2018-09-14 15:54:40,491 INFO L426 ceAbstractionStarter]: For program point L21(line 21) no Hoare annotation was computed. [2018-09-14 15:54:40,491 INFO L426 ceAbstractionStarter]: For program point L14(lines 14 19) no Hoare annotation was computed. [2018-09-14 15:54:40,491 INFO L426 ceAbstractionStarter]: For program point mainFINAL(lines 10 23) no Hoare annotation was computed. [2018-09-14 15:54:40,491 INFO L426 ceAbstractionStarter]: For program point L13-1(lines 13 20) no Hoare annotation was computed. [2018-09-14 15:54:40,493 INFO L422 ceAbstractionStarter]: At program point L14-2(lines 13 20) the Hoare annotation is: (or (and (and (<= main_~x~0 99) (<= 99 main_~y~0) (<= main_~y~0 99)) (<= 99 main_~x~0)) (and (and (<= main_~y~0 92) (<= 92 main_~y~0) (<= main_~x~0 92)) (<= 92 main_~x~0)) (and (<= 65 main_~x~0) (and (<= main_~y~0 65) (<= 65 main_~y~0) (<= main_~x~0 65))) (and (and (<= main_~y~0 100) (< 99 main_~y~0)) (<= 100 main_~x~0)) (and (<= 64 main_~x~0) (and (<= main_~x~0 64) (<= 64 main_~y~0) (<= main_~y~0 64))) (and (<= 76 main_~x~0) (and (<= main_~y~0 76) (<= main_~x~0 76) (<= 76 main_~y~0))) (and (<= 87 main_~x~0) (and (<= main_~x~0 87) (<= main_~y~0 87) (<= 87 main_~y~0))) (and (and (<= main_~y~0 78) (<= 78 main_~y~0) (<= main_~x~0 78)) (<= 78 main_~x~0)) (and (<= 72 main_~x~0) (and (<= main_~y~0 72) (<= main_~x~0 72) (<= 72 main_~y~0))) (and (and (<= main_~y~0 69) (<= 69 main_~y~0) (<= main_~x~0 69)) (<= 69 main_~x~0)) (and (<= 60 main_~x~0) (and (<= main_~x~0 60) (<= main_~y~0 60) (<= 60 main_~y~0))) (and (<= 67 main_~x~0) (and (<= main_~y~0 67) (<= main_~x~0 67) (<= 67 main_~y~0))) (and (and (<= main_~y~0 55) (<= 55 main_~y~0) (<= main_~x~0 55)) (<= 55 main_~x~0)) (and (and (<= 73 main_~y~0) (<= main_~x~0 73) (<= main_~y~0 73)) (<= 73 main_~x~0)) (and (<= 66 main_~x~0) (and (<= main_~y~0 66) (<= 66 main_~y~0) (<= main_~x~0 66))) (and (and (<= main_~x~0 70) (<= main_~y~0 70) (<= 70 main_~y~0)) (<= 70 main_~x~0)) (and (and (<= main_~x~0 95) (<= main_~y~0 95) (<= 95 main_~y~0)) (<= 95 main_~x~0)) (and (and (<= 90 main_~y~0) (<= main_~y~0 90) (<= main_~x~0 90)) (<= 90 main_~x~0)) (and (and (<= main_~y~0 59) (<= main_~x~0 59) (<= 59 main_~y~0)) (<= 59 main_~x~0)) (and (<= 85 main_~x~0) (and (<= 85 main_~y~0) (<= main_~x~0 85) (<= main_~y~0 85))) (and (<= 63 main_~x~0) (and (<= main_~y~0 63) (<= main_~x~0 63) (<= 63 main_~y~0))) (and (and (<= main_~y~0 77) (<= main_~x~0 77) (<= 77 main_~y~0)) (<= 77 main_~x~0)) (and (<= 53 main_~x~0) (and (<= main_~y~0 53) (<= main_~x~0 53) (<= 53 main_~y~0))) (and (and (<= main_~x~0 79) (<= main_~y~0 79) (<= 79 main_~y~0)) (<= 79 main_~x~0)) (and (<= 68 main_~x~0) (and (<= 68 main_~y~0) (<= main_~y~0 68) (<= main_~x~0 68))) (and (<= 51 main_~x~0) (and (<= 51 main_~y~0) (<= main_~x~0 51) (<= main_~y~0 51))) (and (<= 54 main_~x~0) (and (<= main_~x~0 54) (<= 54 main_~y~0) (<= main_~y~0 54))) (and (and (<= 56 main_~y~0) (<= main_~x~0 56) (<= main_~y~0 56)) (<= 56 main_~x~0)) (and (<= 61 main_~x~0) (and (<= main_~y~0 61) (<= 61 main_~y~0) (<= main_~x~0 61))) (and (<= 88 main_~x~0) (and (<= main_~x~0 88) (<= main_~y~0 88) (<= 88 main_~y~0))) (and (<= main_~y~0 50) (<= main_~x~0 50) (<= 50 main_~y~0)) (and (<= 80 main_~x~0) (and (<= main_~x~0 80) (<= 80 main_~y~0) (<= main_~y~0 80))) (and (<= 94 main_~x~0) (and (<= main_~x~0 94) (<= main_~y~0 94) (<= 94 main_~y~0))) (and (<= 89 main_~x~0) (and (<= 89 main_~y~0) (<= main_~y~0 89) (<= main_~x~0 89))) (and (and (<= 86 main_~y~0) (<= main_~x~0 86) (<= main_~y~0 86)) (<= 86 main_~x~0)) (and (<= 58 main_~x~0) (and (<= main_~x~0 58) (<= main_~y~0 58) (<= 58 main_~y~0))) (and (and (<= main_~x~0 91) (<= 91 main_~y~0) (<= main_~y~0 91)) (<= 91 main_~x~0)) (and (and (<= 52 main_~y~0) (<= main_~y~0 52) (<= main_~x~0 52)) (<= 52 main_~x~0)) (and (<= 93 main_~x~0) (and (<= main_~x~0 93) (<= 93 main_~y~0) (<= main_~y~0 93))) (and (<= 74 main_~x~0) (and (<= 74 main_~y~0) (<= main_~y~0 74) (<= main_~x~0 74))) (and (and (<= main_~y~0 71) (<= main_~x~0 71) (<= 71 main_~y~0)) (<= 71 main_~x~0)) (and (<= 57 main_~x~0) (and (<= 57 main_~y~0) (<= main_~x~0 57) (<= main_~y~0 57))) (and (<= 97 main_~x~0) (and (<= 97 main_~y~0) (<= main_~x~0 97) (<= main_~y~0 97))) (and (and (<= main_~x~0 81) (<= 81 main_~y~0) (<= main_~y~0 81)) (<= 81 main_~x~0)) (and (<= 84 main_~x~0) (and (<= main_~y~0 84) (<= 84 main_~y~0) (<= main_~x~0 84))) (and (and (<= 96 main_~y~0) (<= main_~x~0 96) (<= main_~y~0 96)) (<= 96 main_~x~0)) (and (<= 83 main_~x~0) (and (<= main_~y~0 83) (<= 83 main_~y~0) (<= main_~x~0 83))) (and (<= 62 main_~x~0) (and (<= main_~y~0 62) (<= main_~x~0 62) (<= 62 main_~y~0))) (and (and (<= main_~x~0 98) (<= main_~y~0 98) (<= 98 main_~y~0)) (<= 98 main_~x~0)) (and (and (<= 75 main_~y~0) (<= main_~x~0 75) (<= main_~y~0 75)) (<= 75 main_~x~0)) (and (and (<= 82 main_~y~0) (<= main_~y~0 82) (<= main_~x~0 82)) (<= 82 main_~x~0))) [2018-09-14 15:54:40,493 INFO L422 ceAbstractionStarter]: At program point L13-3(lines 13 20) the Hoare annotation is: (and (<= main_~y~0 100) (< 99 main_~y~0)) [2018-09-14 15:54:40,493 INFO L429 ceAbstractionStarter]: At program point __VERIFIER_assertENTRY(lines 3 8) the Hoare annotation is: true [2018-09-14 15:54:40,493 INFO L426 ceAbstractionStarter]: For program point __VERIFIER_assertEXIT(lines 3 8) no Hoare annotation was computed. [2018-09-14 15:54:40,493 INFO L426 ceAbstractionStarter]: For program point __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION(line 5) no Hoare annotation was computed. [2018-09-14 15:54:40,494 INFO L426 ceAbstractionStarter]: For program point L5(line 5) no Hoare annotation was computed. [2018-09-14 15:54:40,494 INFO L426 ceAbstractionStarter]: For program point L4(lines 4 6) no Hoare annotation was computed. [2018-09-14 15:54:40,494 INFO L426 ceAbstractionStarter]: For program point L4-2(lines 3 8) no Hoare annotation was computed. [2018-09-14 15:54:40,522 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 14.09 03:54:40 BoogieIcfgContainer [2018-09-14 15:54:40,522 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-09-14 15:54:40,523 INFO L168 Benchmark]: Toolchain (without parser) took 162048.70 ms. Allocated memory was 1.5 GB in the beginning and 2.6 GB in the end (delta: 1.0 GB). Free memory was 1.4 GB in the beginning and 2.0 GB in the end (delta: -528.6 MB). Peak memory consumption was 488.0 MB. Max. memory is 7.1 GB. [2018-09-14 15:54:40,524 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-09-14 15:54:40,524 INFO L168 Benchmark]: CACSL2BoogieTranslator took 255.03 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. [2018-09-14 15:54:40,525 INFO L168 Benchmark]: Boogie Procedure Inliner took 22.53 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-09-14 15:54:40,525 INFO L168 Benchmark]: Boogie Preprocessor took 21.39 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-09-14 15:54:40,525 INFO L168 Benchmark]: RCFGBuilder took 409.72 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 788.5 MB). Free memory was 1.4 GB in the beginning and 2.3 GB in the end (delta: -838.9 MB). Peak memory consumption was 26.6 MB. Max. memory is 7.1 GB. [2018-09-14 15:54:40,526 INFO L168 Benchmark]: TraceAbstraction took 161333.23 ms. Allocated memory was 2.3 GB in the beginning and 2.6 GB in the end (delta: 228.1 MB). Free memory was 2.3 GB in the beginning and 2.0 GB in the end (delta: 299.8 MB). Peak memory consumption was 527.8 MB. Max. memory is 7.1 GB. [2018-09-14 15:54:40,528 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 255.03 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 22.53 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Preprocessor took 21.39 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * RCFGBuilder took 409.72 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 788.5 MB). Free memory was 1.4 GB in the beginning and 2.3 GB in the end (delta: -838.9 MB). Peak memory consumption was 26.6 MB. Max. memory is 7.1 GB. * TraceAbstraction took 161333.23 ms. Allocated memory was 2.3 GB in the beginning and 2.6 GB in the end (delta: 228.1 MB). Free memory was 2.3 GB in the beginning and 2.0 GB in the end (delta: 299.8 MB). Peak memory consumption was 527.8 MB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - PositiveResult [Line: 5]: call of __VERIFIER_error() unreachable For all program executions holds that call of __VERIFIER_error() unreachable at this location - AllSpecificationsHoldResult: All specifications hold 1 specifications checked. All of them hold - InvariantResult [Line: 13]: Loop Invariant Derived loop invariant: ((((((((((((((((((((((((((((((((((((((((((((((((((((x <= 99 && 99 <= y) && y <= 99) && 99 <= x) || (((y <= 92 && 92 <= y) && x <= 92) && 92 <= x)) || (65 <= x && (y <= 65 && 65 <= y) && x <= 65)) || ((y <= 100 && 99 < y) && 100 <= x)) || (64 <= x && (x <= 64 && 64 <= y) && y <= 64)) || (76 <= x && (y <= 76 && x <= 76) && 76 <= y)) || (87 <= x && (x <= 87 && y <= 87) && 87 <= y)) || (((y <= 78 && 78 <= y) && x <= 78) && 78 <= x)) || (72 <= x && (y <= 72 && x <= 72) && 72 <= y)) || (((y <= 69 && 69 <= y) && x <= 69) && 69 <= x)) || (60 <= x && (x <= 60 && y <= 60) && 60 <= y)) || (67 <= x && (y <= 67 && x <= 67) && 67 <= y)) || (((y <= 55 && 55 <= y) && x <= 55) && 55 <= x)) || (((73 <= y && x <= 73) && y <= 73) && 73 <= x)) || (66 <= x && (y <= 66 && 66 <= y) && x <= 66)) || (((x <= 70 && y <= 70) && 70 <= y) && 70 <= x)) || (((x <= 95 && y <= 95) && 95 <= y) && 95 <= x)) || (((90 <= y && y <= 90) && x <= 90) && 90 <= x)) || (((y <= 59 && x <= 59) && 59 <= y) && 59 <= x)) || (85 <= x && (85 <= y && x <= 85) && y <= 85)) || (63 <= x && (y <= 63 && x <= 63) && 63 <= y)) || (((y <= 77 && x <= 77) && 77 <= y) && 77 <= x)) || (53 <= x && (y <= 53 && x <= 53) && 53 <= y)) || (((x <= 79 && y <= 79) && 79 <= y) && 79 <= x)) || (68 <= x && (68 <= y && y <= 68) && x <= 68)) || (51 <= x && (51 <= y && x <= 51) && y <= 51)) || (54 <= x && (x <= 54 && 54 <= y) && y <= 54)) || (((56 <= y && x <= 56) && y <= 56) && 56 <= x)) || (61 <= x && (y <= 61 && 61 <= y) && x <= 61)) || (88 <= x && (x <= 88 && y <= 88) && 88 <= y)) || ((y <= 50 && x <= 50) && 50 <= y)) || (80 <= x && (x <= 80 && 80 <= y) && y <= 80)) || (94 <= x && (x <= 94 && y <= 94) && 94 <= y)) || (89 <= x && (89 <= y && y <= 89) && x <= 89)) || (((86 <= y && x <= 86) && y <= 86) && 86 <= x)) || (58 <= x && (x <= 58 && y <= 58) && 58 <= y)) || (((x <= 91 && 91 <= y) && y <= 91) && 91 <= x)) || (((52 <= y && y <= 52) && x <= 52) && 52 <= x)) || (93 <= x && (x <= 93 && 93 <= y) && y <= 93)) || (74 <= x && (74 <= y && y <= 74) && x <= 74)) || (((y <= 71 && x <= 71) && 71 <= y) && 71 <= x)) || (57 <= x && (57 <= y && x <= 57) && y <= 57)) || (97 <= x && (97 <= y && x <= 97) && y <= 97)) || (((x <= 81 && 81 <= y) && y <= 81) && 81 <= x)) || (84 <= x && (y <= 84 && 84 <= y) && x <= 84)) || (((96 <= y && x <= 96) && y <= 96) && 96 <= x)) || (83 <= x && (y <= 83 && 83 <= y) && x <= 83)) || (62 <= x && (y <= 62 && x <= 62) && 62 <= y)) || (((x <= 98 && y <= 98) && 98 <= y) && 98 <= x)) || (((75 <= y && x <= 75) && y <= 75) && 75 <= x)) || (((82 <= y && y <= 82) && x <= 82) && 82 <= x) - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 20 locations, 1 error locations. SAFE Result, 161.2s OverallTime, 58 OverallIterations, 102 TraceHistogramMax, 16.1s AutomataDifference, 0.0s DeadEndRemovalTime, 4.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 887 SDtfs, 708 SDslu, 15252 SDs, 0 SdLazy, 7859 SolverSat, 1969 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 11.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 33778 GetRequests, 29751 SyntacticMatches, 1526 SemanticMatches, 2501 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 72565 ImplicationChecksByTransitivity, 108.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=315occurred in iteration=57, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.3s AutomataMinimizationTime, 58 MinimizatonAttempts, 3988 StatesRemovedByMinimization, 15 NontrivialMinimizations, HoareAnnotationStatistics: 0.0s HoareAnnotationTime, 7 LocationsWithAnnotation, 64 PreInvPairs, 166 NumberOfFragments, 720 HoareAnnotationTreeSize, 64 FomulaSimplifications, 13400 FormulaSimplificationTreeSizeReduction, 0.8s HoareSimplificationTime, 7 FomulaSimplificationsInter, 200 FormulaSimplificationTreeSizeReductionInter, 3.2s HoareSimplificationTimeInter, RefinementEngineStatistics: TraceCheckStatistics: 0.5s SsaConstructionTime, 19.1s SatisfiabilityAnalysisTime, 116.8s InterpolantComputationTime, 24528 NumberOfCodeBlocks, 23544 NumberOfCodeBlocksAsserted, 2455 NumberOfCheckSat, 40376 ConstructedInterpolants, 0 QuantifiedInterpolants, 18639664 SizeOfPredicates, 58 NumberOfNonLiveVariables, 29976 ConjunctsInSsa, 3252 ConjunctsInUnsatCore, 276 InterpolantComputations, 5 PerfectInterpolantSequences, 700100/1151308 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be correct! Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/gj2007_true-unreach-call_true-termination.c.i_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-Benchmark-0-2018-09-14_15-54-40-544.csv Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/gj2007_true-unreach-call_true-termination.c.i_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-TraceAbstractionBenchmarks-0-2018-09-14_15-54-40-544.csv Received shutdown request...