java -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data --generate-csv --csv-dir csv -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml -s ../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf -i ../../../trunk/examples/svcomp/loop-lit/gr2006_true-unreach-call_true-termination.c.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-dace188-m [2018-09-14 15:52:17,385 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-09-14 15:52:17,388 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-09-14 15:52:17,403 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-09-14 15:52:17,404 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-09-14 15:52:17,405 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-09-14 15:52:17,407 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-09-14 15:52:17,409 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-09-14 15:52:17,412 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-09-14 15:52:17,412 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-09-14 15:52:17,413 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-09-14 15:52:17,414 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-09-14 15:52:17,418 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-09-14 15:52:17,420 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-09-14 15:52:17,423 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-09-14 15:52:17,424 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-09-14 15:52:17,425 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-09-14 15:52:17,429 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-09-14 15:52:17,434 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-09-14 15:52:17,437 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-09-14 15:52:17,440 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-09-14 15:52:17,441 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-09-14 15:52:17,444 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-09-14 15:52:17,444 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-09-14 15:52:17,444 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-09-14 15:52:17,447 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-09-14 15:52:17,448 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-09-14 15:52:17,449 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-09-14 15:52:17,450 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-09-14 15:52:17,452 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-09-14 15:52:17,452 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-09-14 15:52:17,453 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... 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[2018-09-14 15:52:17,458 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf [2018-09-14 15:52:17,482 INFO L110 SettingsManager]: Loading preferences was successful [2018-09-14 15:52:17,482 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-09-14 15:52:17,484 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-09-14 15:52:17,484 INFO L133 SettingsManager]: * User list type=DISABLED [2018-09-14 15:52:17,484 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-09-14 15:52:17,485 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-09-14 15:52:17,485 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-09-14 15:52:17,485 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-09-14 15:52:17,485 INFO L133 SettingsManager]: * Log string format=TERM [2018-09-14 15:52:17,486 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-09-14 15:52:17,486 INFO L133 SettingsManager]: * Interval Domain=false [2018-09-14 15:52:17,487 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-09-14 15:52:17,487 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-09-14 15:52:17,487 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-09-14 15:52:17,488 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-09-14 15:52:17,488 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-09-14 15:52:17,488 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-09-14 15:52:17,488 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-09-14 15:52:17,490 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-09-14 15:52:17,490 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-09-14 15:52:17,490 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-09-14 15:52:17,491 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-09-14 15:52:17,491 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-09-14 15:52:17,491 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-09-14 15:52:17,491 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-09-14 15:52:17,491 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-09-14 15:52:17,492 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-09-14 15:52:17,492 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-09-14 15:52:17,492 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-09-14 15:52:17,492 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-09-14 15:52:17,492 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-09-14 15:52:17,493 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-09-14 15:52:17,493 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-09-14 15:52:17,556 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-09-14 15:52:17,569 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-09-14 15:52:17,576 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-09-14 15:52:17,578 INFO L271 PluginConnector]: Initializing CDTParser... [2018-09-14 15:52:17,578 INFO L276 PluginConnector]: CDTParser initialized [2018-09-14 15:52:17,579 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-lit/gr2006_true-unreach-call_true-termination.c.i [2018-09-14 15:52:17,940 INFO L221 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/93163709a/4ddbcb64d3704764bbb79c95817c3f6f/FLAG5dd9723c7 [2018-09-14 15:52:18,099 INFO L277 CDTParser]: Found 1 translation units. [2018-09-14 15:52:18,100 INFO L159 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-lit/gr2006_true-unreach-call_true-termination.c.i [2018-09-14 15:52:18,106 INFO L325 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/93163709a/4ddbcb64d3704764bbb79c95817c3f6f/FLAG5dd9723c7 [2018-09-14 15:52:18,122 INFO L333 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/93163709a/4ddbcb64d3704764bbb79c95817c3f6f [2018-09-14 15:52:18,133 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-09-14 15:52:18,136 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-09-14 15:52:18,137 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-09-14 15:52:18,137 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-09-14 15:52:18,144 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-09-14 15:52:18,145 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.09 03:52:18" (1/1) ... [2018-09-14 15:52:18,148 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@32853091 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:52:18, skipping insertion in model container [2018-09-14 15:52:18,149 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.09 03:52:18" (1/1) ... [2018-09-14 15:52:18,160 INFO L160 ieTranslatorObserver]: Starting translation in SV-COMP mode [2018-09-14 15:52:18,375 INFO L170 PostProcessor]: Settings: Checked method=main [2018-09-14 15:52:18,397 INFO L424 MainDispatcher]: Starting main dispatcher in SV-COMP mode [2018-09-14 15:52:18,403 INFO L170 PostProcessor]: Settings: Checked method=main [2018-09-14 15:52:18,419 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:52:18 WrapperNode [2018-09-14 15:52:18,419 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-09-14 15:52:18,420 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-09-14 15:52:18,420 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-09-14 15:52:18,420 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-09-14 15:52:18,431 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:52:18" (1/1) ... [2018-09-14 15:52:18,439 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:52:18" (1/1) ... [2018-09-14 15:52:18,446 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-09-14 15:52:18,447 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-09-14 15:52:18,447 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-09-14 15:52:18,447 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-09-14 15:52:18,458 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:52:18" (1/1) ... [2018-09-14 15:52:18,459 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:52:18" (1/1) ... [2018-09-14 15:52:18,464 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:52:18" (1/1) ... [2018-09-14 15:52:18,464 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:52:18" (1/1) ... [2018-09-14 15:52:18,466 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:52:18" (1/1) ... [2018-09-14 15:52:18,473 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:52:18" (1/1) ... [2018-09-14 15:52:18,474 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:52:18" (1/1) ... [2018-09-14 15:52:18,476 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-09-14 15:52:18,483 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-09-14 15:52:18,483 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-09-14 15:52:18,483 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-09-14 15:52:18,484 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:52:18" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-09-14 15:52:18,561 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-09-14 15:52:18,561 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-09-14 15:52:18,561 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-09-14 15:52:18,561 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-09-14 15:52:18,562 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-09-14 15:52:18,562 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-09-14 15:52:18,562 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-09-14 15:52:18,562 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-09-14 15:52:18,995 INFO L353 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-09-14 15:52:18,996 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.09 03:52:18 BoogieIcfgContainer [2018-09-14 15:52:18,997 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-09-14 15:52:19,004 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-09-14 15:52:19,004 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-09-14 15:52:19,016 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-09-14 15:52:19,016 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 14.09 03:52:18" (1/3) ... [2018-09-14 15:52:19,017 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@48e1536e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.09 03:52:19, skipping insertion in model container [2018-09-14 15:52:19,017 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:52:18" (2/3) ... [2018-09-14 15:52:19,018 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@48e1536e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.09 03:52:19, skipping insertion in model container [2018-09-14 15:52:19,018 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.09 03:52:18" (3/3) ... [2018-09-14 15:52:19,026 INFO L112 eAbstractionObserver]: Analyzing ICFG gr2006_true-unreach-call_true-termination.c.i [2018-09-14 15:52:19,041 INFO L137 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-09-14 15:52:19,064 INFO L149 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-09-14 15:52:19,132 INFO L130 ementStrategyFactory]: Using default assertion order modulation [2018-09-14 15:52:19,132 INFO L381 AbstractCegarLoop]: Interprodecural is true [2018-09-14 15:52:19,133 INFO L382 AbstractCegarLoop]: Hoare is true [2018-09-14 15:52:19,133 INFO L383 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-09-14 15:52:19,133 INFO L384 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-09-14 15:52:19,133 INFO L385 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-09-14 15:52:19,133 INFO L386 AbstractCegarLoop]: Difference is false [2018-09-14 15:52:19,133 INFO L387 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-09-14 15:52:19,133 INFO L392 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-09-14 15:52:19,151 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states. [2018-09-14 15:52:19,158 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2018-09-14 15:52:19,158 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:19,159 INFO L376 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:19,160 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:19,166 INFO L82 PathProgramCache]: Analyzing trace with hash -859010367, now seen corresponding path program 1 times [2018-09-14 15:52:19,169 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:19,216 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:19,216 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:19,216 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:19,217 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:19,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:19,273 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:19,275 INFO L313 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-09-14 15:52:19,276 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-09-14 15:52:19,276 INFO L265 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-09-14 15:52:19,281 INFO L459 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-09-14 15:52:19,296 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-09-14 15:52:19,297 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-09-14 15:52:19,300 INFO L87 Difference]: Start difference. First operand 21 states. Second operand 2 states. [2018-09-14 15:52:19,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:19,323 INFO L93 Difference]: Finished difference Result 33 states and 38 transitions. [2018-09-14 15:52:19,323 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-09-14 15:52:19,325 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 10 [2018-09-14 15:52:19,325 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:19,334 INFO L225 Difference]: With dead ends: 33 [2018-09-14 15:52:19,334 INFO L226 Difference]: Without dead ends: 14 [2018-09-14 15:52:19,338 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-09-14 15:52:19,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states. [2018-09-14 15:52:19,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 14. [2018-09-14 15:52:19,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2018-09-14 15:52:19,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 15 transitions. [2018-09-14 15:52:19,380 INFO L78 Accepts]: Start accepts. Automaton has 14 states and 15 transitions. Word has length 10 [2018-09-14 15:52:19,381 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:19,381 INFO L480 AbstractCegarLoop]: Abstraction has 14 states and 15 transitions. [2018-09-14 15:52:19,381 INFO L481 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-09-14 15:52:19,381 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 15 transitions. [2018-09-14 15:52:19,382 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-09-14 15:52:19,382 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:19,382 INFO L376 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:19,383 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:19,383 INFO L82 PathProgramCache]: Analyzing trace with hash 220608140, now seen corresponding path program 1 times [2018-09-14 15:52:19,383 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:19,384 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:19,385 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:19,385 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:19,385 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:19,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:19,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:19,468 INFO L313 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-09-14 15:52:19,468 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-09-14 15:52:19,468 INFO L265 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-09-14 15:52:19,469 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-09-14 15:52:19,470 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-09-14 15:52:19,470 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-09-14 15:52:19,470 INFO L87 Difference]: Start difference. First operand 14 states and 15 transitions. Second operand 4 states. [2018-09-14 15:52:19,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:19,535 INFO L93 Difference]: Finished difference Result 24 states and 27 transitions. [2018-09-14 15:52:19,535 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-09-14 15:52:19,536 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2018-09-14 15:52:19,536 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:19,536 INFO L225 Difference]: With dead ends: 24 [2018-09-14 15:52:19,537 INFO L226 Difference]: Without dead ends: 19 [2018-09-14 15:52:19,537 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-09-14 15:52:19,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2018-09-14 15:52:19,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 19. [2018-09-14 15:52:19,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19 states. [2018-09-14 15:52:19,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 21 transitions. [2018-09-14 15:52:19,543 INFO L78 Accepts]: Start accepts. Automaton has 19 states and 21 transitions. Word has length 13 [2018-09-14 15:52:19,543 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:19,543 INFO L480 AbstractCegarLoop]: Abstraction has 19 states and 21 transitions. [2018-09-14 15:52:19,543 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-09-14 15:52:19,544 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 21 transitions. [2018-09-14 15:52:19,544 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-09-14 15:52:19,544 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:19,545 INFO L376 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:19,545 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:19,545 INFO L82 PathProgramCache]: Analyzing trace with hash 277866442, now seen corresponding path program 1 times [2018-09-14 15:52:19,545 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:19,546 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:19,547 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:19,547 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:19,547 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:19,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:19,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:19,572 INFO L313 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-09-14 15:52:19,572 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-09-14 15:52:19,572 INFO L265 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-09-14 15:52:19,574 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-09-14 15:52:19,574 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-09-14 15:52:19,575 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-09-14 15:52:19,575 INFO L87 Difference]: Start difference. First operand 19 states and 21 transitions. Second operand 3 states. [2018-09-14 15:52:19,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:19,608 INFO L93 Difference]: Finished difference Result 37 states and 42 transitions. [2018-09-14 15:52:19,610 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-09-14 15:52:19,610 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 13 [2018-09-14 15:52:19,610 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:19,611 INFO L225 Difference]: With dead ends: 37 [2018-09-14 15:52:19,611 INFO L226 Difference]: Without dead ends: 23 [2018-09-14 15:52:19,612 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-09-14 15:52:19,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states. [2018-09-14 15:52:19,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 22. [2018-09-14 15:52:19,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2018-09-14 15:52:19,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 24 transitions. [2018-09-14 15:52:19,617 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 24 transitions. Word has length 13 [2018-09-14 15:52:19,618 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:19,618 INFO L480 AbstractCegarLoop]: Abstraction has 22 states and 24 transitions. [2018-09-14 15:52:19,618 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-09-14 15:52:19,618 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 24 transitions. [2018-09-14 15:52:19,619 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-09-14 15:52:19,619 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:19,619 INFO L376 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:19,620 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:19,620 INFO L82 PathProgramCache]: Analyzing trace with hash 1383636324, now seen corresponding path program 1 times [2018-09-14 15:52:19,620 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:19,621 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:19,621 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:19,621 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:19,622 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:19,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:19,696 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:19,696 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:19,696 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:19,714 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:19,715 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:19,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:19,751 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:19,775 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:19,775 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:19,849 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:19,880 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:19,880 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:19,910 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:19,910 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:19,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:19,943 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:19,952 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:19,952 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:20,005 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:20,007 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:20,007 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 6 [2018-09-14 15:52:20,007 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:20,008 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-09-14 15:52:20,008 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-09-14 15:52:20,008 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-09-14 15:52:20,012 INFO L87 Difference]: Start difference. First operand 22 states and 24 transitions. Second operand 4 states. [2018-09-14 15:52:20,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:20,100 INFO L93 Difference]: Finished difference Result 41 states and 46 transitions. [2018-09-14 15:52:20,101 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-09-14 15:52:20,101 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 21 [2018-09-14 15:52:20,102 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:20,102 INFO L225 Difference]: With dead ends: 41 [2018-09-14 15:52:20,103 INFO L226 Difference]: Without dead ends: 27 [2018-09-14 15:52:20,104 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 86 GetRequests, 82 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-09-14 15:52:20,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states. [2018-09-14 15:52:20,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 26. [2018-09-14 15:52:20,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2018-09-14 15:52:20,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 28 transitions. [2018-09-14 15:52:20,113 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 28 transitions. Word has length 21 [2018-09-14 15:52:20,113 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:20,113 INFO L480 AbstractCegarLoop]: Abstraction has 26 states and 28 transitions. [2018-09-14 15:52:20,113 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-09-14 15:52:20,113 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 28 transitions. [2018-09-14 15:52:20,114 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-09-14 15:52:20,116 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:20,116 INFO L376 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:20,116 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:20,117 INFO L82 PathProgramCache]: Analyzing trace with hash -1112171374, now seen corresponding path program 2 times [2018-09-14 15:52:20,117 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:20,119 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:20,119 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:20,122 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:20,122 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:20,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:20,304 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 13 proven. 10 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:20,305 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:20,305 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:20,319 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:20,320 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:20,354 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:20,354 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:20,356 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:20,366 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 13 proven. 10 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:20,367 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:20,495 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 13 proven. 10 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:20,516 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:20,516 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:20,532 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:20,532 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:20,553 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:20,554 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:20,557 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:20,563 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 13 proven. 10 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:20,564 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:20,626 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 13 proven. 10 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:20,629 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:20,629 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 8 [2018-09-14 15:52:20,629 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:20,629 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-09-14 15:52:20,630 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-09-14 15:52:20,630 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-09-14 15:52:20,630 INFO L87 Difference]: Start difference. First operand 26 states and 28 transitions. Second operand 5 states. [2018-09-14 15:52:20,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:20,677 INFO L93 Difference]: Finished difference Result 45 states and 50 transitions. [2018-09-14 15:52:20,677 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-09-14 15:52:20,677 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 25 [2018-09-14 15:52:20,678 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:20,678 INFO L225 Difference]: With dead ends: 45 [2018-09-14 15:52:20,679 INFO L226 Difference]: Without dead ends: 31 [2018-09-14 15:52:20,680 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 103 GetRequests, 97 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-09-14 15:52:20,680 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2018-09-14 15:52:20,684 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 30. [2018-09-14 15:52:20,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-09-14 15:52:20,685 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 32 transitions. [2018-09-14 15:52:20,685 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 32 transitions. Word has length 25 [2018-09-14 15:52:20,686 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:20,686 INFO L480 AbstractCegarLoop]: Abstraction has 30 states and 32 transitions. [2018-09-14 15:52:20,686 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-09-14 15:52:20,686 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 32 transitions. [2018-09-14 15:52:20,687 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-09-14 15:52:20,687 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:20,687 INFO L376 BasicCegarLoop]: trace histogram [5, 5, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:20,688 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:20,688 INFO L82 PathProgramCache]: Analyzing trace with hash 920868032, now seen corresponding path program 3 times [2018-09-14 15:52:20,688 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:20,689 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:20,690 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:20,690 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:20,690 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:20,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:20,827 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 18 proven. 21 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:20,828 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:20,828 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:20,844 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:20,844 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:20,926 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2018-09-14 15:52:20,927 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:20,929 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:20,937 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 18 proven. 21 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:20,937 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:21,130 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 18 proven. 21 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:21,151 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:21,151 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:21,169 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:21,169 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:21,202 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2018-09-14 15:52:21,202 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:21,206 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:21,213 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 18 proven. 21 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:21,213 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:21,238 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 18 proven. 21 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:21,239 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:21,239 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 10 [2018-09-14 15:52:21,240 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:21,240 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-09-14 15:52:21,240 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-09-14 15:52:21,241 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-09-14 15:52:21,241 INFO L87 Difference]: Start difference. First operand 30 states and 32 transitions. Second operand 6 states. [2018-09-14 15:52:21,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:21,288 INFO L93 Difference]: Finished difference Result 49 states and 54 transitions. [2018-09-14 15:52:21,292 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-09-14 15:52:21,292 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 29 [2018-09-14 15:52:21,293 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:21,293 INFO L225 Difference]: With dead ends: 49 [2018-09-14 15:52:21,293 INFO L226 Difference]: Without dead ends: 35 [2018-09-14 15:52:21,294 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 120 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-09-14 15:52:21,294 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states. [2018-09-14 15:52:21,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 34. [2018-09-14 15:52:21,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34 states. [2018-09-14 15:52:21,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 36 transitions. [2018-09-14 15:52:21,300 INFO L78 Accepts]: Start accepts. Automaton has 34 states and 36 transitions. Word has length 29 [2018-09-14 15:52:21,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:21,300 INFO L480 AbstractCegarLoop]: Abstraction has 34 states and 36 transitions. [2018-09-14 15:52:21,301 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-09-14 15:52:21,301 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 36 transitions. [2018-09-14 15:52:21,302 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-09-14 15:52:21,302 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:21,302 INFO L376 BasicCegarLoop]: trace histogram [6, 6, 5, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:21,302 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:21,302 INFO L82 PathProgramCache]: Analyzing trace with hash 1962755566, now seen corresponding path program 4 times [2018-09-14 15:52:21,302 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:21,303 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:21,303 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:21,304 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:21,304 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:21,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:21,406 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 23 proven. 36 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:21,407 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:21,407 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:21,416 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:21,416 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:21,454 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:21,455 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:21,457 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:21,465 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 23 proven. 36 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:21,465 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:21,848 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 23 proven. 36 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:21,869 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:21,870 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:21,885 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:21,886 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:21,911 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:21,911 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:21,915 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:21,921 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 23 proven. 36 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:21,922 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:21,940 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 23 proven. 36 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:21,942 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:21,942 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 12 [2018-09-14 15:52:21,942 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:21,943 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-09-14 15:52:21,943 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-09-14 15:52:21,943 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-09-14 15:52:21,944 INFO L87 Difference]: Start difference. First operand 34 states and 36 transitions. Second operand 7 states. [2018-09-14 15:52:21,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:21,993 INFO L93 Difference]: Finished difference Result 53 states and 58 transitions. [2018-09-14 15:52:21,994 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-09-14 15:52:21,994 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 33 [2018-09-14 15:52:21,994 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:21,995 INFO L225 Difference]: With dead ends: 53 [2018-09-14 15:52:21,995 INFO L226 Difference]: Without dead ends: 39 [2018-09-14 15:52:21,996 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 137 GetRequests, 127 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-09-14 15:52:21,996 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states. [2018-09-14 15:52:22,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 38. [2018-09-14 15:52:22,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2018-09-14 15:52:22,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 40 transitions. [2018-09-14 15:52:22,001 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 40 transitions. Word has length 33 [2018-09-14 15:52:22,002 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:22,002 INFO L480 AbstractCegarLoop]: Abstraction has 38 states and 40 transitions. [2018-09-14 15:52:22,002 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-09-14 15:52:22,002 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 40 transitions. [2018-09-14 15:52:22,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-09-14 15:52:22,003 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:22,004 INFO L376 BasicCegarLoop]: trace histogram [7, 7, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:22,004 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:22,004 INFO L82 PathProgramCache]: Analyzing trace with hash 1161752604, now seen corresponding path program 5 times [2018-09-14 15:52:22,004 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:22,005 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:22,005 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:22,005 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:22,006 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:22,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:22,158 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 28 proven. 55 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:22,159 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:22,159 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:22,166 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:22,167 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:22,197 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-09-14 15:52:22,198 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:22,200 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:22,208 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 28 proven. 55 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:22,208 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:22,361 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 28 proven. 55 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:22,381 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:22,381 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:22,398 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:22,399 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:22,441 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-09-14 15:52:22,441 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:22,445 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:22,453 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 28 proven. 55 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:22,453 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:22,490 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 28 proven. 55 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:22,493 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:22,493 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 14 [2018-09-14 15:52:22,493 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:22,494 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-09-14 15:52:22,494 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-09-14 15:52:22,495 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-09-14 15:52:22,495 INFO L87 Difference]: Start difference. First operand 38 states and 40 transitions. Second operand 8 states. [2018-09-14 15:52:22,575 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:22,576 INFO L93 Difference]: Finished difference Result 57 states and 62 transitions. [2018-09-14 15:52:22,577 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-09-14 15:52:22,577 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 37 [2018-09-14 15:52:22,577 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:22,578 INFO L225 Difference]: With dead ends: 57 [2018-09-14 15:52:22,578 INFO L226 Difference]: Without dead ends: 43 [2018-09-14 15:52:22,578 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 154 GetRequests, 142 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-09-14 15:52:22,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2018-09-14 15:52:22,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 42. [2018-09-14 15:52:22,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2018-09-14 15:52:22,584 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 44 transitions. [2018-09-14 15:52:22,584 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 44 transitions. Word has length 37 [2018-09-14 15:52:22,584 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:22,584 INFO L480 AbstractCegarLoop]: Abstraction has 42 states and 44 transitions. [2018-09-14 15:52:22,585 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-09-14 15:52:22,585 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 44 transitions. [2018-09-14 15:52:22,586 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-09-14 15:52:22,586 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:22,586 INFO L376 BasicCegarLoop]: trace histogram [8, 8, 7, 6, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:22,586 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:22,586 INFO L82 PathProgramCache]: Analyzing trace with hash 1797509962, now seen corresponding path program 6 times [2018-09-14 15:52:22,587 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:22,587 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:22,588 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:22,588 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:22,588 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:22,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:22,713 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 33 proven. 78 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:22,713 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:22,713 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:22,721 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:22,721 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:22,749 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-09-14 15:52:22,750 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:22,752 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:22,928 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 100 proven. 7 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-09-14 15:52:22,928 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:23,237 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 100 proven. 7 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-09-14 15:52:23,257 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:23,257 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:23,275 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:23,275 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:23,336 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-09-14 15:52:23,337 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:23,341 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:23,348 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 33 proven. 78 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:23,348 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:23,504 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 33 proven. 78 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:52:23,506 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:23,506 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 27 [2018-09-14 15:52:23,506 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:23,507 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-09-14 15:52:23,507 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-09-14 15:52:23,508 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=197, Invalid=505, Unknown=0, NotChecked=0, Total=702 [2018-09-14 15:52:23,508 INFO L87 Difference]: Start difference. First operand 42 states and 44 transitions. Second operand 16 states. [2018-09-14 15:52:23,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:23,929 INFO L93 Difference]: Finished difference Result 106 states and 126 transitions. [2018-09-14 15:52:23,929 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-09-14 15:52:23,929 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 41 [2018-09-14 15:52:23,930 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:23,931 INFO L225 Difference]: With dead ends: 106 [2018-09-14 15:52:23,931 INFO L226 Difference]: Without dead ends: 92 [2018-09-14 15:52:23,932 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 184 GetRequests, 142 SyntacticMatches, 4 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 325 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=488, Invalid=1072, Unknown=0, NotChecked=0, Total=1560 [2018-09-14 15:52:23,933 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92 states. [2018-09-14 15:52:23,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92 to 66. [2018-09-14 15:52:23,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-09-14 15:52:23,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 73 transitions. [2018-09-14 15:52:23,949 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 73 transitions. Word has length 41 [2018-09-14 15:52:23,950 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:23,950 INFO L480 AbstractCegarLoop]: Abstraction has 66 states and 73 transitions. [2018-09-14 15:52:23,950 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-09-14 15:52:23,950 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 73 transitions. [2018-09-14 15:52:23,951 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-09-14 15:52:23,951 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:23,952 INFO L376 BasicCegarLoop]: trace histogram [14, 14, 13, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:23,952 INFO L423 AbstractCegarLoop]: === Iteration 10 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:23,952 INFO L82 PathProgramCache]: Analyzing trace with hash 710909332, now seen corresponding path program 7 times [2018-09-14 15:52:23,953 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:23,953 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:23,954 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:23,954 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:23,954 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:23,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:24,103 INFO L134 CoverageAnalysis]: Checked inductivity of 364 backedges. 193 proven. 105 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2018-09-14 15:52:24,103 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:24,103 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:24,113 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:24,113 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:24,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:24,137 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:24,149 INFO L134 CoverageAnalysis]: Checked inductivity of 364 backedges. 193 proven. 105 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2018-09-14 15:52:24,149 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:24,324 INFO L134 CoverageAnalysis]: Checked inductivity of 364 backedges. 193 proven. 105 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2018-09-14 15:52:24,345 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:24,345 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:24,365 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:24,365 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:24,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:24,408 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:24,420 INFO L134 CoverageAnalysis]: Checked inductivity of 364 backedges. 193 proven. 105 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2018-09-14 15:52:24,420 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:24,489 INFO L134 CoverageAnalysis]: Checked inductivity of 364 backedges. 193 proven. 105 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (15)] Exception during sending of exit command (exit): Broken pipe [2018-09-14 15:52:24,494 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:24,494 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 18 [2018-09-14 15:52:24,494 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:24,495 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-09-14 15:52:24,495 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-09-14 15:52:24,495 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-09-14 15:52:24,496 INFO L87 Difference]: Start difference. First operand 66 states and 73 transitions. Second operand 10 states. [2018-09-14 15:52:24,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:24,707 INFO L93 Difference]: Finished difference Result 105 states and 120 transitions. [2018-09-14 15:52:24,708 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-09-14 15:52:24,708 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 65 [2018-09-14 15:52:24,708 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:24,709 INFO L225 Difference]: With dead ends: 105 [2018-09-14 15:52:24,709 INFO L226 Difference]: Without dead ends: 71 [2018-09-14 15:52:24,710 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 268 GetRequests, 252 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-09-14 15:52:24,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states. [2018-09-14 15:52:24,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 70. [2018-09-14 15:52:24,716 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-09-14 15:52:24,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 77 transitions. [2018-09-14 15:52:24,717 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 77 transitions. Word has length 65 [2018-09-14 15:52:24,718 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:24,718 INFO L480 AbstractCegarLoop]: Abstraction has 70 states and 77 transitions. [2018-09-14 15:52:24,718 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-09-14 15:52:24,718 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 77 transitions. [2018-09-14 15:52:24,719 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-09-14 15:52:24,719 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:24,719 INFO L376 BasicCegarLoop]: trace histogram [15, 15, 14, 8, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:24,720 INFO L423 AbstractCegarLoop]: === Iteration 11 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:24,720 INFO L82 PathProgramCache]: Analyzing trace with hash -1774383166, now seen corresponding path program 8 times [2018-09-14 15:52:24,720 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:24,721 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:24,721 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:24,721 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:24,721 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:24,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:24,852 INFO L134 CoverageAnalysis]: Checked inductivity of 420 backedges. 218 proven. 136 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2018-09-14 15:52:24,852 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:24,852 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:24,861 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:24,861 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:24,888 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:24,889 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:24,890 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:24,900 INFO L134 CoverageAnalysis]: Checked inductivity of 420 backedges. 218 proven. 136 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2018-09-14 15:52:24,901 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:25,607 INFO L134 CoverageAnalysis]: Checked inductivity of 420 backedges. 218 proven. 136 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2018-09-14 15:52:25,640 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:25,640 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:25,658 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:25,658 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:25,702 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:25,702 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:25,707 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:25,720 INFO L134 CoverageAnalysis]: Checked inductivity of 420 backedges. 218 proven. 136 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2018-09-14 15:52:25,720 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:25,785 INFO L134 CoverageAnalysis]: Checked inductivity of 420 backedges. 218 proven. 136 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2018-09-14 15:52:25,788 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:25,789 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 20 [2018-09-14 15:52:25,789 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:25,790 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-09-14 15:52:25,790 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-09-14 15:52:25,790 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-09-14 15:52:25,791 INFO L87 Difference]: Start difference. First operand 70 states and 77 transitions. Second operand 11 states. [2018-09-14 15:52:25,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:25,895 INFO L93 Difference]: Finished difference Result 109 states and 124 transitions. [2018-09-14 15:52:25,898 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-09-14 15:52:25,898 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 69 [2018-09-14 15:52:25,898 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:25,899 INFO L225 Difference]: With dead ends: 109 [2018-09-14 15:52:25,899 INFO L226 Difference]: Without dead ends: 75 [2018-09-14 15:52:25,900 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 285 GetRequests, 267 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-09-14 15:52:25,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states. [2018-09-14 15:52:25,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 74. [2018-09-14 15:52:25,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-09-14 15:52:25,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 81 transitions. [2018-09-14 15:52:25,908 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 81 transitions. Word has length 69 [2018-09-14 15:52:25,908 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:25,908 INFO L480 AbstractCegarLoop]: Abstraction has 74 states and 81 transitions. [2018-09-14 15:52:25,909 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-09-14 15:52:25,909 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 81 transitions. [2018-09-14 15:52:25,910 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-09-14 15:52:25,910 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:25,910 INFO L376 BasicCegarLoop]: trace histogram [16, 16, 15, 9, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:25,910 INFO L423 AbstractCegarLoop]: === Iteration 12 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:25,911 INFO L82 PathProgramCache]: Analyzing trace with hash 345619184, now seen corresponding path program 9 times [2018-09-14 15:52:25,911 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:25,912 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:25,912 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:25,912 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:25,912 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:25,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:26,110 INFO L134 CoverageAnalysis]: Checked inductivity of 480 backedges. 243 proven. 171 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2018-09-14 15:52:26,111 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:26,111 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:26,122 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:26,122 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:26,266 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-09-14 15:52:26,266 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:26,268 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:26,574 INFO L134 CoverageAnalysis]: Checked inductivity of 480 backedges. 298 proven. 157 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-09-14 15:52:26,575 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:26,942 INFO L134 CoverageAnalysis]: Checked inductivity of 480 backedges. 298 proven. 157 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-09-14 15:52:26,962 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:26,962 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:26,978 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:26,978 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:27,104 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-09-14 15:52:27,104 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:27,108 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:27,118 INFO L134 CoverageAnalysis]: Checked inductivity of 480 backedges. 243 proven. 171 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2018-09-14 15:52:27,118 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:27,495 INFO L134 CoverageAnalysis]: Checked inductivity of 480 backedges. 243 proven. 171 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2018-09-14 15:52:27,497 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:27,497 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 34 [2018-09-14 15:52:27,498 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:27,498 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-09-14 15:52:27,498 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-09-14 15:52:27,499 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-09-14 15:52:27,499 INFO L87 Difference]: Start difference. First operand 74 states and 81 transitions. Second operand 22 states. [2018-09-14 15:52:27,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:27,849 INFO L93 Difference]: Finished difference Result 200 states and 239 transitions. [2018-09-14 15:52:27,849 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-09-14 15:52:27,849 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 73 [2018-09-14 15:52:27,849 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:27,850 INFO L225 Difference]: With dead ends: 200 [2018-09-14 15:52:27,851 INFO L226 Difference]: Without dead ends: 166 [2018-09-14 15:52:27,852 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 321 GetRequests, 256 SyntacticMatches, 14 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 683 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=823, Invalid=1933, Unknown=0, NotChecked=0, Total=2756 [2018-09-14 15:52:27,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166 states. [2018-09-14 15:52:27,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166 to 90. [2018-09-14 15:52:27,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. [2018-09-14 15:52:27,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 100 transitions. [2018-09-14 15:52:27,862 INFO L78 Accepts]: Start accepts. Automaton has 90 states and 100 transitions. Word has length 73 [2018-09-14 15:52:27,863 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:27,863 INFO L480 AbstractCegarLoop]: Abstraction has 90 states and 100 transitions. [2018-09-14 15:52:27,863 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-09-14 15:52:27,863 INFO L276 IsEmpty]: Start isEmpty. Operand 90 states and 100 transitions. [2018-09-14 15:52:27,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-09-14 15:52:27,864 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:27,865 INFO L376 BasicCegarLoop]: trace histogram [20, 20, 19, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:27,865 INFO L423 AbstractCegarLoop]: === Iteration 13 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:27,865 INFO L82 PathProgramCache]: Analyzing trace with hash -350630558, now seen corresponding path program 10 times [2018-09-14 15:52:27,865 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:27,866 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:27,866 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:27,866 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:27,866 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:27,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:28,029 INFO L134 CoverageAnalysis]: Checked inductivity of 760 backedges. 397 proven. 210 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:28,029 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:28,029 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:28,038 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:28,038 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:28,080 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:28,081 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:28,083 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:28,094 INFO L134 CoverageAnalysis]: Checked inductivity of 760 backedges. 397 proven. 210 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:28,094 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:28,344 INFO L134 CoverageAnalysis]: Checked inductivity of 760 backedges. 397 proven. 210 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:28,367 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:28,367 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:28,383 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:28,383 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:28,440 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:28,440 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:28,444 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:28,457 INFO L134 CoverageAnalysis]: Checked inductivity of 760 backedges. 397 proven. 210 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:28,458 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:28,474 INFO L134 CoverageAnalysis]: Checked inductivity of 760 backedges. 397 proven. 210 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:28,475 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:28,476 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 24 [2018-09-14 15:52:28,476 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:28,476 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-09-14 15:52:28,476 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-09-14 15:52:28,477 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-09-14 15:52:28,477 INFO L87 Difference]: Start difference. First operand 90 states and 100 transitions. Second operand 13 states. [2018-09-14 15:52:28,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:28,539 INFO L93 Difference]: Finished difference Result 141 states and 162 transitions. [2018-09-14 15:52:28,539 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-09-14 15:52:28,539 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 89 [2018-09-14 15:52:28,540 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:28,540 INFO L225 Difference]: With dead ends: 141 [2018-09-14 15:52:28,540 INFO L226 Difference]: Without dead ends: 95 [2018-09-14 15:52:28,541 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 367 GetRequests, 345 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-09-14 15:52:28,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states. [2018-09-14 15:52:28,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 94. [2018-09-14 15:52:28,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2018-09-14 15:52:28,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 104 transitions. [2018-09-14 15:52:28,551 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 104 transitions. Word has length 89 [2018-09-14 15:52:28,551 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:28,551 INFO L480 AbstractCegarLoop]: Abstraction has 94 states and 104 transitions. [2018-09-14 15:52:28,551 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-09-14 15:52:28,551 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 104 transitions. [2018-09-14 15:52:28,552 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-09-14 15:52:28,552 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:28,553 INFO L376 BasicCegarLoop]: trace histogram [21, 21, 20, 11, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:28,553 INFO L423 AbstractCegarLoop]: === Iteration 14 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:28,553 INFO L82 PathProgramCache]: Analyzing trace with hash 317658512, now seen corresponding path program 11 times [2018-09-14 15:52:28,553 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:28,554 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:28,554 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:28,554 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:28,554 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:28,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:28,724 INFO L134 CoverageAnalysis]: Checked inductivity of 840 backedges. 434 proven. 253 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:28,725 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:28,725 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:28,732 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:28,732 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:28,766 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 21 check-sat command(s) [2018-09-14 15:52:28,766 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:28,768 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:28,781 INFO L134 CoverageAnalysis]: Checked inductivity of 840 backedges. 434 proven. 253 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:28,781 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:29,261 INFO L134 CoverageAnalysis]: Checked inductivity of 840 backedges. 434 proven. 253 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:29,282 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:29,283 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:29,297 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:29,297 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:29,468 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 21 check-sat command(s) [2018-09-14 15:52:29,468 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:29,472 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:29,482 INFO L134 CoverageAnalysis]: Checked inductivity of 840 backedges. 434 proven. 253 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:29,482 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:29,508 INFO L134 CoverageAnalysis]: Checked inductivity of 840 backedges. 434 proven. 253 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:29,509 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:29,510 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 26 [2018-09-14 15:52:29,510 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:29,510 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-09-14 15:52:29,510 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-09-14 15:52:29,511 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-09-14 15:52:29,511 INFO L87 Difference]: Start difference. First operand 94 states and 104 transitions. Second operand 14 states. [2018-09-14 15:52:29,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:29,566 INFO L93 Difference]: Finished difference Result 145 states and 166 transitions. [2018-09-14 15:52:29,566 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-09-14 15:52:29,566 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 93 [2018-09-14 15:52:29,567 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:29,567 INFO L225 Difference]: With dead ends: 145 [2018-09-14 15:52:29,567 INFO L226 Difference]: Without dead ends: 99 [2018-09-14 15:52:29,568 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 384 GetRequests, 360 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-09-14 15:52:29,568 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states. [2018-09-14 15:52:29,574 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 98. [2018-09-14 15:52:29,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 98 states. [2018-09-14 15:52:29,575 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 108 transitions. [2018-09-14 15:52:29,575 INFO L78 Accepts]: Start accepts. Automaton has 98 states and 108 transitions. Word has length 93 [2018-09-14 15:52:29,576 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:29,576 INFO L480 AbstractCegarLoop]: Abstraction has 98 states and 108 transitions. [2018-09-14 15:52:29,576 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-09-14 15:52:29,576 INFO L276 IsEmpty]: Start isEmpty. Operand 98 states and 108 transitions. [2018-09-14 15:52:29,577 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-09-14 15:52:29,577 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:29,578 INFO L376 BasicCegarLoop]: trace histogram [22, 22, 21, 12, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:29,578 INFO L423 AbstractCegarLoop]: === Iteration 15 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:29,578 INFO L82 PathProgramCache]: Analyzing trace with hash 1097373374, now seen corresponding path program 12 times [2018-09-14 15:52:29,578 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:29,579 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:29,579 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:29,579 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:29,579 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:29,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:29,751 INFO L134 CoverageAnalysis]: Checked inductivity of 924 backedges. 471 proven. 300 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:29,752 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:29,752 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:29,760 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:29,760 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:29,794 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 20 check-sat command(s) [2018-09-14 15:52:29,794 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:29,796 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:29,807 INFO L134 CoverageAnalysis]: Checked inductivity of 924 backedges. 471 proven. 300 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:29,807 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:30,060 INFO L134 CoverageAnalysis]: Checked inductivity of 924 backedges. 471 proven. 300 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:30,081 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:30,082 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:30,097 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:30,097 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:30,260 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 20 check-sat command(s) [2018-09-14 15:52:30,260 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:30,264 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:30,282 INFO L134 CoverageAnalysis]: Checked inductivity of 924 backedges. 471 proven. 300 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:30,282 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:30,321 INFO L134 CoverageAnalysis]: Checked inductivity of 924 backedges. 471 proven. 300 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:30,322 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:30,323 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 28 [2018-09-14 15:52:30,323 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:30,323 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-09-14 15:52:30,324 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-09-14 15:52:30,324 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-09-14 15:52:30,324 INFO L87 Difference]: Start difference. First operand 98 states and 108 transitions. Second operand 15 states. [2018-09-14 15:52:30,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:30,386 INFO L93 Difference]: Finished difference Result 149 states and 170 transitions. [2018-09-14 15:52:30,386 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-09-14 15:52:30,386 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 97 [2018-09-14 15:52:30,386 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:30,387 INFO L225 Difference]: With dead ends: 149 [2018-09-14 15:52:30,387 INFO L226 Difference]: Without dead ends: 103 [2018-09-14 15:52:30,389 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 401 GetRequests, 375 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-09-14 15:52:30,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states. [2018-09-14 15:52:30,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 102. [2018-09-14 15:52:30,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-09-14 15:52:30,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 112 transitions. [2018-09-14 15:52:30,400 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 112 transitions. Word has length 97 [2018-09-14 15:52:30,400 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:30,400 INFO L480 AbstractCegarLoop]: Abstraction has 102 states and 112 transitions. [2018-09-14 15:52:30,400 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-09-14 15:52:30,400 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 112 transitions. [2018-09-14 15:52:30,402 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2018-09-14 15:52:30,402 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:30,402 INFO L376 BasicCegarLoop]: trace histogram [23, 23, 22, 13, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:30,402 INFO L423 AbstractCegarLoop]: === Iteration 16 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:30,402 INFO L82 PathProgramCache]: Analyzing trace with hash -1480470292, now seen corresponding path program 13 times [2018-09-14 15:52:30,403 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:30,404 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:30,404 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:30,404 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:30,405 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:30,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:30,746 INFO L134 CoverageAnalysis]: Checked inductivity of 1012 backedges. 508 proven. 351 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:30,746 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:30,746 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:30,754 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:30,754 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:30,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:30,789 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:30,809 INFO L134 CoverageAnalysis]: Checked inductivity of 1012 backedges. 508 proven. 351 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:30,809 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:31,214 INFO L134 CoverageAnalysis]: Checked inductivity of 1012 backedges. 508 proven. 351 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:31,236 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:31,236 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:31,254 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:31,254 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:31,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:31,313 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:31,323 INFO L134 CoverageAnalysis]: Checked inductivity of 1012 backedges. 508 proven. 351 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:31,323 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:31,369 INFO L134 CoverageAnalysis]: Checked inductivity of 1012 backedges. 508 proven. 351 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:31,370 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:31,371 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 30 [2018-09-14 15:52:31,371 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:31,371 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-09-14 15:52:31,372 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-09-14 15:52:31,372 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-09-14 15:52:31,372 INFO L87 Difference]: Start difference. First operand 102 states and 112 transitions. Second operand 16 states. [2018-09-14 15:52:31,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:31,505 INFO L93 Difference]: Finished difference Result 153 states and 174 transitions. [2018-09-14 15:52:31,505 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-09-14 15:52:31,506 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 101 [2018-09-14 15:52:31,506 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:31,506 INFO L225 Difference]: With dead ends: 153 [2018-09-14 15:52:31,506 INFO L226 Difference]: Without dead ends: 107 [2018-09-14 15:52:31,507 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 418 GetRequests, 390 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-09-14 15:52:31,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-09-14 15:52:31,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 106. [2018-09-14 15:52:31,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2018-09-14 15:52:31,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 116 transitions. [2018-09-14 15:52:31,513 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 116 transitions. Word has length 101 [2018-09-14 15:52:31,514 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:31,514 INFO L480 AbstractCegarLoop]: Abstraction has 106 states and 116 transitions. [2018-09-14 15:52:31,514 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-09-14 15:52:31,514 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 116 transitions. [2018-09-14 15:52:31,515 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-09-14 15:52:31,515 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:31,515 INFO L376 BasicCegarLoop]: trace histogram [24, 24, 23, 14, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:31,516 INFO L423 AbstractCegarLoop]: === Iteration 17 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:31,516 INFO L82 PathProgramCache]: Analyzing trace with hash 1836467226, now seen corresponding path program 14 times [2018-09-14 15:52:31,516 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:31,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:31,517 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:31,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:31,517 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:31,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:31,710 INFO L134 CoverageAnalysis]: Checked inductivity of 1104 backedges. 545 proven. 406 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:31,711 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:31,711 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:31,718 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:31,719 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:31,757 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:31,758 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:31,760 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:31,774 INFO L134 CoverageAnalysis]: Checked inductivity of 1104 backedges. 545 proven. 406 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:31,775 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:32,132 INFO L134 CoverageAnalysis]: Checked inductivity of 1104 backedges. 545 proven. 406 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:32,152 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:32,152 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:32,167 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:32,167 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:32,228 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:32,228 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:32,233 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:32,247 INFO L134 CoverageAnalysis]: Checked inductivity of 1104 backedges. 545 proven. 406 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:32,248 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:32,308 INFO L134 CoverageAnalysis]: Checked inductivity of 1104 backedges. 545 proven. 406 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:32,310 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:32,310 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 32 [2018-09-14 15:52:32,310 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:32,311 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-09-14 15:52:32,311 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-09-14 15:52:32,311 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-09-14 15:52:32,312 INFO L87 Difference]: Start difference. First operand 106 states and 116 transitions. Second operand 17 states. [2018-09-14 15:52:32,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:32,407 INFO L93 Difference]: Finished difference Result 157 states and 178 transitions. [2018-09-14 15:52:32,407 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-09-14 15:52:32,407 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 105 [2018-09-14 15:52:32,407 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:32,408 INFO L225 Difference]: With dead ends: 157 [2018-09-14 15:52:32,408 INFO L226 Difference]: Without dead ends: 111 [2018-09-14 15:52:32,409 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 435 GetRequests, 405 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-09-14 15:52:32,409 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2018-09-14 15:52:32,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 110. [2018-09-14 15:52:32,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110 states. [2018-09-14 15:52:32,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 120 transitions. [2018-09-14 15:52:32,414 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 120 transitions. Word has length 105 [2018-09-14 15:52:32,414 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:32,414 INFO L480 AbstractCegarLoop]: Abstraction has 110 states and 120 transitions. [2018-09-14 15:52:32,414 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-09-14 15:52:32,414 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 120 transitions. [2018-09-14 15:52:32,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-09-14 15:52:32,415 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:32,416 INFO L376 BasicCegarLoop]: trace histogram [25, 25, 24, 15, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:32,416 INFO L423 AbstractCegarLoop]: === Iteration 18 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:32,416 INFO L82 PathProgramCache]: Analyzing trace with hash -1874759608, now seen corresponding path program 15 times [2018-09-14 15:52:32,416 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:32,417 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:32,417 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:32,417 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:32,417 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:32,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:32,825 INFO L134 CoverageAnalysis]: Checked inductivity of 1200 backedges. 582 proven. 465 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:32,825 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:32,825 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:32,832 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:32,833 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:32,869 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 25 check-sat command(s) [2018-09-14 15:52:32,870 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:32,872 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:32,887 INFO L134 CoverageAnalysis]: Checked inductivity of 1200 backedges. 582 proven. 465 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:32,887 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:33,485 INFO L134 CoverageAnalysis]: Checked inductivity of 1200 backedges. 582 proven. 465 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:33,505 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:33,505 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:33,520 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:33,520 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:33,749 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 25 check-sat command(s) [2018-09-14 15:52:33,749 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:33,753 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:33,768 INFO L134 CoverageAnalysis]: Checked inductivity of 1200 backedges. 582 proven. 465 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:33,768 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:33,802 INFO L134 CoverageAnalysis]: Checked inductivity of 1200 backedges. 582 proven. 465 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:33,804 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:33,804 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 34 [2018-09-14 15:52:33,804 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:33,804 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-09-14 15:52:33,805 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-09-14 15:52:33,805 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-09-14 15:52:33,805 INFO L87 Difference]: Start difference. First operand 110 states and 120 transitions. Second operand 18 states. [2018-09-14 15:52:33,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:33,905 INFO L93 Difference]: Finished difference Result 161 states and 182 transitions. [2018-09-14 15:52:33,906 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-09-14 15:52:33,907 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 109 [2018-09-14 15:52:33,907 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:33,907 INFO L225 Difference]: With dead ends: 161 [2018-09-14 15:52:33,908 INFO L226 Difference]: Without dead ends: 115 [2018-09-14 15:52:33,908 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 452 GetRequests, 420 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-09-14 15:52:33,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-09-14 15:52:33,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 114. [2018-09-14 15:52:33,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-09-14 15:52:33,915 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 124 transitions. [2018-09-14 15:52:33,915 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 124 transitions. Word has length 109 [2018-09-14 15:52:33,915 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:33,915 INFO L480 AbstractCegarLoop]: Abstraction has 114 states and 124 transitions. [2018-09-14 15:52:33,915 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-09-14 15:52:33,916 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 124 transitions. [2018-09-14 15:52:33,917 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-09-14 15:52:33,917 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:33,917 INFO L376 BasicCegarLoop]: trace histogram [26, 26, 25, 16, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:33,917 INFO L423 AbstractCegarLoop]: === Iteration 19 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:33,917 INFO L82 PathProgramCache]: Analyzing trace with hash -1004612234, now seen corresponding path program 16 times [2018-09-14 15:52:33,917 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:33,918 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:33,918 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:33,918 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:33,919 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:33,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:34,837 INFO L134 CoverageAnalysis]: Checked inductivity of 1300 backedges. 619 proven. 528 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:34,837 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:34,837 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:34,844 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:34,844 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:34,875 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:34,875 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:34,877 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:34,889 INFO L134 CoverageAnalysis]: Checked inductivity of 1300 backedges. 619 proven. 528 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:34,889 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:35,473 INFO L134 CoverageAnalysis]: Checked inductivity of 1300 backedges. 619 proven. 528 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:35,492 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:35,493 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:35,511 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:35,511 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:35,582 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:35,582 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:35,587 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:35,601 INFO L134 CoverageAnalysis]: Checked inductivity of 1300 backedges. 619 proven. 528 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:35,601 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:35,620 INFO L134 CoverageAnalysis]: Checked inductivity of 1300 backedges. 619 proven. 528 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:35,621 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:35,621 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 36 [2018-09-14 15:52:35,622 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:35,622 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-09-14 15:52:35,622 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-09-14 15:52:35,623 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-09-14 15:52:35,623 INFO L87 Difference]: Start difference. First operand 114 states and 124 transitions. Second operand 19 states. [2018-09-14 15:52:35,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:35,707 INFO L93 Difference]: Finished difference Result 165 states and 186 transitions. [2018-09-14 15:52:35,707 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-09-14 15:52:35,707 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 113 [2018-09-14 15:52:35,708 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:35,708 INFO L225 Difference]: With dead ends: 165 [2018-09-14 15:52:35,708 INFO L226 Difference]: Without dead ends: 119 [2018-09-14 15:52:35,709 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 469 GetRequests, 435 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-09-14 15:52:35,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states. [2018-09-14 15:52:35,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 118. [2018-09-14 15:52:35,716 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-09-14 15:52:35,716 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 128 transitions. [2018-09-14 15:52:35,717 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 128 transitions. Word has length 113 [2018-09-14 15:52:35,717 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:35,717 INFO L480 AbstractCegarLoop]: Abstraction has 118 states and 128 transitions. [2018-09-14 15:52:35,717 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-09-14 15:52:35,717 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 128 transitions. [2018-09-14 15:52:35,718 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2018-09-14 15:52:35,718 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:35,718 INFO L376 BasicCegarLoop]: trace histogram [27, 27, 26, 17, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:35,719 INFO L423 AbstractCegarLoop]: === Iteration 20 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:35,719 INFO L82 PathProgramCache]: Analyzing trace with hash 1397355428, now seen corresponding path program 17 times [2018-09-14 15:52:35,719 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:35,720 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:35,720 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:35,720 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:35,720 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:35,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:36,681 INFO L134 CoverageAnalysis]: Checked inductivity of 1404 backedges. 656 proven. 595 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:36,682 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:36,682 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:36,692 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:36,692 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:36,745 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 27 check-sat command(s) [2018-09-14 15:52:36,746 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:36,748 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:36,769 INFO L134 CoverageAnalysis]: Checked inductivity of 1404 backedges. 656 proven. 595 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:36,770 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:37,573 INFO L134 CoverageAnalysis]: Checked inductivity of 1404 backedges. 656 proven. 595 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:37,594 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:37,594 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:37,609 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:37,609 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:37,843 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 27 check-sat command(s) [2018-09-14 15:52:37,843 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:37,847 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:37,865 INFO L134 CoverageAnalysis]: Checked inductivity of 1404 backedges. 656 proven. 595 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:37,866 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:37,920 INFO L134 CoverageAnalysis]: Checked inductivity of 1404 backedges. 656 proven. 595 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:37,921 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:37,921 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 38 [2018-09-14 15:52:37,921 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:37,922 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-09-14 15:52:37,922 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-09-14 15:52:37,923 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-09-14 15:52:37,923 INFO L87 Difference]: Start difference. First operand 118 states and 128 transitions. Second operand 20 states. [2018-09-14 15:52:37,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:37,993 INFO L93 Difference]: Finished difference Result 169 states and 190 transitions. [2018-09-14 15:52:37,994 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-09-14 15:52:37,994 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 117 [2018-09-14 15:52:37,994 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:37,995 INFO L225 Difference]: With dead ends: 169 [2018-09-14 15:52:37,995 INFO L226 Difference]: Without dead ends: 123 [2018-09-14 15:52:37,995 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 486 GetRequests, 450 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-09-14 15:52:37,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states. [2018-09-14 15:52:38,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 122. [2018-09-14 15:52:38,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 122 states. [2018-09-14 15:52:38,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 132 transitions. [2018-09-14 15:52:38,001 INFO L78 Accepts]: Start accepts. Automaton has 122 states and 132 transitions. Word has length 117 [2018-09-14 15:52:38,002 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:38,002 INFO L480 AbstractCegarLoop]: Abstraction has 122 states and 132 transitions. [2018-09-14 15:52:38,002 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-09-14 15:52:38,002 INFO L276 IsEmpty]: Start isEmpty. Operand 122 states and 132 transitions. [2018-09-14 15:52:38,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 122 [2018-09-14 15:52:38,003 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:38,003 INFO L376 BasicCegarLoop]: trace histogram [28, 28, 27, 18, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:38,003 INFO L423 AbstractCegarLoop]: === Iteration 21 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:38,003 INFO L82 PathProgramCache]: Analyzing trace with hash -29472046, now seen corresponding path program 18 times [2018-09-14 15:52:38,004 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:38,004 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:38,004 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:38,004 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:38,005 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:38,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:38,310 INFO L134 CoverageAnalysis]: Checked inductivity of 1512 backedges. 693 proven. 666 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:38,310 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:38,310 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:38,318 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:38,318 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:38,358 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 28 check-sat command(s) [2018-09-14 15:52:38,358 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:38,361 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:38,692 INFO L134 CoverageAnalysis]: Checked inductivity of 1512 backedges. 1132 proven. 343 refuted. 0 times theorem prover too weak. 37 trivial. 0 not checked. [2018-09-14 15:52:38,692 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:39,065 INFO L134 CoverageAnalysis]: Checked inductivity of 1512 backedges. 1132 proven. 343 refuted. 0 times theorem prover too weak. 37 trivial. 0 not checked. [2018-09-14 15:52:39,085 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:39,085 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:39,101 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:39,101 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:39,377 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 28 check-sat command(s) [2018-09-14 15:52:39,378 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:39,382 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:39,399 INFO L134 CoverageAnalysis]: Checked inductivity of 1512 backedges. 693 proven. 666 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:39,400 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:40,325 INFO L134 CoverageAnalysis]: Checked inductivity of 1512 backedges. 693 proven. 666 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:52:40,326 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:40,326 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 67 [2018-09-14 15:52:40,326 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:40,327 INFO L459 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-09-14 15:52:40,327 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-09-14 15:52:40,329 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1185, Invalid=3237, Unknown=0, NotChecked=0, Total=4422 [2018-09-14 15:52:40,329 INFO L87 Difference]: Start difference. First operand 122 states and 132 transitions. Second operand 40 states. [2018-09-14 15:52:41,138 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:41,138 INFO L93 Difference]: Finished difference Result 542 states and 662 transitions. [2018-09-14 15:52:41,139 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2018-09-14 15:52:41,139 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 121 [2018-09-14 15:52:41,139 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:41,141 INFO L225 Difference]: With dead ends: 542 [2018-09-14 15:52:41,141 INFO L226 Difference]: Without dead ends: 496 [2018-09-14 15:52:41,145 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 540 GetRequests, 418 SyntacticMatches, 20 SemanticMatches, 102 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2825 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=3052, Invalid=7660, Unknown=0, NotChecked=0, Total=10712 [2018-09-14 15:52:41,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 496 states. [2018-09-14 15:52:41,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 496 to 162. [2018-09-14 15:52:41,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-09-14 15:52:41,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 181 transitions. [2018-09-14 15:52:41,162 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 181 transitions. Word has length 121 [2018-09-14 15:52:41,162 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:41,162 INFO L480 AbstractCegarLoop]: Abstraction has 162 states and 181 transitions. [2018-09-14 15:52:41,162 INFO L481 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-09-14 15:52:41,162 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 181 transitions. [2018-09-14 15:52:41,163 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 162 [2018-09-14 15:52:41,163 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:41,164 INFO L376 BasicCegarLoop]: trace histogram [38, 38, 37, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:41,164 INFO L423 AbstractCegarLoop]: === Iteration 22 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:41,164 INFO L82 PathProgramCache]: Analyzing trace with hash -1933849908, now seen corresponding path program 19 times [2018-09-14 15:52:41,164 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:41,165 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:41,165 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:41,165 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:41,165 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:41,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:41,455 INFO L134 CoverageAnalysis]: Checked inductivity of 2812 backedges. 1441 proven. 741 refuted. 0 times theorem prover too weak. 630 trivial. 0 not checked. [2018-09-14 15:52:41,455 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:41,455 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:41,465 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:41,465 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:41,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:41,512 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:41,553 INFO L134 CoverageAnalysis]: Checked inductivity of 2812 backedges. 1441 proven. 741 refuted. 0 times theorem prover too weak. 630 trivial. 0 not checked. [2018-09-14 15:52:41,553 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:42,442 INFO L134 CoverageAnalysis]: Checked inductivity of 2812 backedges. 1441 proven. 741 refuted. 0 times theorem prover too weak. 630 trivial. 0 not checked. [2018-09-14 15:52:42,462 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:42,462 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:42,480 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:42,480 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:42,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:42,570 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:42,593 INFO L134 CoverageAnalysis]: Checked inductivity of 2812 backedges. 1441 proven. 741 refuted. 0 times theorem prover too weak. 630 trivial. 0 not checked. [2018-09-14 15:52:42,593 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:42,633 INFO L134 CoverageAnalysis]: Checked inductivity of 2812 backedges. 1441 proven. 741 refuted. 0 times theorem prover too weak. 630 trivial. 0 not checked. [2018-09-14 15:52:42,635 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:42,635 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22, 22, 22] total 42 [2018-09-14 15:52:42,635 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:42,636 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-09-14 15:52:42,636 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-09-14 15:52:42,636 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-09-14 15:52:42,636 INFO L87 Difference]: Start difference. First operand 162 states and 181 transitions. Second operand 22 states. [2018-09-14 15:52:42,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:42,717 INFO L93 Difference]: Finished difference Result 249 states and 288 transitions. [2018-09-14 15:52:42,719 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-09-14 15:52:42,719 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 161 [2018-09-14 15:52:42,719 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:42,720 INFO L225 Difference]: With dead ends: 249 [2018-09-14 15:52:42,720 INFO L226 Difference]: Without dead ends: 167 [2018-09-14 15:52:42,722 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 664 GetRequests, 624 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-09-14 15:52:42,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 167 states. [2018-09-14 15:52:42,736 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 167 to 166. [2018-09-14 15:52:42,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 166 states. [2018-09-14 15:52:42,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 185 transitions. [2018-09-14 15:52:42,737 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 185 transitions. Word has length 161 [2018-09-14 15:52:42,737 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:42,737 INFO L480 AbstractCegarLoop]: Abstraction has 166 states and 185 transitions. [2018-09-14 15:52:42,738 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-09-14 15:52:42,738 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 185 transitions. [2018-09-14 15:52:42,738 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 166 [2018-09-14 15:52:42,738 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:42,739 INFO L376 BasicCegarLoop]: trace histogram [39, 39, 38, 20, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:42,739 INFO L423 AbstractCegarLoop]: === Iteration 23 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:42,739 INFO L82 PathProgramCache]: Analyzing trace with hash 78419194, now seen corresponding path program 20 times [2018-09-14 15:52:42,739 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:42,740 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:42,740 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:42,740 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:42,740 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:42,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:43,055 INFO L134 CoverageAnalysis]: Checked inductivity of 2964 backedges. 1514 proven. 820 refuted. 0 times theorem prover too weak. 630 trivial. 0 not checked. [2018-09-14 15:52:43,056 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:43,056 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:43,064 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:43,064 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:43,107 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:43,107 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:43,110 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:43,138 INFO L134 CoverageAnalysis]: Checked inductivity of 2964 backedges. 1514 proven. 820 refuted. 0 times theorem prover too weak. 630 trivial. 0 not checked. [2018-09-14 15:52:43,138 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:43,717 INFO L134 CoverageAnalysis]: Checked inductivity of 2964 backedges. 1514 proven. 820 refuted. 0 times theorem prover too weak. 630 trivial. 0 not checked. [2018-09-14 15:52:43,738 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:43,738 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:43,754 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:43,755 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:43,847 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:43,847 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:43,854 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:43,881 INFO L134 CoverageAnalysis]: Checked inductivity of 2964 backedges. 1514 proven. 820 refuted. 0 times theorem prover too weak. 630 trivial. 0 not checked. [2018-09-14 15:52:43,881 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:43,952 INFO L134 CoverageAnalysis]: Checked inductivity of 2964 backedges. 1514 proven. 820 refuted. 0 times theorem prover too weak. 630 trivial. 0 not checked. [2018-09-14 15:52:43,953 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:43,954 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 44 [2018-09-14 15:52:43,954 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:43,954 INFO L459 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-09-14 15:52:43,955 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-09-14 15:52:43,955 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-09-14 15:52:43,956 INFO L87 Difference]: Start difference. First operand 166 states and 185 transitions. Second operand 23 states. [2018-09-14 15:52:44,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:44,133 INFO L93 Difference]: Finished difference Result 253 states and 292 transitions. [2018-09-14 15:52:44,135 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-09-14 15:52:44,136 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 165 [2018-09-14 15:52:44,136 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:44,137 INFO L225 Difference]: With dead ends: 253 [2018-09-14 15:52:44,137 INFO L226 Difference]: Without dead ends: 171 [2018-09-14 15:52:44,138 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 681 GetRequests, 639 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-09-14 15:52:44,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states. [2018-09-14 15:52:44,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 170. [2018-09-14 15:52:44,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 170 states. [2018-09-14 15:52:44,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 189 transitions. [2018-09-14 15:52:44,154 INFO L78 Accepts]: Start accepts. Automaton has 170 states and 189 transitions. Word has length 165 [2018-09-14 15:52:44,154 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:44,155 INFO L480 AbstractCegarLoop]: Abstraction has 170 states and 189 transitions. [2018-09-14 15:52:44,155 INFO L481 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-09-14 15:52:44,155 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states and 189 transitions. [2018-09-14 15:52:44,156 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 170 [2018-09-14 15:52:44,156 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:44,156 INFO L376 BasicCegarLoop]: trace histogram [40, 40, 39, 21, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:44,156 INFO L423 AbstractCegarLoop]: === Iteration 24 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:44,156 INFO L82 PathProgramCache]: Analyzing trace with hash 632330280, now seen corresponding path program 21 times [2018-09-14 15:52:44,157 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:44,157 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:44,157 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:44,157 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:44,158 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:44,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:44,467 INFO L134 CoverageAnalysis]: Checked inductivity of 3120 backedges. 1587 proven. 903 refuted. 0 times theorem prover too weak. 630 trivial. 0 not checked. [2018-09-14 15:52:44,467 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:44,467 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:44,475 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:44,475 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:44,536 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 40 check-sat command(s) [2018-09-14 15:52:44,536 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:44,539 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:45,254 INFO L134 CoverageAnalysis]: Checked inductivity of 3120 backedges. 1714 proven. 1333 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2018-09-14 15:52:45,254 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:46,143 INFO L134 CoverageAnalysis]: Checked inductivity of 3120 backedges. 1714 proven. 1333 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2018-09-14 15:52:46,163 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:46,164 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:46,180 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:46,180 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:46,669 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 40 check-sat command(s) [2018-09-14 15:52:46,670 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:46,675 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:46,694 INFO L134 CoverageAnalysis]: Checked inductivity of 3120 backedges. 1587 proven. 903 refuted. 0 times theorem prover too weak. 630 trivial. 0 not checked. [2018-09-14 15:52:46,694 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:47,612 INFO L134 CoverageAnalysis]: Checked inductivity of 3120 backedges. 1587 proven. 903 refuted. 0 times theorem prover too weak. 630 trivial. 0 not checked. [2018-09-14 15:52:47,614 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:47,614 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 70 [2018-09-14 15:52:47,614 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:47,614 INFO L459 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-09-14 15:52:47,615 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-09-14 15:52:47,616 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1359, Invalid=3471, Unknown=0, NotChecked=0, Total=4830 [2018-09-14 15:52:47,616 INFO L87 Difference]: Start difference. First operand 170 states and 189 transitions. Second operand 46 states. [2018-09-14 15:52:48,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:48,608 INFO L93 Difference]: Finished difference Result 488 states and 587 transitions. [2018-09-14 15:52:48,611 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2018-09-14 15:52:48,612 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 169 [2018-09-14 15:52:48,612 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:48,614 INFO L225 Difference]: With dead ends: 488 [2018-09-14 15:52:48,614 INFO L226 Difference]: Without dead ends: 406 [2018-09-14 15:52:48,618 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 741 GetRequests, 592 SyntacticMatches, 38 SemanticMatches, 111 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3611 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=3529, Invalid=9127, Unknown=0, NotChecked=0, Total=12656 [2018-09-14 15:52:48,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 406 states. [2018-09-14 15:52:48,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 406 to 186. [2018-09-14 15:52:48,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-09-14 15:52:48,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 208 transitions. [2018-09-14 15:52:48,649 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 208 transitions. Word has length 169 [2018-09-14 15:52:48,649 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:48,650 INFO L480 AbstractCegarLoop]: Abstraction has 186 states and 208 transitions. [2018-09-14 15:52:48,650 INFO L481 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-09-14 15:52:48,650 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 208 transitions. [2018-09-14 15:52:48,651 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2018-09-14 15:52:48,651 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:48,651 INFO L376 BasicCegarLoop]: trace histogram [44, 44, 43, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:48,651 INFO L423 AbstractCegarLoop]: === Iteration 25 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:48,651 INFO L82 PathProgramCache]: Analyzing trace with hash 762179226, now seen corresponding path program 22 times [2018-09-14 15:52:48,652 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:48,652 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:48,652 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:48,652 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:48,652 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:48,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:49,519 INFO L134 CoverageAnalysis]: Checked inductivity of 3784 backedges. 1933 proven. 990 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:52:49,519 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:49,519 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:49,528 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:49,528 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:49,593 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:49,593 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:49,597 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:49,629 INFO L134 CoverageAnalysis]: Checked inductivity of 3784 backedges. 1933 proven. 990 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:52:49,629 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:50,308 INFO L134 CoverageAnalysis]: Checked inductivity of 3784 backedges. 1933 proven. 990 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:52:50,329 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:50,330 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:50,344 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:50,345 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:50,455 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:50,455 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:50,460 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:50,488 INFO L134 CoverageAnalysis]: Checked inductivity of 3784 backedges. 1933 proven. 990 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:52:50,488 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:50,535 INFO L134 CoverageAnalysis]: Checked inductivity of 3784 backedges. 1933 proven. 990 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:52:50,536 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:50,537 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 48 [2018-09-14 15:52:50,537 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:50,537 INFO L459 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-09-14 15:52:50,537 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-09-14 15:52:50,538 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-09-14 15:52:50,539 INFO L87 Difference]: Start difference. First operand 186 states and 208 transitions. Second operand 25 states. [2018-09-14 15:52:50,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:50,680 INFO L93 Difference]: Finished difference Result 285 states and 330 transitions. [2018-09-14 15:52:50,680 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-09-14 15:52:50,680 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 185 [2018-09-14 15:52:50,681 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:50,681 INFO L225 Difference]: With dead ends: 285 [2018-09-14 15:52:50,682 INFO L226 Difference]: Without dead ends: 191 [2018-09-14 15:52:50,682 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 763 GetRequests, 717 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-09-14 15:52:50,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191 states. [2018-09-14 15:52:50,700 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191 to 190. [2018-09-14 15:52:50,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190 states. [2018-09-14 15:52:50,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 212 transitions. [2018-09-14 15:52:50,701 INFO L78 Accepts]: Start accepts. Automaton has 190 states and 212 transitions. Word has length 185 [2018-09-14 15:52:50,701 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:50,701 INFO L480 AbstractCegarLoop]: Abstraction has 190 states and 212 transitions. [2018-09-14 15:52:50,701 INFO L481 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-09-14 15:52:50,701 INFO L276 IsEmpty]: Start isEmpty. Operand 190 states and 212 transitions. [2018-09-14 15:52:50,702 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 190 [2018-09-14 15:52:50,702 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:50,703 INFO L376 BasicCegarLoop]: trace histogram [45, 45, 44, 23, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:50,703 INFO L423 AbstractCegarLoop]: === Iteration 26 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:50,703 INFO L82 PathProgramCache]: Analyzing trace with hash -1295085880, now seen corresponding path program 23 times [2018-09-14 15:52:50,703 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:50,704 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:50,704 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:50,704 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:50,704 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:50,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:51,070 INFO L134 CoverageAnalysis]: Checked inductivity of 3960 backedges. 2018 proven. 1081 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:52:51,071 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:51,071 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:51,078 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:51,078 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:51,149 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 45 check-sat command(s) [2018-09-14 15:52:51,149 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:51,153 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:51,187 INFO L134 CoverageAnalysis]: Checked inductivity of 3960 backedges. 2018 proven. 1081 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:52:51,187 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:52,675 INFO L134 CoverageAnalysis]: Checked inductivity of 3960 backedges. 2018 proven. 1081 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:52:52,696 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:52,696 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:52,712 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:52,712 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:53,263 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 45 check-sat command(s) [2018-09-14 15:52:53,263 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:53,270 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:53,302 INFO L134 CoverageAnalysis]: Checked inductivity of 3960 backedges. 2018 proven. 1081 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:52:53,302 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:53,342 INFO L134 CoverageAnalysis]: Checked inductivity of 3960 backedges. 2018 proven. 1081 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:52:53,343 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:53,344 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 50 [2018-09-14 15:52:53,344 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:53,344 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-09-14 15:52:53,345 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-09-14 15:52:53,345 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-09-14 15:52:53,345 INFO L87 Difference]: Start difference. First operand 190 states and 212 transitions. Second operand 26 states. [2018-09-14 15:52:53,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:53,460 INFO L93 Difference]: Finished difference Result 289 states and 334 transitions. [2018-09-14 15:52:53,463 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-09-14 15:52:53,463 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 189 [2018-09-14 15:52:53,463 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:53,464 INFO L225 Difference]: With dead ends: 289 [2018-09-14 15:52:53,464 INFO L226 Difference]: Without dead ends: 195 [2018-09-14 15:52:53,465 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 780 GetRequests, 732 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-09-14 15:52:53,465 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states. [2018-09-14 15:52:53,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 194. [2018-09-14 15:52:53,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 194 states. [2018-09-14 15:52:53,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194 states to 194 states and 216 transitions. [2018-09-14 15:52:53,490 INFO L78 Accepts]: Start accepts. Automaton has 194 states and 216 transitions. Word has length 189 [2018-09-14 15:52:53,490 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:53,490 INFO L480 AbstractCegarLoop]: Abstraction has 194 states and 216 transitions. [2018-09-14 15:52:53,491 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-09-14 15:52:53,491 INFO L276 IsEmpty]: Start isEmpty. Operand 194 states and 216 transitions. [2018-09-14 15:52:53,492 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 194 [2018-09-14 15:52:53,492 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:53,492 INFO L376 BasicCegarLoop]: trace histogram [46, 46, 45, 24, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:53,492 INFO L423 AbstractCegarLoop]: === Iteration 27 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:53,493 INFO L82 PathProgramCache]: Analyzing trace with hash 1499949046, now seen corresponding path program 24 times [2018-09-14 15:52:53,493 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:53,493 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:53,493 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:53,494 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:53,494 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:53,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:53,946 INFO L134 CoverageAnalysis]: Checked inductivity of 4140 backedges. 2103 proven. 1176 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:52:53,947 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:53,947 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:53,955 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:53,956 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:54,037 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 44 check-sat command(s) [2018-09-14 15:52:54,037 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:54,040 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:54,065 INFO L134 CoverageAnalysis]: Checked inductivity of 4140 backedges. 2103 proven. 1176 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:52:54,066 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:54,995 INFO L134 CoverageAnalysis]: Checked inductivity of 4140 backedges. 2103 proven. 1176 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:52:55,017 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:55,017 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:55,033 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:55,033 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:55,657 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 44 check-sat command(s) [2018-09-14 15:52:55,658 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:55,664 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:55,719 INFO L134 CoverageAnalysis]: Checked inductivity of 4140 backedges. 2103 proven. 1176 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:52:55,720 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:55,834 INFO L134 CoverageAnalysis]: Checked inductivity of 4140 backedges. 2103 proven. 1176 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:52:55,836 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:55,836 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 52 [2018-09-14 15:52:55,836 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:55,837 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-09-14 15:52:55,837 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-09-14 15:52:55,838 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:52:55,838 INFO L87 Difference]: Start difference. First operand 194 states and 216 transitions. Second operand 27 states. [2018-09-14 15:52:56,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:56,133 INFO L93 Difference]: Finished difference Result 293 states and 338 transitions. [2018-09-14 15:52:56,136 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-09-14 15:52:56,136 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 193 [2018-09-14 15:52:56,136 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:56,137 INFO L225 Difference]: With dead ends: 293 [2018-09-14 15:52:56,137 INFO L226 Difference]: Without dead ends: 199 [2018-09-14 15:52:56,138 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 797 GetRequests, 747 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:52:56,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 199 states. [2018-09-14 15:52:56,159 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 199 to 198. [2018-09-14 15:52:56,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 198 states. [2018-09-14 15:52:56,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198 states to 198 states and 220 transitions. [2018-09-14 15:52:56,160 INFO L78 Accepts]: Start accepts. Automaton has 198 states and 220 transitions. Word has length 193 [2018-09-14 15:52:56,161 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:56,161 INFO L480 AbstractCegarLoop]: Abstraction has 198 states and 220 transitions. [2018-09-14 15:52:56,161 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-09-14 15:52:56,161 INFO L276 IsEmpty]: Start isEmpty. Operand 198 states and 220 transitions. [2018-09-14 15:52:56,162 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 198 [2018-09-14 15:52:56,162 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:56,162 INFO L376 BasicCegarLoop]: trace histogram [47, 47, 46, 25, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:56,162 INFO L423 AbstractCegarLoop]: === Iteration 28 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:56,163 INFO L82 PathProgramCache]: Analyzing trace with hash -395052508, now seen corresponding path program 25 times [2018-09-14 15:52:56,163 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:56,163 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:56,164 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:56,164 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:56,164 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:56,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:56,556 INFO L134 CoverageAnalysis]: Checked inductivity of 4324 backedges. 2188 proven. 1275 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:52:56,557 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:56,557 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:56,564 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:56,564 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:56,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:56,619 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:56,655 INFO L134 CoverageAnalysis]: Checked inductivity of 4324 backedges. 2188 proven. 1275 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:52:56,655 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:57,850 INFO L134 CoverageAnalysis]: Checked inductivity of 4324 backedges. 2188 proven. 1275 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:52:57,889 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:57,889 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:57,916 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:57,917 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:58,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:58,032 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:58,071 INFO L134 CoverageAnalysis]: Checked inductivity of 4324 backedges. 2188 proven. 1275 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:52:58,071 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:58,567 INFO L134 CoverageAnalysis]: Checked inductivity of 4324 backedges. 2188 proven. 1275 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:52:58,569 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:58,569 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28, 28, 28] total 52 [2018-09-14 15:52:58,569 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:58,570 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-09-14 15:52:58,570 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-09-14 15:52:58,571 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:52:58,571 INFO L87 Difference]: Start difference. First operand 198 states and 220 transitions. Second operand 28 states. [2018-09-14 15:52:58,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:58,877 INFO L93 Difference]: Finished difference Result 297 states and 342 transitions. [2018-09-14 15:52:58,877 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-09-14 15:52:58,877 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 197 [2018-09-14 15:52:58,878 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:58,879 INFO L225 Difference]: With dead ends: 297 [2018-09-14 15:52:58,879 INFO L226 Difference]: Without dead ends: 203 [2018-09-14 15:52:58,879 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 814 GetRequests, 760 SyntacticMatches, 4 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 98 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:52:58,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 203 states. [2018-09-14 15:52:58,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 203 to 202. [2018-09-14 15:52:58,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 202 states. [2018-09-14 15:52:58,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 202 states to 202 states and 224 transitions. [2018-09-14 15:52:58,906 INFO L78 Accepts]: Start accepts. Automaton has 202 states and 224 transitions. Word has length 197 [2018-09-14 15:52:58,906 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:58,906 INFO L480 AbstractCegarLoop]: Abstraction has 202 states and 224 transitions. [2018-09-14 15:52:58,907 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-09-14 15:52:58,907 INFO L276 IsEmpty]: Start isEmpty. Operand 202 states and 224 transitions. [2018-09-14 15:52:58,908 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 202 [2018-09-14 15:52:58,908 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:58,908 INFO L376 BasicCegarLoop]: trace histogram [48, 48, 47, 26, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:58,909 INFO L423 AbstractCegarLoop]: === Iteration 29 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:58,909 INFO L82 PathProgramCache]: Analyzing trace with hash 493864274, now seen corresponding path program 26 times [2018-09-14 15:52:58,909 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:58,910 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:58,910 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:58,910 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:58,910 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:58,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:00,125 INFO L134 CoverageAnalysis]: Checked inductivity of 4512 backedges. 2273 proven. 1378 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:00,125 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:00,125 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:00,133 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:53:00,133 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:00,196 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:53:00,197 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:00,200 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:00,238 INFO L134 CoverageAnalysis]: Checked inductivity of 4512 backedges. 2273 proven. 1378 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:00,238 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:01,326 INFO L134 CoverageAnalysis]: Checked inductivity of 4512 backedges. 2273 proven. 1378 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:01,346 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:01,346 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:01,374 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:53:01,374 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:01,481 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:53:01,482 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:01,487 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:01,524 INFO L134 CoverageAnalysis]: Checked inductivity of 4512 backedges. 2273 proven. 1378 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:01,525 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:01,713 INFO L134 CoverageAnalysis]: Checked inductivity of 4512 backedges. 2273 proven. 1378 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:01,714 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:01,714 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 52 [2018-09-14 15:53:01,714 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:01,715 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-09-14 15:53:01,715 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-09-14 15:53:01,715 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:01,716 INFO L87 Difference]: Start difference. First operand 202 states and 224 transitions. Second operand 29 states. [2018-09-14 15:53:01,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:01,925 INFO L93 Difference]: Finished difference Result 301 states and 346 transitions. [2018-09-14 15:53:01,925 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-09-14 15:53:01,926 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 201 [2018-09-14 15:53:01,926 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:01,927 INFO L225 Difference]: With dead ends: 301 [2018-09-14 15:53:01,927 INFO L226 Difference]: Without dead ends: 207 [2018-09-14 15:53:01,928 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 831 GetRequests, 773 SyntacticMatches, 8 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 196 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:01,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 207 states. [2018-09-14 15:53:01,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 207 to 206. [2018-09-14 15:53:01,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 206 states. [2018-09-14 15:53:01,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 228 transitions. [2018-09-14 15:53:01,953 INFO L78 Accepts]: Start accepts. Automaton has 206 states and 228 transitions. Word has length 201 [2018-09-14 15:53:01,954 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:01,954 INFO L480 AbstractCegarLoop]: Abstraction has 206 states and 228 transitions. [2018-09-14 15:53:01,954 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-09-14 15:53:01,954 INFO L276 IsEmpty]: Start isEmpty. Operand 206 states and 228 transitions. [2018-09-14 15:53:01,955 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 206 [2018-09-14 15:53:01,955 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:01,955 INFO L376 BasicCegarLoop]: trace histogram [49, 49, 48, 27, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:01,956 INFO L423 AbstractCegarLoop]: === Iteration 30 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:01,956 INFO L82 PathProgramCache]: Analyzing trace with hash -1944696448, now seen corresponding path program 27 times [2018-09-14 15:53:01,956 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:01,957 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:01,957 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:01,957 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:01,957 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:01,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:02,619 INFO L134 CoverageAnalysis]: Checked inductivity of 4704 backedges. 2358 proven. 1485 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:02,619 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:02,619 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:02,627 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:53:02,627 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:53:02,703 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 49 check-sat command(s) [2018-09-14 15:53:02,704 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:02,706 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:02,746 INFO L134 CoverageAnalysis]: Checked inductivity of 4704 backedges. 2358 proven. 1485 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:02,746 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:04,448 INFO L134 CoverageAnalysis]: Checked inductivity of 4704 backedges. 2358 proven. 1485 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:04,478 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:04,478 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:04,496 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:53:04,496 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:53:05,178 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 49 check-sat command(s) [2018-09-14 15:53:05,178 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:05,183 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:05,213 INFO L134 CoverageAnalysis]: Checked inductivity of 4704 backedges. 2358 proven. 1485 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:05,213 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:05,372 INFO L134 CoverageAnalysis]: Checked inductivity of 4704 backedges. 2358 proven. 1485 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:05,373 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:05,374 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 30, 30] total 52 [2018-09-14 15:53:05,374 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:05,374 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-09-14 15:53:05,375 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-09-14 15:53:05,375 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:05,375 INFO L87 Difference]: Start difference. First operand 206 states and 228 transitions. Second operand 30 states. [2018-09-14 15:53:05,507 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:05,507 INFO L93 Difference]: Finished difference Result 305 states and 350 transitions. [2018-09-14 15:53:05,514 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-09-14 15:53:05,515 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 205 [2018-09-14 15:53:05,515 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:05,516 INFO L225 Difference]: With dead ends: 305 [2018-09-14 15:53:05,516 INFO L226 Difference]: Without dead ends: 211 [2018-09-14 15:53:05,517 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 848 GetRequests, 786 SyntacticMatches, 12 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 294 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:05,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 211 states. [2018-09-14 15:53:05,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 211 to 210. [2018-09-14 15:53:05,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 210 states. [2018-09-14 15:53:05,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 210 states to 210 states and 232 transitions. [2018-09-14 15:53:05,543 INFO L78 Accepts]: Start accepts. Automaton has 210 states and 232 transitions. Word has length 205 [2018-09-14 15:53:05,544 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:05,544 INFO L480 AbstractCegarLoop]: Abstraction has 210 states and 232 transitions. [2018-09-14 15:53:05,544 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-09-14 15:53:05,544 INFO L276 IsEmpty]: Start isEmpty. Operand 210 states and 232 transitions. [2018-09-14 15:53:05,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 210 [2018-09-14 15:53:05,545 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:05,545 INFO L376 BasicCegarLoop]: trace histogram [50, 50, 49, 28, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:05,546 INFO L423 AbstractCegarLoop]: === Iteration 31 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:05,546 INFO L82 PathProgramCache]: Analyzing trace with hash 2120418990, now seen corresponding path program 28 times [2018-09-14 15:53:05,546 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:05,547 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:05,547 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:05,547 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:05,547 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:05,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:06,277 INFO L134 CoverageAnalysis]: Checked inductivity of 4900 backedges. 2443 proven. 1596 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:06,277 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:06,277 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:06,285 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:53:06,285 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:53:06,359 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:53:06,360 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:06,364 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:06,410 INFO L134 CoverageAnalysis]: Checked inductivity of 4900 backedges. 2443 proven. 1596 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:06,410 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:07,762 INFO L134 CoverageAnalysis]: Checked inductivity of 4900 backedges. 2443 proven. 1596 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:07,782 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:07,782 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:07,797 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:53:07,797 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:53:07,921 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:53:07,921 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:07,926 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:07,955 INFO L134 CoverageAnalysis]: Checked inductivity of 4900 backedges. 2443 proven. 1596 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:07,955 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:08,149 INFO L134 CoverageAnalysis]: Checked inductivity of 4900 backedges. 2443 proven. 1596 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:08,151 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:08,151 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31, 31, 31, 31] total 52 [2018-09-14 15:53:08,151 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:08,151 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-09-14 15:53:08,152 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-09-14 15:53:08,152 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:08,152 INFO L87 Difference]: Start difference. First operand 210 states and 232 transitions. Second operand 31 states. [2018-09-14 15:53:08,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:08,284 INFO L93 Difference]: Finished difference Result 309 states and 354 transitions. [2018-09-14 15:53:08,285 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-09-14 15:53:08,285 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 209 [2018-09-14 15:53:08,285 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:08,286 INFO L225 Difference]: With dead ends: 309 [2018-09-14 15:53:08,286 INFO L226 Difference]: Without dead ends: 215 [2018-09-14 15:53:08,287 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 865 GetRequests, 799 SyntacticMatches, 16 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 392 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:08,287 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 215 states. [2018-09-14 15:53:08,312 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 215 to 214. [2018-09-14 15:53:08,312 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 214 states. [2018-09-14 15:53:08,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 214 states to 214 states and 236 transitions. [2018-09-14 15:53:08,313 INFO L78 Accepts]: Start accepts. Automaton has 214 states and 236 transitions. Word has length 209 [2018-09-14 15:53:08,313 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:08,314 INFO L480 AbstractCegarLoop]: Abstraction has 214 states and 236 transitions. [2018-09-14 15:53:08,314 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-09-14 15:53:08,314 INFO L276 IsEmpty]: Start isEmpty. Operand 214 states and 236 transitions. [2018-09-14 15:53:08,315 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 214 [2018-09-14 15:53:08,315 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:08,315 INFO L376 BasicCegarLoop]: trace histogram [51, 51, 50, 29, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:08,315 INFO L423 AbstractCegarLoop]: === Iteration 32 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:08,316 INFO L82 PathProgramCache]: Analyzing trace with hash -728662820, now seen corresponding path program 29 times [2018-09-14 15:53:08,316 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:08,319 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:08,319 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:08,319 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:08,319 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:08,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:08,876 INFO L134 CoverageAnalysis]: Checked inductivity of 5100 backedges. 2528 proven. 1711 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:08,876 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:08,876 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:08,884 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:53:08,884 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:08,966 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 51 check-sat command(s) [2018-09-14 15:53:08,966 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:08,970 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:09,012 INFO L134 CoverageAnalysis]: Checked inductivity of 5100 backedges. 2528 proven. 1711 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:09,012 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:09,904 INFO L134 CoverageAnalysis]: Checked inductivity of 5100 backedges. 2528 proven. 1711 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:09,924 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:09,924 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:09,940 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:53:09,940 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:10,625 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 51 check-sat command(s) [2018-09-14 15:53:10,625 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:10,630 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:10,662 INFO L134 CoverageAnalysis]: Checked inductivity of 5100 backedges. 2528 proven. 1711 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:10,663 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:10,889 INFO L134 CoverageAnalysis]: Checked inductivity of 5100 backedges. 2528 proven. 1711 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:10,891 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:10,891 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32, 32, 32, 32] total 52 [2018-09-14 15:53:10,891 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:10,892 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-09-14 15:53:10,892 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-09-14 15:53:10,892 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:10,893 INFO L87 Difference]: Start difference. First operand 214 states and 236 transitions. Second operand 32 states. [2018-09-14 15:53:11,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:11,039 INFO L93 Difference]: Finished difference Result 313 states and 358 transitions. [2018-09-14 15:53:11,040 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-09-14 15:53:11,040 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 213 [2018-09-14 15:53:11,040 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:11,041 INFO L225 Difference]: With dead ends: 313 [2018-09-14 15:53:11,041 INFO L226 Difference]: Without dead ends: 219 [2018-09-14 15:53:11,042 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 882 GetRequests, 812 SyntacticMatches, 20 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 490 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:11,042 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219 states. [2018-09-14 15:53:11,065 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219 to 218. [2018-09-14 15:53:11,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 218 states. [2018-09-14 15:53:11,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 218 states to 218 states and 240 transitions. [2018-09-14 15:53:11,067 INFO L78 Accepts]: Start accepts. Automaton has 218 states and 240 transitions. Word has length 213 [2018-09-14 15:53:11,067 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:11,067 INFO L480 AbstractCegarLoop]: Abstraction has 218 states and 240 transitions. [2018-09-14 15:53:11,067 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-09-14 15:53:11,068 INFO L276 IsEmpty]: Start isEmpty. Operand 218 states and 240 transitions. [2018-09-14 15:53:11,069 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 218 [2018-09-14 15:53:11,069 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:11,069 INFO L376 BasicCegarLoop]: trace histogram [52, 52, 51, 30, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:11,070 INFO L423 AbstractCegarLoop]: === Iteration 33 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:11,070 INFO L82 PathProgramCache]: Analyzing trace with hash -451073014, now seen corresponding path program 30 times [2018-09-14 15:53:11,070 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:11,071 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:11,071 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:11,071 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:11,071 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:11,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:12,863 INFO L134 CoverageAnalysis]: Checked inductivity of 5304 backedges. 2613 proven. 1830 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:12,864 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:12,864 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:12,872 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:53:12,872 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:53:12,949 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2018-09-14 15:53:12,950 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:12,952 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:12,982 INFO L134 CoverageAnalysis]: Checked inductivity of 5304 backedges. 2613 proven. 1830 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:12,982 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:13,778 INFO L134 CoverageAnalysis]: Checked inductivity of 5304 backedges. 2613 proven. 1830 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:13,799 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:13,799 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:13,814 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:53:13,814 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:53:14,498 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2018-09-14 15:53:14,498 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:14,504 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:14,537 INFO L134 CoverageAnalysis]: Checked inductivity of 5304 backedges. 2613 proven. 1830 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:14,537 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:14,804 INFO L134 CoverageAnalysis]: Checked inductivity of 5304 backedges. 2613 proven. 1830 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:14,805 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:14,806 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33, 33, 33, 33] total 52 [2018-09-14 15:53:14,806 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:14,806 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-09-14 15:53:14,806 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-09-14 15:53:14,807 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:14,807 INFO L87 Difference]: Start difference. First operand 218 states and 240 transitions. Second operand 33 states. [2018-09-14 15:53:14,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:14,958 INFO L93 Difference]: Finished difference Result 317 states and 362 transitions. [2018-09-14 15:53:14,958 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-09-14 15:53:14,958 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 217 [2018-09-14 15:53:14,958 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:14,959 INFO L225 Difference]: With dead ends: 317 [2018-09-14 15:53:14,959 INFO L226 Difference]: Without dead ends: 223 [2018-09-14 15:53:14,960 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 899 GetRequests, 825 SyntacticMatches, 24 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 588 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:14,960 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states. [2018-09-14 15:53:14,984 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 222. [2018-09-14 15:53:14,984 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 222 states. [2018-09-14 15:53:14,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 222 states to 222 states and 244 transitions. [2018-09-14 15:53:14,986 INFO L78 Accepts]: Start accepts. Automaton has 222 states and 244 transitions. Word has length 217 [2018-09-14 15:53:14,986 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:14,986 INFO L480 AbstractCegarLoop]: Abstraction has 222 states and 244 transitions. [2018-09-14 15:53:14,986 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-09-14 15:53:14,986 INFO L276 IsEmpty]: Start isEmpty. Operand 222 states and 244 transitions. [2018-09-14 15:53:14,987 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 222 [2018-09-14 15:53:14,988 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:14,988 INFO L376 BasicCegarLoop]: trace histogram [53, 53, 52, 31, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:14,988 INFO L423 AbstractCegarLoop]: === Iteration 34 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:14,988 INFO L82 PathProgramCache]: Analyzing trace with hash 1556190264, now seen corresponding path program 31 times [2018-09-14 15:53:14,988 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:14,989 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:14,989 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:14,989 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:14,996 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:15,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:15,817 INFO L134 CoverageAnalysis]: Checked inductivity of 5512 backedges. 2698 proven. 1953 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:15,817 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:15,817 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:15,825 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:53:15,825 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:53:15,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:15,886 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:15,921 INFO L134 CoverageAnalysis]: Checked inductivity of 5512 backedges. 2698 proven. 1953 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:15,921 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:16,805 INFO L134 CoverageAnalysis]: Checked inductivity of 5512 backedges. 2698 proven. 1953 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:16,825 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:16,826 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:16,840 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:53:16,840 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:53:16,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:16,962 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:16,999 INFO L134 CoverageAnalysis]: Checked inductivity of 5512 backedges. 2698 proven. 1953 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:17,000 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:17,297 INFO L134 CoverageAnalysis]: Checked inductivity of 5512 backedges. 2698 proven. 1953 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:17,299 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:17,299 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34, 34, 34, 34] total 52 [2018-09-14 15:53:17,299 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:17,299 INFO L459 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-09-14 15:53:17,300 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-09-14 15:53:17,300 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:17,300 INFO L87 Difference]: Start difference. First operand 222 states and 244 transitions. Second operand 34 states. [2018-09-14 15:53:17,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:17,511 INFO L93 Difference]: Finished difference Result 321 states and 366 transitions. [2018-09-14 15:53:17,511 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-09-14 15:53:17,511 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 221 [2018-09-14 15:53:17,512 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:17,512 INFO L225 Difference]: With dead ends: 321 [2018-09-14 15:53:17,512 INFO L226 Difference]: Without dead ends: 227 [2018-09-14 15:53:17,513 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 916 GetRequests, 838 SyntacticMatches, 28 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 686 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:17,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 227 states. [2018-09-14 15:53:17,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 227 to 226. [2018-09-14 15:53:17,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 226 states. [2018-09-14 15:53:17,533 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 226 states to 226 states and 248 transitions. [2018-09-14 15:53:17,533 INFO L78 Accepts]: Start accepts. Automaton has 226 states and 248 transitions. Word has length 221 [2018-09-14 15:53:17,533 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:17,533 INFO L480 AbstractCegarLoop]: Abstraction has 226 states and 248 transitions. [2018-09-14 15:53:17,533 INFO L481 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-09-14 15:53:17,533 INFO L276 IsEmpty]: Start isEmpty. Operand 226 states and 248 transitions. [2018-09-14 15:53:17,535 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 226 [2018-09-14 15:53:17,535 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:17,535 INFO L376 BasicCegarLoop]: trace histogram [54, 54, 53, 32, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:17,535 INFO L423 AbstractCegarLoop]: === Iteration 35 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:17,535 INFO L82 PathProgramCache]: Analyzing trace with hash 511325542, now seen corresponding path program 32 times [2018-09-14 15:53:17,535 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:17,536 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:17,536 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:53:17,536 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:17,537 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:17,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:19,445 INFO L134 CoverageAnalysis]: Checked inductivity of 5724 backedges. 2783 proven. 2080 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:19,445 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:19,446 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:19,453 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:53:19,454 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:19,519 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:53:19,519 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:19,522 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:19,557 INFO L134 CoverageAnalysis]: Checked inductivity of 5724 backedges. 2783 proven. 2080 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:19,558 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:20,413 INFO L134 CoverageAnalysis]: Checked inductivity of 5724 backedges. 2783 proven. 2080 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:20,432 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:20,432 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:20,447 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:53:20,447 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:20,574 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:53:20,574 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:20,579 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:20,620 INFO L134 CoverageAnalysis]: Checked inductivity of 5724 backedges. 2783 proven. 2080 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:20,620 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:20,950 INFO L134 CoverageAnalysis]: Checked inductivity of 5724 backedges. 2783 proven. 2080 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:20,952 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:20,952 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35, 35, 35, 35] total 52 [2018-09-14 15:53:20,952 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:20,953 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-09-14 15:53:20,953 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-09-14 15:53:20,953 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:20,954 INFO L87 Difference]: Start difference. First operand 226 states and 248 transitions. Second operand 35 states. [2018-09-14 15:53:21,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:21,096 INFO L93 Difference]: Finished difference Result 325 states and 370 transitions. [2018-09-14 15:53:21,096 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-09-14 15:53:21,097 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 225 [2018-09-14 15:53:21,097 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:21,098 INFO L225 Difference]: With dead ends: 325 [2018-09-14 15:53:21,098 INFO L226 Difference]: Without dead ends: 231 [2018-09-14 15:53:21,098 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 933 GetRequests, 851 SyntacticMatches, 32 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 784 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:21,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 231 states. [2018-09-14 15:53:21,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 231 to 230. [2018-09-14 15:53:21,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 230 states. [2018-09-14 15:53:21,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 252 transitions. [2018-09-14 15:53:21,124 INFO L78 Accepts]: Start accepts. Automaton has 230 states and 252 transitions. Word has length 225 [2018-09-14 15:53:21,124 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:21,124 INFO L480 AbstractCegarLoop]: Abstraction has 230 states and 252 transitions. [2018-09-14 15:53:21,124 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-09-14 15:53:21,124 INFO L276 IsEmpty]: Start isEmpty. Operand 230 states and 252 transitions. [2018-09-14 15:53:21,125 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 230 [2018-09-14 15:53:21,125 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:21,126 INFO L376 BasicCegarLoop]: trace histogram [55, 55, 54, 33, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:21,126 INFO L423 AbstractCegarLoop]: === Iteration 36 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:21,126 INFO L82 PathProgramCache]: Analyzing trace with hash 595758996, now seen corresponding path program 33 times [2018-09-14 15:53:21,126 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:21,127 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:21,127 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:21,127 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:21,127 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:21,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:22,133 INFO L134 CoverageAnalysis]: Checked inductivity of 5940 backedges. 2868 proven. 2211 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:22,133 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:22,133 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:22,141 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:53:22,142 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:53:22,234 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 55 check-sat command(s) [2018-09-14 15:53:22,234 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:22,238 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:23,434 INFO L134 CoverageAnalysis]: Checked inductivity of 5940 backedges. 4048 proven. 1807 refuted. 0 times theorem prover too weak. 85 trivial. 0 not checked. [2018-09-14 15:53:23,434 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:24,635 INFO L134 CoverageAnalysis]: Checked inductivity of 5940 backedges. 4048 proven. 1807 refuted. 0 times theorem prover too weak. 85 trivial. 0 not checked. [2018-09-14 15:53:24,655 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:24,655 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:24,670 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:53:24,670 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:53:25,512 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 55 check-sat command(s) [2018-09-14 15:53:25,512 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:25,519 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:25,568 INFO L134 CoverageAnalysis]: Checked inductivity of 5940 backedges. 2868 proven. 2211 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:25,568 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:26,896 INFO L134 CoverageAnalysis]: Checked inductivity of 5940 backedges. 2868 proven. 2211 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-09-14 15:53:26,897 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:26,898 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36, 36, 36, 36] total 97 [2018-09-14 15:53:26,898 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:26,898 INFO L459 AbstractCegarLoop]: Interpolant automaton has 70 states [2018-09-14 15:53:26,899 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2018-09-14 15:53:26,900 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=2406, Invalid=6906, Unknown=0, NotChecked=0, Total=9312 [2018-09-14 15:53:26,900 INFO L87 Difference]: Start difference. First operand 230 states and 252 transitions. Second operand 70 states. [2018-09-14 15:53:29,288 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:29,289 INFO L93 Difference]: Finished difference Result 1397 states and 1718 transitions. [2018-09-14 15:53:29,289 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 103 states. [2018-09-14 15:53:29,289 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 229 [2018-09-14 15:53:29,289 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:29,294 INFO L225 Difference]: With dead ends: 1397 [2018-09-14 15:53:29,294 INFO L226 Difference]: Without dead ends: 1303 [2018-09-14 15:53:29,296 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1017 GetRequests, 793 SyntacticMatches, 62 SemanticMatches, 162 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8978 ImplicationChecksByTransitivity, 5.4s TimeCoverageRelationStatistics Valid=6793, Invalid=19939, Unknown=0, NotChecked=0, Total=26732 [2018-09-14 15:53:29,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1303 states. [2018-09-14 15:53:29,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1303 to 282. [2018-09-14 15:53:29,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 282 states. [2018-09-14 15:53:29,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 282 states to 282 states and 316 transitions. [2018-09-14 15:53:29,372 INFO L78 Accepts]: Start accepts. Automaton has 282 states and 316 transitions. Word has length 229 [2018-09-14 15:53:29,372 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:29,372 INFO L480 AbstractCegarLoop]: Abstraction has 282 states and 316 transitions. [2018-09-14 15:53:29,372 INFO L481 AbstractCegarLoop]: Interpolant automaton has 70 states. [2018-09-14 15:53:29,372 INFO L276 IsEmpty]: Start isEmpty. Operand 282 states and 316 transitions. [2018-09-14 15:53:29,373 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 282 [2018-09-14 15:53:29,373 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:29,373 INFO L376 BasicCegarLoop]: trace histogram [68, 68, 67, 34, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:29,373 INFO L423 AbstractCegarLoop]: === Iteration 37 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:29,374 INFO L82 PathProgramCache]: Analyzing trace with hash -760881198, now seen corresponding path program 34 times [2018-09-14 15:53:29,374 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:29,374 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:29,374 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:29,375 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:29,375 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:29,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:32,066 INFO L134 CoverageAnalysis]: Checked inductivity of 9112 backedges. 4621 proven. 2346 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:32,066 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:32,066 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:32,073 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:53:32,074 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:53:32,141 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:53:32,142 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:32,145 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:32,201 INFO L134 CoverageAnalysis]: Checked inductivity of 9112 backedges. 4621 proven. 2346 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:32,202 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:33,411 INFO L134 CoverageAnalysis]: Checked inductivity of 9112 backedges. 4621 proven. 2346 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:33,431 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:33,431 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 69 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:33,447 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:53:33,447 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:53:33,615 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:53:33,615 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:33,623 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:33,680 INFO L134 CoverageAnalysis]: Checked inductivity of 9112 backedges. 4621 proven. 2346 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:33,680 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:34,135 INFO L134 CoverageAnalysis]: Checked inductivity of 9112 backedges. 4621 proven. 2346 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:34,137 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:34,137 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37, 37, 37, 37] total 52 [2018-09-14 15:53:34,137 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:34,137 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-09-14 15:53:34,138 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-09-14 15:53:34,138 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:34,138 INFO L87 Difference]: Start difference. First operand 282 states and 316 transitions. Second operand 37 states. [2018-09-14 15:53:34,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:34,308 INFO L93 Difference]: Finished difference Result 429 states and 498 transitions. [2018-09-14 15:53:34,309 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-09-14 15:53:34,309 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 281 [2018-09-14 15:53:34,309 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:34,310 INFO L225 Difference]: With dead ends: 429 [2018-09-14 15:53:34,311 INFO L226 Difference]: Without dead ends: 287 [2018-09-14 15:53:34,311 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1159 GetRequests, 1069 SyntacticMatches, 40 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 980 ImplicationChecksByTransitivity, 4.1s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:34,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 287 states. [2018-09-14 15:53:34,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 287 to 286. [2018-09-14 15:53:34,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 286 states. [2018-09-14 15:53:34,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 286 states to 286 states and 320 transitions. [2018-09-14 15:53:34,385 INFO L78 Accepts]: Start accepts. Automaton has 286 states and 320 transitions. Word has length 281 [2018-09-14 15:53:34,386 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:34,386 INFO L480 AbstractCegarLoop]: Abstraction has 286 states and 320 transitions. [2018-09-14 15:53:34,386 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-09-14 15:53:34,386 INFO L276 IsEmpty]: Start isEmpty. Operand 286 states and 320 transitions. [2018-09-14 15:53:34,388 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 286 [2018-09-14 15:53:34,388 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:34,388 INFO L376 BasicCegarLoop]: trace histogram [69, 69, 68, 35, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:34,388 INFO L423 AbstractCegarLoop]: === Iteration 38 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:34,389 INFO L82 PathProgramCache]: Analyzing trace with hash -344860672, now seen corresponding path program 35 times [2018-09-14 15:53:34,389 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:34,389 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:34,389 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:34,389 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:34,390 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:34,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:35,103 INFO L134 CoverageAnalysis]: Checked inductivity of 9384 backedges. 4754 proven. 2485 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:35,103 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:35,103 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:35,111 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:53:35,112 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:35,235 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 69 check-sat command(s) [2018-09-14 15:53:35,236 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:35,240 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:35,291 INFO L134 CoverageAnalysis]: Checked inductivity of 9384 backedges. 4754 proven. 2485 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:35,291 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:36,172 INFO L134 CoverageAnalysis]: Checked inductivity of 9384 backedges. 4754 proven. 2485 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:36,192 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:36,193 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:36,208 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:53:36,208 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:37,378 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 69 check-sat command(s) [2018-09-14 15:53:37,378 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:37,385 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:37,436 INFO L134 CoverageAnalysis]: Checked inductivity of 9384 backedges. 4754 proven. 2485 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:37,437 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:38,107 INFO L134 CoverageAnalysis]: Checked inductivity of 9384 backedges. 4754 proven. 2485 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:38,109 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:38,109 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38, 38, 38, 38] total 52 [2018-09-14 15:53:38,109 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:38,110 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-09-14 15:53:38,110 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-09-14 15:53:38,111 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:38,111 INFO L87 Difference]: Start difference. First operand 286 states and 320 transitions. Second operand 38 states. [2018-09-14 15:53:38,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:38,317 INFO L93 Difference]: Finished difference Result 433 states and 502 transitions. [2018-09-14 15:53:38,318 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-09-14 15:53:38,318 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 285 [2018-09-14 15:53:38,318 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:38,320 INFO L225 Difference]: With dead ends: 433 [2018-09-14 15:53:38,320 INFO L226 Difference]: Without dead ends: 291 [2018-09-14 15:53:38,321 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1176 GetRequests, 1082 SyntacticMatches, 44 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1078 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:38,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 291 states. [2018-09-14 15:53:38,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 291 to 290. [2018-09-14 15:53:38,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 290 states. [2018-09-14 15:53:38,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 290 states to 290 states and 324 transitions. [2018-09-14 15:53:38,434 INFO L78 Accepts]: Start accepts. Automaton has 290 states and 324 transitions. Word has length 285 [2018-09-14 15:53:38,434 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:38,434 INFO L480 AbstractCegarLoop]: Abstraction has 290 states and 324 transitions. [2018-09-14 15:53:38,434 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-09-14 15:53:38,435 INFO L276 IsEmpty]: Start isEmpty. Operand 290 states and 324 transitions. [2018-09-14 15:53:38,436 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 290 [2018-09-14 15:53:38,436 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:38,436 INFO L376 BasicCegarLoop]: trace histogram [70, 70, 69, 36, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:38,437 INFO L423 AbstractCegarLoop]: === Iteration 39 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:38,437 INFO L82 PathProgramCache]: Analyzing trace with hash 1342834990, now seen corresponding path program 36 times [2018-09-14 15:53:38,437 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:38,438 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:38,438 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:38,438 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:38,438 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:38,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:40,604 INFO L134 CoverageAnalysis]: Checked inductivity of 9660 backedges. 4887 proven. 2628 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:40,604 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:40,604 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:40,611 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:53:40,612 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:53:40,729 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 68 check-sat command(s) [2018-09-14 15:53:40,729 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:40,733 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:40,801 INFO L134 CoverageAnalysis]: Checked inductivity of 9660 backedges. 4887 proven. 2628 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:40,801 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:41,703 INFO L134 CoverageAnalysis]: Checked inductivity of 9660 backedges. 4887 proven. 2628 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:41,723 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:41,723 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:41,737 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:53:41,738 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:53:42,963 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 68 check-sat command(s) [2018-09-14 15:53:42,963 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:42,970 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:43,023 INFO L134 CoverageAnalysis]: Checked inductivity of 9660 backedges. 4887 proven. 2628 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:43,023 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:43,661 INFO L134 CoverageAnalysis]: Checked inductivity of 9660 backedges. 4887 proven. 2628 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:43,662 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:43,662 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39, 39, 39, 39] total 52 [2018-09-14 15:53:43,662 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:43,663 INFO L459 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-09-14 15:53:43,663 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-09-14 15:53:43,664 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:43,664 INFO L87 Difference]: Start difference. First operand 290 states and 324 transitions. Second operand 39 states. [2018-09-14 15:53:43,837 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:43,837 INFO L93 Difference]: Finished difference Result 437 states and 506 transitions. [2018-09-14 15:53:43,837 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-09-14 15:53:43,837 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 289 [2018-09-14 15:53:43,838 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:43,839 INFO L225 Difference]: With dead ends: 437 [2018-09-14 15:53:43,839 INFO L226 Difference]: Without dead ends: 295 [2018-09-14 15:53:43,839 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1193 GetRequests, 1095 SyntacticMatches, 48 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1176 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:43,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 295 states. [2018-09-14 15:53:43,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 295 to 294. [2018-09-14 15:53:43,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 294 states. [2018-09-14 15:53:43,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 294 states to 294 states and 328 transitions. [2018-09-14 15:53:43,900 INFO L78 Accepts]: Start accepts. Automaton has 294 states and 328 transitions. Word has length 289 [2018-09-14 15:53:43,900 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:43,900 INFO L480 AbstractCegarLoop]: Abstraction has 294 states and 328 transitions. [2018-09-14 15:53:43,900 INFO L481 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-09-14 15:53:43,901 INFO L276 IsEmpty]: Start isEmpty. Operand 294 states and 328 transitions. [2018-09-14 15:53:43,902 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 294 [2018-09-14 15:53:43,902 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:43,902 INFO L376 BasicCegarLoop]: trace histogram [71, 71, 70, 37, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:43,902 INFO L423 AbstractCegarLoop]: === Iteration 40 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:43,902 INFO L82 PathProgramCache]: Analyzing trace with hash 1571418972, now seen corresponding path program 37 times [2018-09-14 15:53:43,903 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:43,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:43,903 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:43,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:43,903 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:43,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:45,292 INFO L134 CoverageAnalysis]: Checked inductivity of 9940 backedges. 5020 proven. 2775 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:45,292 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:45,292 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:45,300 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:53:45,300 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:53:45,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:45,378 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:45,433 INFO L134 CoverageAnalysis]: Checked inductivity of 9940 backedges. 5020 proven. 2775 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:45,433 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:46,321 INFO L134 CoverageAnalysis]: Checked inductivity of 9940 backedges. 5020 proven. 2775 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:46,341 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:46,341 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 75 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:46,356 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:53:46,356 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:53:46,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:46,517 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:46,563 INFO L134 CoverageAnalysis]: Checked inductivity of 9940 backedges. 5020 proven. 2775 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:46,563 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:47,125 INFO L134 CoverageAnalysis]: Checked inductivity of 9940 backedges. 5020 proven. 2775 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:47,127 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:47,127 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40, 40, 40, 40] total 52 [2018-09-14 15:53:47,127 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:47,127 INFO L459 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-09-14 15:53:47,128 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-09-14 15:53:47,128 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:47,128 INFO L87 Difference]: Start difference. First operand 294 states and 328 transitions. Second operand 40 states. [2018-09-14 15:53:47,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:47,301 INFO L93 Difference]: Finished difference Result 441 states and 510 transitions. [2018-09-14 15:53:47,301 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-09-14 15:53:47,301 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 293 [2018-09-14 15:53:47,301 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:47,302 INFO L225 Difference]: With dead ends: 441 [2018-09-14 15:53:47,302 INFO L226 Difference]: Without dead ends: 299 [2018-09-14 15:53:47,303 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1210 GetRequests, 1108 SyntacticMatches, 52 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1274 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:47,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 299 states. [2018-09-14 15:53:47,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 299 to 298. [2018-09-14 15:53:47,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 298 states. [2018-09-14 15:53:47,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 298 states to 298 states and 332 transitions. [2018-09-14 15:53:47,369 INFO L78 Accepts]: Start accepts. Automaton has 298 states and 332 transitions. Word has length 293 [2018-09-14 15:53:47,370 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:47,370 INFO L480 AbstractCegarLoop]: Abstraction has 298 states and 332 transitions. [2018-09-14 15:53:47,370 INFO L481 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-09-14 15:53:47,370 INFO L276 IsEmpty]: Start isEmpty. Operand 298 states and 332 transitions. [2018-09-14 15:53:47,371 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 298 [2018-09-14 15:53:47,371 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:47,372 INFO L376 BasicCegarLoop]: trace histogram [72, 72, 71, 38, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:47,372 INFO L423 AbstractCegarLoop]: === Iteration 41 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:47,372 INFO L82 PathProgramCache]: Analyzing trace with hash 1741493898, now seen corresponding path program 38 times [2018-09-14 15:53:47,372 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:47,373 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:47,373 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:53:47,373 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:47,373 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:47,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:48,262 INFO L134 CoverageAnalysis]: Checked inductivity of 10224 backedges. 5153 proven. 2926 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:48,262 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:48,262 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:48,269 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:53:48,269 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:48,369 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:53:48,370 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:48,373 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:48,429 INFO L134 CoverageAnalysis]: Checked inductivity of 10224 backedges. 5153 proven. 2926 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:48,429 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:49,342 INFO L134 CoverageAnalysis]: Checked inductivity of 10224 backedges. 5153 proven. 2926 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:49,362 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:49,362 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 77 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:49,377 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:53:49,378 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:49,543 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:53:49,543 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:49,549 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:49,597 INFO L134 CoverageAnalysis]: Checked inductivity of 10224 backedges. 5153 proven. 2926 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:49,597 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:50,169 INFO L134 CoverageAnalysis]: Checked inductivity of 10224 backedges. 5153 proven. 2926 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:50,171 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:50,171 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41, 41, 41, 41] total 52 [2018-09-14 15:53:50,172 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:50,172 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-09-14 15:53:50,172 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-09-14 15:53:50,173 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:50,173 INFO L87 Difference]: Start difference. First operand 298 states and 332 transitions. Second operand 41 states. [2018-09-14 15:53:50,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:50,350 INFO L93 Difference]: Finished difference Result 445 states and 514 transitions. [2018-09-14 15:53:50,351 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-09-14 15:53:50,351 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 297 [2018-09-14 15:53:50,351 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:50,352 INFO L225 Difference]: With dead ends: 445 [2018-09-14 15:53:50,352 INFO L226 Difference]: Without dead ends: 303 [2018-09-14 15:53:50,353 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1227 GetRequests, 1121 SyntacticMatches, 56 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1372 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:50,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 303 states. [2018-09-14 15:53:50,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 303 to 302. [2018-09-14 15:53:50,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 302 states. [2018-09-14 15:53:50,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 302 states to 302 states and 336 transitions. [2018-09-14 15:53:50,416 INFO L78 Accepts]: Start accepts. Automaton has 302 states and 336 transitions. Word has length 297 [2018-09-14 15:53:50,417 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:50,417 INFO L480 AbstractCegarLoop]: Abstraction has 302 states and 336 transitions. [2018-09-14 15:53:50,417 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-09-14 15:53:50,417 INFO L276 IsEmpty]: Start isEmpty. Operand 302 states and 336 transitions. [2018-09-14 15:53:50,418 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 302 [2018-09-14 15:53:50,418 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:50,418 INFO L376 BasicCegarLoop]: trace histogram [73, 73, 72, 39, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:50,419 INFO L423 AbstractCegarLoop]: === Iteration 42 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:50,419 INFO L82 PathProgramCache]: Analyzing trace with hash -1741753672, now seen corresponding path program 39 times [2018-09-14 15:53:50,419 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:50,419 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:50,420 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:50,420 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:50,420 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:50,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:51,711 INFO L134 CoverageAnalysis]: Checked inductivity of 10512 backedges. 5286 proven. 3081 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:51,711 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:51,711 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:51,719 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:53:51,719 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:53:51,852 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 73 check-sat command(s) [2018-09-14 15:53:51,852 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:51,856 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:51,937 INFO L134 CoverageAnalysis]: Checked inductivity of 10512 backedges. 5286 proven. 3081 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:51,937 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:52,919 INFO L134 CoverageAnalysis]: Checked inductivity of 10512 backedges. 5286 proven. 3081 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:52,939 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:52,939 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 79 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:52,954 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:53:52,955 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:53:54,356 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 73 check-sat command(s) [2018-09-14 15:53:54,357 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:54,365 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:54,423 INFO L134 CoverageAnalysis]: Checked inductivity of 10512 backedges. 5286 proven. 3081 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:54,424 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:55,058 INFO L134 CoverageAnalysis]: Checked inductivity of 10512 backedges. 5286 proven. 3081 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:55,060 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:55,060 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42, 42, 42, 42] total 52 [2018-09-14 15:53:55,060 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:55,061 INFO L459 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-09-14 15:53:55,061 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-09-14 15:53:55,061 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:55,061 INFO L87 Difference]: Start difference. First operand 302 states and 336 transitions. Second operand 42 states. [2018-09-14 15:53:55,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:55,264 INFO L93 Difference]: Finished difference Result 449 states and 518 transitions. [2018-09-14 15:53:55,264 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-09-14 15:53:55,264 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 301 [2018-09-14 15:53:55,265 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:55,266 INFO L225 Difference]: With dead ends: 449 [2018-09-14 15:53:55,266 INFO L226 Difference]: Without dead ends: 307 [2018-09-14 15:53:55,267 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1244 GetRequests, 1134 SyntacticMatches, 60 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1470 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:55,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 307 states. [2018-09-14 15:53:55,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 307 to 306. [2018-09-14 15:53:55,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 306 states. [2018-09-14 15:53:55,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 306 states to 306 states and 340 transitions. [2018-09-14 15:53:55,321 INFO L78 Accepts]: Start accepts. Automaton has 306 states and 340 transitions. Word has length 301 [2018-09-14 15:53:55,322 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:55,322 INFO L480 AbstractCegarLoop]: Abstraction has 306 states and 340 transitions. [2018-09-14 15:53:55,322 INFO L481 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-09-14 15:53:55,322 INFO L276 IsEmpty]: Start isEmpty. Operand 306 states and 340 transitions. [2018-09-14 15:53:55,323 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 306 [2018-09-14 15:53:55,323 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:55,323 INFO L376 BasicCegarLoop]: trace histogram [74, 74, 73, 40, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:55,323 INFO L423 AbstractCegarLoop]: === Iteration 43 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:55,324 INFO L82 PathProgramCache]: Analyzing trace with hash -825554970, now seen corresponding path program 40 times [2018-09-14 15:53:55,324 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:55,324 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:55,324 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:55,324 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:55,325 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:55,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:56,199 INFO L134 CoverageAnalysis]: Checked inductivity of 10804 backedges. 5419 proven. 3240 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:56,199 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:56,199 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:56,206 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:53:56,206 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:53:56,285 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:53:56,286 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:56,289 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:56,349 INFO L134 CoverageAnalysis]: Checked inductivity of 10804 backedges. 5419 proven. 3240 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:56,349 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:57,485 INFO L134 CoverageAnalysis]: Checked inductivity of 10804 backedges. 5419 proven. 3240 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:57,505 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:57,505 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 81 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:57,520 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:53:57,520 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:53:57,703 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:53:57,703 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:57,710 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:57,769 INFO L134 CoverageAnalysis]: Checked inductivity of 10804 backedges. 5419 proven. 3240 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:57,769 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:58,514 INFO L134 CoverageAnalysis]: Checked inductivity of 10804 backedges. 5419 proven. 3240 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:58,516 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:58,516 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43, 43, 43, 43] total 52 [2018-09-14 15:53:58,516 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:58,517 INFO L459 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-09-14 15:53:58,517 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-09-14 15:53:58,517 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:58,517 INFO L87 Difference]: Start difference. First operand 306 states and 340 transitions. Second operand 43 states. [2018-09-14 15:53:58,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:58,806 INFO L93 Difference]: Finished difference Result 453 states and 522 transitions. [2018-09-14 15:53:58,809 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-09-14 15:53:58,810 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 305 [2018-09-14 15:53:58,810 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:58,811 INFO L225 Difference]: With dead ends: 453 [2018-09-14 15:53:58,811 INFO L226 Difference]: Without dead ends: 311 [2018-09-14 15:53:58,812 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1261 GetRequests, 1147 SyntacticMatches, 64 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1568 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:53:58,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 311 states. [2018-09-14 15:53:58,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 311 to 310. [2018-09-14 15:53:58,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 310 states. [2018-09-14 15:53:58,903 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 310 states to 310 states and 344 transitions. [2018-09-14 15:53:58,904 INFO L78 Accepts]: Start accepts. Automaton has 310 states and 344 transitions. Word has length 305 [2018-09-14 15:53:58,904 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:58,904 INFO L480 AbstractCegarLoop]: Abstraction has 310 states and 344 transitions. [2018-09-14 15:53:58,904 INFO L481 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-09-14 15:53:58,904 INFO L276 IsEmpty]: Start isEmpty. Operand 310 states and 344 transitions. [2018-09-14 15:53:58,907 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 310 [2018-09-14 15:53:58,907 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:58,908 INFO L376 BasicCegarLoop]: trace histogram [75, 75, 74, 41, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:58,908 INFO L423 AbstractCegarLoop]: === Iteration 44 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:58,908 INFO L82 PathProgramCache]: Analyzing trace with hash -2116233708, now seen corresponding path program 41 times [2018-09-14 15:53:58,908 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:58,909 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:58,909 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:58,909 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:58,909 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:58,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:59,926 INFO L134 CoverageAnalysis]: Checked inductivity of 11100 backedges. 5552 proven. 3403 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:53:59,927 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:59,927 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:59,934 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:53:59,934 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:54:00,074 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 75 check-sat command(s) [2018-09-14 15:54:00,074 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:00,078 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:00,140 INFO L134 CoverageAnalysis]: Checked inductivity of 11100 backedges. 5552 proven. 3403 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:54:00,141 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:01,103 INFO L134 CoverageAnalysis]: Checked inductivity of 11100 backedges. 5552 proven. 3403 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:54:01,124 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:01,124 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 83 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 83 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:01,139 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:54:01,139 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:54:02,504 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 75 check-sat command(s) [2018-09-14 15:54:02,504 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:02,512 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:02,586 INFO L134 CoverageAnalysis]: Checked inductivity of 11100 backedges. 5552 proven. 3403 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:54:02,587 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:03,261 INFO L134 CoverageAnalysis]: Checked inductivity of 11100 backedges. 5552 proven. 3403 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:54:03,262 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:03,263 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44, 44, 44, 44] total 52 [2018-09-14 15:54:03,263 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:03,263 INFO L459 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-09-14 15:54:03,264 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-09-14 15:54:03,264 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:03,264 INFO L87 Difference]: Start difference. First operand 310 states and 344 transitions. Second operand 44 states. [2018-09-14 15:54:03,469 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:03,470 INFO L93 Difference]: Finished difference Result 457 states and 526 transitions. [2018-09-14 15:54:03,470 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-09-14 15:54:03,470 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 309 [2018-09-14 15:54:03,470 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:03,471 INFO L225 Difference]: With dead ends: 457 [2018-09-14 15:54:03,471 INFO L226 Difference]: Without dead ends: 315 [2018-09-14 15:54:03,472 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1278 GetRequests, 1160 SyntacticMatches, 68 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1666 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:03,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 315 states. [2018-09-14 15:54:03,524 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 315 to 314. [2018-09-14 15:54:03,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 314 states. [2018-09-14 15:54:03,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 314 states to 314 states and 348 transitions. [2018-09-14 15:54:03,525 INFO L78 Accepts]: Start accepts. Automaton has 314 states and 348 transitions. Word has length 309 [2018-09-14 15:54:03,525 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:03,525 INFO L480 AbstractCegarLoop]: Abstraction has 314 states and 348 transitions. [2018-09-14 15:54:03,525 INFO L481 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-09-14 15:54:03,525 INFO L276 IsEmpty]: Start isEmpty. Operand 314 states and 348 transitions. [2018-09-14 15:54:03,527 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 314 [2018-09-14 15:54:03,527 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:03,527 INFO L376 BasicCegarLoop]: trace histogram [76, 76, 75, 42, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:03,528 INFO L423 AbstractCegarLoop]: === Iteration 45 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:03,528 INFO L82 PathProgramCache]: Analyzing trace with hash -1646273214, now seen corresponding path program 42 times [2018-09-14 15:54:03,528 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:03,529 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:03,529 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:03,529 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:03,529 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:03,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:04,578 INFO L134 CoverageAnalysis]: Checked inductivity of 11400 backedges. 5685 proven. 3570 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:54:04,578 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:04,578 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:04,586 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:54:04,586 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:54:04,717 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 73 check-sat command(s) [2018-09-14 15:54:04,717 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:04,722 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:04,785 INFO L134 CoverageAnalysis]: Checked inductivity of 11400 backedges. 5685 proven. 3570 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:54:04,785 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:05,766 INFO L134 CoverageAnalysis]: Checked inductivity of 11400 backedges. 5685 proven. 3570 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:54:05,786 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:05,786 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 85 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 85 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:05,801 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:54:05,801 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:54:07,194 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 73 check-sat command(s) [2018-09-14 15:54:07,195 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:07,202 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:07,265 INFO L134 CoverageAnalysis]: Checked inductivity of 11400 backedges. 5685 proven. 3570 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:54:07,266 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:07,970 INFO L134 CoverageAnalysis]: Checked inductivity of 11400 backedges. 5685 proven. 3570 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:54:07,972 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:07,972 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45, 45, 45, 45] total 52 [2018-09-14 15:54:07,972 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:07,973 INFO L459 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-09-14 15:54:07,973 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-09-14 15:54:07,973 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:07,973 INFO L87 Difference]: Start difference. First operand 314 states and 348 transitions. Second operand 45 states. [2018-09-14 15:54:08,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:08,160 INFO L93 Difference]: Finished difference Result 461 states and 530 transitions. [2018-09-14 15:54:08,160 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-09-14 15:54:08,160 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 313 [2018-09-14 15:54:08,161 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:08,162 INFO L225 Difference]: With dead ends: 461 [2018-09-14 15:54:08,162 INFO L226 Difference]: Without dead ends: 319 [2018-09-14 15:54:08,162 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1295 GetRequests, 1173 SyntacticMatches, 72 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1764 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:08,162 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 319 states. [2018-09-14 15:54:08,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 319 to 318. [2018-09-14 15:54:08,214 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 318 states. [2018-09-14 15:54:08,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 318 states to 318 states and 352 transitions. [2018-09-14 15:54:08,215 INFO L78 Accepts]: Start accepts. Automaton has 318 states and 352 transitions. Word has length 313 [2018-09-14 15:54:08,215 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:08,215 INFO L480 AbstractCegarLoop]: Abstraction has 318 states and 352 transitions. [2018-09-14 15:54:08,215 INFO L481 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-09-14 15:54:08,215 INFO L276 IsEmpty]: Start isEmpty. Operand 318 states and 352 transitions. [2018-09-14 15:54:08,216 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 318 [2018-09-14 15:54:08,216 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:08,217 INFO L376 BasicCegarLoop]: trace histogram [77, 77, 76, 43, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:08,217 INFO L423 AbstractCegarLoop]: === Iteration 46 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:08,217 INFO L82 PathProgramCache]: Analyzing trace with hash 1703910768, now seen corresponding path program 43 times [2018-09-14 15:54:08,217 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:08,218 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:08,218 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:08,218 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:08,218 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:08,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:09,418 INFO L134 CoverageAnalysis]: Checked inductivity of 11704 backedges. 5818 proven. 3741 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:54:09,418 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:09,418 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:09,426 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:54:09,426 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:54:09,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:09,513 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:09,579 INFO L134 CoverageAnalysis]: Checked inductivity of 11704 backedges. 5818 proven. 3741 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:54:09,579 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:10,527 INFO L134 CoverageAnalysis]: Checked inductivity of 11704 backedges. 5818 proven. 3741 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:54:10,547 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:10,547 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 87 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 87 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:10,575 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:54:10,576 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:54:10,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:10,749 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:10,815 INFO L134 CoverageAnalysis]: Checked inductivity of 11704 backedges. 5818 proven. 3741 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:54:10,815 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:11,553 INFO L134 CoverageAnalysis]: Checked inductivity of 11704 backedges. 5818 proven. 3741 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:54:11,554 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:11,555 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46, 46, 46, 46] total 52 [2018-09-14 15:54:11,555 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:11,556 INFO L459 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-09-14 15:54:11,556 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-09-14 15:54:11,556 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:11,556 INFO L87 Difference]: Start difference. First operand 318 states and 352 transitions. Second operand 46 states. [2018-09-14 15:54:11,772 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:11,772 INFO L93 Difference]: Finished difference Result 465 states and 534 transitions. [2018-09-14 15:54:11,773 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-09-14 15:54:11,773 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 317 [2018-09-14 15:54:11,773 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:11,774 INFO L225 Difference]: With dead ends: 465 [2018-09-14 15:54:11,774 INFO L226 Difference]: Without dead ends: 323 [2018-09-14 15:54:11,775 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1312 GetRequests, 1186 SyntacticMatches, 76 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1862 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:11,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 323 states. [2018-09-14 15:54:11,848 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 323 to 322. [2018-09-14 15:54:11,849 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 322 states. [2018-09-14 15:54:11,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 322 states to 322 states and 356 transitions. [2018-09-14 15:54:11,850 INFO L78 Accepts]: Start accepts. Automaton has 322 states and 356 transitions. Word has length 317 [2018-09-14 15:54:11,850 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:11,850 INFO L480 AbstractCegarLoop]: Abstraction has 322 states and 356 transitions. [2018-09-14 15:54:11,850 INFO L481 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-09-14 15:54:11,850 INFO L276 IsEmpty]: Start isEmpty. Operand 322 states and 356 transitions. [2018-09-14 15:54:11,852 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 322 [2018-09-14 15:54:11,852 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:11,852 INFO L376 BasicCegarLoop]: trace histogram [78, 78, 77, 44, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:11,853 INFO L423 AbstractCegarLoop]: === Iteration 47 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:11,853 INFO L82 PathProgramCache]: Analyzing trace with hash 1374131870, now seen corresponding path program 44 times [2018-09-14 15:54:11,853 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:11,853 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:11,854 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:54:11,854 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:11,854 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:11,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:12,900 INFO L134 CoverageAnalysis]: Checked inductivity of 12012 backedges. 5951 proven. 3916 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:54:12,901 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:12,901 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:12,909 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:54:12,909 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:54:12,993 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:54:12,994 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:12,997 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:13,066 INFO L134 CoverageAnalysis]: Checked inductivity of 12012 backedges. 5951 proven. 3916 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:54:13,067 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:14,274 INFO L134 CoverageAnalysis]: Checked inductivity of 12012 backedges. 5951 proven. 3916 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:54:14,294 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:14,294 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 89 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 89 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:14,309 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:54:14,309 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:54:14,491 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:54:14,491 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:14,500 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:14,594 INFO L134 CoverageAnalysis]: Checked inductivity of 12012 backedges. 5951 proven. 3916 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:54:14,595 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:15,380 INFO L134 CoverageAnalysis]: Checked inductivity of 12012 backedges. 5951 proven. 3916 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:54:15,382 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:15,382 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47, 47, 47, 47] total 52 [2018-09-14 15:54:15,382 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:15,383 INFO L459 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-09-14 15:54:15,383 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-09-14 15:54:15,383 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:15,383 INFO L87 Difference]: Start difference. First operand 322 states and 356 transitions. Second operand 47 states. [2018-09-14 15:54:15,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:15,607 INFO L93 Difference]: Finished difference Result 469 states and 538 transitions. [2018-09-14 15:54:15,607 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-09-14 15:54:15,607 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 321 [2018-09-14 15:54:15,608 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:15,609 INFO L225 Difference]: With dead ends: 469 [2018-09-14 15:54:15,609 INFO L226 Difference]: Without dead ends: 327 [2018-09-14 15:54:15,609 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1329 GetRequests, 1199 SyntacticMatches, 80 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1960 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:15,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states. [2018-09-14 15:54:15,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 326. [2018-09-14 15:54:15,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 326 states. [2018-09-14 15:54:15,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 326 states to 326 states and 360 transitions. [2018-09-14 15:54:15,666 INFO L78 Accepts]: Start accepts. Automaton has 326 states and 360 transitions. Word has length 321 [2018-09-14 15:54:15,666 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:15,666 INFO L480 AbstractCegarLoop]: Abstraction has 326 states and 360 transitions. [2018-09-14 15:54:15,666 INFO L481 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-09-14 15:54:15,666 INFO L276 IsEmpty]: Start isEmpty. Operand 326 states and 360 transitions. [2018-09-14 15:54:15,668 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 326 [2018-09-14 15:54:15,668 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:15,669 INFO L376 BasicCegarLoop]: trace histogram [79, 79, 78, 45, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:15,669 INFO L423 AbstractCegarLoop]: === Iteration 48 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:15,669 INFO L82 PathProgramCache]: Analyzing trace with hash -232568628, now seen corresponding path program 45 times [2018-09-14 15:54:15,669 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:15,670 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:15,670 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:15,670 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:15,670 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:15,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:16,887 INFO L134 CoverageAnalysis]: Checked inductivity of 12324 backedges. 6084 proven. 4095 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:54:16,887 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:16,887 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:16,894 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:54:16,895 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:54:17,057 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 79 check-sat command(s) [2018-09-14 15:54:17,057 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:17,062 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:18,709 INFO L134 CoverageAnalysis]: Checked inductivity of 12324 backedges. 7768 proven. 4423 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-09-14 15:54:18,710 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:21,435 INFO L134 CoverageAnalysis]: Checked inductivity of 12324 backedges. 7768 proven. 4423 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-09-14 15:54:21,455 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:21,456 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 91 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 91 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:21,470 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:54:21,470 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:54:23,067 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 79 check-sat command(s) [2018-09-14 15:54:23,068 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:23,076 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:23,142 INFO L134 CoverageAnalysis]: Checked inductivity of 12324 backedges. 6084 proven. 4095 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:54:23,142 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:24,540 INFO L134 CoverageAnalysis]: Checked inductivity of 12324 backedges. 6084 proven. 4095 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-09-14 15:54:24,542 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:24,542 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48, 48, 48] total 109 [2018-09-14 15:54:24,543 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:24,543 INFO L459 AbstractCegarLoop]: Interpolant automaton has 94 states [2018-09-14 15:54:24,544 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 94 interpolants. [2018-09-14 15:54:24,545 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=3036, Invalid=8736, Unknown=0, NotChecked=0, Total=11772 [2018-09-14 15:54:24,545 INFO L87 Difference]: Start difference. First operand 326 states and 360 transitions. Second operand 94 states. [2018-09-14 15:54:27,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:27,492 INFO L93 Difference]: Finished difference Result 2117 states and 2606 transitions. [2018-09-14 15:54:27,492 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 139 states. [2018-09-14 15:54:27,492 INFO L78 Accepts]: Start accepts. Automaton has 94 states. Word has length 325 [2018-09-14 15:54:27,492 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:27,498 INFO L225 Difference]: With dead ends: 2117 [2018-09-14 15:54:27,498 INFO L226 Difference]: Without dead ends: 1975 [2018-09-14 15:54:27,500 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1437 GetRequests, 1129 SyntacticMatches, 110 SemanticMatches, 198 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15758 ImplicationChecksByTransitivity, 7.9s TimeCoverageRelationStatistics Valid=8995, Invalid=30805, Unknown=0, NotChecked=0, Total=39800 [2018-09-14 15:54:27,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1975 states. [2018-09-14 15:54:27,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1975 to 378. [2018-09-14 15:54:27,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 378 states. [2018-09-14 15:54:27,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 378 states to 378 states and 424 transitions. [2018-09-14 15:54:27,640 INFO L78 Accepts]: Start accepts. Automaton has 378 states and 424 transitions. Word has length 325 [2018-09-14 15:54:27,640 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:27,640 INFO L480 AbstractCegarLoop]: Abstraction has 378 states and 424 transitions. [2018-09-14 15:54:27,640 INFO L481 AbstractCegarLoop]: Interpolant automaton has 94 states. [2018-09-14 15:54:27,640 INFO L276 IsEmpty]: Start isEmpty. Operand 378 states and 424 transitions. [2018-09-14 15:54:27,641 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 378 [2018-09-14 15:54:27,641 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:27,642 INFO L376 BasicCegarLoop]: trace histogram [92, 92, 91, 46, 46, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:27,642 INFO L423 AbstractCegarLoop]: === Iteration 49 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:27,642 INFO L82 PathProgramCache]: Analyzing trace with hash -597581558, now seen corresponding path program 46 times [2018-09-14 15:54:27,642 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:27,642 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:27,643 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:27,643 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:27,643 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:27,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:28,698 INFO L134 CoverageAnalysis]: Checked inductivity of 16744 backedges. 8461 proven. 4278 refuted. 0 times theorem prover too weak. 4005 trivial. 0 not checked. [2018-09-14 15:54:28,698 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:28,698 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:28,706 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:54:28,706 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:54:28,806 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:54:28,806 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:28,811 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:28,899 INFO L134 CoverageAnalysis]: Checked inductivity of 16744 backedges. 8461 proven. 4278 refuted. 0 times theorem prover too weak. 4005 trivial. 0 not checked. [2018-09-14 15:54:28,899 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:30,202 INFO L134 CoverageAnalysis]: Checked inductivity of 16744 backedges. 8461 proven. 4278 refuted. 0 times theorem prover too weak. 4005 trivial. 0 not checked. [2018-09-14 15:54:30,224 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:30,224 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 93 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 93 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:30,239 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:54:30,239 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:54:30,456 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:54:30,456 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:30,464 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:30,549 INFO L134 CoverageAnalysis]: Checked inductivity of 16744 backedges. 8461 proven. 4278 refuted. 0 times theorem prover too weak. 4005 trivial. 0 not checked. [2018-09-14 15:54:30,549 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:31,421 INFO L134 CoverageAnalysis]: Checked inductivity of 16744 backedges. 8461 proven. 4278 refuted. 0 times theorem prover too weak. 4005 trivial. 0 not checked. [2018-09-14 15:54:31,423 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:31,423 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49, 49, 49, 49] total 52 [2018-09-14 15:54:31,423 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:31,423 INFO L459 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-09-14 15:54:31,424 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-09-14 15:54:31,424 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:31,424 INFO L87 Difference]: Start difference. First operand 378 states and 424 transitions. Second operand 49 states. [2018-09-14 15:54:31,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:31,699 INFO L93 Difference]: Finished difference Result 573 states and 666 transitions. [2018-09-14 15:54:31,699 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-09-14 15:54:31,699 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 377 [2018-09-14 15:54:31,699 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:31,701 INFO L225 Difference]: With dead ends: 573 [2018-09-14 15:54:31,701 INFO L226 Difference]: Without dead ends: 383 [2018-09-14 15:54:31,701 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1555 GetRequests, 1417 SyntacticMatches, 88 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2156 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:31,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 383 states. [2018-09-14 15:54:31,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 383 to 382. [2018-09-14 15:54:31,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 382 states. [2018-09-14 15:54:31,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 382 states to 382 states and 428 transitions. [2018-09-14 15:54:31,833 INFO L78 Accepts]: Start accepts. Automaton has 382 states and 428 transitions. Word has length 377 [2018-09-14 15:54:31,833 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:31,834 INFO L480 AbstractCegarLoop]: Abstraction has 382 states and 428 transitions. [2018-09-14 15:54:31,834 INFO L481 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-09-14 15:54:31,834 INFO L276 IsEmpty]: Start isEmpty. Operand 382 states and 428 transitions. [2018-09-14 15:54:31,836 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 382 [2018-09-14 15:54:31,836 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:31,836 INFO L376 BasicCegarLoop]: trace histogram [93, 93, 92, 47, 46, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:31,836 INFO L423 AbstractCegarLoop]: === Iteration 50 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:31,836 INFO L82 PathProgramCache]: Analyzing trace with hash 1048113464, now seen corresponding path program 47 times [2018-09-14 15:54:31,837 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:31,837 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:31,837 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:31,837 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:31,837 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:31,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:33,006 INFO L134 CoverageAnalysis]: Checked inductivity of 17112 backedges. 8642 proven. 4465 refuted. 0 times theorem prover too weak. 4005 trivial. 0 not checked. [2018-09-14 15:54:33,006 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:33,006 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:33,014 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:54:33,014 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:54:33,217 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 93 check-sat command(s) [2018-09-14 15:54:33,217 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:33,224 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:33,306 INFO L134 CoverageAnalysis]: Checked inductivity of 17112 backedges. 8642 proven. 4465 refuted. 0 times theorem prover too weak. 4005 trivial. 0 not checked. [2018-09-14 15:54:33,307 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:34,521 INFO L134 CoverageAnalysis]: Checked inductivity of 17112 backedges. 8642 proven. 4465 refuted. 0 times theorem prover too weak. 4005 trivial. 0 not checked. [2018-09-14 15:54:34,541 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:34,541 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 95 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 95 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:34,562 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:54:34,562 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:54:36,606 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 93 check-sat command(s) [2018-09-14 15:54:36,606 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:36,616 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:36,705 INFO L134 CoverageAnalysis]: Checked inductivity of 17112 backedges. 8642 proven. 4465 refuted. 0 times theorem prover too weak. 4005 trivial. 0 not checked. [2018-09-14 15:54:36,706 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:37,623 INFO L134 CoverageAnalysis]: Checked inductivity of 17112 backedges. 8642 proven. 4465 refuted. 0 times theorem prover too weak. 4005 trivial. 0 not checked. [2018-09-14 15:54:37,625 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:37,625 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50, 50, 50, 50] total 52 [2018-09-14 15:54:37,625 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:37,626 INFO L459 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-09-14 15:54:37,627 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-09-14 15:54:37,627 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:37,627 INFO L87 Difference]: Start difference. First operand 382 states and 428 transitions. Second operand 50 states. [2018-09-14 15:54:37,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:37,932 INFO L93 Difference]: Finished difference Result 577 states and 670 transitions. [2018-09-14 15:54:37,932 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-09-14 15:54:37,932 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 381 [2018-09-14 15:54:37,933 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:37,934 INFO L225 Difference]: With dead ends: 577 [2018-09-14 15:54:37,934 INFO L226 Difference]: Without dead ends: 387 [2018-09-14 15:54:37,934 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1572 GetRequests, 1430 SyntacticMatches, 92 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2254 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:37,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 387 states. [2018-09-14 15:54:38,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 387 to 386. [2018-09-14 15:54:38,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 386 states. [2018-09-14 15:54:38,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 386 states to 386 states and 432 transitions. [2018-09-14 15:54:38,052 INFO L78 Accepts]: Start accepts. Automaton has 386 states and 432 transitions. Word has length 381 [2018-09-14 15:54:38,053 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:38,053 INFO L480 AbstractCegarLoop]: Abstraction has 386 states and 432 transitions. [2018-09-14 15:54:38,053 INFO L481 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-09-14 15:54:38,053 INFO L276 IsEmpty]: Start isEmpty. Operand 386 states and 432 transitions. [2018-09-14 15:54:38,055 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 386 [2018-09-14 15:54:38,055 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:38,055 INFO L376 BasicCegarLoop]: trace histogram [94, 94, 93, 48, 46, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:38,055 INFO L423 AbstractCegarLoop]: === Iteration 51 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:38,056 INFO L82 PathProgramCache]: Analyzing trace with hash 653294182, now seen corresponding path program 48 times [2018-09-14 15:54:38,056 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:38,056 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:38,056 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:38,057 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:38,057 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:38,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:39,195 INFO L134 CoverageAnalysis]: Checked inductivity of 17484 backedges. 8823 proven. 4656 refuted. 0 times theorem prover too weak. 4005 trivial. 0 not checked. [2018-09-14 15:54:39,196 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:39,196 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 96 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 96 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:39,204 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:54:39,204 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:54:39,524 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 92 check-sat command(s) [2018-09-14 15:54:39,524 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:39,528 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:39,620 INFO L134 CoverageAnalysis]: Checked inductivity of 17484 backedges. 8823 proven. 4656 refuted. 0 times theorem prover too weak. 4005 trivial. 0 not checked. [2018-09-14 15:54:39,620 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:40,660 INFO L134 CoverageAnalysis]: Checked inductivity of 17484 backedges. 8823 proven. 4656 refuted. 0 times theorem prover too weak. 4005 trivial. 0 not checked. [2018-09-14 15:54:40,681 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:40,681 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 97 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 97 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:40,695 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:54:40,696 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:54:42,780 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 92 check-sat command(s) [2018-09-14 15:54:42,780 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:42,790 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:42,892 INFO L134 CoverageAnalysis]: Checked inductivity of 17484 backedges. 8823 proven. 4656 refuted. 0 times theorem prover too weak. 4005 trivial. 0 not checked. [2018-09-14 15:54:42,892 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:43,835 INFO L134 CoverageAnalysis]: Checked inductivity of 17484 backedges. 8823 proven. 4656 refuted. 0 times theorem prover too weak. 4005 trivial. 0 not checked. [2018-09-14 15:54:43,837 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:43,838 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 51, 51, 51, 51] total 52 [2018-09-14 15:54:43,838 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:43,839 INFO L459 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-09-14 15:54:43,839 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-09-14 15:54:43,839 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:43,840 INFO L87 Difference]: Start difference. First operand 386 states and 432 transitions. Second operand 51 states. [2018-09-14 15:54:44,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:44,145 INFO L93 Difference]: Finished difference Result 581 states and 674 transitions. [2018-09-14 15:54:44,145 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-09-14 15:54:44,146 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 385 [2018-09-14 15:54:44,146 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:44,147 INFO L225 Difference]: With dead ends: 581 [2018-09-14 15:54:44,147 INFO L226 Difference]: Without dead ends: 391 [2018-09-14 15:54:44,148 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1589 GetRequests, 1443 SyntacticMatches, 96 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2352 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:44,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 391 states. [2018-09-14 15:54:44,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 391 to 390. [2018-09-14 15:54:44,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 390 states. [2018-09-14 15:54:44,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 390 states to 390 states and 436 transitions. [2018-09-14 15:54:44,266 INFO L78 Accepts]: Start accepts. Automaton has 390 states and 436 transitions. Word has length 385 [2018-09-14 15:54:44,266 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:44,266 INFO L480 AbstractCegarLoop]: Abstraction has 390 states and 436 transitions. [2018-09-14 15:54:44,267 INFO L481 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-09-14 15:54:44,267 INFO L276 IsEmpty]: Start isEmpty. Operand 390 states and 436 transitions. [2018-09-14 15:54:44,269 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 390 [2018-09-14 15:54:44,269 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:44,269 INFO L376 BasicCegarLoop]: trace histogram [95, 95, 94, 49, 46, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:44,269 INFO L423 AbstractCegarLoop]: === Iteration 52 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:44,269 INFO L82 PathProgramCache]: Analyzing trace with hash -1996243820, now seen corresponding path program 49 times [2018-09-14 15:54:44,269 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:44,270 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:44,270 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:44,270 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:44,270 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:44,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:45,492 INFO L134 CoverageAnalysis]: Checked inductivity of 17860 backedges. 9004 proven. 4851 refuted. 0 times theorem prover too weak. 4005 trivial. 0 not checked. [2018-09-14 15:54:45,492 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:45,492 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 98 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 98 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:45,499 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:54:45,499 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:54:45,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:45,604 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:45,713 INFO L134 CoverageAnalysis]: Checked inductivity of 17860 backedges. 9004 proven. 4851 refuted. 0 times theorem prover too weak. 4005 trivial. 0 not checked. [2018-09-14 15:54:45,713 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:46,704 INFO L134 CoverageAnalysis]: Checked inductivity of 17860 backedges. 9004 proven. 4851 refuted. 0 times theorem prover too weak. 4005 trivial. 0 not checked. [2018-09-14 15:54:46,724 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:46,724 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 99 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 99 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:46,740 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:54:46,740 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:54:46,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:46,953 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:47,047 INFO L134 CoverageAnalysis]: Checked inductivity of 17860 backedges. 9004 proven. 4851 refuted. 0 times theorem prover too weak. 4005 trivial. 0 not checked. [2018-09-14 15:54:47,047 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:48,042 INFO L134 CoverageAnalysis]: Checked inductivity of 17860 backedges. 9004 proven. 4851 refuted. 0 times theorem prover too weak. 4005 trivial. 0 not checked. [2018-09-14 15:54:48,044 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:48,044 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 52, 52, 52, 52] total 52 [2018-09-14 15:54:48,044 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:48,045 INFO L459 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-09-14 15:54:48,045 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-09-14 15:54:48,045 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:48,046 INFO L87 Difference]: Start difference. First operand 390 states and 436 transitions. Second operand 52 states. [2018-09-14 15:54:48,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:48,409 INFO L93 Difference]: Finished difference Result 628 states and 721 transitions. [2018-09-14 15:54:48,413 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-09-14 15:54:48,414 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 389 [2018-09-14 15:54:48,414 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:48,417 INFO L225 Difference]: With dead ends: 628 [2018-09-14 15:54:48,417 INFO L226 Difference]: Without dead ends: 438 [2018-09-14 15:54:48,417 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1606 GetRequests, 1456 SyntacticMatches, 100 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2450 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:48,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 438 states. [2018-09-14 15:54:48,555 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 438 to 394. [2018-09-14 15:54:48,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 394 states. [2018-09-14 15:54:48,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 394 states to 394 states and 440 transitions. [2018-09-14 15:54:48,556 INFO L78 Accepts]: Start accepts. Automaton has 394 states and 440 transitions. Word has length 389 [2018-09-14 15:54:48,556 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:48,556 INFO L480 AbstractCegarLoop]: Abstraction has 394 states and 440 transitions. [2018-09-14 15:54:48,556 INFO L481 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-09-14 15:54:48,557 INFO L276 IsEmpty]: Start isEmpty. Operand 394 states and 440 transitions. [2018-09-14 15:54:48,558 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 394 [2018-09-14 15:54:48,559 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:48,559 INFO L376 BasicCegarLoop]: trace histogram [96, 96, 95, 50, 46, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:48,559 INFO L423 AbstractCegarLoop]: === Iteration 53 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:48,559 INFO L82 PathProgramCache]: Analyzing trace with hash 1311651778, now seen corresponding path program 50 times [2018-09-14 15:54:48,559 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:48,560 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:48,560 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:54:48,560 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:48,560 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:48,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:50,607 INFO L134 CoverageAnalysis]: Checked inductivity of 18240 backedges. 9868 proven. 8191 refuted. 0 times theorem prover too weak. 181 trivial. 0 not checked. [2018-09-14 15:54:50,607 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:50,607 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 100 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 100 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:50,615 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:54:50,615 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:54:50,720 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:54:50,720 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:50,726 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:50,874 INFO L134 CoverageAnalysis]: Checked inductivity of 18240 backedges. 9868 proven. 8191 refuted. 0 times theorem prover too weak. 181 trivial. 0 not checked. [2018-09-14 15:54:50,874 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:52,574 INFO L134 CoverageAnalysis]: Checked inductivity of 18240 backedges. 9868 proven. 8191 refuted. 0 times theorem prover too weak. 181 trivial. 0 not checked. [2018-09-14 15:54:52,595 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:52,595 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 101 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 101 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:52,610 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:54:52,610 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:54:52,831 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:54:52,831 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:52,841 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:53,101 INFO L134 CoverageAnalysis]: Checked inductivity of 18240 backedges. 9583 proven. 8476 refuted. 0 times theorem prover too weak. 181 trivial. 0 not checked. [2018-09-14 15:54:53,101 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:55,035 INFO L134 CoverageAnalysis]: Checked inductivity of 18240 backedges. 9868 proven. 8191 refuted. 0 times theorem prover too weak. 181 trivial. 0 not checked. [2018-09-14 15:54:55,037 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:55,037 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [53, 53, 53, 53, 52] total 58 [2018-09-14 15:54:55,037 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:55,038 INFO L459 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-09-14 15:54:55,038 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-09-14 15:54:55,038 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1603, Invalid=1703, Unknown=0, NotChecked=0, Total=3306 [2018-09-14 15:54:55,038 INFO L87 Difference]: Start difference. First operand 394 states and 440 transitions. Second operand 53 states. [2018-09-14 15:54:56,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:56,117 INFO L93 Difference]: Finished difference Result 1324 states and 1604 transitions. [2018-09-14 15:54:56,118 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-09-14 15:54:56,118 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 393 [2018-09-14 15:54:56,118 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:56,125 INFO L225 Difference]: With dead ends: 1324 [2018-09-14 15:54:56,126 INFO L226 Difference]: Without dead ends: 1319 [2018-09-14 15:54:56,126 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1669 GetRequests, 1427 SyntacticMatches, 186 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6215 ImplicationChecksByTransitivity, 5.2s TimeCoverageRelationStatistics Valid=1603, Invalid=1703, Unknown=0, NotChecked=0, Total=3306 [2018-09-14 15:54:56,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1319 states. [2018-09-14 15:54:56,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1319 to 414. [2018-09-14 15:54:56,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 414 states. [2018-09-14 15:54:56,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 414 states to 414 states and 465 transitions. [2018-09-14 15:54:56,317 INFO L78 Accepts]: Start accepts. Automaton has 414 states and 465 transitions. Word has length 393 [2018-09-14 15:54:56,318 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:56,318 INFO L480 AbstractCegarLoop]: Abstraction has 414 states and 465 transitions. [2018-09-14 15:54:56,318 INFO L481 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-09-14 15:54:56,318 INFO L276 IsEmpty]: Start isEmpty. Operand 414 states and 465 transitions. [2018-09-14 15:54:56,320 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 414 [2018-09-14 15:54:56,320 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:56,321 INFO L376 BasicCegarLoop]: trace histogram [101, 101, 100, 51, 50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:56,321 INFO L423 AbstractCegarLoop]: === Iteration 54 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:56,321 INFO L82 PathProgramCache]: Analyzing trace with hash 2099862750, now seen corresponding path program 51 times [2018-09-14 15:54:56,321 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:56,322 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:56,322 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:56,322 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:56,322 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:56,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:58,306 INFO L134 CoverageAnalysis]: Checked inductivity of 20200 backedges. 10198 proven. 5151 refuted. 0 times theorem prover too weak. 4851 trivial. 0 not checked. [2018-09-14 15:54:58,306 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:58,306 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 102 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 102 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:58,313 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:54:58,313 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:54:58,450 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 69 check-sat command(s) [2018-09-14 15:54:58,450 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:58,456 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:58,800 INFO L134 CoverageAnalysis]: Checked inductivity of 20200 backedges. 10198 proven. 5151 refuted. 0 times theorem prover too weak. 4851 trivial. 0 not checked. [2018-09-14 15:54:58,800 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:59,318 INFO L134 CoverageAnalysis]: Checked inductivity of 20200 backedges. 10198 proven. 5151 refuted. 0 times theorem prover too weak. 4851 trivial. 0 not checked. [2018-09-14 15:54:59,338 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:59,339 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 103 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 103 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:59,354 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:54:59,354 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:55:00,686 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 69 check-sat command(s) [2018-09-14 15:55:00,686 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:55:00,697 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:55:01,111 INFO L134 CoverageAnalysis]: Checked inductivity of 20200 backedges. 10198 proven. 5151 refuted. 0 times theorem prover too weak. 4851 trivial. 0 not checked. [2018-09-14 15:55:01,111 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:55:01,368 INFO L134 CoverageAnalysis]: Checked inductivity of 20200 backedges. 10198 proven. 5151 refuted. 0 times theorem prover too weak. 4851 trivial. 0 not checked. [2018-09-14 15:55:01,370 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:55:01,371 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [57, 57, 57, 57, 57] total 59 [2018-09-14 15:55:01,371 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:55:01,371 INFO L459 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-09-14 15:55:01,372 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-09-14 15:55:01,372 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=119, Invalid=3303, Unknown=0, NotChecked=0, Total=3422 [2018-09-14 15:55:01,372 INFO L87 Difference]: Start difference. First operand 414 states and 465 transitions. Second operand 57 states. [2018-09-14 15:55:10,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:55:10,016 INFO L93 Difference]: Finished difference Result 5825 states and 7252 transitions. [2018-09-14 15:55:10,018 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2018-09-14 15:55:10,018 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 413 [2018-09-14 15:55:10,018 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:55:10,041 INFO L225 Difference]: With dead ends: 5825 [2018-09-14 15:55:10,041 INFO L226 Difference]: Without dead ends: 5612 [2018-09-14 15:55:10,043 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1708 GetRequests, 1640 SyntacticMatches, 10 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 127 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=125, Invalid=3415, Unknown=0, NotChecked=0, Total=3540 [2018-09-14 15:55:10,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5612 states. [2018-09-14 15:55:14,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5612 to 5563. [2018-09-14 15:55:14,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5563 states. [2018-09-14 15:55:14,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5563 states to 5563 states and 5663 transitions. [2018-09-14 15:55:14,451 INFO L78 Accepts]: Start accepts. Automaton has 5563 states and 5663 transitions. Word has length 413 [2018-09-14 15:55:14,452 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:55:14,452 INFO L480 AbstractCegarLoop]: Abstraction has 5563 states and 5663 transitions. [2018-09-14 15:55:14,452 INFO L481 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-09-14 15:55:14,453 INFO L276 IsEmpty]: Start isEmpty. Operand 5563 states and 5663 transitions. [2018-09-14 15:55:14,455 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 418 [2018-09-14 15:55:14,455 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:55:14,455 INFO L376 BasicCegarLoop]: trace histogram [102, 102, 101, 52, 50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:55:14,455 INFO L423 AbstractCegarLoop]: === Iteration 55 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:55:14,456 INFO L82 PathProgramCache]: Analyzing trace with hash 1583456842, now seen corresponding path program 52 times [2018-09-14 15:55:14,456 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:55:14,457 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:55:14,457 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:55:14,457 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:55:14,457 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:55:14,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:55:16,044 INFO L134 CoverageAnalysis]: Checked inductivity of 20604 backedges. 10504 proven. 9901 refuted. 0 times theorem prover too weak. 199 trivial. 0 not checked. [2018-09-14 15:55:16,045 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:55:16,045 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 104 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 104 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:55:16,052 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:55:16,052 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:55:16,164 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:55:16,164 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:55:16,170 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:55:16,374 INFO L134 CoverageAnalysis]: Checked inductivity of 20604 backedges. 10504 proven. 9901 refuted. 0 times theorem prover too weak. 199 trivial. 0 not checked. [2018-09-14 15:55:16,374 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:55:18,420 INFO L134 CoverageAnalysis]: Checked inductivity of 20604 backedges. 10504 proven. 9901 refuted. 0 times theorem prover too weak. 199 trivial. 0 not checked. [2018-09-14 15:55:18,441 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:55:18,441 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 105 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 105 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:55:18,456 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:55:18,457 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:55:18,696 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:55:18,696 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:55:18,707 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:55:18,856 INFO L134 CoverageAnalysis]: Checked inductivity of 20604 backedges. 10504 proven. 9901 refuted. 0 times theorem prover too weak. 199 trivial. 0 not checked. [2018-09-14 15:55:18,856 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:55:21,237 INFO L134 CoverageAnalysis]: Checked inductivity of 20604 backedges. 10504 proven. 9901 refuted. 0 times theorem prover too weak. 199 trivial. 0 not checked. [2018-09-14 15:55:21,239 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:55:21,239 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 54, 54, 54, 54] total 54 [2018-09-14 15:55:21,239 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:55:21,240 INFO L459 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-09-14 15:55:21,240 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-09-14 15:55:21,240 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1431, Invalid=1431, Unknown=0, NotChecked=0, Total=2862 [2018-09-14 15:55:21,241 INFO L87 Difference]: Start difference. First operand 5563 states and 5663 transitions. Second operand 54 states. [2018-09-14 15:55:26,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:55:26,907 INFO L93 Difference]: Finished difference Result 11127 states and 11328 transitions. [2018-09-14 15:55:26,908 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-09-14 15:55:26,908 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 417 [2018-09-14 15:55:26,908 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:55:26,922 INFO L225 Difference]: With dead ends: 11127 [2018-09-14 15:55:26,922 INFO L226 Difference]: Without dead ends: 5567 [2018-09-14 15:55:26,930 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1770 GetRequests, 1514 SyntacticMatches, 204 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5800 ImplicationChecksByTransitivity, 5.4s TimeCoverageRelationStatistics Valid=1431, Invalid=1431, Unknown=0, NotChecked=0, Total=2862 [2018-09-14 15:55:26,933 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5567 states. [2018-09-14 15:55:31,416 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5567 to 5567. [2018-09-14 15:55:31,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5567 states. [2018-09-14 15:55:31,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5567 states to 5567 states and 5667 transitions. [2018-09-14 15:55:31,421 INFO L78 Accepts]: Start accepts. Automaton has 5567 states and 5667 transitions. Word has length 417 [2018-09-14 15:55:31,421 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:55:31,421 INFO L480 AbstractCegarLoop]: Abstraction has 5567 states and 5667 transitions. [2018-09-14 15:55:31,421 INFO L481 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-09-14 15:55:31,421 INFO L276 IsEmpty]: Start isEmpty. Operand 5567 states and 5667 transitions. [2018-09-14 15:55:31,423 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 422 [2018-09-14 15:55:31,424 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:55:31,424 INFO L376 BasicCegarLoop]: trace histogram [103, 103, 102, 52, 51, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:55:31,424 INFO L423 AbstractCegarLoop]: === Iteration 56 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:55:31,424 INFO L82 PathProgramCache]: Analyzing trace with hash -273634184, now seen corresponding path program 53 times [2018-09-14 15:55:31,424 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:55:31,425 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:55:31,425 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:55:31,425 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:55:31,425 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:55:31,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:55:32,709 INFO L134 CoverageAnalysis]: Checked inductivity of 21012 backedges. 15656 proven. 0 refuted. 0 times theorem prover too weak. 5356 trivial. 0 not checked. [2018-09-14 15:55:32,709 INFO L313 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-09-14 15:55:32,710 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [53] imperfect sequences [] total 53 [2018-09-14 15:55:32,710 INFO L265 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-09-14 15:55:32,710 INFO L459 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-09-14 15:55:32,710 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-09-14 15:55:32,711 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1378, Invalid=1378, Unknown=0, NotChecked=0, Total=2756 [2018-09-14 15:55:32,711 INFO L87 Difference]: Start difference. First operand 5567 states and 5667 transitions. Second operand 53 states. [2018-09-14 15:55:33,040 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:55:33,040 INFO L93 Difference]: Finished difference Result 5567 states and 5667 transitions. [2018-09-14 15:55:33,041 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-09-14 15:55:33,041 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 421 [2018-09-14 15:55:33,041 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:55:33,042 INFO L225 Difference]: With dead ends: 5567 [2018-09-14 15:55:33,042 INFO L226 Difference]: Without dead ends: 0 [2018-09-14 15:55:33,050 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1378, Invalid=1378, Unknown=0, NotChecked=0, Total=2756 [2018-09-14 15:55:33,050 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 0 states. [2018-09-14 15:55:33,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 0 to 0. [2018-09-14 15:55:33,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 0 states. [2018-09-14 15:55:33,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 0 states to 0 states and 0 transitions. [2018-09-14 15:55:33,051 INFO L78 Accepts]: Start accepts. Automaton has 0 states and 0 transitions. Word has length 421 [2018-09-14 15:55:33,051 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:55:33,051 INFO L480 AbstractCegarLoop]: Abstraction has 0 states and 0 transitions. [2018-09-14 15:55:33,051 INFO L481 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-09-14 15:55:33,052 INFO L276 IsEmpty]: Start isEmpty. Operand 0 states and 0 transitions. [2018-09-14 15:55:33,052 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-09-14 15:55:33,057 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends 0 states and 0 transitions. [2018-09-14 15:55:43,592 WARN L178 SmtUtils]: Spent 10.52 s on a formula simplification. DAG size of input: 1852 DAG size of output: 1441 Received shutdown request... [2018-09-14 15:56:08,551 WARN L186 SmtUtils]: Removed 45 from assertion stack [2018-09-14 15:56:08,551 INFO L256 ToolchainWalker]: Toolchain cancelled while executing plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction. Reason: Timeout or Toolchain cancelled by user [2018-09-14 15:56:08,553 INFO L168 Benchmark]: Toolchain (without parser) took 230419.28 ms. Allocated memory was 1.5 GB in the beginning and 3.2 GB in the end (delta: 1.7 GB). Free memory was 1.4 GB in the beginning and 2.6 GB in the end (delta: -1.2 GB). Peak memory consumption was 1.5 GB. Max. memory is 7.1 GB. [2018-09-14 15:56:08,554 INFO L168 Benchmark]: CDTParser took 0.20 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-09-14 15:56:08,555 INFO L168 Benchmark]: CACSL2BoogieTranslator took 282.33 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. [2018-09-14 15:56:08,555 INFO L168 Benchmark]: Boogie Procedure Inliner took 26.43 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-09-14 15:56:08,555 INFO L168 Benchmark]: Boogie Preprocessor took 29.56 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-09-14 15:56:08,556 INFO L168 Benchmark]: RCFGBuilder took 514.12 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 767.0 MB). Free memory was 1.4 GB in the beginning and 2.2 GB in the end (delta: -809.1 MB). Peak memory consumption was 26.7 MB. Max. memory is 7.1 GB. [2018-09-14 15:56:08,556 INFO L168 Benchmark]: TraceAbstraction took 229548.24 ms. Allocated memory was 2.3 GB in the beginning and 3.2 GB in the end (delta: 913.3 MB). Free memory was 2.2 GB in the beginning and 2.6 GB in the end (delta: -403.1 MB). Peak memory consumption was 1.6 GB. Max. memory is 7.1 GB. [2018-09-14 15:56:08,559 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 282.33 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 26.43 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Preprocessor took 29.56 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * RCFGBuilder took 514.12 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 767.0 MB). Free memory was 1.4 GB in the beginning and 2.2 GB in the end (delta: -809.1 MB). Peak memory consumption was 26.7 MB. Max. memory is 7.1 GB. * TraceAbstraction took 229548.24 ms. Allocated memory was 2.3 GB in the beginning and 3.2 GB in the end (delta: 913.3 MB). Free memory was 2.2 GB in the beginning and 2.6 GB in the end (delta: -403.1 MB). Peak memory consumption was 1.6 GB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - PositiveResult [Line: 5]: call of __VERIFIER_error() unreachable For all program executions holds that call of __VERIFIER_error() unreachable at this location - TimeoutResult: Timeout (de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction) Toolchain cancelled while SimplifyDDAWithTimeout was simplifying term of DAG size 1420. RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/gr2006_true-unreach-call_true-termination.c.i_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-Benchmark-0-2018-09-14_15-56-08-568.csv Completed graceful shutdown