java -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data --generate-csv --csv-dir csv -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml -s ../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf -i ../../../trunk/examples/svcomp/loop-invgen/seq_true-unreach-call_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-dace188-m [2018-09-14 15:51:13,443 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-09-14 15:51:13,445 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-09-14 15:51:13,457 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-09-14 15:51:13,458 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-09-14 15:51:13,459 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-09-14 15:51:13,460 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-09-14 15:51:13,462 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-09-14 15:51:13,463 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-09-14 15:51:13,464 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-09-14 15:51:13,465 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-09-14 15:51:13,466 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-09-14 15:51:13,467 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-09-14 15:51:13,468 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-09-14 15:51:13,469 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-09-14 15:51:13,470 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-09-14 15:51:13,471 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-09-14 15:51:13,472 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-09-14 15:51:13,474 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-09-14 15:51:13,476 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-09-14 15:51:13,477 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-09-14 15:51:13,479 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-09-14 15:51:13,481 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-09-14 15:51:13,481 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-09-14 15:51:13,482 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-09-14 15:51:13,483 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-09-14 15:51:13,484 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-09-14 15:51:13,485 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-09-14 15:51:13,485 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-09-14 15:51:13,487 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-09-14 15:51:13,487 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-09-14 15:51:13,487 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-09-14 15:51:13,488 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-09-14 15:51:13,488 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-09-14 15:51:13,489 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-09-14 15:51:13,490 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-09-14 15:51:13,490 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf [2018-09-14 15:51:13,517 INFO L110 SettingsManager]: Loading preferences was successful [2018-09-14 15:51:13,517 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-09-14 15:51:13,518 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-09-14 15:51:13,518 INFO L133 SettingsManager]: * User list type=DISABLED [2018-09-14 15:51:13,518 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-09-14 15:51:13,519 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-09-14 15:51:13,519 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-09-14 15:51:13,519 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-09-14 15:51:13,519 INFO L133 SettingsManager]: * Log string format=TERM [2018-09-14 15:51:13,522 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-09-14 15:51:13,522 INFO L133 SettingsManager]: * Interval Domain=false [2018-09-14 15:51:13,523 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-09-14 15:51:13,523 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-09-14 15:51:13,523 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-09-14 15:51:13,523 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-09-14 15:51:13,524 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-09-14 15:51:13,524 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-09-14 15:51:13,524 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-09-14 15:51:13,524 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-09-14 15:51:13,526 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-09-14 15:51:13,526 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-09-14 15:51:13,526 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-09-14 15:51:13,526 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-09-14 15:51:13,527 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-09-14 15:51:13,527 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-09-14 15:51:13,527 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-09-14 15:51:13,527 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-09-14 15:51:13,527 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-09-14 15:51:13,528 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-09-14 15:51:13,528 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-09-14 15:51:13,528 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-09-14 15:51:13,528 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-09-14 15:51:13,528 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-09-14 15:51:13,585 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-09-14 15:51:13,604 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-09-14 15:51:13,608 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-09-14 15:51:13,610 INFO L271 PluginConnector]: Initializing CDTParser... [2018-09-14 15:51:13,610 INFO L276 PluginConnector]: CDTParser initialized [2018-09-14 15:51:13,611 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-invgen/seq_true-unreach-call_true-termination.i [2018-09-14 15:51:13,957 INFO L221 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ef2ab085a/a37f6d6c99114549a5923fccdb306a4a/FLAGa74b25cce [2018-09-14 15:51:14,085 INFO L277 CDTParser]: Found 1 translation units. [2018-09-14 15:51:14,085 INFO L159 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-invgen/seq_true-unreach-call_true-termination.i [2018-09-14 15:51:14,091 INFO L325 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ef2ab085a/a37f6d6c99114549a5923fccdb306a4a/FLAGa74b25cce [2018-09-14 15:51:14,106 INFO L333 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ef2ab085a/a37f6d6c99114549a5923fccdb306a4a [2018-09-14 15:51:14,118 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-09-14 15:51:14,122 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-09-14 15:51:14,124 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-09-14 15:51:14,124 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-09-14 15:51:14,133 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-09-14 15:51:14,134 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.09 03:51:14" (1/1) ... [2018-09-14 15:51:14,138 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@75c8fe19 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:14, skipping insertion in model container [2018-09-14 15:51:14,138 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.09 03:51:14" (1/1) ... [2018-09-14 15:51:14,149 INFO L160 ieTranslatorObserver]: Starting translation in SV-COMP mode [2018-09-14 15:51:14,403 INFO L170 PostProcessor]: Settings: Checked method=main [2018-09-14 15:51:14,423 INFO L424 MainDispatcher]: Starting main dispatcher in SV-COMP mode [2018-09-14 15:51:14,431 INFO L170 PostProcessor]: Settings: Checked method=main [2018-09-14 15:51:14,445 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:14 WrapperNode [2018-09-14 15:51:14,445 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-09-14 15:51:14,446 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-09-14 15:51:14,446 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-09-14 15:51:14,446 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-09-14 15:51:14,455 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:14" (1/1) ... [2018-09-14 15:51:14,462 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:14" (1/1) ... [2018-09-14 15:51:14,468 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-09-14 15:51:14,469 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-09-14 15:51:14,469 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-09-14 15:51:14,469 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-09-14 15:51:14,479 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:14" (1/1) ... [2018-09-14 15:51:14,479 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:14" (1/1) ... [2018-09-14 15:51:14,480 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:14" (1/1) ... [2018-09-14 15:51:14,481 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:14" (1/1) ... [2018-09-14 15:51:14,483 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:14" (1/1) ... [2018-09-14 15:51:14,489 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:14" (1/1) ... [2018-09-14 15:51:14,490 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:14" (1/1) ... [2018-09-14 15:51:14,492 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-09-14 15:51:14,492 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-09-14 15:51:14,493 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-09-14 15:51:14,493 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-09-14 15:51:14,494 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:14" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-09-14 15:51:14,565 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-09-14 15:51:14,565 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-09-14 15:51:14,565 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-09-14 15:51:14,565 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-09-14 15:51:14,566 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-09-14 15:51:14,566 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-09-14 15:51:14,566 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-09-14 15:51:14,566 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-09-14 15:51:15,017 INFO L353 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-09-14 15:51:15,018 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.09 03:51:15 BoogieIcfgContainer [2018-09-14 15:51:15,018 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-09-14 15:51:15,019 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-09-14 15:51:15,019 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-09-14 15:51:15,023 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-09-14 15:51:15,023 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 14.09 03:51:14" (1/3) ... [2018-09-14 15:51:15,024 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@331bd659 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.09 03:51:15, skipping insertion in model container [2018-09-14 15:51:15,024 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:51:14" (2/3) ... [2018-09-14 15:51:15,024 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@331bd659 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.09 03:51:15, skipping insertion in model container [2018-09-14 15:51:15,025 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.09 03:51:15" (3/3) ... [2018-09-14 15:51:15,026 INFO L112 eAbstractionObserver]: Analyzing ICFG seq_true-unreach-call_true-termination.i [2018-09-14 15:51:15,036 INFO L137 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-09-14 15:51:15,050 INFO L149 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-09-14 15:51:15,094 INFO L130 ementStrategyFactory]: Using default assertion order modulation [2018-09-14 15:51:15,094 INFO L381 AbstractCegarLoop]: Interprodecural is true [2018-09-14 15:51:15,095 INFO L382 AbstractCegarLoop]: Hoare is true [2018-09-14 15:51:15,095 INFO L383 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-09-14 15:51:15,095 INFO L384 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-09-14 15:51:15,095 INFO L385 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-09-14 15:51:15,095 INFO L386 AbstractCegarLoop]: Difference is false [2018-09-14 15:51:15,095 INFO L387 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-09-14 15:51:15,095 INFO L392 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-09-14 15:51:15,112 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states. [2018-09-14 15:51:15,119 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-09-14 15:51:15,119 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:15,120 INFO L376 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:15,122 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:15,126 INFO L82 PathProgramCache]: Analyzing trace with hash 301890663, now seen corresponding path program 1 times [2018-09-14 15:51:15,129 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:15,179 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:15,179 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:15,180 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:15,180 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:15,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:15,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:15,256 INFO L313 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-09-14 15:51:15,256 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-09-14 15:51:15,256 INFO L265 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-09-14 15:51:15,260 INFO L459 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-09-14 15:51:15,272 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-09-14 15:51:15,273 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-09-14 15:51:15,276 INFO L87 Difference]: Start difference. First operand 27 states. Second operand 2 states. [2018-09-14 15:51:15,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:15,299 INFO L93 Difference]: Finished difference Result 45 states and 58 transitions. [2018-09-14 15:51:15,299 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-09-14 15:51:15,300 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 17 [2018-09-14 15:51:15,301 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:15,308 INFO L225 Difference]: With dead ends: 45 [2018-09-14 15:51:15,309 INFO L226 Difference]: Without dead ends: 23 [2018-09-14 15:51:15,313 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-09-14 15:51:15,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states. [2018-09-14 15:51:15,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 23. [2018-09-14 15:51:15,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23 states. [2018-09-14 15:51:15,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 25 transitions. [2018-09-14 15:51:15,352 INFO L78 Accepts]: Start accepts. Automaton has 23 states and 25 transitions. Word has length 17 [2018-09-14 15:51:15,353 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:15,353 INFO L480 AbstractCegarLoop]: Abstraction has 23 states and 25 transitions. [2018-09-14 15:51:15,353 INFO L481 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-09-14 15:51:15,353 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states and 25 transitions. [2018-09-14 15:51:15,354 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-09-14 15:51:15,354 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:15,355 INFO L376 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:15,355 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:15,355 INFO L82 PathProgramCache]: Analyzing trace with hash 1130037681, now seen corresponding path program 1 times [2018-09-14 15:51:15,356 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:15,357 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:15,357 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:15,357 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:15,357 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:15,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:15,763 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:15,764 INFO L313 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-09-14 15:51:15,764 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-09-14 15:51:15,764 INFO L265 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-09-14 15:51:15,766 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-09-14 15:51:15,766 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-09-14 15:51:15,767 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-09-14 15:51:15,767 INFO L87 Difference]: Start difference. First operand 23 states and 25 transitions. Second operand 7 states. [2018-09-14 15:51:16,174 WARN L178 SmtUtils]: Spent 111.00 ms on a formula simplification that was a NOOP. DAG size: 14 [2018-09-14 15:51:16,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:16,247 INFO L93 Difference]: Finished difference Result 48 states and 54 transitions. [2018-09-14 15:51:16,248 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-09-14 15:51:16,248 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 19 [2018-09-14 15:51:16,248 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:16,250 INFO L225 Difference]: With dead ends: 48 [2018-09-14 15:51:16,251 INFO L226 Difference]: Without dead ends: 35 [2018-09-14 15:51:16,252 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=39, Invalid=71, Unknown=0, NotChecked=0, Total=110 [2018-09-14 15:51:16,252 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states. [2018-09-14 15:51:16,262 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 28. [2018-09-14 15:51:16,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28 states. [2018-09-14 15:51:16,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 31 transitions. [2018-09-14 15:51:16,265 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 31 transitions. Word has length 19 [2018-09-14 15:51:16,265 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:16,265 INFO L480 AbstractCegarLoop]: Abstraction has 28 states and 31 transitions. [2018-09-14 15:51:16,266 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-09-14 15:51:16,266 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 31 transitions. [2018-09-14 15:51:16,267 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-09-14 15:51:16,267 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:16,267 INFO L376 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:16,267 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:16,268 INFO L82 PathProgramCache]: Analyzing trace with hash -1499928661, now seen corresponding path program 1 times [2018-09-14 15:51:16,268 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:16,269 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:16,269 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:16,269 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:16,269 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:16,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:16,361 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:16,362 INFO L313 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-09-14 15:51:16,362 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-09-14 15:51:16,365 INFO L265 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-09-14 15:51:16,366 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-09-14 15:51:16,366 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-09-14 15:51:16,366 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-09-14 15:51:16,367 INFO L87 Difference]: Start difference. First operand 28 states and 31 transitions. Second operand 6 states. [2018-09-14 15:51:16,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:16,500 INFO L93 Difference]: Finished difference Result 42 states and 46 transitions. [2018-09-14 15:51:16,504 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-09-14 15:51:16,505 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 21 [2018-09-14 15:51:16,505 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:16,506 INFO L225 Difference]: With dead ends: 42 [2018-09-14 15:51:16,507 INFO L226 Difference]: Without dead ends: 40 [2018-09-14 15:51:16,507 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-09-14 15:51:16,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-09-14 15:51:16,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 35. [2018-09-14 15:51:16,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35 states. [2018-09-14 15:51:16,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 38 transitions. [2018-09-14 15:51:16,521 INFO L78 Accepts]: Start accepts. Automaton has 35 states and 38 transitions. Word has length 21 [2018-09-14 15:51:16,521 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:16,522 INFO L480 AbstractCegarLoop]: Abstraction has 35 states and 38 transitions. [2018-09-14 15:51:16,522 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-09-14 15:51:16,522 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 38 transitions. [2018-09-14 15:51:16,523 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-09-14 15:51:16,523 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:16,523 INFO L376 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:16,523 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:16,524 INFO L82 PathProgramCache]: Analyzing trace with hash -1355895601, now seen corresponding path program 1 times [2018-09-14 15:51:16,524 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:16,525 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:16,525 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:16,525 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:16,526 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:16,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:16,793 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:16,794 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:16,794 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:16,803 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:16,803 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:51:16,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:16,828 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:17,254 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:17,255 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:17,527 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:17,557 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:17,557 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:17,574 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:17,574 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:51:17,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:17,601 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:17,613 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:17,613 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:17,716 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:17,718 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:17,718 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 14 [2018-09-14 15:51:17,718 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:17,719 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-09-14 15:51:17,719 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-09-14 15:51:17,720 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=137, Unknown=0, NotChecked=0, Total=182 [2018-09-14 15:51:17,720 INFO L87 Difference]: Start difference. First operand 35 states and 38 transitions. Second operand 14 states. [2018-09-14 15:51:18,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:18,070 INFO L93 Difference]: Finished difference Result 64 states and 72 transitions. [2018-09-14 15:51:18,071 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-09-14 15:51:18,071 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 29 [2018-09-14 15:51:18,072 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:18,075 INFO L225 Difference]: With dead ends: 64 [2018-09-14 15:51:18,075 INFO L226 Difference]: Without dead ends: 47 [2018-09-14 15:51:18,076 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 129 GetRequests, 99 SyntacticMatches, 12 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 122 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=105, Invalid=275, Unknown=0, NotChecked=0, Total=380 [2018-09-14 15:51:18,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2018-09-14 15:51:18,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 37. [2018-09-14 15:51:18,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2018-09-14 15:51:18,084 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 40 transitions. [2018-09-14 15:51:18,085 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 40 transitions. Word has length 29 [2018-09-14 15:51:18,085 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:18,085 INFO L480 AbstractCegarLoop]: Abstraction has 37 states and 40 transitions. [2018-09-14 15:51:18,085 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-09-14 15:51:18,086 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 40 transitions. [2018-09-14 15:51:18,087 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-09-14 15:51:18,087 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:18,087 INFO L376 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:18,087 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:18,088 INFO L82 PathProgramCache]: Analyzing trace with hash 95654235, now seen corresponding path program 1 times [2018-09-14 15:51:18,088 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:18,089 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:18,089 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:18,089 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:18,089 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:18,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:18,226 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:18,226 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:18,227 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:18,245 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:18,245 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:51:18,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:18,271 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:18,420 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:18,421 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:18,548 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:18,569 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:18,569 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:18,584 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:18,584 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:51:18,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:18,608 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:18,617 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:18,617 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:18,785 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:18,787 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:18,787 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 13 [2018-09-14 15:51:18,787 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:18,788 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-09-14 15:51:18,788 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-09-14 15:51:18,788 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=117, Unknown=0, NotChecked=0, Total=156 [2018-09-14 15:51:18,789 INFO L87 Difference]: Start difference. First operand 37 states and 40 transitions. Second operand 13 states. [2018-09-14 15:51:19,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:19,212 INFO L93 Difference]: Finished difference Result 79 states and 91 transitions. [2018-09-14 15:51:19,214 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-09-14 15:51:19,214 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 29 [2018-09-14 15:51:19,215 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:19,216 INFO L225 Difference]: With dead ends: 79 [2018-09-14 15:51:19,216 INFO L226 Difference]: Without dead ends: 62 [2018-09-14 15:51:19,217 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 130 GetRequests, 100 SyntacticMatches, 12 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 103 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=105, Invalid=275, Unknown=0, NotChecked=0, Total=380 [2018-09-14 15:51:19,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2018-09-14 15:51:19,225 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 40. [2018-09-14 15:51:19,225 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40 states. [2018-09-14 15:51:19,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 44 transitions. [2018-09-14 15:51:19,226 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 44 transitions. Word has length 29 [2018-09-14 15:51:19,227 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:19,227 INFO L480 AbstractCegarLoop]: Abstraction has 40 states and 44 transitions. [2018-09-14 15:51:19,227 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-09-14 15:51:19,227 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 44 transitions. [2018-09-14 15:51:19,228 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-09-14 15:51:19,228 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:19,229 INFO L376 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:19,229 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:19,229 INFO L82 PathProgramCache]: Analyzing trace with hash -446111159, now seen corresponding path program 2 times [2018-09-14 15:51:19,230 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:19,230 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:19,231 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:19,231 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:19,231 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:19,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:19,467 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 7 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:19,468 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:19,468 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:19,476 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:51:19,476 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:51:19,492 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:51:19,493 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:19,497 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:19,530 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:19,531 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:19,608 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:19,628 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:19,629 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:19,644 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:51:19,644 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:51:19,672 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:51:19,672 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:19,677 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:19,684 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:19,685 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:19,737 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:19,739 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:19,739 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7, 7, 7] total 10 [2018-09-14 15:51:19,739 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:19,739 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-09-14 15:51:19,740 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-09-14 15:51:19,740 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=68, Unknown=0, NotChecked=0, Total=90 [2018-09-14 15:51:19,741 INFO L87 Difference]: Start difference. First operand 40 states and 44 transitions. Second operand 10 states. [2018-09-14 15:51:19,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:19,918 INFO L93 Difference]: Finished difference Result 50 states and 54 transitions. [2018-09-14 15:51:19,918 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-09-14 15:51:19,918 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 31 [2018-09-14 15:51:19,919 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:19,920 INFO L225 Difference]: With dead ends: 50 [2018-09-14 15:51:19,920 INFO L226 Difference]: Without dead ends: 48 [2018-09-14 15:51:19,921 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 135 GetRequests, 115 SyntacticMatches, 10 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=35, Invalid=97, Unknown=0, NotChecked=0, Total=132 [2018-09-14 15:51:19,921 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states. [2018-09-14 15:51:19,928 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 48. [2018-09-14 15:51:19,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-09-14 15:51:19,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 52 transitions. [2018-09-14 15:51:19,931 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 52 transitions. Word has length 31 [2018-09-14 15:51:19,931 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:19,931 INFO L480 AbstractCegarLoop]: Abstraction has 48 states and 52 transitions. [2018-09-14 15:51:19,931 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-09-14 15:51:19,931 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 52 transitions. [2018-09-14 15:51:19,932 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-09-14 15:51:19,933 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:19,933 INFO L376 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:19,933 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:19,933 INFO L82 PathProgramCache]: Analyzing trace with hash 94447981, now seen corresponding path program 3 times [2018-09-14 15:51:19,934 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:19,934 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:19,934 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:19,935 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:19,935 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:19,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:20,064 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-14 15:51:20,064 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:20,065 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:20,072 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:51:20,073 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:51:20,096 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-09-14 15:51:20,097 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:20,099 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:20,325 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-14 15:51:20,326 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:20,392 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-14 15:51:20,414 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:20,415 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:20,430 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:51:20,430 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:51:20,466 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-09-14 15:51:20,466 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:20,470 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:20,483 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-14 15:51:20,483 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:20,596 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-14 15:51:20,598 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:20,598 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 18 [2018-09-14 15:51:20,598 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:20,599 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-09-14 15:51:20,599 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-09-14 15:51:20,600 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=71, Invalid=235, Unknown=0, NotChecked=0, Total=306 [2018-09-14 15:51:20,600 INFO L87 Difference]: Start difference. First operand 48 states and 52 transitions. Second operand 18 states. [2018-09-14 15:51:21,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:21,074 INFO L93 Difference]: Finished difference Result 87 states and 98 transitions. [2018-09-14 15:51:21,074 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-09-14 15:51:21,074 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 39 [2018-09-14 15:51:21,075 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:21,076 INFO L225 Difference]: With dead ends: 87 [2018-09-14 15:51:21,076 INFO L226 Difference]: Without dead ends: 66 [2018-09-14 15:51:21,077 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 173 GetRequests, 133 SyntacticMatches, 16 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 267 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=163, Invalid=487, Unknown=0, NotChecked=0, Total=650 [2018-09-14 15:51:21,078 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2018-09-14 15:51:21,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 50. [2018-09-14 15:51:21,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-09-14 15:51:21,087 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2018-09-14 15:51:21,087 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 39 [2018-09-14 15:51:21,088 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:21,088 INFO L480 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2018-09-14 15:51:21,088 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-09-14 15:51:21,088 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2018-09-14 15:51:21,089 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-09-14 15:51:21,089 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:21,089 INFO L376 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:21,090 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:21,090 INFO L82 PathProgramCache]: Analyzing trace with hash 594202361, now seen corresponding path program 1 times [2018-09-14 15:51:21,090 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:21,091 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:21,091 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:21,091 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:21,092 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:21,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:21,343 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 14 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-14 15:51:21,343 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:21,344 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:21,352 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:21,352 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:51:21,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:21,370 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:21,536 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 14 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-14 15:51:21,537 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:21,698 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 14 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-14 15:51:21,718 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:21,718 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:21,736 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:21,736 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:51:21,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:21,765 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:21,778 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 14 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-14 15:51:21,779 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:21,994 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 14 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-14 15:51:21,997 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:21,997 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 17 [2018-09-14 15:51:21,998 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:21,998 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-09-14 15:51:21,998 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-09-14 15:51:21,999 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=210, Unknown=0, NotChecked=0, Total=272 [2018-09-14 15:51:21,999 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 17 states. [2018-09-14 15:51:22,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:22,367 INFO L93 Difference]: Finished difference Result 103 states and 118 transitions. [2018-09-14 15:51:22,369 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-09-14 15:51:22,369 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 39 [2018-09-14 15:51:22,369 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:22,370 INFO L225 Difference]: With dead ends: 103 [2018-09-14 15:51:22,370 INFO L226 Difference]: Without dead ends: 82 [2018-09-14 15:51:22,371 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 175 GetRequests, 134 SyntacticMatches, 16 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 251 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=171, Invalid=531, Unknown=0, NotChecked=0, Total=702 [2018-09-14 15:51:22,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2018-09-14 15:51:22,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 50. [2018-09-14 15:51:22,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-09-14 15:51:22,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2018-09-14 15:51:22,382 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 39 [2018-09-14 15:51:22,382 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:22,382 INFO L480 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2018-09-14 15:51:22,382 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-09-14 15:51:22,382 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2018-09-14 15:51:22,383 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-09-14 15:51:22,383 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:22,384 INFO L376 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:22,384 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:22,384 INFO L82 PathProgramCache]: Analyzing trace with hash -1103599739, now seen corresponding path program 2 times [2018-09-14 15:51:22,384 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:22,385 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:22,385 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:22,386 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:22,386 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:22,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:22,511 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-14 15:51:22,511 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:22,511 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:22,520 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:51:22,521 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:51:22,533 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:51:22,534 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:22,537 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:22,777 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-14 15:51:22,777 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:22,915 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-14 15:51:22,935 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:22,935 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:22,951 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:51:22,951 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:51:22,982 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:51:22,982 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:22,986 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:22,995 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-14 15:51:22,996 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:23,118 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-14 15:51:23,120 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:23,120 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 16 [2018-09-14 15:51:23,120 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:23,121 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-09-14 15:51:23,121 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-09-14 15:51:23,121 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=183, Unknown=0, NotChecked=0, Total=240 [2018-09-14 15:51:23,122 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 16 states. [2018-09-14 15:51:23,460 WARN L178 SmtUtils]: Spent 109.00 ms on a formula simplification that was a NOOP. DAG size: 11 [2018-09-14 15:51:23,765 WARN L178 SmtUtils]: Spent 144.00 ms on a formula simplification that was a NOOP. DAG size: 13 [2018-09-14 15:51:24,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:24,151 INFO L93 Difference]: Finished difference Result 122 states and 142 transitions. [2018-09-14 15:51:24,152 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-09-14 15:51:24,152 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 39 [2018-09-14 15:51:24,152 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:24,153 INFO L225 Difference]: With dead ends: 122 [2018-09-14 15:51:24,153 INFO L226 Difference]: Without dead ends: 101 [2018-09-14 15:51:24,154 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 175 GetRequests, 135 SyntacticMatches, 16 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 212 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=163, Invalid=487, Unknown=0, NotChecked=0, Total=650 [2018-09-14 15:51:24,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states. [2018-09-14 15:51:24,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 53. [2018-09-14 15:51:24,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53 states. [2018-09-14 15:51:24,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 58 transitions. [2018-09-14 15:51:24,165 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 58 transitions. Word has length 39 [2018-09-14 15:51:24,165 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:24,165 INFO L480 AbstractCegarLoop]: Abstraction has 53 states and 58 transitions. [2018-09-14 15:51:24,166 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-09-14 15:51:24,166 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 58 transitions. [2018-09-14 15:51:24,166 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-09-14 15:51:24,166 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:24,167 INFO L376 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:24,167 INFO L423 AbstractCegarLoop]: === Iteration 10 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:24,167 INFO L82 PathProgramCache]: Analyzing trace with hash -1990570393, now seen corresponding path program 4 times [2018-09-14 15:51:24,167 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:24,168 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:24,168 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:24,168 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:24,168 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:24,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:24,278 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 15 proven. 14 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-09-14 15:51:24,278 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:24,279 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:24,289 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:51:24,289 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:51:24,328 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:51:24,329 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:24,331 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:24,605 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-14 15:51:24,605 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:24,656 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-14 15:51:24,682 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:24,683 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:24,700 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:51:24,700 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:51:24,737 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:51:24,737 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:24,741 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:24,748 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-14 15:51:24,748 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:24,871 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-09-14 15:51:24,872 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:24,873 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 8, 8, 8] total 11 [2018-09-14 15:51:24,873 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:24,873 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-09-14 15:51:24,873 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-09-14 15:51:24,873 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2018-09-14 15:51:24,874 INFO L87 Difference]: Start difference. First operand 53 states and 58 transitions. Second operand 11 states. [2018-09-14 15:51:25,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:25,282 INFO L93 Difference]: Finished difference Result 63 states and 68 transitions. [2018-09-14 15:51:25,283 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-09-14 15:51:25,283 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 41 [2018-09-14 15:51:25,283 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:25,284 INFO L225 Difference]: With dead ends: 63 [2018-09-14 15:51:25,284 INFO L226 Difference]: Without dead ends: 61 [2018-09-14 15:51:25,285 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 177 GetRequests, 152 SyntacticMatches, 14 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 51 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=40, Invalid=116, Unknown=0, NotChecked=0, Total=156 [2018-09-14 15:51:25,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2018-09-14 15:51:25,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 61. [2018-09-14 15:51:25,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61 states. [2018-09-14 15:51:25,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 66 transitions. [2018-09-14 15:51:25,295 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 66 transitions. Word has length 41 [2018-09-14 15:51:25,295 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:25,295 INFO L480 AbstractCegarLoop]: Abstraction has 61 states and 66 transitions. [2018-09-14 15:51:25,295 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-09-14 15:51:25,295 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 66 transitions. [2018-09-14 15:51:25,296 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-09-14 15:51:25,296 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:25,297 INFO L376 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:25,297 INFO L423 AbstractCegarLoop]: === Iteration 11 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:25,297 INFO L82 PathProgramCache]: Analyzing trace with hash 1735104395, now seen corresponding path program 5 times [2018-09-14 15:51:25,297 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:25,298 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:25,298 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:25,298 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:25,298 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:25,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:25,505 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:25,506 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:25,506 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:25,513 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:51:25,513 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:51:25,531 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2018-09-14 15:51:25,532 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:25,534 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:25,912 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:25,913 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:25,994 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:26,014 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:26,014 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:26,029 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:51:26,029 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:51:26,082 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2018-09-14 15:51:26,082 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:26,087 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:26,097 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:26,097 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:26,271 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:26,273 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:26,273 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 22 [2018-09-14 15:51:26,273 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:26,274 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-09-14 15:51:26,274 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-09-14 15:51:26,274 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=103, Invalid=359, Unknown=0, NotChecked=0, Total=462 [2018-09-14 15:51:26,274 INFO L87 Difference]: Start difference. First operand 61 states and 66 transitions. Second operand 22 states. [2018-09-14 15:51:26,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:26,614 INFO L93 Difference]: Finished difference Result 110 states and 124 transitions. [2018-09-14 15:51:26,614 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-09-14 15:51:26,614 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 49 [2018-09-14 15:51:26,615 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:26,615 INFO L225 Difference]: With dead ends: 110 [2018-09-14 15:51:26,615 INFO L226 Difference]: Without dead ends: 85 [2018-09-14 15:51:26,616 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 217 GetRequests, 167 SyntacticMatches, 20 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 467 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=233, Invalid=759, Unknown=0, NotChecked=0, Total=992 [2018-09-14 15:51:26,617 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-09-14 15:51:26,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 63. [2018-09-14 15:51:26,626 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-09-14 15:51:26,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 68 transitions. [2018-09-14 15:51:26,627 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 68 transitions. Word has length 49 [2018-09-14 15:51:26,627 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:26,627 INFO L480 AbstractCegarLoop]: Abstraction has 63 states and 68 transitions. [2018-09-14 15:51:26,627 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-09-14 15:51:26,627 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 68 transitions. [2018-09-14 15:51:26,628 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-09-14 15:51:26,628 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:26,628 INFO L376 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:26,629 INFO L423 AbstractCegarLoop]: === Iteration 12 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:26,629 INFO L82 PathProgramCache]: Analyzing trace with hash 1916583447, now seen corresponding path program 2 times [2018-09-14 15:51:26,629 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:26,630 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:26,630 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:26,630 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:26,630 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:26,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:26,764 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:26,764 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:26,764 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:26,771 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:51:26,771 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:51:26,786 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:51:26,786 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:26,788 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:26,925 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:26,925 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:27,156 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:27,177 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:27,177 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:27,195 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:51:27,195 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:51:27,232 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:51:27,232 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:27,235 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:27,247 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:27,247 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:27,321 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:27,323 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:27,324 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 21 [2018-09-14 15:51:27,324 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:27,324 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-09-14 15:51:27,325 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-09-14 15:51:27,325 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=329, Unknown=0, NotChecked=0, Total=420 [2018-09-14 15:51:27,325 INFO L87 Difference]: Start difference. First operand 63 states and 68 transitions. Second operand 21 states. [2018-09-14 15:51:27,705 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:27,705 INFO L93 Difference]: Finished difference Result 132 states and 151 transitions. [2018-09-14 15:51:27,705 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-09-14 15:51:27,705 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 49 [2018-09-14 15:51:27,706 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:27,707 INFO L225 Difference]: With dead ends: 132 [2018-09-14 15:51:27,707 INFO L226 Difference]: Without dead ends: 107 [2018-09-14 15:51:27,708 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 220 GetRequests, 168 SyntacticMatches, 20 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 464 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=253, Invalid=869, Unknown=0, NotChecked=0, Total=1122 [2018-09-14 15:51:27,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-09-14 15:51:27,719 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 63. [2018-09-14 15:51:27,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-09-14 15:51:27,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 68 transitions. [2018-09-14 15:51:27,721 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 68 transitions. Word has length 49 [2018-09-14 15:51:27,721 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:27,721 INFO L480 AbstractCegarLoop]: Abstraction has 63 states and 68 transitions. [2018-09-14 15:51:27,721 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-09-14 15:51:27,721 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 68 transitions. [2018-09-14 15:51:27,722 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-09-14 15:51:27,722 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:27,722 INFO L376 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:27,723 INFO L423 AbstractCegarLoop]: === Iteration 13 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:27,723 INFO L82 PathProgramCache]: Analyzing trace with hash -402778205, now seen corresponding path program 3 times [2018-09-14 15:51:27,723 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:27,724 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:27,724 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:27,724 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:27,724 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:27,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:27,848 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:27,848 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:27,848 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:27,856 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:51:27,856 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:51:27,870 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-09-14 15:51:27,870 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:27,873 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:28,020 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:28,021 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:28,090 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:28,111 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:28,111 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:28,128 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:51:28,128 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:51:28,172 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-09-14 15:51:28,173 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:28,176 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:28,185 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:28,186 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:28,277 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:28,279 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:28,279 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 20 [2018-09-14 15:51:28,279 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:28,279 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-09-14 15:51:28,280 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-09-14 15:51:28,280 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=297, Unknown=0, NotChecked=0, Total=380 [2018-09-14 15:51:28,280 INFO L87 Difference]: Start difference. First operand 63 states and 68 transitions. Second operand 20 states. [2018-09-14 15:51:28,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:28,736 INFO L93 Difference]: Finished difference Result 152 states and 176 transitions. [2018-09-14 15:51:28,736 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-09-14 15:51:28,736 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 49 [2018-09-14 15:51:28,736 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:28,737 INFO L225 Difference]: With dead ends: 152 [2018-09-14 15:51:28,738 INFO L226 Difference]: Without dead ends: 127 [2018-09-14 15:51:28,739 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 221 GetRequests, 169 SyntacticMatches, 20 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 430 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=253, Invalid=869, Unknown=0, NotChecked=0, Total=1122 [2018-09-14 15:51:28,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2018-09-14 15:51:28,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 63. [2018-09-14 15:51:28,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-09-14 15:51:28,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 68 transitions. [2018-09-14 15:51:28,751 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 68 transitions. Word has length 49 [2018-09-14 15:51:28,752 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:28,752 INFO L480 AbstractCegarLoop]: Abstraction has 63 states and 68 transitions. [2018-09-14 15:51:28,752 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-09-14 15:51:28,752 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 68 transitions. [2018-09-14 15:51:28,753 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-09-14 15:51:28,753 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:28,754 INFO L376 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:28,754 INFO L423 AbstractCegarLoop]: === Iteration 14 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:28,755 INFO L82 PathProgramCache]: Analyzing trace with hash 488662063, now seen corresponding path program 3 times [2018-09-14 15:51:28,755 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:28,755 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:28,756 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:28,756 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:28,756 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:28,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:28,866 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:28,867 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:28,867 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:28,874 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:51:28,874 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:51:28,887 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-09-14 15:51:28,888 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:28,890 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:29,341 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:29,342 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:29,409 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:29,429 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:29,429 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:29,444 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:51:29,444 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:51:29,494 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-09-14 15:51:29,494 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:29,497 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:29,507 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:29,507 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:29,605 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:29,607 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:29,607 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 19 [2018-09-14 15:51:29,607 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:29,607 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-09-14 15:51:29,608 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-09-14 15:51:29,608 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=79, Invalid=263, Unknown=0, NotChecked=0, Total=342 [2018-09-14 15:51:29,608 INFO L87 Difference]: Start difference. First operand 63 states and 68 transitions. Second operand 19 states. [2018-09-14 15:51:30,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:30,183 INFO L93 Difference]: Finished difference Result 175 states and 205 transitions. [2018-09-14 15:51:30,183 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-09-14 15:51:30,184 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 49 [2018-09-14 15:51:30,184 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:30,185 INFO L225 Difference]: With dead ends: 175 [2018-09-14 15:51:30,185 INFO L226 Difference]: Without dead ends: 150 [2018-09-14 15:51:30,186 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 220 GetRequests, 170 SyntacticMatches, 20 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 359 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=233, Invalid=759, Unknown=0, NotChecked=0, Total=992 [2018-09-14 15:51:30,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-09-14 15:51:30,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 66. [2018-09-14 15:51:30,202 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-09-14 15:51:30,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 72 transitions. [2018-09-14 15:51:30,202 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 72 transitions. Word has length 49 [2018-09-14 15:51:30,202 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:30,203 INFO L480 AbstractCegarLoop]: Abstraction has 66 states and 72 transitions. [2018-09-14 15:51:30,203 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-09-14 15:51:30,203 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 72 transitions. [2018-09-14 15:51:30,203 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-09-14 15:51:30,204 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:30,204 INFO L376 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:30,204 INFO L423 AbstractCegarLoop]: === Iteration 15 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:30,204 INFO L82 PathProgramCache]: Analyzing trace with hash -396473339, now seen corresponding path program 6 times [2018-09-14 15:51:30,204 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:30,205 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:30,205 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:30,205 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:30,205 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:30,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:30,375 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 25 proven. 28 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-09-14 15:51:30,376 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:30,376 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:30,395 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:51:30,396 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:51:30,415 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2018-09-14 15:51:30,415 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:30,417 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:30,441 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 26 proven. 21 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:30,442 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:30,486 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 26 proven. 21 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:30,505 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:30,505 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:30,521 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:51:30,521 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:51:30,570 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2018-09-14 15:51:30,571 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:30,574 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:30,578 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 26 proven. 21 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:30,579 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:30,668 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 26 proven. 21 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-09-14 15:51:30,670 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:30,670 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 9, 9, 9] total 12 [2018-09-14 15:51:30,670 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:30,670 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-09-14 15:51:30,670 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-09-14 15:51:30,670 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=99, Unknown=0, NotChecked=0, Total=132 [2018-09-14 15:51:30,671 INFO L87 Difference]: Start difference. First operand 66 states and 72 transitions. Second operand 12 states. [2018-09-14 15:51:30,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:30,861 INFO L93 Difference]: Finished difference Result 76 states and 82 transitions. [2018-09-14 15:51:30,861 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-09-14 15:51:30,861 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 51 [2018-09-14 15:51:30,861 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:30,862 INFO L225 Difference]: With dead ends: 76 [2018-09-14 15:51:30,863 INFO L226 Difference]: Without dead ends: 74 [2018-09-14 15:51:30,863 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 219 GetRequests, 189 SyntacticMatches, 18 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 74 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=46, Invalid=136, Unknown=0, NotChecked=0, Total=182 [2018-09-14 15:51:30,864 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states. [2018-09-14 15:51:30,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 74. [2018-09-14 15:51:30,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-09-14 15:51:30,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 80 transitions. [2018-09-14 15:51:30,874 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 80 transitions. Word has length 51 [2018-09-14 15:51:30,875 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:30,875 INFO L480 AbstractCegarLoop]: Abstraction has 74 states and 80 transitions. [2018-09-14 15:51:30,875 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-09-14 15:51:30,875 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 80 transitions. [2018-09-14 15:51:30,876 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-09-14 15:51:30,876 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:30,876 INFO L376 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:30,877 INFO L423 AbstractCegarLoop]: === Iteration 16 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:30,877 INFO L82 PathProgramCache]: Analyzing trace with hash 928978729, now seen corresponding path program 7 times [2018-09-14 15:51:30,877 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:30,878 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:30,878 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:30,878 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:30,878 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:30,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:31,082 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:31,082 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:31,082 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:31,092 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:31,092 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:51:31,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:31,109 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:31,310 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:31,310 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:31,389 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:31,409 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:31,409 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:31,424 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:31,424 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:51:31,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:31,461 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:31,472 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:31,472 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:31,574 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:31,575 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:31,575 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 26 [2018-09-14 15:51:31,576 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:31,576 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-09-14 15:51:31,576 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-09-14 15:51:31,577 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=509, Unknown=0, NotChecked=0, Total=650 [2018-09-14 15:51:31,577 INFO L87 Difference]: Start difference. First operand 74 states and 80 transitions. Second operand 26 states. [2018-09-14 15:51:31,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:31,984 INFO L93 Difference]: Finished difference Result 133 states and 150 transitions. [2018-09-14 15:51:31,984 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-09-14 15:51:31,985 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 59 [2018-09-14 15:51:31,985 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:31,986 INFO L225 Difference]: With dead ends: 133 [2018-09-14 15:51:31,986 INFO L226 Difference]: Without dead ends: 104 [2018-09-14 15:51:31,987 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 261 GetRequests, 201 SyntacticMatches, 24 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 722 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=315, Invalid=1091, Unknown=0, NotChecked=0, Total=1406 [2018-09-14 15:51:31,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states. [2018-09-14 15:51:32,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 76. [2018-09-14 15:51:32,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76 states. [2018-09-14 15:51:32,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 82 transitions. [2018-09-14 15:51:32,001 INFO L78 Accepts]: Start accepts. Automaton has 76 states and 82 transitions. Word has length 59 [2018-09-14 15:51:32,001 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:32,001 INFO L480 AbstractCegarLoop]: Abstraction has 76 states and 82 transitions. [2018-09-14 15:51:32,001 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-09-14 15:51:32,001 INFO L276 IsEmpty]: Start isEmpty. Operand 76 states and 82 transitions. [2018-09-14 15:51:32,002 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-09-14 15:51:32,002 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:32,002 INFO L376 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 4, 4, 4, 4, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:32,002 INFO L423 AbstractCegarLoop]: === Iteration 17 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:32,003 INFO L82 PathProgramCache]: Analyzing trace with hash 277511861, now seen corresponding path program 4 times [2018-09-14 15:51:32,003 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:32,003 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:32,004 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:32,004 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:32,004 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:32,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:32,163 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:32,163 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:32,163 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:32,171 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:51:32,171 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:51:32,190 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:51:32,190 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:32,191 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:32,449 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:32,449 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:32,609 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:32,629 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:32,629 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:32,644 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:51:32,644 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:51:32,687 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:51:32,687 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:32,690 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:32,700 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:32,700 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:32,865 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:32,866 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:32,867 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 25 [2018-09-14 15:51:32,867 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:32,867 INFO L459 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-09-14 15:51:32,867 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-09-14 15:51:32,868 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=126, Invalid=474, Unknown=0, NotChecked=0, Total=600 [2018-09-14 15:51:32,868 INFO L87 Difference]: Start difference. First operand 76 states and 82 transitions. Second operand 25 states. [2018-09-14 15:51:33,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:33,483 INFO L93 Difference]: Finished difference Result 161 states and 184 transitions. [2018-09-14 15:51:33,483 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-09-14 15:51:33,483 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 59 [2018-09-14 15:51:33,483 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:33,484 INFO L225 Difference]: With dead ends: 161 [2018-09-14 15:51:33,484 INFO L226 Difference]: Without dead ends: 132 [2018-09-14 15:51:33,485 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 265 GetRequests, 202 SyntacticMatches, 24 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 742 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=351, Invalid=1289, Unknown=0, NotChecked=0, Total=1640 [2018-09-14 15:51:33,486 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-09-14 15:51:33,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 76. [2018-09-14 15:51:33,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76 states. [2018-09-14 15:51:33,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 82 transitions. [2018-09-14 15:51:33,501 INFO L78 Accepts]: Start accepts. Automaton has 76 states and 82 transitions. Word has length 59 [2018-09-14 15:51:33,501 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:33,501 INFO L480 AbstractCegarLoop]: Abstraction has 76 states and 82 transitions. [2018-09-14 15:51:33,501 INFO L481 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-09-14 15:51:33,501 INFO L276 IsEmpty]: Start isEmpty. Operand 76 states and 82 transitions. [2018-09-14 15:51:33,502 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-09-14 15:51:33,502 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:33,502 INFO L376 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 4, 4, 4, 4, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:33,502 INFO L423 AbstractCegarLoop]: === Iteration 18 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:33,502 INFO L82 PathProgramCache]: Analyzing trace with hash -129869503, now seen corresponding path program 5 times [2018-09-14 15:51:33,502 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:33,503 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:33,503 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:33,503 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:33,503 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:33,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:33,738 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 44 proven. 12 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:33,738 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:33,738 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:33,745 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:51:33,745 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:51:33,764 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2018-09-14 15:51:33,764 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:33,766 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:33,906 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 44 proven. 12 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:33,906 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:33,975 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 44 proven. 12 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:33,996 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:33,996 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:34,012 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:51:34,012 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:51:34,065 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2018-09-14 15:51:34,065 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:34,069 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:34,080 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 44 proven. 12 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:34,080 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:34,230 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 44 proven. 12 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:34,232 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:34,232 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 24 [2018-09-14 15:51:34,232 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:34,232 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-09-14 15:51:34,233 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-09-14 15:51:34,233 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=115, Invalid=437, Unknown=0, NotChecked=0, Total=552 [2018-09-14 15:51:34,233 INFO L87 Difference]: Start difference. First operand 76 states and 82 transitions. Second operand 24 states. [2018-09-14 15:51:34,754 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:34,754 INFO L93 Difference]: Finished difference Result 187 states and 216 transitions. [2018-09-14 15:51:34,754 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-09-14 15:51:34,754 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 59 [2018-09-14 15:51:34,755 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:34,756 INFO L225 Difference]: With dead ends: 187 [2018-09-14 15:51:34,756 INFO L226 Difference]: Without dead ends: 158 [2018-09-14 15:51:34,757 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 267 GetRequests, 203 SyntacticMatches, 24 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 724 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=364, Invalid=1358, Unknown=0, NotChecked=0, Total=1722 [2018-09-14 15:51:34,757 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states. [2018-09-14 15:51:34,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 76. [2018-09-14 15:51:34,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76 states. [2018-09-14 15:51:34,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 82 transitions. [2018-09-14 15:51:34,775 INFO L78 Accepts]: Start accepts. Automaton has 76 states and 82 transitions. Word has length 59 [2018-09-14 15:51:34,775 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:34,775 INFO L480 AbstractCegarLoop]: Abstraction has 76 states and 82 transitions. [2018-09-14 15:51:34,775 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-09-14 15:51:34,775 INFO L276 IsEmpty]: Start isEmpty. Operand 76 states and 82 transitions. [2018-09-14 15:51:34,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-09-14 15:51:34,776 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:34,776 INFO L376 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 4, 4, 4, 4, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:34,776 INFO L423 AbstractCegarLoop]: === Iteration 19 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:34,777 INFO L82 PathProgramCache]: Analyzing trace with hash -49846579, now seen corresponding path program 6 times [2018-09-14 15:51:34,777 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:34,777 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:34,778 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:34,778 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:34,778 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:34,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:36,015 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:36,015 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:36,015 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:36,023 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:51:36,023 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:51:36,045 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2018-09-14 15:51:36,046 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:36,049 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:37,665 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:37,665 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:37,793 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:37,814 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:37,814 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:37,832 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:51:37,832 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:51:37,895 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2018-09-14 15:51:37,895 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:37,899 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:37,911 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:37,911 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:38,110 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 44 proven. 14 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:38,111 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:38,111 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 23 [2018-09-14 15:51:38,111 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:38,112 INFO L459 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-09-14 15:51:38,112 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-09-14 15:51:38,112 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=108, Invalid=398, Unknown=0, NotChecked=0, Total=506 [2018-09-14 15:51:38,112 INFO L87 Difference]: Start difference. First operand 76 states and 82 transitions. Second operand 23 states. [2018-09-14 15:51:38,633 WARN L178 SmtUtils]: Spent 142.00 ms on a formula simplification that was a NOOP. DAG size: 13 [2018-09-14 15:51:38,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:38,780 INFO L93 Difference]: Finished difference Result 211 states and 246 transitions. [2018-09-14 15:51:38,780 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-09-14 15:51:38,780 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 59 [2018-09-14 15:51:38,780 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:38,782 INFO L225 Difference]: With dead ends: 211 [2018-09-14 15:51:38,782 INFO L226 Difference]: Without dead ends: 182 [2018-09-14 15:51:38,783 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 267 GetRequests, 204 SyntacticMatches, 24 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 659 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=351, Invalid=1289, Unknown=0, NotChecked=0, Total=1640 [2018-09-14 15:51:38,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states. [2018-09-14 15:51:38,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 76. [2018-09-14 15:51:38,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76 states. [2018-09-14 15:51:38,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 82 transitions. [2018-09-14 15:51:38,805 INFO L78 Accepts]: Start accepts. Automaton has 76 states and 82 transitions. Word has length 59 [2018-09-14 15:51:38,805 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:38,805 INFO L480 AbstractCegarLoop]: Abstraction has 76 states and 82 transitions. [2018-09-14 15:51:38,806 INFO L481 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-09-14 15:51:38,806 INFO L276 IsEmpty]: Start isEmpty. Operand 76 states and 82 transitions. [2018-09-14 15:51:38,806 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-09-14 15:51:38,806 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:38,807 INFO L376 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:38,807 INFO L423 AbstractCegarLoop]: === Iteration 20 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:38,807 INFO L82 PathProgramCache]: Analyzing trace with hash 1451911001, now seen corresponding path program 4 times [2018-09-14 15:51:38,807 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:38,808 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:38,808 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:38,808 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:38,808 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:38,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:38,998 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:38,998 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:38,998 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:39,006 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:51:39,006 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:51:39,049 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:51:39,050 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:39,051 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:39,162 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:39,162 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:39,244 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:39,264 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:39,264 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:39,279 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:51:39,279 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:51:39,325 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:51:39,326 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:39,329 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:39,337 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:39,337 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:39,434 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:39,435 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:39,435 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 22 [2018-09-14 15:51:39,435 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:39,436 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-09-14 15:51:39,436 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-09-14 15:51:39,436 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=357, Unknown=0, NotChecked=0, Total=462 [2018-09-14 15:51:39,436 INFO L87 Difference]: Start difference. First operand 76 states and 82 transitions. Second operand 22 states. [2018-09-14 15:51:39,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:39,840 INFO L93 Difference]: Finished difference Result 238 states and 280 transitions. [2018-09-14 15:51:39,841 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-09-14 15:51:39,841 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 59 [2018-09-14 15:51:39,841 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:39,842 INFO L225 Difference]: With dead ends: 238 [2018-09-14 15:51:39,842 INFO L226 Difference]: Without dead ends: 209 [2018-09-14 15:51:39,843 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 265 GetRequests, 205 SyntacticMatches, 24 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 544 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=315, Invalid=1091, Unknown=0, NotChecked=0, Total=1406 [2018-09-14 15:51:39,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 209 states. [2018-09-14 15:51:39,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 209 to 79. [2018-09-14 15:51:39,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79 states. [2018-09-14 15:51:39,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 86 transitions. [2018-09-14 15:51:39,868 INFO L78 Accepts]: Start accepts. Automaton has 79 states and 86 transitions. Word has length 59 [2018-09-14 15:51:39,868 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:39,868 INFO L480 AbstractCegarLoop]: Abstraction has 79 states and 86 transitions. [2018-09-14 15:51:39,868 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-09-14 15:51:39,868 INFO L276 IsEmpty]: Start isEmpty. Operand 79 states and 86 transitions. [2018-09-14 15:51:39,869 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-09-14 15:51:39,869 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:39,869 INFO L376 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:39,869 INFO L423 AbstractCegarLoop]: === Iteration 21 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:39,870 INFO L82 PathProgramCache]: Analyzing trace with hash 1954413347, now seen corresponding path program 8 times [2018-09-14 15:51:39,870 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:39,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:39,870 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:39,871 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:39,871 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:39,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:39,961 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 37 proven. 46 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-09-14 15:51:39,962 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:39,962 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:39,969 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:51:39,969 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:51:39,987 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:51:39,987 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:39,989 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:40,046 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 36 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:40,046 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:40,235 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 36 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:40,254 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:40,255 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:40,270 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:51:40,270 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:51:40,311 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:51:40,312 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:40,315 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:40,321 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 36 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:40,322 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:40,420 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 36 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-09-14 15:51:40,422 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:40,422 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 10, 10, 10] total 13 [2018-09-14 15:51:40,422 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:40,422 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-09-14 15:51:40,422 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-09-14 15:51:40,423 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=116, Unknown=0, NotChecked=0, Total=156 [2018-09-14 15:51:40,423 INFO L87 Difference]: Start difference. First operand 79 states and 86 transitions. Second operand 13 states. [2018-09-14 15:51:40,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:40,565 INFO L93 Difference]: Finished difference Result 89 states and 96 transitions. [2018-09-14 15:51:40,565 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-09-14 15:51:40,565 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 61 [2018-09-14 15:51:40,565 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:40,566 INFO L225 Difference]: With dead ends: 89 [2018-09-14 15:51:40,566 INFO L226 Difference]: Without dead ends: 87 [2018-09-14 15:51:40,567 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 261 GetRequests, 226 SyntacticMatches, 22 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 101 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=53, Invalid=157, Unknown=0, NotChecked=0, Total=210 [2018-09-14 15:51:40,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2018-09-14 15:51:40,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 87. [2018-09-14 15:51:40,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2018-09-14 15:51:40,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 94 transitions. [2018-09-14 15:51:40,585 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 94 transitions. Word has length 61 [2018-09-14 15:51:40,585 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:40,585 INFO L480 AbstractCegarLoop]: Abstraction has 87 states and 94 transitions. [2018-09-14 15:51:40,585 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-09-14 15:51:40,585 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 94 transitions. [2018-09-14 15:51:40,586 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-09-14 15:51:40,586 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:40,586 INFO L376 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:40,586 INFO L423 AbstractCegarLoop]: === Iteration 22 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:40,587 INFO L82 PathProgramCache]: Analyzing trace with hash 1550108743, now seen corresponding path program 9 times [2018-09-14 15:51:40,587 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:40,587 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:40,587 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:40,588 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:40,588 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:40,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:40,779 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:40,779 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:40,779 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:40,788 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:51:40,788 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:51:40,812 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-09-14 15:51:40,812 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:40,815 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:41,211 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:41,211 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:41,304 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:41,323 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:41,324 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:41,339 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:51:41,339 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:51:41,413 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-09-14 15:51:41,414 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:41,417 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:41,432 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:41,432 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:41,573 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:41,574 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:41,574 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 30 [2018-09-14 15:51:41,574 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:41,575 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-09-14 15:51:41,575 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-09-14 15:51:41,575 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=185, Invalid=685, Unknown=0, NotChecked=0, Total=870 [2018-09-14 15:51:41,575 INFO L87 Difference]: Start difference. First operand 87 states and 94 transitions. Second operand 30 states. [2018-09-14 15:51:42,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:42,016 INFO L93 Difference]: Finished difference Result 156 states and 176 transitions. [2018-09-14 15:51:42,017 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-09-14 15:51:42,018 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 69 [2018-09-14 15:51:42,018 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:42,019 INFO L225 Difference]: With dead ends: 156 [2018-09-14 15:51:42,019 INFO L226 Difference]: Without dead ends: 123 [2018-09-14 15:51:42,020 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 305 GetRequests, 235 SyntacticMatches, 28 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1032 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=409, Invalid=1483, Unknown=0, NotChecked=0, Total=1892 [2018-09-14 15:51:42,020 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states. [2018-09-14 15:51:42,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 89. [2018-09-14 15:51:42,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-09-14 15:51:42,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 96 transitions. [2018-09-14 15:51:42,047 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 96 transitions. Word has length 69 [2018-09-14 15:51:42,047 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:42,047 INFO L480 AbstractCegarLoop]: Abstraction has 89 states and 96 transitions. [2018-09-14 15:51:42,047 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-09-14 15:51:42,047 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 96 transitions. [2018-09-14 15:51:42,048 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-09-14 15:51:42,048 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:42,048 INFO L376 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 5, 5, 5, 5, 5, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:42,048 INFO L423 AbstractCegarLoop]: === Iteration 23 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:42,049 INFO L82 PathProgramCache]: Analyzing trace with hash 1825386707, now seen corresponding path program 7 times [2018-09-14 15:51:42,049 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:42,049 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:42,050 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:42,050 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:42,050 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:42,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:42,279 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:42,279 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:42,279 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:42,286 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:42,286 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:51:42,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:42,309 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:42,771 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:42,771 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:42,862 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:42,883 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:42,883 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:42,898 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:42,898 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:51:42,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:42,945 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:42,956 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:42,956 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:43,074 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:43,075 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:43,076 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 29 [2018-09-14 15:51:43,076 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:43,076 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-09-14 15:51:43,076 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-09-14 15:51:43,077 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=167, Invalid=645, Unknown=0, NotChecked=0, Total=812 [2018-09-14 15:51:43,077 INFO L87 Difference]: Start difference. First operand 89 states and 96 transitions. Second operand 29 states. [2018-09-14 15:51:43,586 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:43,586 INFO L93 Difference]: Finished difference Result 190 states and 217 transitions. [2018-09-14 15:51:43,587 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-09-14 15:51:43,587 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 69 [2018-09-14 15:51:43,587 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:43,588 INFO L225 Difference]: With dead ends: 190 [2018-09-14 15:51:43,588 INFO L226 Difference]: Without dead ends: 157 [2018-09-14 15:51:43,589 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 310 GetRequests, 236 SyntacticMatches, 28 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1085 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=465, Invalid=1791, Unknown=0, NotChecked=0, Total=2256 [2018-09-14 15:51:43,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-09-14 15:51:43,618 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 89. [2018-09-14 15:51:43,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-09-14 15:51:43,619 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 96 transitions. [2018-09-14 15:51:43,619 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 96 transitions. Word has length 69 [2018-09-14 15:51:43,619 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:43,619 INFO L480 AbstractCegarLoop]: Abstraction has 89 states and 96 transitions. [2018-09-14 15:51:43,619 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-09-14 15:51:43,619 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 96 transitions. [2018-09-14 15:51:43,620 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-09-14 15:51:43,620 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:43,620 INFO L376 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 5, 5, 5, 5, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:43,620 INFO L423 AbstractCegarLoop]: === Iteration 24 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:43,620 INFO L82 PathProgramCache]: Analyzing trace with hash -1995551649, now seen corresponding path program 8 times [2018-09-14 15:51:43,620 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:43,621 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:43,621 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:43,621 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:43,621 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:43,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:44,228 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:44,228 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:44,228 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:44,237 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:51:44,237 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:51:44,256 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:51:44,257 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:44,259 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:44,497 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:44,497 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:44,585 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:44,604 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:44,605 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:44,620 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:51:44,620 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:51:44,668 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:51:44,668 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:44,672 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:44,686 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:44,687 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:44,824 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:44,826 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:44,826 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 28 [2018-09-14 15:51:44,826 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:44,826 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-09-14 15:51:44,827 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-09-14 15:51:44,827 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=603, Unknown=0, NotChecked=0, Total=756 [2018-09-14 15:51:44,827 INFO L87 Difference]: Start difference. First operand 89 states and 96 transitions. Second operand 28 states. [2018-09-14 15:51:45,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:45,527 INFO L93 Difference]: Finished difference Result 222 states and 256 transitions. [2018-09-14 15:51:45,527 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-09-14 15:51:45,527 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 69 [2018-09-14 15:51:45,528 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:45,529 INFO L225 Difference]: With dead ends: 222 [2018-09-14 15:51:45,529 INFO L226 Difference]: Without dead ends: 189 [2018-09-14 15:51:45,530 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 313 GetRequests, 237 SyntacticMatches, 28 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1095 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=496, Invalid=1954, Unknown=0, NotChecked=0, Total=2450 [2018-09-14 15:51:45,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2018-09-14 15:51:45,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 89. [2018-09-14 15:51:45,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-09-14 15:51:45,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 96 transitions. [2018-09-14 15:51:45,576 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 96 transitions. Word has length 69 [2018-09-14 15:51:45,576 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:45,576 INFO L480 AbstractCegarLoop]: Abstraction has 89 states and 96 transitions. [2018-09-14 15:51:45,576 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-09-14 15:51:45,576 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 96 transitions. [2018-09-14 15:51:45,577 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-09-14 15:51:45,577 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:45,577 INFO L376 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 5, 5, 5, 5, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:45,577 INFO L423 AbstractCegarLoop]: === Iteration 25 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:45,578 INFO L82 PathProgramCache]: Analyzing trace with hash 632871659, now seen corresponding path program 9 times [2018-09-14 15:51:45,578 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:45,579 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:45,579 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:45,580 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:45,580 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:45,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:45,789 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:45,789 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:45,789 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:45,797 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:51:45,797 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:51:45,820 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-09-14 15:51:45,820 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:45,823 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:46,003 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:46,003 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:46,090 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:46,110 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:46,110 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:46,125 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:51:46,125 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:51:46,198 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-09-14 15:51:46,198 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:46,202 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:46,215 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:46,215 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:46,350 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 65 proven. 18 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:46,352 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:46,353 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 27 [2018-09-14 15:51:46,353 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:46,355 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-09-14 15:51:46,355 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-09-14 15:51:46,355 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=143, Invalid=559, Unknown=0, NotChecked=0, Total=702 [2018-09-14 15:51:46,356 INFO L87 Difference]: Start difference. First operand 89 states and 96 transitions. Second operand 27 states. [2018-09-14 15:51:47,339 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:47,340 INFO L93 Difference]: Finished difference Result 252 states and 293 transitions. [2018-09-14 15:51:47,341 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-09-14 15:51:47,341 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 69 [2018-09-14 15:51:47,341 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:47,342 INFO L225 Difference]: With dead ends: 252 [2018-09-14 15:51:47,342 INFO L226 Difference]: Without dead ends: 219 [2018-09-14 15:51:47,343 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 314 GetRequests, 238 SyntacticMatches, 28 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1048 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=496, Invalid=1954, Unknown=0, NotChecked=0, Total=2450 [2018-09-14 15:51:47,343 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219 states. [2018-09-14 15:51:47,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219 to 89. [2018-09-14 15:51:47,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-09-14 15:51:47,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 96 transitions. [2018-09-14 15:51:47,380 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 96 transitions. Word has length 69 [2018-09-14 15:51:47,380 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:47,380 INFO L480 AbstractCegarLoop]: Abstraction has 89 states and 96 transitions. [2018-09-14 15:51:47,380 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-09-14 15:51:47,380 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 96 transitions. [2018-09-14 15:51:47,381 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-09-14 15:51:47,381 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:47,381 INFO L376 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 5, 5, 5, 5, 5, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:47,381 INFO L423 AbstractCegarLoop]: === Iteration 26 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:47,381 INFO L82 PathProgramCache]: Analyzing trace with hash 613260407, now seen corresponding path program 10 times [2018-09-14 15:51:47,381 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:47,382 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:47,382 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:47,382 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:47,382 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:47,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:47,626 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:47,626 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:47,626 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:47,633 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:51:47,633 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:51:47,651 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:51:47,651 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:47,653 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:47,910 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:47,910 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:47,999 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:48,019 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:48,019 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:48,036 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:51:48,036 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:51:48,082 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:51:48,083 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:48,087 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:48,100 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:48,100 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:48,248 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 65 proven. 22 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:48,250 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:48,250 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 26 [2018-09-14 15:51:48,250 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:48,250 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-09-14 15:51:48,251 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-09-14 15:51:48,251 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=137, Invalid=513, Unknown=0, NotChecked=0, Total=650 [2018-09-14 15:51:48,251 INFO L87 Difference]: Start difference. First operand 89 states and 96 transitions. Second operand 26 states. [2018-09-14 15:51:48,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:48,818 INFO L93 Difference]: Finished difference Result 280 states and 328 transitions. [2018-09-14 15:51:48,818 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-09-14 15:51:48,818 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 69 [2018-09-14 15:51:48,819 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:48,820 INFO L225 Difference]: With dead ends: 280 [2018-09-14 15:51:48,820 INFO L226 Difference]: Without dead ends: 247 [2018-09-14 15:51:48,821 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 313 GetRequests, 239 SyntacticMatches, 28 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 938 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=465, Invalid=1791, Unknown=0, NotChecked=0, Total=2256 [2018-09-14 15:51:48,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 247 states. [2018-09-14 15:51:48,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 247 to 89. [2018-09-14 15:51:48,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-09-14 15:51:48,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 96 transitions. [2018-09-14 15:51:48,856 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 96 transitions. Word has length 69 [2018-09-14 15:51:48,857 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:48,857 INFO L480 AbstractCegarLoop]: Abstraction has 89 states and 96 transitions. [2018-09-14 15:51:48,857 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-09-14 15:51:48,857 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 96 transitions. [2018-09-14 15:51:48,857 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-09-14 15:51:48,858 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:48,858 INFO L376 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:48,858 INFO L423 AbstractCegarLoop]: === Iteration 27 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:48,858 INFO L82 PathProgramCache]: Analyzing trace with hash 1618825475, now seen corresponding path program 5 times [2018-09-14 15:51:48,858 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:48,859 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:48,859 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:48,859 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:48,859 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:48,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:49,028 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:49,028 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:49,028 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:49,037 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:51:49,037 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:51:49,058 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-09-14 15:51:49,059 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:49,062 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:49,376 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:49,376 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:49,461 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:49,480 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:49,481 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:49,496 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:51:49,496 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:51:49,567 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-09-14 15:51:49,567 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:49,570 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:49,584 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:49,584 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:49,765 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:49,766 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:49,766 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 25 [2018-09-14 15:51:49,766 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:49,767 INFO L459 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-09-14 15:51:49,767 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-09-14 15:51:49,767 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=135, Invalid=465, Unknown=0, NotChecked=0, Total=600 [2018-09-14 15:51:49,767 INFO L87 Difference]: Start difference. First operand 89 states and 96 transitions. Second operand 25 states. [2018-09-14 15:51:50,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:50,438 INFO L93 Difference]: Finished difference Result 311 states and 367 transitions. [2018-09-14 15:51:50,438 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-09-14 15:51:50,438 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 69 [2018-09-14 15:51:50,438 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:50,440 INFO L225 Difference]: With dead ends: 311 [2018-09-14 15:51:50,440 INFO L226 Difference]: Without dead ends: 278 [2018-09-14 15:51:50,441 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 310 GetRequests, 240 SyntacticMatches, 28 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 767 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=409, Invalid=1483, Unknown=0, NotChecked=0, Total=1892 [2018-09-14 15:51:50,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 278 states. [2018-09-14 15:51:50,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 278 to 92. [2018-09-14 15:51:50,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2018-09-14 15:51:50,481 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 100 transitions. [2018-09-14 15:51:50,481 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 100 transitions. Word has length 69 [2018-09-14 15:51:50,481 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:50,481 INFO L480 AbstractCegarLoop]: Abstraction has 92 states and 100 transitions. [2018-09-14 15:51:50,481 INFO L481 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-09-14 15:51:50,481 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 100 transitions. [2018-09-14 15:51:50,482 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-09-14 15:51:50,482 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:50,482 INFO L376 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 6, 6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:50,482 INFO L423 AbstractCegarLoop]: === Iteration 28 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:50,483 INFO L82 PathProgramCache]: Analyzing trace with hash 2111470529, now seen corresponding path program 10 times [2018-09-14 15:51:50,483 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:50,483 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:50,483 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:50,483 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:50,484 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:50,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:51,065 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 51 proven. 68 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-09-14 15:51:51,065 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:51,065 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:51,080 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:51:51,080 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:51:51,125 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:51:51,126 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:51,128 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:51,234 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 52 proven. 55 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:51,234 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:51,292 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 52 proven. 55 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:51,311 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:51,311 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:51,326 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:51:51,327 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:51:51,381 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:51:51,381 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:51,385 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:51,393 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 52 proven. 55 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:51,394 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:51,473 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 52 proven. 55 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-09-14 15:51:51,474 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:51,474 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11, 11, 11, 11] total 14 [2018-09-14 15:51:51,474 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:51,474 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-09-14 15:51:51,475 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-09-14 15:51:51,475 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=134, Unknown=0, NotChecked=0, Total=182 [2018-09-14 15:51:51,475 INFO L87 Difference]: Start difference. First operand 92 states and 100 transitions. Second operand 14 states. [2018-09-14 15:51:52,255 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:52,255 INFO L93 Difference]: Finished difference Result 102 states and 110 transitions. [2018-09-14 15:51:52,256 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-09-14 15:51:52,256 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 71 [2018-09-14 15:51:52,256 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:52,257 INFO L225 Difference]: With dead ends: 102 [2018-09-14 15:51:52,257 INFO L226 Difference]: Without dead ends: 100 [2018-09-14 15:51:52,258 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 303 GetRequests, 263 SyntacticMatches, 26 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 132 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=61, Invalid=179, Unknown=0, NotChecked=0, Total=240 [2018-09-14 15:51:52,258 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states. [2018-09-14 15:51:52,286 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 100. [2018-09-14 15:51:52,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 100 states. [2018-09-14 15:51:52,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 108 transitions. [2018-09-14 15:51:52,286 INFO L78 Accepts]: Start accepts. Automaton has 100 states and 108 transitions. Word has length 71 [2018-09-14 15:51:52,287 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:52,287 INFO L480 AbstractCegarLoop]: Abstraction has 100 states and 108 transitions. [2018-09-14 15:51:52,287 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-09-14 15:51:52,287 INFO L276 IsEmpty]: Start isEmpty. Operand 100 states and 108 transitions. [2018-09-14 15:51:52,287 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-09-14 15:51:52,287 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:52,287 INFO L376 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:52,288 INFO L423 AbstractCegarLoop]: === Iteration 29 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:52,288 INFO L82 PathProgramCache]: Analyzing trace with hash 58575589, now seen corresponding path program 11 times [2018-09-14 15:51:52,288 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:52,288 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:52,288 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:52,289 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:52,289 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:52,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:52,492 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:51:52,492 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:52,493 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:52,501 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:51:52,502 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:51:52,530 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-09-14 15:51:52,530 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:52,533 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:53,844 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:51:53,844 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:53,964 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:51:53,984 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:53,984 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:53,999 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:51:53,999 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:51:54,084 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-09-14 15:51:54,084 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:54,089 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:54,106 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:51:54,106 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:54,240 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:51:54,241 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:54,242 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 34 [2018-09-14 15:51:54,242 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:54,242 INFO L459 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-09-14 15:51:54,242 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-09-14 15:51:54,243 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=235, Invalid=887, Unknown=0, NotChecked=0, Total=1122 [2018-09-14 15:51:54,243 INFO L87 Difference]: Start difference. First operand 100 states and 108 transitions. Second operand 34 states. [2018-09-14 15:51:54,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:54,935 INFO L93 Difference]: Finished difference Result 179 states and 202 transitions. [2018-09-14 15:51:54,935 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-09-14 15:51:54,935 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 79 [2018-09-14 15:51:54,935 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:54,936 INFO L225 Difference]: With dead ends: 179 [2018-09-14 15:51:54,936 INFO L226 Difference]: Without dead ends: 142 [2018-09-14 15:51:54,937 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 349 GetRequests, 269 SyntacticMatches, 32 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1397 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=515, Invalid=1935, Unknown=0, NotChecked=0, Total=2450 [2018-09-14 15:51:54,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2018-09-14 15:51:54,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 102. [2018-09-14 15:51:54,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-09-14 15:51:54,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 110 transitions. [2018-09-14 15:51:54,972 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 110 transitions. Word has length 79 [2018-09-14 15:51:54,972 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:54,972 INFO L480 AbstractCegarLoop]: Abstraction has 102 states and 110 transitions. [2018-09-14 15:51:54,972 INFO L481 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-09-14 15:51:54,972 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 110 transitions. [2018-09-14 15:51:54,973 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-09-14 15:51:54,973 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:54,973 INFO L376 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 6, 6, 6, 6, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:54,973 INFO L423 AbstractCegarLoop]: === Iteration 30 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:54,974 INFO L82 PathProgramCache]: Analyzing trace with hash 127267953, now seen corresponding path program 11 times [2018-09-14 15:51:54,974 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:54,974 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:54,975 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:54,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:54,975 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:54,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:55,186 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:51:55,186 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:55,186 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:55,193 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:51:55,193 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:51:55,304 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-09-14 15:51:55,305 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:55,307 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:55,775 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:51:55,776 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:55,886 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:51:55,907 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:55,908 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:55,923 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:51:55,923 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:51:56,006 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-09-14 15:51:56,006 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:56,010 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:56,026 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:51:56,026 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:56,188 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:51:56,189 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:56,189 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 33 [2018-09-14 15:51:56,189 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:56,190 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-09-14 15:51:56,190 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-09-14 15:51:56,190 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=214, Invalid=842, Unknown=0, NotChecked=0, Total=1056 [2018-09-14 15:51:56,191 INFO L87 Difference]: Start difference. First operand 102 states and 110 transitions. Second operand 33 states. [2018-09-14 15:51:56,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:56,900 INFO L93 Difference]: Finished difference Result 219 states and 250 transitions. [2018-09-14 15:51:56,901 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-09-14 15:51:56,901 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 79 [2018-09-14 15:51:56,902 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:56,902 INFO L225 Difference]: With dead ends: 219 [2018-09-14 15:51:56,902 INFO L226 Difference]: Without dead ends: 182 [2018-09-14 15:51:56,904 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 355 GetRequests, 270 SyntacticMatches, 32 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1493 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=595, Invalid=2375, Unknown=0, NotChecked=0, Total=2970 [2018-09-14 15:51:56,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states. [2018-09-14 15:51:56,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 102. [2018-09-14 15:51:56,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-09-14 15:51:56,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 110 transitions. [2018-09-14 15:51:56,937 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 110 transitions. Word has length 79 [2018-09-14 15:51:56,938 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:56,938 INFO L480 AbstractCegarLoop]: Abstraction has 102 states and 110 transitions. [2018-09-14 15:51:56,938 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-09-14 15:51:56,938 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 110 transitions. [2018-09-14 15:51:56,938 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-09-14 15:51:56,938 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:56,938 INFO L376 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 6, 6, 6, 6, 5, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:56,939 INFO L423 AbstractCegarLoop]: === Iteration 31 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:56,939 INFO L82 PathProgramCache]: Analyzing trace with hash 310579453, now seen corresponding path program 12 times [2018-09-14 15:51:56,939 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:56,940 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:56,940 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:56,940 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:56,940 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:56,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:57,167 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:51:57,167 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:57,167 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:57,174 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:51:57,174 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:51:57,199 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-09-14 15:51:57,199 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:57,202 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:57,497 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:51:57,497 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:57,617 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:51:57,638 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:57,638 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:57,653 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:51:57,653 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:51:57,740 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-09-14 15:51:57,740 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:57,744 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:57,757 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:51:57,758 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:58,250 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:51:58,251 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:58,251 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 32 [2018-09-14 15:51:58,252 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:58,252 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-09-14 15:51:58,252 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-09-14 15:51:58,253 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=197, Invalid=795, Unknown=0, NotChecked=0, Total=992 [2018-09-14 15:51:58,253 INFO L87 Difference]: Start difference. First operand 102 states and 110 transitions. Second operand 32 states. [2018-09-14 15:51:59,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:59,627 INFO L93 Difference]: Finished difference Result 257 states and 296 transitions. [2018-09-14 15:51:59,627 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-09-14 15:51:59,627 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 79 [2018-09-14 15:51:59,628 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:59,629 INFO L225 Difference]: With dead ends: 257 [2018-09-14 15:51:59,629 INFO L226 Difference]: Without dead ends: 220 [2018-09-14 15:51:59,631 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 359 GetRequests, 271 SyntacticMatches, 32 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1543 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=649, Invalid=2657, Unknown=0, NotChecked=0, Total=3306 [2018-09-14 15:51:59,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 220 states. [2018-09-14 15:51:59,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 220 to 102. [2018-09-14 15:51:59,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-09-14 15:51:59,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 110 transitions. [2018-09-14 15:51:59,698 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 110 transitions. Word has length 79 [2018-09-14 15:51:59,698 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:59,699 INFO L480 AbstractCegarLoop]: Abstraction has 102 states and 110 transitions. [2018-09-14 15:51:59,699 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-09-14 15:51:59,699 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 110 transitions. [2018-09-14 15:51:59,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-09-14 15:51:59,700 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:59,700 INFO L376 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 6, 6, 6, 6, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:59,700 INFO L423 AbstractCegarLoop]: === Iteration 32 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:59,700 INFO L82 PathProgramCache]: Analyzing trace with hash -1427775351, now seen corresponding path program 13 times [2018-09-14 15:51:59,700 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:59,701 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:59,701 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:59,701 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:59,702 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:59,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:00,193 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 90 proven. 24 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:00,193 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:00,193 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:00,202 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:00,202 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:00,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:00,227 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:00,433 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 90 proven. 24 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:00,433 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:00,625 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 90 proven. 24 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:00,645 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:00,646 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:00,661 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:00,661 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:00,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:00,712 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:00,726 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 90 proven. 24 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:00,726 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:00,973 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 90 proven. 24 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:00,974 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:00,974 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 31 [2018-09-14 15:52:00,974 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:00,975 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-09-14 15:52:00,975 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-09-14 15:52:00,975 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=184, Invalid=746, Unknown=0, NotChecked=0, Total=930 [2018-09-14 15:52:00,976 INFO L87 Difference]: Start difference. First operand 102 states and 110 transitions. Second operand 31 states. [2018-09-14 15:52:01,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:01,767 INFO L93 Difference]: Finished difference Result 293 states and 340 transitions. [2018-09-14 15:52:01,768 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-09-14 15:52:01,768 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 79 [2018-09-14 15:52:01,768 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:01,769 INFO L225 Difference]: With dead ends: 293 [2018-09-14 15:52:01,769 INFO L226 Difference]: Without dead ends: 256 [2018-09-14 15:52:01,771 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 361 GetRequests, 272 SyntacticMatches, 32 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1527 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=668, Invalid=2754, Unknown=0, NotChecked=0, Total=3422 [2018-09-14 15:52:01,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states. [2018-09-14 15:52:01,813 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 102. [2018-09-14 15:52:01,813 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-09-14 15:52:01,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 110 transitions. [2018-09-14 15:52:01,814 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 110 transitions. Word has length 79 [2018-09-14 15:52:01,814 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:01,814 INFO L480 AbstractCegarLoop]: Abstraction has 102 states and 110 transitions. [2018-09-14 15:52:01,815 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-09-14 15:52:01,815 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 110 transitions. [2018-09-14 15:52:01,815 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-09-14 15:52:01,815 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:01,815 INFO L376 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 6, 6, 6, 6, 5, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:01,816 INFO L423 AbstractCegarLoop]: === Iteration 33 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:01,816 INFO L82 PathProgramCache]: Analyzing trace with hash 143598357, now seen corresponding path program 14 times [2018-09-14 15:52:01,816 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:01,817 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:01,817 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:01,817 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:01,817 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:01,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:02,063 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:02,064 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:02,064 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:02,071 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:02,071 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:02,105 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:02,106 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:02,108 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:02,403 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:02,403 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:02,515 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:02,535 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:02,535 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:02,550 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:02,550 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:02,602 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:02,603 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:02,606 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:02,634 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:02,634 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:02,794 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 90 proven. 26 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:02,795 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:02,795 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 30 [2018-09-14 15:52:02,795 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:02,796 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-09-14 15:52:02,796 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-09-14 15:52:02,797 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=175, Invalid=695, Unknown=0, NotChecked=0, Total=870 [2018-09-14 15:52:02,797 INFO L87 Difference]: Start difference. First operand 102 states and 110 transitions. Second operand 30 states. [2018-09-14 15:52:03,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:03,640 INFO L93 Difference]: Finished difference Result 327 states and 382 transitions. [2018-09-14 15:52:03,640 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-09-14 15:52:03,641 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 79 [2018-09-14 15:52:03,641 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:03,642 INFO L225 Difference]: With dead ends: 327 [2018-09-14 15:52:03,643 INFO L226 Difference]: Without dead ends: 290 [2018-09-14 15:52:03,644 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 361 GetRequests, 273 SyntacticMatches, 32 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1436 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=649, Invalid=2657, Unknown=0, NotChecked=0, Total=3306 [2018-09-14 15:52:03,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 290 states. [2018-09-14 15:52:03,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 290 to 102. [2018-09-14 15:52:03,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-09-14 15:52:03,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 110 transitions. [2018-09-14 15:52:03,704 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 110 transitions. Word has length 79 [2018-09-14 15:52:03,704 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:03,704 INFO L480 AbstractCegarLoop]: Abstraction has 102 states and 110 transitions. [2018-09-14 15:52:03,704 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-09-14 15:52:03,704 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 110 transitions. [2018-09-14 15:52:03,705 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-09-14 15:52:03,705 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:03,705 INFO L376 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 6, 6, 6, 6, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:03,705 INFO L423 AbstractCegarLoop]: === Iteration 34 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:03,705 INFO L82 PathProgramCache]: Analyzing trace with hash -1602250591, now seen corresponding path program 15 times [2018-09-14 15:52:03,705 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:03,706 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:03,706 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:03,706 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:03,706 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:03,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:04,119 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:04,119 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:04,119 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:04,126 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:04,126 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:04,152 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2018-09-14 15:52:04,153 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:04,156 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:04,491 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:04,491 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:04,603 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:04,624 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:04,624 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:04,639 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:04,639 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:04,725 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2018-09-14 15:52:04,725 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:04,729 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:04,745 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:04,745 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:05,007 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 90 proven. 32 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:05,008 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:05,008 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 29 [2018-09-14 15:52:05,008 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:05,009 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-09-14 15:52:05,009 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-09-14 15:52:05,009 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=170, Invalid=642, Unknown=0, NotChecked=0, Total=812 [2018-09-14 15:52:05,010 INFO L87 Difference]: Start difference. First operand 102 states and 110 transitions. Second operand 29 states. [2018-09-14 15:52:06,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:06,519 INFO L93 Difference]: Finished difference Result 359 states and 422 transitions. [2018-09-14 15:52:06,520 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-09-14 15:52:06,521 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 79 [2018-09-14 15:52:06,521 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:06,523 INFO L225 Difference]: With dead ends: 359 [2018-09-14 15:52:06,523 INFO L226 Difference]: Without dead ends: 322 [2018-09-14 15:52:06,524 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 359 GetRequests, 274 SyntacticMatches, 32 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1267 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=595, Invalid=2375, Unknown=0, NotChecked=0, Total=2970 [2018-09-14 15:52:06,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 322 states. [2018-09-14 15:52:06,589 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 322 to 102. [2018-09-14 15:52:06,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-09-14 15:52:06,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 110 transitions. [2018-09-14 15:52:06,590 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 110 transitions. Word has length 79 [2018-09-14 15:52:06,590 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:06,591 INFO L480 AbstractCegarLoop]: Abstraction has 102 states and 110 transitions. [2018-09-14 15:52:06,591 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-09-14 15:52:06,591 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 110 transitions. [2018-09-14 15:52:06,591 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-09-14 15:52:06,593 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:06,593 INFO L376 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:06,593 INFO L423 AbstractCegarLoop]: === Iteration 35 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:06,594 INFO L82 PathProgramCache]: Analyzing trace with hash -1326972627, now seen corresponding path program 6 times [2018-09-14 15:52:06,594 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:06,594 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:06,594 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:06,594 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:06,595 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:06,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:07,323 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:07,323 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:07,323 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:07,330 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:07,331 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:07,360 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-09-14 15:52:07,360 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:07,363 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:07,552 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:07,552 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:07,663 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:07,683 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:07,683 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:07,698 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:07,698 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:07,780 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-09-14 15:52:07,780 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:07,784 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:07,798 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:07,798 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:07,944 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:07,945 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:07,945 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 28 [2018-09-14 15:52:07,945 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:07,945 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-09-14 15:52:07,945 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-09-14 15:52:07,946 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=169, Invalid=587, Unknown=0, NotChecked=0, Total=756 [2018-09-14 15:52:07,946 INFO L87 Difference]: Start difference. First operand 102 states and 110 transitions. Second operand 28 states. [2018-09-14 15:52:08,763 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:08,763 INFO L93 Difference]: Finished difference Result 394 states and 466 transitions. [2018-09-14 15:52:08,763 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-09-14 15:52:08,763 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 79 [2018-09-14 15:52:08,764 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:08,765 INFO L225 Difference]: With dead ends: 394 [2018-09-14 15:52:08,765 INFO L226 Difference]: Without dead ends: 357 [2018-09-14 15:52:08,766 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 355 GetRequests, 275 SyntacticMatches, 32 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1028 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=515, Invalid=1935, Unknown=0, NotChecked=0, Total=2450 [2018-09-14 15:52:08,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 357 states. [2018-09-14 15:52:08,819 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 357 to 105. [2018-09-14 15:52:08,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-09-14 15:52:08,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 114 transitions. [2018-09-14 15:52:08,820 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 114 transitions. Word has length 79 [2018-09-14 15:52:08,820 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:08,820 INFO L480 AbstractCegarLoop]: Abstraction has 105 states and 114 transitions. [2018-09-14 15:52:08,820 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-09-14 15:52:08,820 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 114 transitions. [2018-09-14 15:52:08,821 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-09-14 15:52:08,821 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:08,821 INFO L376 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:08,821 INFO L423 AbstractCegarLoop]: === Iteration 36 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:08,821 INFO L82 PathProgramCache]: Analyzing trace with hash 1957490143, now seen corresponding path program 12 times [2018-09-14 15:52:08,821 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:08,822 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:08,822 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:08,822 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:08,822 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:08,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:09,192 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 67 proven. 94 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-09-14 15:52:09,192 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:09,192 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:09,198 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:09,199 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:09,224 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-09-14 15:52:09,224 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:09,227 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:09,260 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 68 proven. 78 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:09,261 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:09,346 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 68 proven. 78 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:09,367 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:09,367 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:09,381 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:09,381 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:09,474 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-09-14 15:52:09,474 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:09,477 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:09,485 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 68 proven. 78 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:09,485 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:09,604 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 68 proven. 78 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-09-14 15:52:09,606 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:09,606 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 12, 12, 12, 12] total 15 [2018-09-14 15:52:09,606 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:09,606 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-09-14 15:52:09,606 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-09-14 15:52:09,607 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=153, Unknown=0, NotChecked=0, Total=210 [2018-09-14 15:52:09,607 INFO L87 Difference]: Start difference. First operand 105 states and 114 transitions. Second operand 15 states. [2018-09-14 15:52:09,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:09,865 INFO L93 Difference]: Finished difference Result 115 states and 124 transitions. [2018-09-14 15:52:09,865 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-09-14 15:52:09,866 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 81 [2018-09-14 15:52:09,866 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:09,867 INFO L225 Difference]: With dead ends: 115 [2018-09-14 15:52:09,867 INFO L226 Difference]: Without dead ends: 113 [2018-09-14 15:52:09,867 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 345 GetRequests, 300 SyntacticMatches, 30 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 167 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=70, Invalid=202, Unknown=0, NotChecked=0, Total=272 [2018-09-14 15:52:09,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2018-09-14 15:52:09,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 113. [2018-09-14 15:52:09,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-09-14 15:52:09,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 122 transitions. [2018-09-14 15:52:09,939 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 122 transitions. Word has length 81 [2018-09-14 15:52:09,939 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:09,939 INFO L480 AbstractCegarLoop]: Abstraction has 113 states and 122 transitions. [2018-09-14 15:52:09,940 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-09-14 15:52:09,940 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 122 transitions. [2018-09-14 15:52:09,940 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-09-14 15:52:09,942 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:09,942 INFO L376 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:09,943 INFO L423 AbstractCegarLoop]: === Iteration 37 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:09,943 INFO L82 PathProgramCache]: Analyzing trace with hash -507298045, now seen corresponding path program 13 times [2018-09-14 15:52:09,943 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:09,943 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:09,943 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:09,944 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:09,944 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:09,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:10,417 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:10,418 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:10,418 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:10,426 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:10,426 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:10,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:10,453 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:10,777 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:10,777 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:11,190 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:11,210 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:11,210 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 69 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:11,225 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:11,225 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:11,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:11,278 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:11,293 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:11,293 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:11,459 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:11,460 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:11,460 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 38 [2018-09-14 15:52:11,460 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:11,461 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-09-14 15:52:11,461 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-09-14 15:52:11,461 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=291, Invalid=1115, Unknown=0, NotChecked=0, Total=1406 [2018-09-14 15:52:11,461 INFO L87 Difference]: Start difference. First operand 113 states and 122 transitions. Second operand 38 states. [2018-09-14 15:52:12,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:12,103 INFO L93 Difference]: Finished difference Result 202 states and 228 transitions. [2018-09-14 15:52:12,103 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-09-14 15:52:12,103 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 89 [2018-09-14 15:52:12,103 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:12,104 INFO L225 Difference]: With dead ends: 202 [2018-09-14 15:52:12,104 INFO L226 Difference]: Without dead ends: 161 [2018-09-14 15:52:12,105 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 393 GetRequests, 303 SyntacticMatches, 36 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1817 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=633, Invalid=2447, Unknown=0, NotChecked=0, Total=3080 [2018-09-14 15:52:12,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161 states. [2018-09-14 15:52:12,167 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161 to 115. [2018-09-14 15:52:12,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-09-14 15:52:12,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 124 transitions. [2018-09-14 15:52:12,168 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 124 transitions. Word has length 89 [2018-09-14 15:52:12,168 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:12,168 INFO L480 AbstractCegarLoop]: Abstraction has 115 states and 124 transitions. [2018-09-14 15:52:12,168 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-09-14 15:52:12,168 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 124 transitions. [2018-09-14 15:52:12,169 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-09-14 15:52:12,169 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:12,169 INFO L376 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 7, 7, 7, 7, 7, 6, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:12,169 INFO L423 AbstractCegarLoop]: === Iteration 38 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:12,170 INFO L82 PathProgramCache]: Analyzing trace with hash -1248990833, now seen corresponding path program 16 times [2018-09-14 15:52:12,170 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:12,170 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:12,170 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:12,170 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:12,170 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:12,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:12,397 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:12,398 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:12,398 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:12,404 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:12,404 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:12,432 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:12,432 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:12,434 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:12,808 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:12,809 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:12,951 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:12,970 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:12,970 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:12,985 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:12,986 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:13,049 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:13,049 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:13,053 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:13,071 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:13,072 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:13,227 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:13,228 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:13,228 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 37 [2018-09-14 15:52:13,228 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:13,228 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-09-14 15:52:13,229 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-09-14 15:52:13,229 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=267, Invalid=1065, Unknown=0, NotChecked=0, Total=1332 [2018-09-14 15:52:13,229 INFO L87 Difference]: Start difference. First operand 115 states and 124 transitions. Second operand 37 states. [2018-09-14 15:52:13,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:13,914 INFO L93 Difference]: Finished difference Result 248 states and 283 transitions. [2018-09-14 15:52:13,914 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-09-14 15:52:13,914 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 89 [2018-09-14 15:52:13,915 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:13,916 INFO L225 Difference]: With dead ends: 248 [2018-09-14 15:52:13,916 INFO L226 Difference]: Without dead ends: 207 [2018-09-14 15:52:13,917 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 400 GetRequests, 304 SyntacticMatches, 36 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1966 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=741, Invalid=3041, Unknown=0, NotChecked=0, Total=3782 [2018-09-14 15:52:13,917 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 207 states. [2018-09-14 15:52:14,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 207 to 115. [2018-09-14 15:52:14,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-09-14 15:52:14,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 124 transitions. [2018-09-14 15:52:14,003 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 124 transitions. Word has length 89 [2018-09-14 15:52:14,003 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:14,003 INFO L480 AbstractCegarLoop]: Abstraction has 115 states and 124 transitions. [2018-09-14 15:52:14,003 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-09-14 15:52:14,003 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 124 transitions. [2018-09-14 15:52:14,004 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-09-14 15:52:14,004 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:14,004 INFO L376 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 7, 7, 7, 7, 6, 5, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:14,004 INFO L423 AbstractCegarLoop]: === Iteration 39 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:14,005 INFO L82 PathProgramCache]: Analyzing trace with hash 752469787, now seen corresponding path program 17 times [2018-09-14 15:52:14,005 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:14,005 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:14,005 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:14,006 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:14,006 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:14,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:14,882 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:14,882 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:14,882 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:14,890 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:14,890 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:15,014 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2018-09-14 15:52:15,015 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:15,017 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:15,511 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:15,511 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:15,663 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:15,682 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:15,682 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:15,697 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:15,697 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:15,793 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2018-09-14 15:52:15,793 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:15,797 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:15,831 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:15,832 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:16,169 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:16,170 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:16,171 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 36 [2018-09-14 15:52:16,171 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:16,171 INFO L459 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-09-14 15:52:16,171 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-09-14 15:52:16,171 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=247, Invalid=1013, Unknown=0, NotChecked=0, Total=1260 [2018-09-14 15:52:16,172 INFO L87 Difference]: Start difference. First operand 115 states and 124 transitions. Second operand 36 states. [2018-09-14 15:52:17,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:17,098 INFO L93 Difference]: Finished difference Result 292 states and 336 transitions. [2018-09-14 15:52:17,098 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-09-14 15:52:17,098 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 89 [2018-09-14 15:52:17,099 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:17,100 INFO L225 Difference]: With dead ends: 292 [2018-09-14 15:52:17,100 INFO L226 Difference]: Without dead ends: 251 [2018-09-14 15:52:17,101 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 405 GetRequests, 305 SyntacticMatches, 36 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2068 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=823, Invalid=3467, Unknown=0, NotChecked=0, Total=4290 [2018-09-14 15:52:17,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 251 states. [2018-09-14 15:52:17,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 251 to 115. [2018-09-14 15:52:17,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-09-14 15:52:17,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 124 transitions. [2018-09-14 15:52:17,178 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 124 transitions. Word has length 89 [2018-09-14 15:52:17,178 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:17,179 INFO L480 AbstractCegarLoop]: Abstraction has 115 states and 124 transitions. [2018-09-14 15:52:17,179 INFO L481 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-09-14 15:52:17,179 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 124 transitions. [2018-09-14 15:52:17,179 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-09-14 15:52:17,179 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:17,179 INFO L376 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 7, 7, 7, 7, 5, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:17,179 INFO L423 AbstractCegarLoop]: === Iteration 40 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:17,180 INFO L82 PathProgramCache]: Analyzing trace with hash -1940416601, now seen corresponding path program 18 times [2018-09-14 15:52:17,180 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:17,180 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:17,180 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:17,181 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:17,181 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:17,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:17,435 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:17,435 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:17,435 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:17,444 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:17,444 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:17,469 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-09-14 15:52:17,470 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:17,472 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:17,740 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:17,741 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:17,888 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:17,907 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:17,907 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 75 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:17,925 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:17,925 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:18,032 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-09-14 15:52:18,032 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:18,037 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:18,055 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:18,055 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:18,217 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:18,219 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:18,219 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 35 [2018-09-14 15:52:18,219 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:18,219 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-09-14 15:52:18,219 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-09-14 15:52:18,220 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=959, Unknown=0, NotChecked=0, Total=1190 [2018-09-14 15:52:18,220 INFO L87 Difference]: Start difference. First operand 115 states and 124 transitions. Second operand 35 states. [2018-09-14 15:52:19,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:19,454 INFO L93 Difference]: Finished difference Result 334 states and 387 transitions. [2018-09-14 15:52:19,455 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-09-14 15:52:19,455 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 89 [2018-09-14 15:52:19,455 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:19,456 INFO L225 Difference]: With dead ends: 334 [2018-09-14 15:52:19,456 INFO L226 Difference]: Without dead ends: 293 [2018-09-14 15:52:19,458 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 408 GetRequests, 306 SyntacticMatches, 36 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2097 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=867, Invalid=3689, Unknown=0, NotChecked=0, Total=4556 [2018-09-14 15:52:19,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 293 states. [2018-09-14 15:52:19,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 293 to 115. [2018-09-14 15:52:19,531 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-09-14 15:52:19,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 124 transitions. [2018-09-14 15:52:19,531 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 124 transitions. Word has length 89 [2018-09-14 15:52:19,532 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:19,532 INFO L480 AbstractCegarLoop]: Abstraction has 115 states and 124 transitions. [2018-09-14 15:52:19,532 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-09-14 15:52:19,532 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 124 transitions. [2018-09-14 15:52:19,533 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-09-14 15:52:19,533 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:19,533 INFO L376 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 7, 7, 7, 7, 5, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:19,533 INFO L423 AbstractCegarLoop]: === Iteration 41 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:19,533 INFO L82 PathProgramCache]: Analyzing trace with hash 233315123, now seen corresponding path program 19 times [2018-09-14 15:52:19,533 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:19,534 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:19,534 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:19,534 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:19,534 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:19,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:20,119 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:20,119 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:20,119 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:20,127 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:20,127 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:20,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:20,153 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:20,412 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:20,413 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:20,547 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:20,566 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:20,566 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 77 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:20,583 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:20,584 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:20,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:20,642 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:20,661 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:20,661 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:20,836 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 119 proven. 32 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:20,837 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:20,837 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 34 [2018-09-14 15:52:20,837 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:20,837 INFO L459 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-09-14 15:52:20,838 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-09-14 15:52:20,838 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=219, Invalid=903, Unknown=0, NotChecked=0, Total=1122 [2018-09-14 15:52:20,838 INFO L87 Difference]: Start difference. First operand 115 states and 124 transitions. Second operand 34 states. [2018-09-14 15:52:22,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:22,088 INFO L93 Difference]: Finished difference Result 374 states and 436 transitions. [2018-09-14 15:52:22,088 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-09-14 15:52:22,088 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 89 [2018-09-14 15:52:22,088 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:22,090 INFO L225 Difference]: With dead ends: 374 [2018-09-14 15:52:22,090 INFO L226 Difference]: Without dead ends: 333 [2018-09-14 15:52:22,090 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 409 GetRequests, 307 SyntacticMatches, 36 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2039 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=867, Invalid=3689, Unknown=0, NotChecked=0, Total=4556 [2018-09-14 15:52:22,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 333 states. [2018-09-14 15:52:22,168 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 333 to 115. [2018-09-14 15:52:22,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-09-14 15:52:22,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 124 transitions. [2018-09-14 15:52:22,169 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 124 transitions. Word has length 89 [2018-09-14 15:52:22,169 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:22,169 INFO L480 AbstractCegarLoop]: Abstraction has 115 states and 124 transitions. [2018-09-14 15:52:22,169 INFO L481 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-09-14 15:52:22,170 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 124 transitions. [2018-09-14 15:52:22,170 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-09-14 15:52:22,170 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:22,170 INFO L376 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 7, 7, 7, 7, 6, 5, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:22,170 INFO L423 AbstractCegarLoop]: === Iteration 42 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:22,170 INFO L82 PathProgramCache]: Analyzing trace with hash 1822167487, now seen corresponding path program 20 times [2018-09-14 15:52:22,170 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:22,171 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:22,171 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:22,171 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:22,171 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:22,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:22,409 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:22,409 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:22,409 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:22,416 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:22,416 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:22,439 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:22,440 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:22,441 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:22,696 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:22,696 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:22,824 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:22,844 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:22,844 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 79 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:22,859 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:22,859 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:22,917 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:22,917 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:22,921 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:22,940 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:22,940 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:24,588 INFO L134 CoverageAnalysis]: Checked inductivity of 239 backedges. 119 proven. 36 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:24,589 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:24,589 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 33 [2018-09-14 15:52:24,589 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:24,590 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-09-14 15:52:24,590 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-09-14 15:52:24,590 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=211, Invalid=845, Unknown=0, NotChecked=0, Total=1056 [2018-09-14 15:52:24,590 INFO L87 Difference]: Start difference. First operand 115 states and 124 transitions. Second operand 33 states. [2018-09-14 15:52:25,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:25,735 INFO L93 Difference]: Finished difference Result 412 states and 483 transitions. [2018-09-14 15:52:25,735 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-09-14 15:52:25,735 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 89 [2018-09-14 15:52:25,735 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:25,737 INFO L225 Difference]: With dead ends: 412 [2018-09-14 15:52:25,737 INFO L226 Difference]: Without dead ends: 371 [2018-09-14 15:52:25,738 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 408 GetRequests, 308 SyntacticMatches, 36 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1888 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=823, Invalid=3467, Unknown=0, NotChecked=0, Total=4290 [2018-09-14 15:52:25,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 371 states. [2018-09-14 15:52:25,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 371 to 115. [2018-09-14 15:52:25,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-09-14 15:52:25,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 124 transitions. [2018-09-14 15:52:25,838 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 124 transitions. Word has length 89 [2018-09-14 15:52:25,838 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:25,838 INFO L480 AbstractCegarLoop]: Abstraction has 115 states and 124 transitions. [2018-09-14 15:52:25,838 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-09-14 15:52:25,839 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 124 transitions. [2018-09-14 15:52:25,839 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-09-14 15:52:25,839 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:25,839 INFO L376 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 7, 7, 7, 7, 7, 6, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:25,840 INFO L423 AbstractCegarLoop]: === Iteration 43 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:25,840 INFO L82 PathProgramCache]: Analyzing trace with hash 1890859851, now seen corresponding path program 21 times [2018-09-14 15:52:25,840 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:25,841 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:25,841 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:25,841 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:25,841 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:25,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:26,275 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:26,275 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:26,275 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:26,282 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:26,282 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:26,310 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2018-09-14 15:52:26,311 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:26,313 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:26,667 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:26,667 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:26,804 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:26,824 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:26,824 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 81 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:26,839 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:26,840 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:26,947 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2018-09-14 15:52:26,948 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:26,952 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:26,971 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:26,971 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:27,148 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 119 proven. 44 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:27,149 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:27,149 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 32 [2018-09-14 15:52:27,149 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:27,149 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-09-14 15:52:27,150 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-09-14 15:52:27,150 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=207, Invalid=785, Unknown=0, NotChecked=0, Total=992 [2018-09-14 15:52:27,150 INFO L87 Difference]: Start difference. First operand 115 states and 124 transitions. Second operand 32 states. [2018-09-14 15:52:28,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:28,690 INFO L93 Difference]: Finished difference Result 448 states and 528 transitions. [2018-09-14 15:52:28,690 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-09-14 15:52:28,690 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 89 [2018-09-14 15:52:28,690 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:28,692 INFO L225 Difference]: With dead ends: 448 [2018-09-14 15:52:28,692 INFO L226 Difference]: Without dead ends: 407 [2018-09-14 15:52:28,693 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 405 GetRequests, 309 SyntacticMatches, 36 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1646 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=741, Invalid=3041, Unknown=0, NotChecked=0, Total=3782 [2018-09-14 15:52:28,693 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 407 states. [2018-09-14 15:52:28,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 407 to 115. [2018-09-14 15:52:28,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-09-14 15:52:28,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 124 transitions. [2018-09-14 15:52:28,780 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 124 transitions. Word has length 89 [2018-09-14 15:52:28,780 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:28,780 INFO L480 AbstractCegarLoop]: Abstraction has 115 states and 124 transitions. [2018-09-14 15:52:28,781 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-09-14 15:52:28,781 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 124 transitions. [2018-09-14 15:52:28,781 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-09-14 15:52:28,781 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:28,782 INFO L376 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:28,782 INFO L423 AbstractCegarLoop]: === Iteration 44 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:28,782 INFO L82 PathProgramCache]: Analyzing trace with hash 2074171351, now seen corresponding path program 7 times [2018-09-14 15:52:28,782 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:28,783 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:28,783 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:28,783 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:28,783 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:28,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:28,997 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:28,997 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:28,997 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:29,005 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:29,006 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:29,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:29,032 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:29,258 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:29,258 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:29,398 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:29,418 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:29,418 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 83 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 83 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:29,433 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:29,433 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:29,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:29,492 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:29,508 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:29,509 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:29,665 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:29,666 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:29,666 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 31 [2018-09-14 15:52:29,667 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:29,667 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-09-14 15:52:29,667 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-09-14 15:52:29,667 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=207, Invalid=723, Unknown=0, NotChecked=0, Total=930 [2018-09-14 15:52:29,667 INFO L87 Difference]: Start difference. First operand 115 states and 124 transitions. Second operand 31 states. [2018-09-14 15:52:30,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:30,883 INFO L93 Difference]: Finished difference Result 487 states and 577 transitions. [2018-09-14 15:52:30,884 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-09-14 15:52:30,884 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 89 [2018-09-14 15:52:30,884 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:30,886 INFO L225 Difference]: With dead ends: 487 [2018-09-14 15:52:30,886 INFO L226 Difference]: Without dead ends: 446 [2018-09-14 15:52:30,887 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 400 GetRequests, 310 SyntacticMatches, 36 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1327 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=633, Invalid=2447, Unknown=0, NotChecked=0, Total=3080 [2018-09-14 15:52:30,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 446 states. [2018-09-14 15:52:30,972 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 446 to 118. [2018-09-14 15:52:30,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-09-14 15:52:30,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 128 transitions. [2018-09-14 15:52:30,972 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 128 transitions. Word has length 89 [2018-09-14 15:52:30,973 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:30,973 INFO L480 AbstractCegarLoop]: Abstraction has 118 states and 128 transitions. [2018-09-14 15:52:30,973 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-09-14 15:52:30,973 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 128 transitions. [2018-09-14 15:52:30,973 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-09-14 15:52:30,973 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:30,974 INFO L376 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:30,974 INFO L423 AbstractCegarLoop]: === Iteration 45 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:30,974 INFO L82 PathProgramCache]: Analyzing trace with hash -1421446787, now seen corresponding path program 14 times [2018-09-14 15:52:30,974 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:30,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:30,975 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:30,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:30,975 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:30,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:31,257 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 85 proven. 124 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2018-09-14 15:52:31,258 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:31,258 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:31,265 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:31,265 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:31,291 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:31,291 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:31,293 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:31,351 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 86 proven. 105 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:31,351 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:31,690 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 86 proven. 105 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:31,709 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:31,709 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 85 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 85 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:31,724 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:31,724 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:31,785 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:31,786 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:31,790 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:31,803 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 86 proven. 105 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:31,803 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:32,007 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 86 proven. 105 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-09-14 15:52:32,008 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:32,008 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13, 13, 13, 13] total 16 [2018-09-14 15:52:32,009 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:32,009 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-09-14 15:52:32,009 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-09-14 15:52:32,009 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=173, Unknown=0, NotChecked=0, Total=240 [2018-09-14 15:52:32,009 INFO L87 Difference]: Start difference. First operand 118 states and 128 transitions. Second operand 16 states. [2018-09-14 15:52:32,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:32,543 INFO L93 Difference]: Finished difference Result 128 states and 138 transitions. [2018-09-14 15:52:32,543 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-09-14 15:52:32,543 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 91 [2018-09-14 15:52:32,544 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:32,545 INFO L225 Difference]: With dead ends: 128 [2018-09-14 15:52:32,545 INFO L226 Difference]: Without dead ends: 126 [2018-09-14 15:52:32,546 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 387 GetRequests, 337 SyntacticMatches, 34 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 206 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=80, Invalid=226, Unknown=0, NotChecked=0, Total=306 [2018-09-14 15:52:32,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-09-14 15:52:32,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 126. [2018-09-14 15:52:32,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 126 states. [2018-09-14 15:52:32,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 136 transitions. [2018-09-14 15:52:32,659 INFO L78 Accepts]: Start accepts. Automaton has 126 states and 136 transitions. Word has length 91 [2018-09-14 15:52:32,659 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:32,659 INFO L480 AbstractCegarLoop]: Abstraction has 126 states and 136 transitions. [2018-09-14 15:52:32,659 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-09-14 15:52:32,659 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 136 transitions. [2018-09-14 15:52:32,660 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-09-14 15:52:32,660 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:32,660 INFO L376 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:32,660 INFO L423 AbstractCegarLoop]: === Iteration 46 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:32,660 INFO L82 PathProgramCache]: Analyzing trace with hash -161069919, now seen corresponding path program 15 times [2018-09-14 15:52:32,661 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:32,661 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:32,661 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:32,661 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:32,662 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:32,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:32,935 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:32,936 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:32,936 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:32,943 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:32,943 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:32,979 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-09-14 15:52:32,979 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:32,982 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:33,360 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:33,360 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:33,990 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:34,010 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:34,010 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 87 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 87 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:34,026 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:34,026 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:34,153 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-09-14 15:52:34,153 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:34,157 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:34,182 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:34,182 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:34,833 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:34,835 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:34,835 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 42 [2018-09-14 15:52:34,835 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:34,836 INFO L459 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-09-14 15:52:34,836 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-09-14 15:52:34,837 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=353, Invalid=1369, Unknown=0, NotChecked=0, Total=1722 [2018-09-14 15:52:34,837 INFO L87 Difference]: Start difference. First operand 126 states and 136 transitions. Second operand 42 states. [2018-09-14 15:52:35,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:35,637 INFO L93 Difference]: Finished difference Result 225 states and 254 transitions. [2018-09-14 15:52:35,638 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-09-14 15:52:35,638 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 99 [2018-09-14 15:52:35,638 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:35,639 INFO L225 Difference]: With dead ends: 225 [2018-09-14 15:52:35,639 INFO L226 Difference]: Without dead ends: 180 [2018-09-14 15:52:35,639 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 437 GetRequests, 337 SyntacticMatches, 40 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2292 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=763, Invalid=3019, Unknown=0, NotChecked=0, Total=3782 [2018-09-14 15:52:35,640 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180 states. [2018-09-14 15:52:35,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180 to 128. [2018-09-14 15:52:35,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-09-14 15:52:35,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-09-14 15:52:35,729 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-09-14 15:52:35,729 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:35,729 INFO L480 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-09-14 15:52:35,729 INFO L481 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-09-14 15:52:35,729 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-09-14 15:52:35,730 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-09-14 15:52:35,730 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:35,730 INFO L376 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 8, 8, 8, 8, 8, 7, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:35,731 INFO L423 AbstractCegarLoop]: === Iteration 47 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:35,731 INFO L82 PathProgramCache]: Analyzing trace with hash 1635135533, now seen corresponding path program 22 times [2018-09-14 15:52:35,731 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:35,732 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:35,732 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:35,732 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:35,732 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:35,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:36,066 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:36,066 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:36,066 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:36,076 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:36,076 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:36,106 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:36,106 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:36,108 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:36,750 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:36,751 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:37,011 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:37,031 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:37,031 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 89 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 89 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:37,046 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:37,047 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:37,121 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:37,121 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:37,125 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:37,142 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:37,142 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:37,334 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:37,335 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:37,335 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 41 [2018-09-14 15:52:37,336 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:37,336 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-09-14 15:52:37,336 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-09-14 15:52:37,336 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=326, Invalid=1314, Unknown=0, NotChecked=0, Total=1640 [2018-09-14 15:52:37,336 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 41 states. [2018-09-14 15:52:38,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:38,394 INFO L93 Difference]: Finished difference Result 277 states and 316 transitions. [2018-09-14 15:52:38,394 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-09-14 15:52:38,395 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 99 [2018-09-14 15:52:38,395 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:38,396 INFO L225 Difference]: With dead ends: 277 [2018-09-14 15:52:38,396 INFO L226 Difference]: Without dead ends: 232 [2018-09-14 15:52:38,396 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 445 GetRequests, 338 SyntacticMatches, 40 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2504 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=903, Invalid=3789, Unknown=0, NotChecked=0, Total=4692 [2018-09-14 15:52:38,397 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 232 states. [2018-09-14 15:52:38,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 232 to 128. [2018-09-14 15:52:38,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-09-14 15:52:38,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-09-14 15:52:38,546 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-09-14 15:52:38,546 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:38,546 INFO L480 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-09-14 15:52:38,546 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-09-14 15:52:38,547 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-09-14 15:52:38,547 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-09-14 15:52:38,547 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:38,548 INFO L376 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 8, 8, 8, 8, 7, 6, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:38,548 INFO L423 AbstractCegarLoop]: === Iteration 48 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:38,548 INFO L82 PathProgramCache]: Analyzing trace with hash 1382256313, now seen corresponding path program 23 times [2018-09-14 15:52:38,548 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:38,549 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:38,549 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:38,549 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:38,549 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:38,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:38,860 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:38,861 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:38,861 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:38,869 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:38,870 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:38,900 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 9 check-sat command(s) [2018-09-14 15:52:38,900 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:38,903 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:39,283 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:39,283 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:39,476 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:39,496 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:39,496 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 91 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 91 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:39,515 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:39,515 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:39,640 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 9 check-sat command(s) [2018-09-14 15:52:39,640 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:39,644 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:39,661 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:39,661 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:39,896 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:39,898 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:39,898 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 40 [2018-09-14 15:52:39,898 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:39,898 INFO L459 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-09-14 15:52:39,899 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-09-14 15:52:39,899 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=303, Invalid=1257, Unknown=0, NotChecked=0, Total=1560 [2018-09-14 15:52:39,899 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 40 states. [2018-09-14 15:52:41,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:41,136 INFO L93 Difference]: Finished difference Result 327 states and 376 transitions. [2018-09-14 15:52:41,136 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-09-14 15:52:41,137 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 99 [2018-09-14 15:52:41,137 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:41,138 INFO L225 Difference]: With dead ends: 327 [2018-09-14 15:52:41,138 INFO L226 Difference]: Without dead ends: 282 [2018-09-14 15:52:41,139 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 451 GetRequests, 339 SyntacticMatches, 40 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2670 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1018, Invalid=4384, Unknown=0, NotChecked=0, Total=5402 [2018-09-14 15:52:41,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282 states. [2018-09-14 15:52:41,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282 to 128. [2018-09-14 15:52:41,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-09-14 15:52:41,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-09-14 15:52:41,238 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-09-14 15:52:41,238 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:41,238 INFO L480 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-09-14 15:52:41,238 INFO L481 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-09-14 15:52:41,238 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-09-14 15:52:41,238 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-09-14 15:52:41,238 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:41,239 INFO L376 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 8, 8, 8, 8, 6, 5, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:41,239 INFO L423 AbstractCegarLoop]: === Iteration 49 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:41,239 INFO L82 PathProgramCache]: Analyzing trace with hash 2012160069, now seen corresponding path program 24 times [2018-09-14 15:52:41,239 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:41,239 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:41,240 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:41,240 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:41,240 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:41,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:41,566 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:41,566 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:41,566 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:41,573 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:41,573 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:41,605 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2018-09-14 15:52:41,605 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:41,608 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:42,083 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:42,083 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:42,248 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:42,267 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:42,267 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 93 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 93 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:42,283 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:52:42,283 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:52:42,410 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2018-09-14 15:52:42,410 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:42,414 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:42,431 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:42,432 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:43,169 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:43,171 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:43,171 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 39 [2018-09-14 15:52:43,171 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:43,171 INFO L459 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-09-14 15:52:43,172 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-09-14 15:52:43,172 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=284, Invalid=1198, Unknown=0, NotChecked=0, Total=1482 [2018-09-14 15:52:43,172 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 39 states. [2018-09-14 15:52:44,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:44,739 INFO L93 Difference]: Finished difference Result 375 states and 434 transitions. [2018-09-14 15:52:44,739 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-09-14 15:52:44,739 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 99 [2018-09-14 15:52:44,740 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:44,741 INFO L225 Difference]: With dead ends: 375 [2018-09-14 15:52:44,741 INFO L226 Difference]: Without dead ends: 330 [2018-09-14 15:52:44,742 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 455 GetRequests, 340 SyntacticMatches, 40 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2758 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1093, Invalid=4759, Unknown=0, NotChecked=0, Total=5852 [2018-09-14 15:52:44,743 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 330 states. [2018-09-14 15:52:44,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 330 to 128. [2018-09-14 15:52:44,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-09-14 15:52:44,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-09-14 15:52:44,847 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-09-14 15:52:44,847 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:44,847 INFO L480 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-09-14 15:52:44,847 INFO L481 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-09-14 15:52:44,847 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-09-14 15:52:44,847 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-09-14 15:52:44,847 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:44,848 INFO L376 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 8, 8, 8, 8, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:44,848 INFO L423 AbstractCegarLoop]: === Iteration 50 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:44,848 INFO L82 PathProgramCache]: Analyzing trace with hash -1173773103, now seen corresponding path program 25 times [2018-09-14 15:52:44,848 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:44,848 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:44,849 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:44,849 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:44,849 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:44,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:45,098 INFO L134 CoverageAnalysis]: Checked inductivity of 304 backedges. 152 proven. 40 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:45,098 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:45,098 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:45,107 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:45,107 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:45,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:45,137 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:45,455 INFO L134 CoverageAnalysis]: Checked inductivity of 304 backedges. 152 proven. 40 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:45,455 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:45,612 INFO L134 CoverageAnalysis]: Checked inductivity of 304 backedges. 152 proven. 40 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:45,641 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:45,641 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 95 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 95 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:45,668 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:45,668 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:52:45,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:45,727 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:45,748 INFO L134 CoverageAnalysis]: Checked inductivity of 304 backedges. 152 proven. 40 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:45,748 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:45,948 INFO L134 CoverageAnalysis]: Checked inductivity of 304 backedges. 152 proven. 40 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:45,949 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:45,949 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 38 [2018-09-14 15:52:45,949 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:45,949 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-09-14 15:52:45,950 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-09-14 15:52:45,950 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=269, Invalid=1137, Unknown=0, NotChecked=0, Total=1406 [2018-09-14 15:52:45,950 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 38 states. [2018-09-14 15:52:47,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:47,561 INFO L93 Difference]: Finished difference Result 421 states and 490 transitions. [2018-09-14 15:52:47,562 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-09-14 15:52:47,562 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 99 [2018-09-14 15:52:47,562 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:47,563 INFO L225 Difference]: With dead ends: 421 [2018-09-14 15:52:47,563 INFO L226 Difference]: Without dead ends: 376 [2018-09-14 15:52:47,564 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 457 GetRequests, 341 SyntacticMatches, 40 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2748 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1119, Invalid=4887, Unknown=0, NotChecked=0, Total=6006 [2018-09-14 15:52:47,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 376 states. [2018-09-14 15:52:47,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 376 to 128. [2018-09-14 15:52:47,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-09-14 15:52:47,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-09-14 15:52:47,689 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-09-14 15:52:47,689 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:47,689 INFO L480 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-09-14 15:52:47,689 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-09-14 15:52:47,689 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-09-14 15:52:47,689 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-09-14 15:52:47,690 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:47,690 INFO L376 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 8, 8, 8, 8, 6, 5, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:47,690 INFO L423 AbstractCegarLoop]: === Iteration 51 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:47,690 INFO L82 PathProgramCache]: Analyzing trace with hash -975971235, now seen corresponding path program 26 times [2018-09-14 15:52:47,690 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:47,691 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:47,691 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:52:47,691 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:47,691 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:47,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:48,192 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:48,193 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:48,193 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 96 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 96 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:48,200 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:48,200 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:48,229 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:48,230 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:48,231 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:48,518 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:48,518 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:48,673 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:48,693 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:48,693 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 97 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 97 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:48,708 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:48,708 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:48,772 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:48,773 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:48,777 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:48,794 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:48,794 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:49,033 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 152 proven. 42 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:49,034 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:49,035 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 37 [2018-09-14 15:52:49,035 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:49,035 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-09-14 15:52:49,035 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-09-14 15:52:49,036 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=258, Invalid=1074, Unknown=0, NotChecked=0, Total=1332 [2018-09-14 15:52:49,036 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 37 states. [2018-09-14 15:52:50,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:50,619 INFO L93 Difference]: Finished difference Result 465 states and 544 transitions. [2018-09-14 15:52:50,619 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-09-14 15:52:50,620 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 99 [2018-09-14 15:52:50,620 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:50,622 INFO L225 Difference]: With dead ends: 465 [2018-09-14 15:52:50,622 INFO L226 Difference]: Without dead ends: 420 [2018-09-14 15:52:50,623 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 457 GetRequests, 342 SyntacticMatches, 40 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2631 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1093, Invalid=4759, Unknown=0, NotChecked=0, Total=5852 [2018-09-14 15:52:50,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 420 states. [2018-09-14 15:52:50,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 420 to 128. [2018-09-14 15:52:50,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-09-14 15:52:50,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-09-14 15:52:50,741 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-09-14 15:52:50,741 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:50,741 INFO L480 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-09-14 15:52:50,741 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-09-14 15:52:50,741 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-09-14 15:52:50,742 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-09-14 15:52:50,742 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:50,742 INFO L376 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 8, 8, 8, 8, 7, 6, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:50,743 INFO L423 AbstractCegarLoop]: === Iteration 52 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:50,743 INFO L82 PathProgramCache]: Analyzing trace with hash -1717664023, now seen corresponding path program 27 times [2018-09-14 15:52:50,743 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:50,743 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:50,743 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:50,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:50,744 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:50,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:51,469 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:51,469 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:51,469 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 98 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 98 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:51,476 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:51,476 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:51,507 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-09-14 15:52:51,507 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:51,509 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:51,940 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:51,940 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:52,173 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:52,195 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:52,195 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 99 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 99 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:52,209 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:52:52,210 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:52,347 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-09-14 15:52:52,348 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:52,352 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:52,369 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:52,369 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:52,552 INFO L134 CoverageAnalysis]: Checked inductivity of 312 backedges. 152 proven. 48 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:52,553 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:52,553 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 36 [2018-09-14 15:52:52,553 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:52,553 INFO L459 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-09-14 15:52:52,553 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-09-14 15:52:52,554 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=251, Invalid=1009, Unknown=0, NotChecked=0, Total=1260 [2018-09-14 15:52:52,554 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 36 states. [2018-09-14 15:52:54,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:54,315 INFO L93 Difference]: Finished difference Result 507 states and 596 transitions. [2018-09-14 15:52:54,315 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-09-14 15:52:54,315 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 99 [2018-09-14 15:52:54,316 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:54,317 INFO L225 Difference]: With dead ends: 507 [2018-09-14 15:52:54,317 INFO L226 Difference]: Without dead ends: 462 [2018-09-14 15:52:54,318 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 455 GetRequests, 343 SyntacticMatches, 40 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2404 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1018, Invalid=4384, Unknown=0, NotChecked=0, Total=5402 [2018-09-14 15:52:54,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 462 states. [2018-09-14 15:52:54,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 462 to 128. [2018-09-14 15:52:54,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-09-14 15:52:54,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-09-14 15:52:54,441 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-09-14 15:52:54,441 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:54,442 INFO L480 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-09-14 15:52:54,442 INFO L481 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-09-14 15:52:54,442 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-09-14 15:52:54,442 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-09-14 15:52:54,442 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:54,442 INFO L376 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 8, 8, 8, 8, 8, 7, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:54,443 INFO L423 AbstractCegarLoop]: === Iteration 53 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:54,443 INFO L82 PathProgramCache]: Analyzing trace with hash 283796597, now seen corresponding path program 28 times [2018-09-14 15:52:54,443 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:54,443 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:54,443 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:54,443 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:54,444 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:54,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:54,736 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:54,736 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:54,736 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 100 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 100 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:54,743 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:54,744 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:54,771 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:54,771 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:54,773 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:55,048 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:55,048 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:55,209 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:55,229 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:55,229 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 101 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 101 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:55,245 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:55,245 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:55,320 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:55,320 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:55,324 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:55,344 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:55,345 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:55,610 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 152 proven. 58 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:55,611 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:55,611 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 35 [2018-09-14 15:52:55,611 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:55,612 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-09-14 15:52:55,612 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-09-14 15:52:55,612 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=248, Invalid=942, Unknown=0, NotChecked=0, Total=1190 [2018-09-14 15:52:55,612 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 35 states. [2018-09-14 15:52:57,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:57,459 INFO L93 Difference]: Finished difference Result 547 states and 646 transitions. [2018-09-14 15:52:57,459 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-09-14 15:52:57,459 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 99 [2018-09-14 15:52:57,460 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:57,462 INFO L225 Difference]: With dead ends: 547 [2018-09-14 15:52:57,462 INFO L226 Difference]: Without dead ends: 502 [2018-09-14 15:52:57,463 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 451 GetRequests, 344 SyntacticMatches, 40 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2075 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=903, Invalid=3789, Unknown=0, NotChecked=0, Total=4692 [2018-09-14 15:52:57,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 502 states. [2018-09-14 15:52:57,595 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 502 to 128. [2018-09-14 15:52:57,595 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-09-14 15:52:57,596 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 138 transitions. [2018-09-14 15:52:57,596 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 138 transitions. Word has length 99 [2018-09-14 15:52:57,596 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:57,596 INFO L480 AbstractCegarLoop]: Abstraction has 128 states and 138 transitions. [2018-09-14 15:52:57,596 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-09-14 15:52:57,596 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 138 transitions. [2018-09-14 15:52:57,596 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-09-14 15:52:57,597 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:57,597 INFO L376 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:57,597 INFO L423 AbstractCegarLoop]: === Iteration 54 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:57,597 INFO L82 PathProgramCache]: Analyzing trace with hash 1885877505, now seen corresponding path program 8 times [2018-09-14 15:52:57,597 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:57,598 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:57,598 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:57,598 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:57,598 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:57,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:57,860 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:57,861 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:57,861 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 102 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 102 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:57,867 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:57,867 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:57,892 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:57,892 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:57,894 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:58,151 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:58,151 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:58,310 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:58,329 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:58,330 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 103 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 103 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:58,344 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:52:58,344 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:58,410 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:52:58,410 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:58,416 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:58,435 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:58,435 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:58,625 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:52:58,627 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:58,627 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 34 [2018-09-14 15:52:58,627 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:58,627 INFO L459 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-09-14 15:52:58,628 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-09-14 15:52:58,628 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=249, Invalid=873, Unknown=0, NotChecked=0, Total=1122 [2018-09-14 15:52:58,628 INFO L87 Difference]: Start difference. First operand 128 states and 138 transitions. Second operand 34 states. [2018-09-14 15:53:00,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:00,302 INFO L93 Difference]: Finished difference Result 590 states and 700 transitions. [2018-09-14 15:53:00,303 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-09-14 15:53:00,303 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 99 [2018-09-14 15:53:00,303 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:00,305 INFO L225 Difference]: With dead ends: 590 [2018-09-14 15:53:00,305 INFO L226 Difference]: Without dead ends: 545 [2018-09-14 15:53:00,306 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 445 GetRequests, 345 SyntacticMatches, 40 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1664 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=763, Invalid=3019, Unknown=0, NotChecked=0, Total=3782 [2018-09-14 15:53:00,306 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 545 states. [2018-09-14 15:53:00,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 545 to 131. [2018-09-14 15:53:00,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2018-09-14 15:53:00,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 142 transitions. [2018-09-14 15:53:00,452 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 142 transitions. Word has length 99 [2018-09-14 15:53:00,452 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:00,453 INFO L480 AbstractCegarLoop]: Abstraction has 131 states and 142 transitions. [2018-09-14 15:53:00,453 INFO L481 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-09-14 15:53:00,453 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 142 transitions. [2018-09-14 15:53:00,453 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2018-09-14 15:53:00,453 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:00,454 INFO L376 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 9, 9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:00,454 INFO L423 AbstractCegarLoop]: === Iteration 55 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:00,454 INFO L82 PathProgramCache]: Analyzing trace with hash -1743772005, now seen corresponding path program 16 times [2018-09-14 15:53:00,454 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:00,455 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:00,455 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:00,455 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:00,455 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:00,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:00,603 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 105 proven. 158 refuted. 0 times theorem prover too weak. 91 trivial. 0 not checked. [2018-09-14 15:53:00,604 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:00,604 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 104 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 104 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:00,610 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:53:00,610 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:53:00,637 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:53:00,638 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:00,639 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:00,692 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 106 proven. 136 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:53:00,692 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:00,801 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 106 proven. 136 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:53:00,821 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:00,821 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 105 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 105 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:00,836 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:53:00,836 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:53:00,914 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:53:00,914 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:00,919 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:00,929 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 106 proven. 136 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:53:00,929 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:01,061 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 106 proven. 136 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-09-14 15:53:01,062 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:01,062 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 14, 14, 14, 14] total 17 [2018-09-14 15:53:01,062 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:01,063 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-09-14 15:53:01,063 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-09-14 15:53:01,063 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=194, Unknown=0, NotChecked=0, Total=272 [2018-09-14 15:53:01,063 INFO L87 Difference]: Start difference. First operand 131 states and 142 transitions. Second operand 17 states. [2018-09-14 15:53:01,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:01,386 INFO L93 Difference]: Finished difference Result 141 states and 152 transitions. [2018-09-14 15:53:01,386 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-09-14 15:53:01,386 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 101 [2018-09-14 15:53:01,387 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:01,387 INFO L225 Difference]: With dead ends: 141 [2018-09-14 15:53:01,388 INFO L226 Difference]: Without dead ends: 139 [2018-09-14 15:53:01,388 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 429 GetRequests, 374 SyntacticMatches, 38 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 249 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=91, Invalid=251, Unknown=0, NotChecked=0, Total=342 [2018-09-14 15:53:01,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2018-09-14 15:53:01,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 139. [2018-09-14 15:53:01,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-09-14 15:53:01,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 150 transitions. [2018-09-14 15:53:01,512 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 150 transitions. Word has length 101 [2018-09-14 15:53:01,512 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:01,512 INFO L480 AbstractCegarLoop]: Abstraction has 139 states and 150 transitions. [2018-09-14 15:53:01,512 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-09-14 15:53:01,512 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 150 transitions. [2018-09-14 15:53:01,513 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-09-14 15:53:01,513 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:01,513 INFO L376 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:01,513 INFO L423 AbstractCegarLoop]: === Iteration 56 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:01,513 INFO L82 PathProgramCache]: Analyzing trace with hash -860881985, now seen corresponding path program 17 times [2018-09-14 15:53:01,513 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:01,514 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:01,514 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:01,514 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:01,514 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:01,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:03,100 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:03,100 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:03,100 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 106 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 106 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:03,108 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:53:03,108 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:03,144 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-09-14 15:53:03,144 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:03,147 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:03,589 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:03,590 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:03,796 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:03,817 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:03,817 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 107 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 107 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:03,833 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:53:03,833 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:03,974 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-09-14 15:53:03,975 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:03,979 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:04,000 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:04,000 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:04,235 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:04,236 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:04,236 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 46 [2018-09-14 15:53:04,236 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:04,237 INFO L459 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-09-14 15:53:04,237 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-09-14 15:53:04,237 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=421, Invalid=1649, Unknown=0, NotChecked=0, Total=2070 [2018-09-14 15:53:04,238 INFO L87 Difference]: Start difference. First operand 139 states and 150 transitions. Second operand 46 states. [2018-09-14 15:53:05,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:05,190 INFO L93 Difference]: Finished difference Result 248 states and 280 transitions. [2018-09-14 15:53:05,190 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-09-14 15:53:05,190 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 109 [2018-09-14 15:53:05,190 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:05,191 INFO L225 Difference]: With dead ends: 248 [2018-09-14 15:53:05,191 INFO L226 Difference]: Without dead ends: 199 [2018-09-14 15:53:05,192 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 481 GetRequests, 371 SyntacticMatches, 44 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2822 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=905, Invalid=3651, Unknown=0, NotChecked=0, Total=4556 [2018-09-14 15:53:05,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 199 states. [2018-09-14 15:53:05,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 199 to 141. [2018-09-14 15:53:05,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-09-14 15:53:05,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-09-14 15:53:05,317 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-09-14 15:53:05,317 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:05,317 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-09-14 15:53:05,318 INFO L481 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-09-14 15:53:05,318 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-09-14 15:53:05,318 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-09-14 15:53:05,318 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:05,318 INFO L376 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 9, 8, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:05,318 INFO L423 AbstractCegarLoop]: === Iteration 57 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:05,319 INFO L82 PathProgramCache]: Analyzing trace with hash 1311238219, now seen corresponding path program 29 times [2018-09-14 15:53:05,319 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:05,319 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:05,319 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:05,319 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:05,319 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:05,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:06,159 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:06,159 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:06,159 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 108 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 108 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:06,181 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:53:06,181 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:06,213 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-09-14 15:53:06,214 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:06,216 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:06,671 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:06,671 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:06,899 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:06,919 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:06,919 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 109 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 109 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:06,934 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:53:06,934 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:07,075 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-09-14 15:53:07,075 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:07,080 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:07,103 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:07,103 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:07,660 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:07,662 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:07,662 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 45 [2018-09-14 15:53:07,662 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:07,662 INFO L459 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-09-14 15:53:07,663 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-09-14 15:53:07,663 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=391, Invalid=1589, Unknown=0, NotChecked=0, Total=1980 [2018-09-14 15:53:07,663 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 45 states. [2018-09-14 15:53:09,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:09,020 INFO L93 Difference]: Finished difference Result 306 states and 349 transitions. [2018-09-14 15:53:09,020 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-09-14 15:53:09,020 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 109 [2018-09-14 15:53:09,021 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:09,022 INFO L225 Difference]: With dead ends: 306 [2018-09-14 15:53:09,022 INFO L226 Difference]: Without dead ends: 257 [2018-09-14 15:53:09,023 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 490 GetRequests, 372 SyntacticMatches, 44 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3107 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1081, Invalid=4619, Unknown=0, NotChecked=0, Total=5700 [2018-09-14 15:53:09,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 257 states. [2018-09-14 15:53:09,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 257 to 141. [2018-09-14 15:53:09,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-09-14 15:53:09,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-09-14 15:53:09,177 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-09-14 15:53:09,177 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:09,178 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-09-14 15:53:09,178 INFO L481 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-09-14 15:53:09,178 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-09-14 15:53:09,178 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-09-14 15:53:09,178 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:09,179 INFO L376 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 8, 7, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:09,179 INFO L423 AbstractCegarLoop]: === Iteration 58 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:09,179 INFO L82 PathProgramCache]: Analyzing trace with hash 562661335, now seen corresponding path program 30 times [2018-09-14 15:53:09,179 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:09,180 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:09,180 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:09,180 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:09,180 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:09,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:10,567 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:10,567 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:10,567 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 110 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 110 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:10,574 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:53:10,574 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:53:10,607 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2018-09-14 15:53:10,608 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:10,609 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:11,006 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:11,006 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:11,205 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:11,225 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:11,225 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 111 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 111 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:11,240 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:53:11,240 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:53:11,390 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2018-09-14 15:53:11,390 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:11,395 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:11,415 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:11,415 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:11,662 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:11,663 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:11,664 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 44 [2018-09-14 15:53:11,664 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:11,664 INFO L459 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-09-14 15:53:11,664 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-09-14 15:53:11,664 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=365, Invalid=1527, Unknown=0, NotChecked=0, Total=1892 [2018-09-14 15:53:11,665 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 44 states. [2018-09-14 15:53:13,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:13,526 INFO L93 Difference]: Finished difference Result 362 states and 416 transitions. [2018-09-14 15:53:13,526 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-09-14 15:53:13,527 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 109 [2018-09-14 15:53:13,527 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:13,528 INFO L225 Difference]: With dead ends: 362 [2018-09-14 15:53:13,528 INFO L226 Difference]: Without dead ends: 313 [2018-09-14 15:53:13,529 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 497 GetRequests, 373 SyntacticMatches, 44 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3349 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=1234, Invalid=5408, Unknown=0, NotChecked=0, Total=6642 [2018-09-14 15:53:13,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 313 states. [2018-09-14 15:53:13,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 313 to 141. [2018-09-14 15:53:13,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-09-14 15:53:13,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-09-14 15:53:13,722 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-09-14 15:53:13,723 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:13,723 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-09-14 15:53:13,723 INFO L481 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-09-14 15:53:13,723 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-09-14 15:53:13,723 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-09-14 15:53:13,723 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:13,724 INFO L376 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 7, 6, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:13,724 INFO L423 AbstractCegarLoop]: === Iteration 59 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:13,724 INFO L82 PathProgramCache]: Analyzing trace with hash 195402339, now seen corresponding path program 31 times [2018-09-14 15:53:13,724 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:13,725 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:13,725 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:13,725 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:13,725 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:13,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:14,209 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:14,209 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:14,209 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 112 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 112 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:14,216 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:53:14,216 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:53:14,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:14,249 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:14,644 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:14,645 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:14,837 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:14,856 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:14,857 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 113 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 113 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:14,871 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:53:14,871 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:53:14,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:14,943 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:14,962 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:14,962 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:15,203 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:15,204 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:15,204 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 43 [2018-09-14 15:53:15,205 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:15,205 INFO L459 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-09-14 15:53:15,205 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-09-14 15:53:15,205 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=343, Invalid=1463, Unknown=0, NotChecked=0, Total=1806 [2018-09-14 15:53:15,206 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 43 states. [2018-09-14 15:53:17,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:17,005 INFO L93 Difference]: Finished difference Result 416 states and 481 transitions. [2018-09-14 15:53:17,005 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-09-14 15:53:17,005 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 109 [2018-09-14 15:53:17,005 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:17,007 INFO L225 Difference]: With dead ends: 416 [2018-09-14 15:53:17,007 INFO L226 Difference]: Without dead ends: 367 [2018-09-14 15:53:17,008 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 502 GetRequests, 374 SyntacticMatches, 44 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3510 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1346, Invalid=5964, Unknown=0, NotChecked=0, Total=7310 [2018-09-14 15:53:17,008 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 367 states. [2018-09-14 15:53:17,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 367 to 141. [2018-09-14 15:53:17,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-09-14 15:53:17,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-09-14 15:53:17,199 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-09-14 15:53:17,199 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:17,199 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-09-14 15:53:17,199 INFO L481 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-09-14 15:53:17,199 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-09-14 15:53:17,200 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-09-14 15:53:17,200 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:17,200 INFO L376 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 6, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:17,201 INFO L423 AbstractCegarLoop]: === Iteration 60 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:17,201 INFO L82 PathProgramCache]: Analyzing trace with hash 1316806639, now seen corresponding path program 32 times [2018-09-14 15:53:17,201 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:17,201 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:17,202 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:53:17,202 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:17,202 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:17,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:18,406 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:18,406 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:18,406 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 114 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 114 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:18,414 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:53:18,414 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:18,442 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:53:18,443 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:18,444 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:18,812 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:18,812 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:19,002 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:19,022 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:19,022 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 115 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 115 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:19,036 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:53:19,037 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:19,108 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:53:19,108 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:19,112 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:19,132 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:19,132 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:19,448 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:19,449 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:19,449 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 42 [2018-09-14 15:53:19,449 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:19,450 INFO L459 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-09-14 15:53:19,450 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-09-14 15:53:19,450 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=1397, Unknown=0, NotChecked=0, Total=1722 [2018-09-14 15:53:19,450 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 42 states. [2018-09-14 15:53:21,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:21,457 INFO L93 Difference]: Finished difference Result 468 states and 544 transitions. [2018-09-14 15:53:21,457 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-09-14 15:53:21,457 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 109 [2018-09-14 15:53:21,457 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:21,459 INFO L225 Difference]: With dead ends: 468 [2018-09-14 15:53:21,459 INFO L226 Difference]: Without dead ends: 419 [2018-09-14 15:53:21,459 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 505 GetRequests, 375 SyntacticMatches, 44 SemanticMatches, 86 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3564 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=1405, Invalid=6251, Unknown=0, NotChecked=0, Total=7656 [2018-09-14 15:53:21,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 419 states. [2018-09-14 15:53:21,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 419 to 141. [2018-09-14 15:53:21,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-09-14 15:53:21,609 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-09-14 15:53:21,610 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-09-14 15:53:21,610 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:21,610 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-09-14 15:53:21,610 INFO L481 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-09-14 15:53:21,610 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-09-14 15:53:21,611 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-09-14 15:53:21,611 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:21,611 INFO L376 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 6, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:21,611 INFO L423 AbstractCegarLoop]: === Iteration 61 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:21,611 INFO L82 PathProgramCache]: Analyzing trace with hash 893393019, now seen corresponding path program 33 times [2018-09-14 15:53:21,611 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:21,612 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:21,612 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:21,612 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:21,612 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:21,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:23,964 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:23,964 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:23,964 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 116 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 116 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:23,972 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:53:23,972 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:53:24,007 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-09-14 15:53:24,007 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:24,010 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:24,375 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:24,376 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:24,825 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:24,845 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:24,845 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 117 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 117 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:24,860 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:53:24,860 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:53:25,012 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-09-14 15:53:25,012 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:25,016 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:25,035 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:25,036 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:25,245 INFO L134 CoverageAnalysis]: Checked inductivity of 383 backedges. 189 proven. 50 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:25,246 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:25,246 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 41 [2018-09-14 15:53:25,247 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:25,247 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-09-14 15:53:25,247 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-09-14 15:53:25,247 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=311, Invalid=1329, Unknown=0, NotChecked=0, Total=1640 [2018-09-14 15:53:25,247 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 41 states. [2018-09-14 15:53:27,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:27,351 INFO L93 Difference]: Finished difference Result 518 states and 605 transitions. [2018-09-14 15:53:27,351 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-09-14 15:53:27,351 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 109 [2018-09-14 15:53:27,352 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:27,353 INFO L225 Difference]: With dead ends: 518 [2018-09-14 15:53:27,353 INFO L226 Difference]: Without dead ends: 469 [2018-09-14 15:53:27,354 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 506 GetRequests, 376 SyntacticMatches, 44 SemanticMatches, 86 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3497 ImplicationChecksByTransitivity, 3.9s TimeCoverageRelationStatistics Valid=1405, Invalid=6251, Unknown=0, NotChecked=0, Total=7656 [2018-09-14 15:53:27,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 469 states. [2018-09-14 15:53:27,530 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 469 to 141. [2018-09-14 15:53:27,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-09-14 15:53:27,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-09-14 15:53:27,531 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-09-14 15:53:27,531 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:27,531 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-09-14 15:53:27,531 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-09-14 15:53:27,532 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-09-14 15:53:27,532 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-09-14 15:53:27,532 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:27,533 INFO L376 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 7, 6, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:27,533 INFO L423 AbstractCegarLoop]: === Iteration 62 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:27,533 INFO L82 PathProgramCache]: Analyzing trace with hash -1605368825, now seen corresponding path program 34 times [2018-09-14 15:53:27,533 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:27,534 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:27,534 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:27,534 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:27,534 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:27,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:27,933 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:27,933 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:27,933 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 118 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 118 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:27,942 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:53:27,942 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:53:27,973 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:53:27,973 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:27,975 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:28,353 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:28,353 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:28,541 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:28,560 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:28,561 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 119 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 119 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:28,575 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:53:28,575 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:53:28,655 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:53:28,655 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:28,660 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:28,678 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:28,678 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:28,980 INFO L134 CoverageAnalysis]: Checked inductivity of 387 backedges. 189 proven. 54 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:28,981 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:28,981 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 40 [2018-09-14 15:53:28,981 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:28,982 INFO L459 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-09-14 15:53:28,982 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-09-14 15:53:28,982 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=301, Invalid=1259, Unknown=0, NotChecked=0, Total=1560 [2018-09-14 15:53:28,982 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 40 states. [2018-09-14 15:53:31,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:31,295 INFO L93 Difference]: Finished difference Result 566 states and 664 transitions. [2018-09-14 15:53:31,296 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-09-14 15:53:31,296 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 109 [2018-09-14 15:53:31,296 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:31,298 INFO L225 Difference]: With dead ends: 566 [2018-09-14 15:53:31,298 INFO L226 Difference]: Without dead ends: 517 [2018-09-14 15:53:31,300 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 505 GetRequests, 377 SyntacticMatches, 44 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3303 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1346, Invalid=5964, Unknown=0, NotChecked=0, Total=7310 [2018-09-14 15:53:31,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 517 states. [2018-09-14 15:53:31,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 517 to 141. [2018-09-14 15:53:31,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-09-14 15:53:31,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-09-14 15:53:31,490 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-09-14 15:53:31,490 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:31,490 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-09-14 15:53:31,491 INFO L481 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-09-14 15:53:31,491 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-09-14 15:53:31,491 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-09-14 15:53:31,491 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:31,491 INFO L376 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 8, 7, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:31,491 INFO L423 AbstractCegarLoop]: === Iteration 63 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:31,492 INFO L82 PathProgramCache]: Analyzing trace with hash -1858248045, now seen corresponding path program 35 times [2018-09-14 15:53:31,492 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:31,492 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:31,492 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:31,492 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:31,492 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:31,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:32,018 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:32,018 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:32,019 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 120 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 120 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:32,027 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:53:32,027 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:32,078 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-09-14 15:53:32,079 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:32,081 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:32,417 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:32,417 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:32,602 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:32,622 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:32,622 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 121 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 121 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:32,637 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:53:32,637 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:32,773 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-09-14 15:53:32,773 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:32,777 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:32,796 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:32,797 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:33,124 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 189 proven. 62 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:33,125 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:33,126 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 39 [2018-09-14 15:53:33,126 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:33,126 INFO L459 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-09-14 15:53:33,126 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-09-14 15:53:33,126 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=295, Invalid=1187, Unknown=0, NotChecked=0, Total=1482 [2018-09-14 15:53:33,127 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 39 states. [2018-09-14 15:53:35,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:35,466 INFO L93 Difference]: Finished difference Result 612 states and 721 transitions. [2018-09-14 15:53:35,466 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-09-14 15:53:35,467 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 109 [2018-09-14 15:53:35,467 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:35,469 INFO L225 Difference]: With dead ends: 612 [2018-09-14 15:53:35,469 INFO L226 Difference]: Without dead ends: 563 [2018-09-14 15:53:35,470 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 502 GetRequests, 378 SyntacticMatches, 44 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2984 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1234, Invalid=5408, Unknown=0, NotChecked=0, Total=6642 [2018-09-14 15:53:35,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 563 states. [2018-09-14 15:53:35,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 563 to 141. [2018-09-14 15:53:35,626 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-09-14 15:53:35,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-09-14 15:53:35,627 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-09-14 15:53:35,627 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:35,627 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-09-14 15:53:35,627 INFO L481 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-09-14 15:53:35,627 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-09-14 15:53:35,628 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-09-14 15:53:35,628 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:35,628 INFO L376 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 9, 9, 9, 9, 9, 8, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:35,628 INFO L423 AbstractCegarLoop]: === Iteration 64 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:35,628 INFO L82 PathProgramCache]: Analyzing trace with hash -1228344289, now seen corresponding path program 36 times [2018-09-14 15:53:35,628 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:35,629 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:35,629 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:35,629 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:35,629 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:35,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:35,868 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:35,869 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:35,869 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 122 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 122 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:35,876 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:53:35,876 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:53:35,908 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2018-09-14 15:53:35,909 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:35,910 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:36,236 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:36,237 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:36,420 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:36,439 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:36,440 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 123 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 123 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:36,455 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:53:36,455 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:53:36,597 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2018-09-14 15:53:36,597 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:36,601 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:36,620 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:36,620 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:36,833 INFO L134 CoverageAnalysis]: Checked inductivity of 407 backedges. 189 proven. 74 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:36,834 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:36,835 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 38 [2018-09-14 15:53:36,835 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:36,835 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-09-14 15:53:36,835 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-09-14 15:53:36,836 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=293, Invalid=1113, Unknown=0, NotChecked=0, Total=1406 [2018-09-14 15:53:36,836 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 38 states. [2018-09-14 15:53:39,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:39,267 INFO L93 Difference]: Finished difference Result 656 states and 776 transitions. [2018-09-14 15:53:39,267 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-09-14 15:53:39,268 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 109 [2018-09-14 15:53:39,268 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:39,270 INFO L225 Difference]: With dead ends: 656 [2018-09-14 15:53:39,270 INFO L226 Difference]: Without dead ends: 607 [2018-09-14 15:53:39,271 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 497 GetRequests, 379 SyntacticMatches, 44 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2554 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1081, Invalid=4619, Unknown=0, NotChecked=0, Total=5700 [2018-09-14 15:53:39,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 607 states. [2018-09-14 15:53:39,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 607 to 141. [2018-09-14 15:53:39,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-09-14 15:53:39,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 152 transitions. [2018-09-14 15:53:39,433 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 152 transitions. Word has length 109 [2018-09-14 15:53:39,434 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:39,434 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 152 transitions. [2018-09-14 15:53:39,434 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-09-14 15:53:39,434 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 152 transitions. [2018-09-14 15:53:39,434 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-09-14 15:53:39,435 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:39,435 INFO L376 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:39,435 INFO L423 AbstractCegarLoop]: === Iteration 65 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:39,435 INFO L82 PathProgramCache]: Analyzing trace with hash -119310165, now seen corresponding path program 9 times [2018-09-14 15:53:39,435 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:39,436 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:39,436 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:39,436 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:39,436 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:39,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:40,466 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:40,467 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:40,467 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 124 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 124 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:40,474 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:53:40,474 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:53:40,511 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-09-14 15:53:40,511 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:40,513 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:40,824 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:40,824 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:41,017 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:41,036 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:41,036 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 125 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 125 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:41,051 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:53:41,051 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:53:41,198 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-09-14 15:53:41,198 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:41,203 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:41,221 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:41,221 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:41,432 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:41,433 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:41,433 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 37 [2018-09-14 15:53:41,433 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:41,434 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-09-14 15:53:41,434 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-09-14 15:53:41,434 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=295, Invalid=1037, Unknown=0, NotChecked=0, Total=1332 [2018-09-14 15:53:41,434 INFO L87 Difference]: Start difference. First operand 141 states and 152 transitions. Second operand 37 states. [2018-09-14 15:53:43,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:43,915 INFO L93 Difference]: Finished difference Result 703 states and 835 transitions. [2018-09-14 15:53:43,916 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-09-14 15:53:43,916 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 109 [2018-09-14 15:53:43,916 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:43,919 INFO L225 Difference]: With dead ends: 703 [2018-09-14 15:53:43,919 INFO L226 Difference]: Without dead ends: 654 [2018-09-14 15:53:43,920 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 490 GetRequests, 380 SyntacticMatches, 44 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2039 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=905, Invalid=3651, Unknown=0, NotChecked=0, Total=4556 [2018-09-14 15:53:43,920 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 654 states. [2018-09-14 15:53:44,101 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 654 to 144. [2018-09-14 15:53:44,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-09-14 15:53:44,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 156 transitions. [2018-09-14 15:53:44,102 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 156 transitions. Word has length 109 [2018-09-14 15:53:44,102 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:44,102 INFO L480 AbstractCegarLoop]: Abstraction has 144 states and 156 transitions. [2018-09-14 15:53:44,102 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-09-14 15:53:44,102 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 156 transitions. [2018-09-14 15:53:44,103 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-09-14 15:53:44,103 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:44,103 INFO L376 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:44,103 INFO L423 AbstractCegarLoop]: === Iteration 66 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:44,103 INFO L82 PathProgramCache]: Analyzing trace with hash -1752486599, now seen corresponding path program 18 times [2018-09-14 15:53:44,103 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:44,104 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:44,104 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:44,104 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:44,104 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:44,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:44,230 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 127 proven. 196 refuted. 0 times theorem prover too weak. 120 trivial. 0 not checked. [2018-09-14 15:53:44,231 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:44,231 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 126 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 126 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:44,238 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:53:44,239 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:53:44,277 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2018-09-14 15:53:44,278 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:44,280 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:44,336 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 128 proven. 171 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:44,336 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:44,471 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 128 proven. 171 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:44,492 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:44,492 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 127 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 127 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:44,507 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:53:44,507 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:53:44,666 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2018-09-14 15:53:44,667 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:44,671 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:44,682 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 128 proven. 171 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:44,682 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:44,823 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 128 proven. 171 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-09-14 15:53:44,824 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:44,824 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 15, 15, 15, 15] total 18 [2018-09-14 15:53:44,824 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:44,825 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-09-14 15:53:44,825 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-09-14 15:53:44,825 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=90, Invalid=216, Unknown=0, NotChecked=0, Total=306 [2018-09-14 15:53:44,825 INFO L87 Difference]: Start difference. First operand 144 states and 156 transitions. Second operand 18 states. [2018-09-14 15:53:45,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:45,275 INFO L93 Difference]: Finished difference Result 154 states and 166 transitions. [2018-09-14 15:53:45,275 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-09-14 15:53:45,276 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 111 [2018-09-14 15:53:45,276 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:45,277 INFO L225 Difference]: With dead ends: 154 [2018-09-14 15:53:45,278 INFO L226 Difference]: Without dead ends: 152 [2018-09-14 15:53:45,278 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 471 GetRequests, 411 SyntacticMatches, 42 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 296 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=103, Invalid=277, Unknown=0, NotChecked=0, Total=380 [2018-09-14 15:53:45,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-09-14 15:53:45,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 152. [2018-09-14 15:53:45,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 152 states. [2018-09-14 15:53:45,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152 states to 152 states and 164 transitions. [2018-09-14 15:53:45,462 INFO L78 Accepts]: Start accepts. Automaton has 152 states and 164 transitions. Word has length 111 [2018-09-14 15:53:45,462 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:45,462 INFO L480 AbstractCegarLoop]: Abstraction has 152 states and 164 transitions. [2018-09-14 15:53:45,462 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-09-14 15:53:45,462 INFO L276 IsEmpty]: Start isEmpty. Operand 152 states and 164 transitions. [2018-09-14 15:53:45,463 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-14 15:53:45,463 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:45,463 INFO L376 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 11, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:45,463 INFO L423 AbstractCegarLoop]: === Iteration 67 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:45,463 INFO L82 PathProgramCache]: Analyzing trace with hash 1040286813, now seen corresponding path program 19 times [2018-09-14 15:53:45,464 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:45,464 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:45,464 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:45,464 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:45,464 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:45,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:45,797 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:53:45,798 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:45,798 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 128 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 128 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:45,807 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:53:45,807 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:53:45,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:45,842 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:46,366 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:53:46,366 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:46,620 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:53:46,640 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:46,640 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 129 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 129 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:46,656 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:53:46,656 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:53:46,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:46,734 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:46,758 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:53:46,758 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:47,018 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:53:47,020 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:47,020 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 50 [2018-09-14 15:53:47,020 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:47,021 INFO L459 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-09-14 15:53:47,021 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-09-14 15:53:47,021 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=495, Invalid=1955, Unknown=0, NotChecked=0, Total=2450 [2018-09-14 15:53:47,021 INFO L87 Difference]: Start difference. First operand 152 states and 164 transitions. Second operand 50 states. [2018-09-14 15:53:48,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:48,460 INFO L93 Difference]: Finished difference Result 271 states and 306 transitions. [2018-09-14 15:53:48,460 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-09-14 15:53:48,460 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 119 [2018-09-14 15:53:48,460 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:48,461 INFO L225 Difference]: With dead ends: 271 [2018-09-14 15:53:48,461 INFO L226 Difference]: Without dead ends: 218 [2018-09-14 15:53:48,462 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 525 GetRequests, 405 SyntacticMatches, 48 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3407 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1059, Invalid=4343, Unknown=0, NotChecked=0, Total=5402 [2018-09-14 15:53:48,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 218 states. [2018-09-14 15:53:48,655 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 218 to 154. [2018-09-14 15:53:48,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-09-14 15:53:48,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-09-14 15:53:48,656 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-09-14 15:53:48,656 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:48,656 INFO L480 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-09-14 15:53:48,656 INFO L481 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-09-14 15:53:48,656 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-09-14 15:53:48,657 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-14 15:53:48,657 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:48,657 INFO L376 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 10, 9, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:48,657 INFO L423 AbstractCegarLoop]: === Iteration 68 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:48,657 INFO L82 PathProgramCache]: Analyzing trace with hash -661376535, now seen corresponding path program 37 times [2018-09-14 15:53:48,658 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:48,658 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:48,658 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:53:48,658 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:48,659 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:48,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:48,960 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:53:48,960 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:48,960 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 130 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 130 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:48,968 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:53:48,969 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:53:49,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:49,004 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:49,491 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:53:49,491 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:49,727 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:53:49,748 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:49,748 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 131 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 131 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:49,764 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:53:49,764 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:53:49,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:49,841 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:49,878 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:53:49,878 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:50,137 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:53:50,138 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:50,138 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 49 [2018-09-14 15:53:50,138 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:50,139 INFO L459 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-09-14 15:53:50,139 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-09-14 15:53:50,139 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=462, Invalid=1890, Unknown=0, NotChecked=0, Total=2352 [2018-09-14 15:53:50,139 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 49 states. [2018-09-14 15:53:51,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:51,971 INFO L93 Difference]: Finished difference Result 335 states and 382 transitions. [2018-09-14 15:53:51,971 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-09-14 15:53:51,971 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 119 [2018-09-14 15:53:51,972 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:51,973 INFO L225 Difference]: With dead ends: 335 [2018-09-14 15:53:51,973 INFO L226 Difference]: Without dead ends: 282 [2018-09-14 15:53:51,974 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 535 GetRequests, 406 SyntacticMatches, 48 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3775 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=1275, Invalid=5531, Unknown=0, NotChecked=0, Total=6806 [2018-09-14 15:53:51,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282 states. [2018-09-14 15:53:52,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282 to 154. [2018-09-14 15:53:52,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-09-14 15:53:52,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-09-14 15:53:52,199 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-09-14 15:53:52,199 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:52,200 INFO L480 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-09-14 15:53:52,200 INFO L481 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-09-14 15:53:52,200 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-09-14 15:53:52,200 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-14 15:53:52,200 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:52,201 INFO L376 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 9, 8, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:52,201 INFO L423 AbstractCegarLoop]: === Iteration 69 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:52,201 INFO L82 PathProgramCache]: Analyzing trace with hash 516739701, now seen corresponding path program 38 times [2018-09-14 15:53:52,201 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:52,202 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:52,202 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:53:52,202 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:52,202 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:52,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:52,539 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:53:52,540 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:52,540 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 132 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 132 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:52,548 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:53:52,548 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:52,582 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:53:52,583 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:52,584 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:53,060 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:53:53,060 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:53,592 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:53:53,613 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:53,613 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 133 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 133 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:53,640 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:53:53,640 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:53,716 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:53:53,716 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:53,720 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:53,749 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:53:53,749 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:54,023 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:53:54,024 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:54,024 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 48 [2018-09-14 15:53:54,024 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:54,024 INFO L459 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-09-14 15:53:54,025 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-09-14 15:53:54,025 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=433, Invalid=1823, Unknown=0, NotChecked=0, Total=2256 [2018-09-14 15:53:54,025 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 48 states. [2018-09-14 15:53:56,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:56,278 INFO L93 Difference]: Finished difference Result 397 states and 456 transitions. [2018-09-14 15:53:56,278 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-09-14 15:53:56,279 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 119 [2018-09-14 15:53:56,279 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:56,280 INFO L225 Difference]: With dead ends: 397 [2018-09-14 15:53:56,280 INFO L226 Difference]: Without dead ends: 344 [2018-09-14 15:53:56,281 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 543 GetRequests, 407 SyntacticMatches, 48 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4105 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1471, Invalid=6539, Unknown=0, NotChecked=0, Total=8010 [2018-09-14 15:53:56,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 344 states. [2018-09-14 15:53:56,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 344 to 154. [2018-09-14 15:53:56,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-09-14 15:53:56,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-09-14 15:53:56,508 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-09-14 15:53:56,508 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:56,508 INFO L480 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-09-14 15:53:56,508 INFO L481 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-09-14 15:53:56,508 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-09-14 15:53:56,509 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-14 15:53:56,509 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:56,509 INFO L376 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 8, 7, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:56,509 INFO L423 AbstractCegarLoop]: === Iteration 70 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:56,509 INFO L82 PathProgramCache]: Analyzing trace with hash -1752422911, now seen corresponding path program 39 times [2018-09-14 15:53:56,510 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:56,510 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:56,510 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:56,510 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:56,511 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:56,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:56,788 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:53:56,789 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:56,789 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 134 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 134 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:56,796 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:53:56,796 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:53:56,834 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-09-14 15:53:56,834 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:56,836 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:57,313 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:53:57,313 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:57,538 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:53:57,559 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:57,559 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 135 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 135 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:53:57,574 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:53:57,574 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:53:57,747 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-09-14 15:53:57,748 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:57,752 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:57,776 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:53:57,776 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:58,022 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:53:58,024 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:58,025 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 47 [2018-09-14 15:53:58,025 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:58,025 INFO L459 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-09-14 15:53:58,026 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-09-14 15:53:58,026 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=408, Invalid=1754, Unknown=0, NotChecked=0, Total=2162 [2018-09-14 15:53:58,026 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 47 states. [2018-09-14 15:54:00,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:00,563 INFO L93 Difference]: Finished difference Result 457 states and 528 transitions. [2018-09-14 15:54:00,563 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-09-14 15:54:00,564 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 119 [2018-09-14 15:54:00,564 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:00,565 INFO L225 Difference]: With dead ends: 457 [2018-09-14 15:54:00,565 INFO L226 Difference]: Without dead ends: 404 [2018-09-14 15:54:00,566 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 549 GetRequests, 408 SyntacticMatches, 48 SemanticMatches, 93 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4353 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1626, Invalid=7304, Unknown=0, NotChecked=0, Total=8930 [2018-09-14 15:54:00,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 404 states. [2018-09-14 15:54:00,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 404 to 154. [2018-09-14 15:54:00,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-09-14 15:54:00,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-09-14 15:54:00,793 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-09-14 15:54:00,793 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:00,793 INFO L480 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-09-14 15:54:00,793 INFO L481 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-09-14 15:54:00,793 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-09-14 15:54:00,794 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-14 15:54:00,794 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:00,794 INFO L376 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 7, 6, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:00,794 INFO L423 AbstractCegarLoop]: === Iteration 71 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:00,794 INFO L82 PathProgramCache]: Analyzing trace with hash -1964839795, now seen corresponding path program 40 times [2018-09-14 15:54:00,795 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:00,795 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:00,795 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:00,795 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:00,795 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:00,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:01,106 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:01,107 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:01,107 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 136 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 136 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:01,114 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:54:01,115 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:54:01,148 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:54:01,148 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:01,150 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:01,586 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:01,586 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:01,811 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:01,831 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:01,831 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 137 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 137 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:01,846 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:54:01,846 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:54:01,935 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:54:01,935 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:01,939 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:01,962 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:01,962 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:02,217 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:02,218 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:02,218 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 46 [2018-09-14 15:54:02,219 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:02,219 INFO L459 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-09-14 15:54:02,219 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-09-14 15:54:02,219 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=387, Invalid=1683, Unknown=0, NotChecked=0, Total=2070 [2018-09-14 15:54:02,220 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 46 states. [2018-09-14 15:54:05,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:05,148 INFO L93 Difference]: Finished difference Result 515 states and 598 transitions. [2018-09-14 15:54:05,148 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-09-14 15:54:05,148 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 119 [2018-09-14 15:54:05,148 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:05,150 INFO L225 Difference]: With dead ends: 515 [2018-09-14 15:54:05,151 INFO L226 Difference]: Without dead ends: 462 [2018-09-14 15:54:05,152 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 553 GetRequests, 409 SyntacticMatches, 48 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4487 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1725, Invalid=7781, Unknown=0, NotChecked=0, Total=9506 [2018-09-14 15:54:05,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 462 states. [2018-09-14 15:54:05,387 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 462 to 154. [2018-09-14 15:54:05,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-09-14 15:54:05,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-09-14 15:54:05,387 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-09-14 15:54:05,387 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:05,387 INFO L480 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-09-14 15:54:05,388 INFO L481 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-09-14 15:54:05,388 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-09-14 15:54:05,388 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-14 15:54:05,388 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:05,388 INFO L376 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 6, 6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:05,388 INFO L423 AbstractCegarLoop]: === Iteration 72 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:05,389 INFO L82 PathProgramCache]: Analyzing trace with hash -1911429607, now seen corresponding path program 41 times [2018-09-14 15:54:05,389 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:05,389 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:05,389 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:05,389 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:05,390 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:05,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:05,824 INFO L134 CoverageAnalysis]: Checked inductivity of 470 backedges. 230 proven. 60 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:05,824 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:05,824 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 138 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 138 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:05,831 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:54:05,831 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:54:05,870 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 11 check-sat command(s) [2018-09-14 15:54:05,870 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:05,873 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:06,292 INFO L134 CoverageAnalysis]: Checked inductivity of 470 backedges. 230 proven. 60 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:06,293 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:06,510 INFO L134 CoverageAnalysis]: Checked inductivity of 470 backedges. 230 proven. 60 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:06,530 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:06,530 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 139 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 139 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:06,545 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:54:06,546 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:54:06,699 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 11 check-sat command(s) [2018-09-14 15:54:06,699 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:06,703 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:06,725 INFO L134 CoverageAnalysis]: Checked inductivity of 470 backedges. 230 proven. 60 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:06,725 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:06,966 INFO L134 CoverageAnalysis]: Checked inductivity of 470 backedges. 230 proven. 60 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:06,968 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:06,968 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 45 [2018-09-14 15:54:06,968 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:06,968 INFO L459 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-09-14 15:54:06,968 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-09-14 15:54:06,969 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=370, Invalid=1610, Unknown=0, NotChecked=0, Total=1980 [2018-09-14 15:54:06,969 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 45 states. [2018-09-14 15:54:09,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:09,989 INFO L93 Difference]: Finished difference Result 571 states and 666 transitions. [2018-09-14 15:54:09,990 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-09-14 15:54:09,990 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 119 [2018-09-14 15:54:09,990 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:09,992 INFO L225 Difference]: With dead ends: 571 [2018-09-14 15:54:09,993 INFO L226 Difference]: Without dead ends: 518 [2018-09-14 15:54:09,994 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 555 GetRequests, 410 SyntacticMatches, 48 SemanticMatches, 97 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4487 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1759, Invalid=7943, Unknown=0, NotChecked=0, Total=9702 [2018-09-14 15:54:09,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518 states. [2018-09-14 15:54:10,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518 to 154. [2018-09-14 15:54:10,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-09-14 15:54:10,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-09-14 15:54:10,220 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-09-14 15:54:10,220 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:10,220 INFO L480 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-09-14 15:54:10,220 INFO L481 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-09-14 15:54:10,220 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-09-14 15:54:10,221 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-14 15:54:10,221 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:10,221 INFO L376 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 7, 6, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:10,221 INFO L423 AbstractCegarLoop]: === Iteration 73 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:10,221 INFO L82 PathProgramCache]: Analyzing trace with hash 260690597, now seen corresponding path program 42 times [2018-09-14 15:54:10,221 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:10,222 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:10,222 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:10,222 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:10,222 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:10,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:10,638 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:10,639 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:10,639 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 140 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 140 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:10,645 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:54:10,646 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:54:10,683 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2018-09-14 15:54:10,683 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:10,685 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:11,089 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:11,089 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:11,312 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:11,332 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:11,332 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 141 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 141 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:11,347 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:54:11,347 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:54:11,515 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2018-09-14 15:54:11,515 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:11,519 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:11,543 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:11,543 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:11,791 INFO L134 CoverageAnalysis]: Checked inductivity of 472 backedges. 230 proven. 62 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:11,792 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:11,792 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 44 [2018-09-14 15:54:11,792 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:11,793 INFO L459 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-09-14 15:54:11,793 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-09-14 15:54:11,793 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=357, Invalid=1535, Unknown=0, NotChecked=0, Total=1892 [2018-09-14 15:54:11,793 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 44 states. [2018-09-14 15:54:14,976 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:14,977 INFO L93 Difference]: Finished difference Result 625 states and 732 transitions. [2018-09-14 15:54:14,977 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-09-14 15:54:14,977 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 119 [2018-09-14 15:54:14,977 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:14,979 INFO L225 Difference]: With dead ends: 625 [2018-09-14 15:54:14,979 INFO L226 Difference]: Without dead ends: 572 [2018-09-14 15:54:14,980 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 555 GetRequests, 411 SyntacticMatches, 48 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4344 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1725, Invalid=7781, Unknown=0, NotChecked=0, Total=9506 [2018-09-14 15:54:14,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 572 states. [2018-09-14 15:54:15,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 572 to 154. [2018-09-14 15:54:15,214 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-09-14 15:54:15,214 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-09-14 15:54:15,214 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-09-14 15:54:15,215 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:15,215 INFO L480 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-09-14 15:54:15,215 INFO L481 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-09-14 15:54:15,215 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-09-14 15:54:15,215 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-14 15:54:15,215 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:15,215 INFO L376 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 8, 7, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:15,216 INFO L423 AbstractCegarLoop]: === Iteration 74 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:15,216 INFO L82 PathProgramCache]: Analyzing trace with hash -487886287, now seen corresponding path program 43 times [2018-09-14 15:54:15,216 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:15,216 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:15,216 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:15,216 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:15,216 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:15,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:15,491 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:15,491 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:15,491 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 142 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 142 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:15,498 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:54:15,498 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:54:15,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:15,533 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:15,955 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:15,955 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:16,184 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:16,203 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:16,203 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 143 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 143 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:16,228 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:54:16,228 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:54:16,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:16,302 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:16,322 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:16,322 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:16,561 INFO L134 CoverageAnalysis]: Checked inductivity of 478 backedges. 230 proven. 68 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:16,562 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:16,562 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 43 [2018-09-14 15:54:16,563 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:16,563 INFO L459 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-09-14 15:54:16,563 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-09-14 15:54:16,563 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=348, Invalid=1458, Unknown=0, NotChecked=0, Total=1806 [2018-09-14 15:54:16,563 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 43 states. [2018-09-14 15:54:20,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:20,008 INFO L93 Difference]: Finished difference Result 677 states and 796 transitions. [2018-09-14 15:54:20,008 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-09-14 15:54:20,008 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 119 [2018-09-14 15:54:20,008 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:20,010 INFO L225 Difference]: With dead ends: 677 [2018-09-14 15:54:20,010 INFO L226 Difference]: Without dead ends: 624 [2018-09-14 15:54:20,011 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 553 GetRequests, 412 SyntacticMatches, 48 SemanticMatches, 93 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4055 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1626, Invalid=7304, Unknown=0, NotChecked=0, Total=8930 [2018-09-14 15:54:20,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 624 states. [2018-09-14 15:54:20,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 624 to 154. [2018-09-14 15:54:20,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-09-14 15:54:20,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-09-14 15:54:20,240 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-09-14 15:54:20,240 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:20,240 INFO L480 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-09-14 15:54:20,240 INFO L481 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-09-14 15:54:20,241 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-09-14 15:54:20,241 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-14 15:54:20,241 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:20,241 INFO L376 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 9, 8, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:20,242 INFO L423 AbstractCegarLoop]: === Iteration 75 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:20,242 INFO L82 PathProgramCache]: Analyzing trace with hash -855145283, now seen corresponding path program 44 times [2018-09-14 15:54:20,242 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:20,242 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:20,243 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:54:20,243 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:20,243 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:20,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:20,571 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:20,572 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:20,572 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 144 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 144 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:20,579 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:54:20,579 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:54:20,613 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:54:20,613 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:20,615 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:21,003 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:21,004 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:21,230 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:21,249 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:21,250 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 145 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 145 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:21,265 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:54:21,265 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:54:21,342 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:54:21,343 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:21,347 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:21,369 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:21,369 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:21,613 INFO L134 CoverageAnalysis]: Checked inductivity of 488 backedges. 230 proven. 78 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:21,614 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:21,614 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 42 [2018-09-14 15:54:21,614 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:21,614 INFO L459 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-09-14 15:54:21,615 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-09-14 15:54:21,615 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=343, Invalid=1379, Unknown=0, NotChecked=0, Total=1722 [2018-09-14 15:54:21,615 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 42 states. [2018-09-14 15:54:25,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:25,000 INFO L93 Difference]: Finished difference Result 727 states and 858 transitions. [2018-09-14 15:54:25,001 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-09-14 15:54:25,001 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 119 [2018-09-14 15:54:25,001 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:25,003 INFO L225 Difference]: With dead ends: 727 [2018-09-14 15:54:25,003 INFO L226 Difference]: Without dead ends: 674 [2018-09-14 15:54:25,004 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 549 GetRequests, 413 SyntacticMatches, 48 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3628 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1471, Invalid=6539, Unknown=0, NotChecked=0, Total=8010 [2018-09-14 15:54:25,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 674 states. [2018-09-14 15:54:25,250 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 674 to 154. [2018-09-14 15:54:25,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-09-14 15:54:25,251 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-09-14 15:54:25,251 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-09-14 15:54:25,251 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:25,251 INFO L480 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-09-14 15:54:25,251 INFO L481 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-09-14 15:54:25,251 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-09-14 15:54:25,252 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-14 15:54:25,252 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:25,252 INFO L376 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 10, 10, 10, 10, 10, 9, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:25,252 INFO L423 AbstractCegarLoop]: === Iteration 76 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:25,252 INFO L82 PathProgramCache]: Analyzing trace with hash 266259017, now seen corresponding path program 45 times [2018-09-14 15:54:25,252 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:25,253 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:25,253 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:25,253 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:25,253 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:25,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:25,533 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:25,534 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:25,534 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 146 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 146 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:25,541 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:54:25,541 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:54:25,581 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-09-14 15:54:25,581 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:25,583 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:25,940 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:25,940 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:26,162 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:26,182 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:26,183 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 147 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 147 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:26,197 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:54:26,197 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:54:26,365 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-09-14 15:54:26,366 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:26,370 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:26,391 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:26,391 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:26,637 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 230 proven. 92 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:26,638 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:26,638 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 41 [2018-09-14 15:54:26,638 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:26,638 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-09-14 15:54:26,639 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-09-14 15:54:26,639 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=342, Invalid=1298, Unknown=0, NotChecked=0, Total=1640 [2018-09-14 15:54:26,639 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 41 states. [2018-09-14 15:54:30,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:30,096 INFO L93 Difference]: Finished difference Result 775 states and 918 transitions. [2018-09-14 15:54:30,097 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-09-14 15:54:30,097 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 119 [2018-09-14 15:54:30,097 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:30,099 INFO L225 Difference]: With dead ends: 775 [2018-09-14 15:54:30,100 INFO L226 Difference]: Without dead ends: 722 [2018-09-14 15:54:30,100 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 543 GetRequests, 414 SyntacticMatches, 48 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3083 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1275, Invalid=5531, Unknown=0, NotChecked=0, Total=6806 [2018-09-14 15:54:30,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 722 states. [2018-09-14 15:54:30,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 722 to 154. [2018-09-14 15:54:30,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-09-14 15:54:30,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 166 transitions. [2018-09-14 15:54:30,369 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 166 transitions. Word has length 119 [2018-09-14 15:54:30,369 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:30,369 INFO L480 AbstractCegarLoop]: Abstraction has 154 states and 166 transitions. [2018-09-14 15:54:30,369 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-09-14 15:54:30,369 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 166 transitions. [2018-09-14 15:54:30,370 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-09-14 15:54:30,370 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:30,370 INFO L376 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 11, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:30,370 INFO L423 AbstractCegarLoop]: === Iteration 77 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:30,370 INFO L82 PathProgramCache]: Analyzing trace with hash -157154603, now seen corresponding path program 10 times [2018-09-14 15:54:30,370 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:30,371 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:30,371 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:30,371 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:30,371 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:30,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:30,655 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:30,656 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:30,656 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 148 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 148 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:30,663 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:54:30,663 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:54:30,698 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:54:30,698 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:30,700 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:31,061 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:31,061 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:31,277 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:31,297 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:31,297 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 149 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 149 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:31,311 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:54:31,311 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:54:31,399 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:54:31,399 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:31,403 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:31,424 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:31,424 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:31,659 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:31,660 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:31,660 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 40 [2018-09-14 15:54:31,660 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:31,660 INFO L459 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-09-14 15:54:31,661 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-09-14 15:54:31,661 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=345, Invalid=1215, Unknown=0, NotChecked=0, Total=1560 [2018-09-14 15:54:31,661 INFO L87 Difference]: Start difference. First operand 154 states and 166 transitions. Second operand 40 states. [2018-09-14 15:54:34,819 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:34,820 INFO L93 Difference]: Finished difference Result 826 states and 982 transitions. [2018-09-14 15:54:34,820 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-09-14 15:54:34,820 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 119 [2018-09-14 15:54:34,820 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:34,823 INFO L225 Difference]: With dead ends: 826 [2018-09-14 15:54:34,823 INFO L226 Difference]: Without dead ends: 773 [2018-09-14 15:54:34,823 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 535 GetRequests, 415 SyntacticMatches, 48 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2452 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=1059, Invalid=4343, Unknown=0, NotChecked=0, Total=5402 [2018-09-14 15:54:34,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 773 states. [2018-09-14 15:54:35,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 773 to 157. [2018-09-14 15:54:35,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 157 states. [2018-09-14 15:54:35,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 170 transitions. [2018-09-14 15:54:35,083 INFO L78 Accepts]: Start accepts. Automaton has 157 states and 170 transitions. Word has length 119 [2018-09-14 15:54:35,083 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:35,083 INFO L480 AbstractCegarLoop]: Abstraction has 157 states and 170 transitions. [2018-09-14 15:54:35,083 INFO L481 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-09-14 15:54:35,083 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 170 transitions. [2018-09-14 15:54:35,083 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 122 [2018-09-14 15:54:35,084 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:35,084 INFO L376 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 11, 11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:35,084 INFO L423 AbstractCegarLoop]: === Iteration 78 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:35,084 INFO L82 PathProgramCache]: Analyzing trace with hash 777037143, now seen corresponding path program 20 times [2018-09-14 15:54:35,084 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:35,084 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:35,085 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:35,085 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:35,085 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:35,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:35,234 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 151 proven. 238 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-09-14 15:54:35,234 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:35,234 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 150 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 150 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:35,242 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:54:35,242 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:54:35,277 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:54:35,277 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:35,279 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:35,314 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 152 proven. 210 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:35,315 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:35,475 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 152 proven. 210 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:35,494 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:35,494 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 151 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 151 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:35,508 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:54:35,509 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:54:35,587 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:54:35,587 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:35,591 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:35,602 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 152 proven. 210 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:35,602 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:35,779 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 152 proven. 210 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-09-14 15:54:35,781 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:35,781 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 16, 16, 16, 16] total 19 [2018-09-14 15:54:35,781 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:35,781 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-09-14 15:54:35,781 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-09-14 15:54:35,781 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=103, Invalid=239, Unknown=0, NotChecked=0, Total=342 [2018-09-14 15:54:35,782 INFO L87 Difference]: Start difference. First operand 157 states and 170 transitions. Second operand 19 states. [2018-09-14 15:54:36,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:36,338 INFO L93 Difference]: Finished difference Result 167 states and 180 transitions. [2018-09-14 15:54:36,338 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-09-14 15:54:36,338 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 121 [2018-09-14 15:54:36,338 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:36,340 INFO L225 Difference]: With dead ends: 167 [2018-09-14 15:54:36,340 INFO L226 Difference]: Without dead ends: 165 [2018-09-14 15:54:36,340 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 513 GetRequests, 448 SyntacticMatches, 46 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 347 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=116, Invalid=304, Unknown=0, NotChecked=0, Total=420 [2018-09-14 15:54:36,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165 states. [2018-09-14 15:54:36,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165 to 165. [2018-09-14 15:54:36,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-09-14 15:54:36,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 178 transitions. [2018-09-14 15:54:36,611 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 178 transitions. Word has length 121 [2018-09-14 15:54:36,611 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:36,611 INFO L480 AbstractCegarLoop]: Abstraction has 165 states and 178 transitions. [2018-09-14 15:54:36,611 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-09-14 15:54:36,611 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 178 transitions. [2018-09-14 15:54:36,612 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-09-14 15:54:36,612 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:36,612 INFO L376 BasicCegarLoop]: trace histogram [12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:36,612 INFO L423 AbstractCegarLoop]: === Iteration 79 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:36,612 INFO L82 PathProgramCache]: Analyzing trace with hash -1277952389, now seen corresponding path program 21 times [2018-09-14 15:54:36,613 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:36,613 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:36,613 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:36,613 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:36,614 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:36,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:37,197 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:37,197 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:37,197 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 152 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 152 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:37,204 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:54:37,204 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:54:37,242 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-09-14 15:54:37,242 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:37,245 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:37,859 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:37,859 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:38,135 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:38,155 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:38,155 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 153 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 153 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:38,170 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:54:38,170 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:54:38,359 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-09-14 15:54:38,360 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:38,364 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:38,392 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:38,392 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:38,685 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:38,686 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:38,687 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 54 [2018-09-14 15:54:38,687 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:38,687 INFO L459 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-09-14 15:54:38,687 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-09-14 15:54:38,688 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=575, Invalid=2287, Unknown=0, NotChecked=0, Total=2862 [2018-09-14 15:54:38,688 INFO L87 Difference]: Start difference. First operand 165 states and 178 transitions. Second operand 54 states. [2018-09-14 15:54:40,576 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:40,576 INFO L93 Difference]: Finished difference Result 294 states and 332 transitions. [2018-09-14 15:54:40,577 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-09-14 15:54:40,577 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 129 [2018-09-14 15:54:40,577 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:40,578 INFO L225 Difference]: With dead ends: 294 [2018-09-14 15:54:40,578 INFO L226 Difference]: Without dead ends: 237 [2018-09-14 15:54:40,578 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 569 GetRequests, 439 SyntacticMatches, 52 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4047 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1225, Invalid=5095, Unknown=0, NotChecked=0, Total=6320 [2018-09-14 15:54:40,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 237 states. [2018-09-14 15:54:40,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 237 to 167. [2018-09-14 15:54:40,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-09-14 15:54:40,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 180 transitions. [2018-09-14 15:54:40,875 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 180 transitions. Word has length 129 [2018-09-14 15:54:40,875 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:40,875 INFO L480 AbstractCegarLoop]: Abstraction has 167 states and 180 transitions. [2018-09-14 15:54:40,875 INFO L481 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-09-14 15:54:40,875 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 180 transitions. [2018-09-14 15:54:40,875 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-09-14 15:54:40,875 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:40,875 INFO L376 BasicCegarLoop]: trace histogram [12, 12, 12, 12, 11, 11, 11, 11, 11, 10, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:40,876 INFO L423 AbstractCegarLoop]: === Iteration 80 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:40,876 INFO L82 PathProgramCache]: Analyzing trace with hash -1178325753, now seen corresponding path program 46 times [2018-09-14 15:54:40,876 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:40,876 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:40,876 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:40,876 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:40,877 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:40,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:41,223 INFO L134 CoverageAnalysis]: Checked inductivity of 607 backedges. 275 proven. 112 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:41,224 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:41,224 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 154 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 154 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:41,231 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:54:41,232 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:54:41,268 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:54:41,268 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:41,269 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:41,835 INFO L134 CoverageAnalysis]: Checked inductivity of 607 backedges. 275 proven. 112 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:41,835 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:42,099 INFO L134 CoverageAnalysis]: Checked inductivity of 607 backedges. 275 proven. 112 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:42,118 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:42,119 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 155 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 155 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:42,133 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:54:42,133 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:54:42,227 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:54:42,228 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:42,232 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:42,259 INFO L134 CoverageAnalysis]: Checked inductivity of 607 backedges. 275 proven. 112 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:42,259 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:42,569 INFO L134 CoverageAnalysis]: Checked inductivity of 607 backedges. 275 proven. 112 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:42,570 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:42,570 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 53 [2018-09-14 15:54:42,570 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:42,571 INFO L459 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-09-14 15:54:42,571 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-09-14 15:54:42,571 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=539, Invalid=2217, Unknown=0, NotChecked=0, Total=2756 [2018-09-14 15:54:42,571 INFO L87 Difference]: Start difference. First operand 167 states and 180 transitions. Second operand 53 states. [2018-09-14 15:54:45,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:45,143 INFO L93 Difference]: Finished difference Result 364 states and 415 transitions. [2018-09-14 15:54:45,143 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-09-14 15:54:45,143 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 129 [2018-09-14 15:54:45,144 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:45,145 INFO L225 Difference]: With dead ends: 364 [2018-09-14 15:54:45,145 INFO L226 Difference]: Without dead ends: 307 [2018-09-14 15:54:45,146 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 580 GetRequests, 440 SyntacticMatches, 52 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4508 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1485, Invalid=6525, Unknown=0, NotChecked=0, Total=8010 [2018-09-14 15:54:45,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 307 states. [2018-09-14 15:54:45,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 307 to 167. [2018-09-14 15:54:45,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-09-14 15:54:45,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 180 transitions. [2018-09-14 15:54:45,476 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 180 transitions. Word has length 129 [2018-09-14 15:54:45,476 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:45,476 INFO L480 AbstractCegarLoop]: Abstraction has 167 states and 180 transitions. [2018-09-14 15:54:45,476 INFO L481 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-09-14 15:54:45,476 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 180 transitions. [2018-09-14 15:54:45,477 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-09-14 15:54:45,477 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:45,477 INFO L376 BasicCegarLoop]: trace histogram [12, 12, 12, 12, 11, 11, 11, 11, 10, 9, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:45,477 INFO L423 AbstractCegarLoop]: === Iteration 81 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:45,477 INFO L82 PathProgramCache]: Analyzing trace with hash -154759533, now seen corresponding path program 47 times [2018-09-14 15:54:45,477 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:45,478 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:45,478 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:45,478 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:45,478 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:45,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:45,818 INFO L134 CoverageAnalysis]: Checked inductivity of 591 backedges. 275 proven. 96 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:45,818 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:45,818 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 156 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 156 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:45,825 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:54:45,825 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:54:45,869 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2018-09-14 15:54:45,869 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:45,871 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:46,418 INFO L134 CoverageAnalysis]: Checked inductivity of 591 backedges. 275 proven. 96 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:46,418 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:46,678 INFO L134 CoverageAnalysis]: Checked inductivity of 591 backedges. 275 proven. 96 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:46,698 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:46,698 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 157 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 157 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:46,713 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:54:46,714 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:54:46,885 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2018-09-14 15:54:46,886 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:46,890 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:46,916 INFO L134 CoverageAnalysis]: Checked inductivity of 591 backedges. 275 proven. 96 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:46,916 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:47,196 INFO L134 CoverageAnalysis]: Checked inductivity of 591 backedges. 275 proven. 96 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:47,198 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:47,198 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 52 [2018-09-14 15:54:47,198 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:47,198 INFO L459 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-09-14 15:54:47,199 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-09-14 15:54:47,199 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=507, Invalid=2145, Unknown=0, NotChecked=0, Total=2652 [2018-09-14 15:54:47,199 INFO L87 Difference]: Start difference. First operand 167 states and 180 transitions. Second operand 52 states. [2018-09-14 15:54:50,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:50,262 INFO L93 Difference]: Finished difference Result 432 states and 496 transitions. [2018-09-14 15:54:50,262 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-09-14 15:54:50,262 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 129 [2018-09-14 15:54:50,262 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:50,264 INFO L225 Difference]: With dead ends: 432 [2018-09-14 15:54:50,264 INFO L226 Difference]: Without dead ends: 375 [2018-09-14 15:54:50,265 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 589 GetRequests, 441 SyntacticMatches, 52 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4938 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1729, Invalid=7777, Unknown=0, NotChecked=0, Total=9506 [2018-09-14 15:54:50,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 375 states. [2018-09-14 15:54:50,574 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 375 to 167. [2018-09-14 15:54:50,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-09-14 15:54:50,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 180 transitions. [2018-09-14 15:54:50,574 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 180 transitions. Word has length 129 [2018-09-14 15:54:50,574 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:50,574 INFO L480 AbstractCegarLoop]: Abstraction has 167 states and 180 transitions. [2018-09-14 15:54:50,575 INFO L481 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-09-14 15:54:50,575 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 180 transitions. [2018-09-14 15:54:50,575 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-09-14 15:54:50,575 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:50,575 INFO L376 BasicCegarLoop]: trace histogram [12, 12, 12, 12, 11, 11, 11, 11, 9, 8, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:50,575 INFO L423 AbstractCegarLoop]: === Iteration 82 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:50,576 INFO L82 PathProgramCache]: Analyzing trace with hash 1607197471, now seen corresponding path program 48 times [2018-09-14 15:54:50,576 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:50,576 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:50,576 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:50,576 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:50,577 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:50,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:50,910 INFO L134 CoverageAnalysis]: Checked inductivity of 579 backedges. 275 proven. 84 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:50,911 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:50,911 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 158 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 158 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:50,917 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:54:50,917 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:54:50,972 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 12 check-sat command(s) [2018-09-14 15:54:50,973 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:50,976 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:51,496 INFO L134 CoverageAnalysis]: Checked inductivity of 579 backedges. 275 proven. 84 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:51,496 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:51,760 INFO L134 CoverageAnalysis]: Checked inductivity of 579 backedges. 275 proven. 84 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:51,780 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:51,780 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 159 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 159 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:51,795 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:54:51,795 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:54:51,979 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 12 check-sat command(s) [2018-09-14 15:54:51,980 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:54:51,984 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:52,011 INFO L134 CoverageAnalysis]: Checked inductivity of 579 backedges. 275 proven. 84 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:52,011 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:52,292 INFO L134 CoverageAnalysis]: Checked inductivity of 579 backedges. 275 proven. 84 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:52,293 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:52,294 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 51 [2018-09-14 15:54:52,294 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:52,294 INFO L459 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-09-14 15:54:52,294 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-09-14 15:54:52,295 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=479, Invalid=2071, Unknown=0, NotChecked=0, Total=2550 [2018-09-14 15:54:52,295 INFO L87 Difference]: Start difference. First operand 167 states and 180 transitions. Second operand 51 states. [2018-09-14 15:54:55,821 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:54:55,821 INFO L93 Difference]: Finished difference Result 498 states and 575 transitions. [2018-09-14 15:54:55,821 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-09-14 15:54:55,822 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 129 [2018-09-14 15:54:55,822 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:54:55,823 INFO L225 Difference]: With dead ends: 498 [2018-09-14 15:54:55,823 INFO L226 Difference]: Without dead ends: 441 [2018-09-14 15:54:55,824 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 596 GetRequests, 442 SyntacticMatches, 52 SemanticMatches, 102 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5287 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1933, Invalid=8779, Unknown=0, NotChecked=0, Total=10712 [2018-09-14 15:54:55,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 441 states. [2018-09-14 15:54:56,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 441 to 167. [2018-09-14 15:54:56,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-09-14 15:54:56,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 180 transitions. [2018-09-14 15:54:56,136 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 180 transitions. Word has length 129 [2018-09-14 15:54:56,136 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:54:56,136 INFO L480 AbstractCegarLoop]: Abstraction has 167 states and 180 transitions. [2018-09-14 15:54:56,136 INFO L481 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-09-14 15:54:56,136 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 180 transitions. [2018-09-14 15:54:56,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-09-14 15:54:56,137 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:54:56,137 INFO L376 BasicCegarLoop]: trace histogram [12, 12, 12, 12, 11, 11, 11, 11, 8, 7, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:54:56,137 INFO L423 AbstractCegarLoop]: === Iteration 83 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:54:56,137 INFO L82 PathProgramCache]: Analyzing trace with hash -285939029, now seen corresponding path program 49 times [2018-09-14 15:54:56,137 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:54:56,138 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:56,138 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:54:56,138 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:54:56,138 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:54:56,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:56,448 INFO L134 CoverageAnalysis]: Checked inductivity of 571 backedges. 275 proven. 76 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:56,448 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:56,448 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 160 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 160 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:54:56,455 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:54:56,455 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:54:56,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:56,492 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:56,994 INFO L134 CoverageAnalysis]: Checked inductivity of 571 backedges. 275 proven. 76 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:56,994 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:57,247 INFO L134 CoverageAnalysis]: Checked inductivity of 571 backedges. 275 proven. 76 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:57,268 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:57,268 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 161 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 161 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:57,283 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:54:57,283 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:54:57,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:54:57,366 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:54:57,392 INFO L134 CoverageAnalysis]: Checked inductivity of 571 backedges. 275 proven. 76 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:57,392 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:54:57,678 INFO L134 CoverageAnalysis]: Checked inductivity of 571 backedges. 275 proven. 76 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:54:57,679 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:54:57,680 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 50 [2018-09-14 15:54:57,680 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:54:57,680 INFO L459 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-09-14 15:54:57,680 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-09-14 15:54:57,680 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=455, Invalid=1995, Unknown=0, NotChecked=0, Total=2450 [2018-09-14 15:54:57,680 INFO L87 Difference]: Start difference. First operand 167 states and 180 transitions. Second operand 50 states. [2018-09-14 15:55:01,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:55:01,498 INFO L93 Difference]: Finished difference Result 562 states and 652 transitions. [2018-09-14 15:55:01,498 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-09-14 15:55:01,499 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 129 [2018-09-14 15:55:01,499 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:55:01,500 INFO L225 Difference]: With dead ends: 562 [2018-09-14 15:55:01,501 INFO L226 Difference]: Without dead ends: 505 [2018-09-14 15:55:01,501 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 601 GetRequests, 443 SyntacticMatches, 52 SemanticMatches, 106 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5517 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=2079, Invalid=9477, Unknown=0, NotChecked=0, Total=11556 [2018-09-14 15:55:01,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 505 states. [2018-09-14 15:55:01,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 505 to 167. [2018-09-14 15:55:01,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-09-14 15:55:01,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 180 transitions. [2018-09-14 15:55:01,853 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 180 transitions. Word has length 129 [2018-09-14 15:55:01,853 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:55:01,853 INFO L480 AbstractCegarLoop]: Abstraction has 167 states and 180 transitions. [2018-09-14 15:55:01,853 INFO L481 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-09-14 15:55:01,853 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 180 transitions. [2018-09-14 15:55:01,854 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-09-14 15:55:01,854 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:55:01,854 INFO L376 BasicCegarLoop]: trace histogram [12, 12, 12, 12, 11, 11, 11, 11, 7, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:55:01,854 INFO L423 AbstractCegarLoop]: === Iteration 84 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:55:01,854 INFO L82 PathProgramCache]: Analyzing trace with hash 798123319, now seen corresponding path program 50 times [2018-09-14 15:55:01,854 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:55:01,855 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:55:01,855 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:55:01,855 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:55:01,855 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:55:01,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:55:02,176 INFO L134 CoverageAnalysis]: Checked inductivity of 567 backedges. 275 proven. 72 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:55:02,176 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:55:02,176 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 162 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 162 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:55:02,184 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:55:02,184 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:55:02,220 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:55:02,220 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:55:02,222 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:55:02,751 INFO L134 CoverageAnalysis]: Checked inductivity of 567 backedges. 275 proven. 72 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:55:02,752 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:55:03,012 INFO L134 CoverageAnalysis]: Checked inductivity of 567 backedges. 275 proven. 72 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:55:03,031 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:55:03,032 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 163 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 163 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:55:03,046 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:55:03,046 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:55:03,129 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:55:03,130 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:55:03,133 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:55:03,156 INFO L134 CoverageAnalysis]: Checked inductivity of 567 backedges. 275 proven. 72 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:55:03,156 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:55:03,435 INFO L134 CoverageAnalysis]: Checked inductivity of 567 backedges. 275 proven. 72 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:55:03,436 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:55:03,437 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 49 [2018-09-14 15:55:03,437 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:55:03,437 INFO L459 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-09-14 15:55:03,437 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-09-14 15:55:03,437 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=1917, Unknown=0, NotChecked=0, Total=2352 [2018-09-14 15:55:03,438 INFO L87 Difference]: Start difference. First operand 167 states and 180 transitions. Second operand 49 states. [2018-09-14 15:55:07,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:55:07,623 INFO L93 Difference]: Finished difference Result 624 states and 727 transitions. [2018-09-14 15:55:07,623 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-09-14 15:55:07,623 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 129 [2018-09-14 15:55:07,624 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:55:07,625 INFO L225 Difference]: With dead ends: 624 [2018-09-14 15:55:07,625 INFO L226 Difference]: Without dead ends: 567 [2018-09-14 15:55:07,626 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 604 GetRequests, 444 SyntacticMatches, 52 SemanticMatches, 108 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5602 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=2155, Invalid=9835, Unknown=0, NotChecked=0, Total=11990 [2018-09-14 15:55:07,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 567 states. [2018-09-14 15:55:07,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 567 to 167. [2018-09-14 15:55:07,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-09-14 15:55:07,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 180 transitions. [2018-09-14 15:55:07,943 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 180 transitions. Word has length 129 [2018-09-14 15:55:07,943 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:55:07,943 INFO L480 AbstractCegarLoop]: Abstraction has 167 states and 180 transitions. [2018-09-14 15:55:07,943 INFO L481 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-09-14 15:55:07,943 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 180 transitions. [2018-09-14 15:55:07,943 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-09-14 15:55:07,944 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:55:07,944 INFO L376 BasicCegarLoop]: trace histogram [12, 12, 12, 12, 11, 11, 11, 11, 7, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:55:07,944 INFO L423 AbstractCegarLoop]: === Iteration 85 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:55:07,944 INFO L82 PathProgramCache]: Analyzing trace with hash -903540029, now seen corresponding path program 51 times [2018-09-14 15:55:07,944 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:55:07,945 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:55:07,945 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:55:07,945 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:55:07,945 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:55:07,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:55:08,243 INFO L134 CoverageAnalysis]: Checked inductivity of 567 backedges. 275 proven. 72 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:55:08,243 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:55:08,243 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 164 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 164 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:55:08,250 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:55:08,251 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:55:08,294 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-09-14 15:55:08,294 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:55:08,297 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:55:08,801 INFO L134 CoverageAnalysis]: Checked inductivity of 567 backedges. 275 proven. 72 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:55:08,802 INFO L316 TraceCheckSpWp]: Computing backward predicates... Received shutdown request... [2018-09-14 15:55:09,070 INFO L134 CoverageAnalysis]: Checked inductivity of 567 backedges. 275 proven. 72 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-09-14 15:55:09,090 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:55:09,091 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 165 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 165 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:55:09,106 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:55:09,106 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:55:09,303 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-09-14 15:55:09,303 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:55:09,307 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:55:09,309 INFO L177 TraceCheckSpWp]: Timeout while computing interpolants [2018-09-14 15:55:09,509 WARN L521 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 165 cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:55:09,510 WARN L549 AbstractCegarLoop]: Verification canceled [2018-09-14 15:55:09,513 WARN L206 ceAbstractionStarter]: Timeout [2018-09-14 15:55:09,514 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 14.09 03:55:09 BoogieIcfgContainer [2018-09-14 15:55:09,514 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-09-14 15:55:09,514 INFO L168 Benchmark]: Toolchain (without parser) took 235395.88 ms. Allocated memory was 1.5 GB in the beginning and 2.1 GB in the end (delta: 615.5 MB). Free memory was 1.4 GB in the beginning and 2.0 GB in the end (delta: -565.2 MB). Peak memory consumption was 50.3 MB. Max. memory is 7.1 GB. [2018-09-14 15:55:09,515 INFO L168 Benchmark]: CDTParser took 0.23 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-09-14 15:55:09,515 INFO L168 Benchmark]: CACSL2BoogieTranslator took 321.69 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. [2018-09-14 15:55:09,516 INFO L168 Benchmark]: Boogie Procedure Inliner took 22.69 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-09-14 15:55:09,516 INFO L168 Benchmark]: Boogie Preprocessor took 23.40 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-09-14 15:55:09,516 INFO L168 Benchmark]: RCFGBuilder took 526.17 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 733.5 MB). Free memory was 1.4 GB in the beginning and 2.2 GB in the end (delta: -786.1 MB). Peak memory consumption was 26.5 MB. Max. memory is 7.1 GB. [2018-09-14 15:55:09,516 INFO L168 Benchmark]: TraceAbstraction took 234494.47 ms. Allocated memory was 2.3 GB in the beginning and 2.1 GB in the end (delta: -118.0 MB). Free memory was 2.2 GB in the beginning and 2.0 GB in the end (delta: 210.3 MB). Peak memory consumption was 92.3 MB. Max. memory is 7.1 GB. [2018-09-14 15:55:09,518 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.23 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 321.69 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 22.69 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Preprocessor took 23.40 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * RCFGBuilder took 526.17 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 733.5 MB). Free memory was 1.4 GB in the beginning and 2.2 GB in the end (delta: -786.1 MB). Peak memory consumption was 26.5 MB. Max. memory is 7.1 GB. * TraceAbstraction took 234494.47 ms. Allocated memory was 2.3 GB in the beginning and 2.1 GB in the end (delta: -118.0 MB). Free memory was 2.2 GB in the beginning and 2.0 GB in the end (delta: 210.3 MB). Peak memory consumption was 92.3 MB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 5]: Timeout (TraceAbstraction) Unable to prove that call of __VERIFIER_error() unreachable (line 5). Cancelled while BasicCegarLoop was analyzing trace of length 130 with TraceHistMax 12, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 27 locations, 1 error locations. TIMEOUT Result, 234.4s OverallTime, 85 OverallIterations, 12 TraceHistogramMax, 113.4s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 3959 SDtfs, 10162 SDslu, 34531 SDs, 0 SdLazy, 31366 SolverSat, 6617 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 30.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 32399 GetRequests, 24875 SyntacticMatches, 2872 SemanticMatches, 4652 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 162778 ImplicationChecksByTransitivity, 121.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=167occurred in iteration=79, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 9.5s AutomataMinimizationTime, 84 MinimizatonAttempts, 14482 StatesRemovedByMinimization, 73 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.7s SsaConstructionTime, 9.0s SatisfiabilityAnalysisTime, 95.0s InterpolantComputationTime, 21564 NumberOfCodeBlocks, 21564 NumberOfCodeBlocksAsserted, 850 NumberOfCheckSat, 35494 ConstructedInterpolants, 0 QuantifiedInterpolants, 14039772 SizeOfPredicates, 1034 NumberOfNonLiveVariables, 30972 ConjunctsInSsa, 3256 ConjunctsInUnsatCore, 408 InterpolantComputations, 3 PerfectInterpolantSequences, 91807/113237 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/seq_true-unreach-call_true-termination.i_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-Benchmark-0-2018-09-14_15-55-09-527.csv Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/seq_true-unreach-call_true-termination.i_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-TraceAbstractionBenchmarks-0-2018-09-14_15-55-09-527.csv Completed graceful shutdown