java -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data --generate-csv --csv-dir csv -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml -s ../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf -i ../../../trunk/examples/svcomp/loop-crafted/simple_array_index_value_true-unreach-call3_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-dace188-m [2018-09-14 15:50:27,629 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-09-14 15:50:27,631 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-09-14 15:50:27,643 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-09-14 15:50:27,643 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-09-14 15:50:27,644 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-09-14 15:50:27,645 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-09-14 15:50:27,647 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-09-14 15:50:27,649 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-09-14 15:50:27,649 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-09-14 15:50:27,650 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-09-14 15:50:27,651 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-09-14 15:50:27,652 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-09-14 15:50:27,653 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-09-14 15:50:27,654 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-09-14 15:50:27,655 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-09-14 15:50:27,655 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-09-14 15:50:27,657 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-09-14 15:50:27,659 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-09-14 15:50:27,661 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-09-14 15:50:27,662 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-09-14 15:50:27,663 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-09-14 15:50:27,665 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-09-14 15:50:27,665 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-09-14 15:50:27,666 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-09-14 15:50:27,667 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-09-14 15:50:27,668 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-09-14 15:50:27,668 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-09-14 15:50:27,669 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-09-14 15:50:27,670 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-09-14 15:50:27,671 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-09-14 15:50:27,671 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... 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[2018-09-14 15:50:27,674 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf [2018-09-14 15:50:27,693 INFO L110 SettingsManager]: Loading preferences was successful [2018-09-14 15:50:27,693 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-09-14 15:50:27,694 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-09-14 15:50:27,694 INFO L133 SettingsManager]: * User list type=DISABLED [2018-09-14 15:50:27,695 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-09-14 15:50:27,695 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-09-14 15:50:27,695 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-09-14 15:50:27,695 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-09-14 15:50:27,695 INFO L133 SettingsManager]: * Log string format=TERM [2018-09-14 15:50:27,696 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-09-14 15:50:27,696 INFO L133 SettingsManager]: * Interval Domain=false [2018-09-14 15:50:27,696 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-09-14 15:50:27,697 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-09-14 15:50:27,697 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-09-14 15:50:27,697 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-09-14 15:50:27,697 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-09-14 15:50:27,698 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-09-14 15:50:27,698 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-09-14 15:50:27,698 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-09-14 15:50:27,698 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-09-14 15:50:27,698 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-09-14 15:50:27,699 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-09-14 15:50:27,699 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-09-14 15:50:27,699 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-09-14 15:50:27,699 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-09-14 15:50:27,700 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-09-14 15:50:27,700 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-09-14 15:50:27,700 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-09-14 15:50:27,700 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-09-14 15:50:27,700 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-09-14 15:50:27,701 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-09-14 15:50:27,701 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-09-14 15:50:27,701 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-09-14 15:50:27,743 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-09-14 15:50:27,755 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-09-14 15:50:27,758 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-09-14 15:50:27,760 INFO L271 PluginConnector]: Initializing CDTParser... [2018-09-14 15:50:27,760 INFO L276 PluginConnector]: CDTParser initialized [2018-09-14 15:50:27,761 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-crafted/simple_array_index_value_true-unreach-call3_true-termination.i [2018-09-14 15:50:28,096 INFO L221 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8dbc06a20/ba6f1ddd4bca4ca0b70e058f9421809d/FLAGf4c9d34f7 [2018-09-14 15:50:28,255 INFO L277 CDTParser]: Found 1 translation units. [2018-09-14 15:50:28,256 INFO L159 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-crafted/simple_array_index_value_true-unreach-call3_true-termination.i [2018-09-14 15:50:28,261 INFO L325 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8dbc06a20/ba6f1ddd4bca4ca0b70e058f9421809d/FLAGf4c9d34f7 [2018-09-14 15:50:28,276 INFO L333 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8dbc06a20/ba6f1ddd4bca4ca0b70e058f9421809d [2018-09-14 15:50:28,289 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-09-14 15:50:28,292 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-09-14 15:50:28,294 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-09-14 15:50:28,294 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-09-14 15:50:28,300 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-09-14 15:50:28,301 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.09 03:50:28" (1/1) ... [2018-09-14 15:50:28,304 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@77eb0580 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:50:28, skipping insertion in model container [2018-09-14 15:50:28,304 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.09 03:50:28" (1/1) ... [2018-09-14 15:50:28,316 INFO L160 ieTranslatorObserver]: Starting translation in SV-COMP mode [2018-09-14 15:50:28,529 INFO L170 PostProcessor]: Settings: Checked method=main [2018-09-14 15:50:28,550 INFO L424 MainDispatcher]: Starting main dispatcher in SV-COMP mode [2018-09-14 15:50:28,563 INFO L170 PostProcessor]: Settings: Checked method=main [2018-09-14 15:50:28,576 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:50:28 WrapperNode [2018-09-14 15:50:28,578 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-09-14 15:50:28,579 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-09-14 15:50:28,579 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-09-14 15:50:28,580 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-09-14 15:50:28,589 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:50:28" (1/1) ... [2018-09-14 15:50:28,597 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:50:28" (1/1) ... [2018-09-14 15:50:28,602 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-09-14 15:50:28,603 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-09-14 15:50:28,603 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-09-14 15:50:28,603 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-09-14 15:50:28,617 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:50:28" (1/1) ... [2018-09-14 15:50:28,617 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:50:28" (1/1) ... [2018-09-14 15:50:28,618 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:50:28" (1/1) ... [2018-09-14 15:50:28,618 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:50:28" (1/1) ... [2018-09-14 15:50:28,620 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:50:28" (1/1) ... [2018-09-14 15:50:28,627 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:50:28" (1/1) ... [2018-09-14 15:50:28,628 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:50:28" (1/1) ... [2018-09-14 15:50:28,630 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-09-14 15:50:28,631 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-09-14 15:50:28,631 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-09-14 15:50:28,631 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-09-14 15:50:28,634 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:50:28" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-09-14 15:50:28,701 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-09-14 15:50:28,702 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-09-14 15:50:28,702 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-09-14 15:50:28,702 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-09-14 15:50:28,702 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-09-14 15:50:28,703 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-09-14 15:50:28,703 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-09-14 15:50:28,703 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-09-14 15:50:29,007 INFO L353 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-09-14 15:50:29,008 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.09 03:50:29 BoogieIcfgContainer [2018-09-14 15:50:29,008 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-09-14 15:50:29,009 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-09-14 15:50:29,009 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-09-14 15:50:29,012 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-09-14 15:50:29,013 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 14.09 03:50:28" (1/3) ... [2018-09-14 15:50:29,013 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@51365869 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.09 03:50:29, skipping insertion in model container [2018-09-14 15:50:29,014 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.09 03:50:28" (2/3) ... [2018-09-14 15:50:29,014 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@51365869 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.09 03:50:29, skipping insertion in model container [2018-09-14 15:50:29,014 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.09 03:50:29" (3/3) ... [2018-09-14 15:50:29,016 INFO L112 eAbstractionObserver]: Analyzing ICFG simple_array_index_value_true-unreach-call3_true-termination.i [2018-09-14 15:50:29,029 INFO L137 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-09-14 15:50:29,038 INFO L149 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-09-14 15:50:29,105 INFO L130 ementStrategyFactory]: Using default assertion order modulation [2018-09-14 15:50:29,106 INFO L381 AbstractCegarLoop]: Interprodecural is true [2018-09-14 15:50:29,106 INFO L382 AbstractCegarLoop]: Hoare is true [2018-09-14 15:50:29,107 INFO L383 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-09-14 15:50:29,107 INFO L384 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-09-14 15:50:29,107 INFO L385 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-09-14 15:50:29,107 INFO L386 AbstractCegarLoop]: Difference is false [2018-09-14 15:50:29,107 INFO L387 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-09-14 15:50:29,107 INFO L392 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-09-14 15:50:29,149 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states. [2018-09-14 15:50:29,160 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-09-14 15:50:29,161 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:50:29,162 INFO L376 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:50:29,163 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:50:29,168 INFO L82 PathProgramCache]: Analyzing trace with hash -1885467766, now seen corresponding path program 1 times [2018-09-14 15:50:29,171 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:50:29,218 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:29,219 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:50:29,219 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:29,219 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:50:29,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:50:29,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:29,278 INFO L313 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-09-14 15:50:29,279 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-09-14 15:50:29,279 INFO L265 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-09-14 15:50:29,282 INFO L459 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-09-14 15:50:29,294 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-09-14 15:50:29,294 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-09-14 15:50:29,297 INFO L87 Difference]: Start difference. First operand 22 states. Second operand 2 states. [2018-09-14 15:50:29,321 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:50:29,321 INFO L93 Difference]: Finished difference Result 37 states and 44 transitions. [2018-09-14 15:50:29,321 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-09-14 15:50:29,323 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 13 [2018-09-14 15:50:29,323 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:50:29,331 INFO L225 Difference]: With dead ends: 37 [2018-09-14 15:50:29,331 INFO L226 Difference]: Without dead ends: 18 [2018-09-14 15:50:29,335 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-09-14 15:50:29,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states. [2018-09-14 15:50:29,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 18. [2018-09-14 15:50:29,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2018-09-14 15:50:29,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 19 transitions. [2018-09-14 15:50:29,371 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 19 transitions. Word has length 13 [2018-09-14 15:50:29,372 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:50:29,372 INFO L480 AbstractCegarLoop]: Abstraction has 18 states and 19 transitions. [2018-09-14 15:50:29,372 INFO L481 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-09-14 15:50:29,372 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 19 transitions. [2018-09-14 15:50:29,373 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-09-14 15:50:29,373 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:50:29,373 INFO L376 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:50:29,374 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:50:29,374 INFO L82 PathProgramCache]: Analyzing trace with hash 1968857590, now seen corresponding path program 1 times [2018-09-14 15:50:29,374 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:50:29,375 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:29,376 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:50:29,376 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:29,376 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:50:29,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:50:29,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:29,486 INFO L313 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-09-14 15:50:29,486 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-09-14 15:50:29,486 INFO L265 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-09-14 15:50:29,488 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-09-14 15:50:29,488 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-09-14 15:50:29,488 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-09-14 15:50:29,489 INFO L87 Difference]: Start difference. First operand 18 states and 19 transitions. Second operand 3 states. [2018-09-14 15:50:29,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:50:29,574 INFO L93 Difference]: Finished difference Result 35 states and 38 transitions. [2018-09-14 15:50:29,574 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-09-14 15:50:29,574 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 14 [2018-09-14 15:50:29,575 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:50:29,577 INFO L225 Difference]: With dead ends: 35 [2018-09-14 15:50:29,577 INFO L226 Difference]: Without dead ends: 24 [2018-09-14 15:50:29,578 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-09-14 15:50:29,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states. [2018-09-14 15:50:29,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 20. [2018-09-14 15:50:29,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2018-09-14 15:50:29,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 21 transitions. [2018-09-14 15:50:29,588 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 21 transitions. Word has length 14 [2018-09-14 15:50:29,589 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:50:29,589 INFO L480 AbstractCegarLoop]: Abstraction has 20 states and 21 transitions. [2018-09-14 15:50:29,589 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-09-14 15:50:29,589 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 21 transitions. [2018-09-14 15:50:29,590 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-09-14 15:50:29,590 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:50:29,590 INFO L376 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:50:29,590 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:50:29,591 INFO L82 PathProgramCache]: Analyzing trace with hash -1961268304, now seen corresponding path program 1 times [2018-09-14 15:50:29,591 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:50:29,592 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:29,592 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:50:29,592 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:29,592 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:50:29,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:50:29,708 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:29,709 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:50:29,709 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:50:29,719 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:50:29,719 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:50:29,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:50:29,743 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:50:29,820 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-09-14 15:50:29,823 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-09-14 15:50:29,829 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-09-14 15:50:29,829 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-09-14 15:50:30,056 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:30,057 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:50:30,447 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 5 [2018-09-14 15:50:30,452 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-09-14 15:50:30,458 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-09-14 15:50:30,459 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-09-14 15:50:30,506 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:30,528 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:50:30,528 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:50:30,545 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:50:30,545 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:50:30,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:50:30,566 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:50:30,580 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:30,580 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:50:30,797 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:30,799 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:50:30,800 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 7, 7, 4, 4] total 16 [2018-09-14 15:50:30,800 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:50:30,801 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-09-14 15:50:30,801 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-09-14 15:50:30,802 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=192, Unknown=0, NotChecked=0, Total=240 [2018-09-14 15:50:30,803 INFO L87 Difference]: Start difference. First operand 20 states and 21 transitions. Second operand 9 states. [2018-09-14 15:50:31,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:50:31,033 INFO L93 Difference]: Finished difference Result 60 states and 68 transitions. [2018-09-14 15:50:31,035 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-09-14 15:50:31,035 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 16 [2018-09-14 15:50:31,035 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:50:31,036 INFO L225 Difference]: With dead ends: 60 [2018-09-14 15:50:31,037 INFO L226 Difference]: Without dead ends: 49 [2018-09-14 15:50:31,038 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 51 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 46 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=61, Invalid=245, Unknown=0, NotChecked=0, Total=306 [2018-09-14 15:50:31,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-09-14 15:50:31,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 32. [2018-09-14 15:50:31,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32 states. [2018-09-14 15:50:31,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 34 transitions. [2018-09-14 15:50:31,047 INFO L78 Accepts]: Start accepts. Automaton has 32 states and 34 transitions. Word has length 16 [2018-09-14 15:50:31,047 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:50:31,047 INFO L480 AbstractCegarLoop]: Abstraction has 32 states and 34 transitions. [2018-09-14 15:50:31,047 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-09-14 15:50:31,048 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 34 transitions. [2018-09-14 15:50:31,048 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-09-14 15:50:31,048 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:50:31,049 INFO L376 BasicCegarLoop]: trace histogram [4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:50:31,049 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:50:31,049 INFO L82 PathProgramCache]: Analyzing trace with hash -728986716, now seen corresponding path program 2 times [2018-09-14 15:50:31,049 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:50:31,050 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:31,051 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:50:31,051 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:31,051 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:50:31,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:50:31,470 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:31,470 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:50:31,470 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:50:31,490 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:50:31,490 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:50:31,507 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:50:31,507 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:50:31,509 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:50:31,534 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:31,534 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:50:31,652 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:31,673 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:50:31,674 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:50:31,690 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:50:31,690 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:50:31,719 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:50:31,720 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:50:31,723 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:50:31,734 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:31,734 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:50:31,744 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:31,745 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:50:31,745 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 10 [2018-09-14 15:50:31,745 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:50:31,746 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-09-14 15:50:31,746 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-09-14 15:50:31,746 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-09-14 15:50:31,747 INFO L87 Difference]: Start difference. First operand 32 states and 34 transitions. Second operand 6 states. [2018-09-14 15:50:31,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:50:31,957 INFO L93 Difference]: Finished difference Result 61 states and 68 transitions. [2018-09-14 15:50:31,959 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-09-14 15:50:31,959 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 20 [2018-09-14 15:50:31,959 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:50:31,960 INFO L225 Difference]: With dead ends: 61 [2018-09-14 15:50:31,960 INFO L226 Difference]: Without dead ends: 42 [2018-09-14 15:50:31,961 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 74 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-09-14 15:50:31,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states. [2018-09-14 15:50:31,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 26. [2018-09-14 15:50:31,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2018-09-14 15:50:31,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 27 transitions. [2018-09-14 15:50:31,967 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 27 transitions. Word has length 20 [2018-09-14 15:50:31,967 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:50:31,967 INFO L480 AbstractCegarLoop]: Abstraction has 26 states and 27 transitions. [2018-09-14 15:50:31,968 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-09-14 15:50:31,968 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 27 transitions. [2018-09-14 15:50:31,968 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-09-14 15:50:31,968 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:50:31,969 INFO L376 BasicCegarLoop]: trace histogram [5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:50:31,969 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:50:31,969 INFO L82 PathProgramCache]: Analyzing trace with hash -429399586, now seen corresponding path program 3 times [2018-09-14 15:50:31,969 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:50:31,970 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:31,970 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:50:31,970 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:31,971 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:50:31,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:50:32,117 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:32,117 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:50:32,117 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:50:32,126 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:50:32,126 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:50:32,154 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2018-09-14 15:50:32,154 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:50:32,158 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:50:32,166 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:32,167 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:50:32,284 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:32,305 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:50:32,305 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:50:32,321 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:50:32,321 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:50:32,391 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2018-09-14 15:50:32,392 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:50:32,398 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:50:32,417 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:32,417 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:50:32,429 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:32,439 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:50:32,439 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 12 [2018-09-14 15:50:32,439 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:50:32,439 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-09-14 15:50:32,440 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-09-14 15:50:32,440 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-09-14 15:50:32,440 INFO L87 Difference]: Start difference. First operand 26 states and 27 transitions. Second operand 7 states. [2018-09-14 15:50:32,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:50:32,675 INFO L93 Difference]: Finished difference Result 59 states and 66 transitions. [2018-09-14 15:50:32,675 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-09-14 15:50:32,675 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 22 [2018-09-14 15:50:32,676 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:50:32,677 INFO L225 Difference]: With dead ends: 59 [2018-09-14 15:50:32,677 INFO L226 Difference]: Without dead ends: 48 [2018-09-14 15:50:32,678 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 81 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-09-14 15:50:32,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states. [2018-09-14 15:50:32,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 28. [2018-09-14 15:50:32,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28 states. [2018-09-14 15:50:32,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 29 transitions. [2018-09-14 15:50:32,684 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 29 transitions. Word has length 22 [2018-09-14 15:50:32,685 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:50:32,685 INFO L480 AbstractCegarLoop]: Abstraction has 28 states and 29 transitions. [2018-09-14 15:50:32,685 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-09-14 15:50:32,685 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 29 transitions. [2018-09-14 15:50:32,686 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-09-14 15:50:32,686 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:50:32,686 INFO L376 BasicCegarLoop]: trace histogram [6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:50:32,686 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:50:32,687 INFO L82 PathProgramCache]: Analyzing trace with hash -288976488, now seen corresponding path program 4 times [2018-09-14 15:50:32,687 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:50:32,688 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:32,688 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:50:32,688 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:32,688 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:50:32,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:50:32,843 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:32,843 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:50:32,843 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:50:32,854 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:50:32,854 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:50:32,871 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:50:32,872 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:50:32,874 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:50:32,891 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:32,891 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:50:33,041 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:33,061 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:50:33,062 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:50:33,078 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:50:33,078 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:50:33,115 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:50:33,115 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:50:33,119 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:50:33,141 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:33,142 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:50:33,197 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:33,200 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:50:33,200 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 14 [2018-09-14 15:50:33,200 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:50:33,201 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-09-14 15:50:33,201 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-09-14 15:50:33,202 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-09-14 15:50:33,202 INFO L87 Difference]: Start difference. First operand 28 states and 29 transitions. Second operand 8 states. [2018-09-14 15:50:33,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:50:33,563 INFO L93 Difference]: Finished difference Result 65 states and 73 transitions. [2018-09-14 15:50:33,563 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-09-14 15:50:33,563 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 24 [2018-09-14 15:50:33,564 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:50:33,565 INFO L225 Difference]: With dead ends: 65 [2018-09-14 15:50:33,565 INFO L226 Difference]: Without dead ends: 54 [2018-09-14 15:50:33,565 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 102 GetRequests, 88 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-09-14 15:50:33,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-09-14 15:50:33,571 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 30. [2018-09-14 15:50:33,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-09-14 15:50:33,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 31 transitions. [2018-09-14 15:50:33,572 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 31 transitions. Word has length 24 [2018-09-14 15:50:33,572 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:50:33,572 INFO L480 AbstractCegarLoop]: Abstraction has 30 states and 31 transitions. [2018-09-14 15:50:33,573 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-09-14 15:50:33,573 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 31 transitions. [2018-09-14 15:50:33,574 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-09-14 15:50:33,574 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:50:33,574 INFO L376 BasicCegarLoop]: trace histogram [7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:50:33,574 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:50:33,575 INFO L82 PathProgramCache]: Analyzing trace with hash 1513634514, now seen corresponding path program 5 times [2018-09-14 15:50:33,575 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:50:33,576 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:33,576 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:50:33,576 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:33,576 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:50:33,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:50:33,808 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:33,808 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:50:33,808 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:50:33,816 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:50:33,816 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:50:33,861 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-09-14 15:50:33,862 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:50:33,864 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:50:33,882 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:33,882 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:50:34,216 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:34,237 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:50:34,237 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:50:34,253 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:50:34,253 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:50:34,368 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-09-14 15:50:34,368 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:50:34,372 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:50:34,391 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:34,392 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:50:34,406 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:34,408 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:50:34,408 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 16 [2018-09-14 15:50:34,408 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:50:34,408 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-09-14 15:50:34,409 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-09-14 15:50:34,409 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-09-14 15:50:34,410 INFO L87 Difference]: Start difference. First operand 30 states and 31 transitions. Second operand 9 states. [2018-09-14 15:50:34,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:50:34,623 INFO L93 Difference]: Finished difference Result 71 states and 80 transitions. [2018-09-14 15:50:34,625 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-09-14 15:50:34,625 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 26 [2018-09-14 15:50:34,625 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:50:34,626 INFO L225 Difference]: With dead ends: 71 [2018-09-14 15:50:34,626 INFO L226 Difference]: Without dead ends: 60 [2018-09-14 15:50:34,627 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 111 GetRequests, 95 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-09-14 15:50:34,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2018-09-14 15:50:34,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 32. [2018-09-14 15:50:34,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32 states. [2018-09-14 15:50:34,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 33 transitions. [2018-09-14 15:50:34,634 INFO L78 Accepts]: Start accepts. Automaton has 32 states and 33 transitions. Word has length 26 [2018-09-14 15:50:34,634 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:50:34,634 INFO L480 AbstractCegarLoop]: Abstraction has 32 states and 33 transitions. [2018-09-14 15:50:34,635 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-09-14 15:50:34,635 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 33 transitions. [2018-09-14 15:50:34,635 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-09-14 15:50:34,636 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:50:34,636 INFO L376 BasicCegarLoop]: trace histogram [8, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:50:34,636 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:50:34,636 INFO L82 PathProgramCache]: Analyzing trace with hash -1343980148, now seen corresponding path program 6 times [2018-09-14 15:50:34,636 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:50:34,637 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:34,637 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:50:34,637 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:34,638 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:50:34,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:50:34,801 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:34,802 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:50:34,802 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:50:34,809 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:50:34,809 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:50:34,872 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-09-14 15:50:34,872 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:50:34,875 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:50:34,903 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:34,903 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:50:35,098 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:35,119 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:50:35,119 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:50:35,134 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:50:35,135 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:50:35,331 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-09-14 15:50:35,331 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:50:35,335 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:50:35,370 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:35,370 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:50:35,423 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:35,425 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:50:35,425 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 18 [2018-09-14 15:50:35,425 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:50:35,426 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-09-14 15:50:35,426 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-09-14 15:50:35,426 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-09-14 15:50:35,427 INFO L87 Difference]: Start difference. First operand 32 states and 33 transitions. Second operand 10 states. [2018-09-14 15:50:35,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:50:35,730 INFO L93 Difference]: Finished difference Result 77 states and 87 transitions. [2018-09-14 15:50:35,731 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-09-14 15:50:35,731 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 28 [2018-09-14 15:50:35,732 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:50:35,733 INFO L225 Difference]: With dead ends: 77 [2018-09-14 15:50:35,733 INFO L226 Difference]: Without dead ends: 66 [2018-09-14 15:50:35,734 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 120 GetRequests, 102 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-09-14 15:50:35,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2018-09-14 15:50:35,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 34. [2018-09-14 15:50:35,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34 states. [2018-09-14 15:50:35,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 35 transitions. [2018-09-14 15:50:35,740 INFO L78 Accepts]: Start accepts. Automaton has 34 states and 35 transitions. Word has length 28 [2018-09-14 15:50:35,741 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:50:35,741 INFO L480 AbstractCegarLoop]: Abstraction has 34 states and 35 transitions. [2018-09-14 15:50:35,741 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-09-14 15:50:35,741 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 35 transitions. [2018-09-14 15:50:35,742 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-09-14 15:50:35,742 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:50:35,742 INFO L376 BasicCegarLoop]: trace histogram [9, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:50:35,742 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:50:35,743 INFO L82 PathProgramCache]: Analyzing trace with hash 1267399110, now seen corresponding path program 7 times [2018-09-14 15:50:35,743 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:50:35,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:35,744 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:50:35,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:35,744 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:50:35,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:50:35,938 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:35,938 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:50:35,938 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:50:35,949 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:50:35,949 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:50:35,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:50:35,978 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:50:36,003 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:36,003 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:50:36,550 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:36,571 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:50:36,571 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:50:36,586 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:50:36,586 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:50:36,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:50:36,641 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:50:36,667 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:36,667 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:50:36,694 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:36,695 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:50:36,696 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 20 [2018-09-14 15:50:36,696 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:50:36,696 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-09-14 15:50:36,696 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-09-14 15:50:36,697 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-09-14 15:50:36,697 INFO L87 Difference]: Start difference. First operand 34 states and 35 transitions. Second operand 11 states. [2018-09-14 15:50:37,112 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:50:37,113 INFO L93 Difference]: Finished difference Result 83 states and 94 transitions. [2018-09-14 15:50:37,116 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-09-14 15:50:37,116 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 30 [2018-09-14 15:50:37,116 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:50:37,117 INFO L225 Difference]: With dead ends: 83 [2018-09-14 15:50:37,117 INFO L226 Difference]: Without dead ends: 72 [2018-09-14 15:50:37,118 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 129 GetRequests, 109 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-09-14 15:50:37,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states. [2018-09-14 15:50:37,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 36. [2018-09-14 15:50:37,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2018-09-14 15:50:37,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 37 transitions. [2018-09-14 15:50:37,125 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 37 transitions. Word has length 30 [2018-09-14 15:50:37,125 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:50:37,125 INFO L480 AbstractCegarLoop]: Abstraction has 36 states and 37 transitions. [2018-09-14 15:50:37,125 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-09-14 15:50:37,126 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 37 transitions. [2018-09-14 15:50:37,126 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-09-14 15:50:37,126 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:50:37,127 INFO L376 BasicCegarLoop]: trace histogram [10, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:50:37,127 INFO L423 AbstractCegarLoop]: === Iteration 10 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:50:37,127 INFO L82 PathProgramCache]: Analyzing trace with hash -1753002112, now seen corresponding path program 8 times [2018-09-14 15:50:37,127 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:50:37,128 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:37,128 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:50:37,128 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:37,129 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:50:37,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:50:37,650 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:37,651 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:50:37,651 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:50:37,660 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:50:37,660 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:50:37,701 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:50:37,701 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:50:37,703 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:50:37,737 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:37,737 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:50:38,012 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:38,034 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:50:38,034 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:50:38,051 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:50:38,051 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:50:38,108 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:50:38,108 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:50:38,111 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:50:38,130 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:38,130 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:50:38,184 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:38,186 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:50:38,186 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 22 [2018-09-14 15:50:38,186 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:50:38,187 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-09-14 15:50:38,187 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-09-14 15:50:38,187 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-09-14 15:50:38,190 INFO L87 Difference]: Start difference. First operand 36 states and 37 transitions. Second operand 12 states. [2018-09-14 15:50:40,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:50:40,802 INFO L93 Difference]: Finished difference Result 89 states and 101 transitions. [2018-09-14 15:50:40,803 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-09-14 15:50:40,803 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 32 [2018-09-14 15:50:40,804 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:50:40,805 INFO L225 Difference]: With dead ends: 89 [2018-09-14 15:50:40,805 INFO L226 Difference]: Without dead ends: 78 [2018-09-14 15:50:40,805 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 138 GetRequests, 116 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-09-14 15:50:40,806 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states. [2018-09-14 15:50:40,811 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 38. [2018-09-14 15:50:40,811 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2018-09-14 15:50:40,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 39 transitions. [2018-09-14 15:50:40,812 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 39 transitions. Word has length 32 [2018-09-14 15:50:40,812 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:50:40,812 INFO L480 AbstractCegarLoop]: Abstraction has 38 states and 39 transitions. [2018-09-14 15:50:40,813 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-09-14 15:50:40,813 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 39 transitions. [2018-09-14 15:50:40,814 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-09-14 15:50:40,814 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:50:40,814 INFO L376 BasicCegarLoop]: trace histogram [11, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:50:40,814 INFO L423 AbstractCegarLoop]: === Iteration 11 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:50:40,814 INFO L82 PathProgramCache]: Analyzing trace with hash -960684358, now seen corresponding path program 9 times [2018-09-14 15:50:40,814 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:50:40,815 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:40,815 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:50:40,815 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:40,815 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:50:40,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:50:41,208 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:41,208 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:50:41,209 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:50:41,218 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:50:41,218 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:50:41,307 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-09-14 15:50:41,308 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:50:41,310 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:50:41,344 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:41,344 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:50:41,824 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:41,845 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:50:41,845 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:50:41,861 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:50:41,862 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:50:55,118 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-09-14 15:50:55,118 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:50:55,123 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:50:55,137 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:55,137 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:50:55,191 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:55,195 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:50:55,195 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 24 [2018-09-14 15:50:55,196 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:50:55,196 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-09-14 15:50:55,196 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-09-14 15:50:55,197 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-09-14 15:50:55,197 INFO L87 Difference]: Start difference. First operand 38 states and 39 transitions. Second operand 13 states. [2018-09-14 15:50:55,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:50:55,737 INFO L93 Difference]: Finished difference Result 95 states and 108 transitions. [2018-09-14 15:50:55,738 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-09-14 15:50:55,738 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 34 [2018-09-14 15:50:55,738 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:50:55,740 INFO L225 Difference]: With dead ends: 95 [2018-09-14 15:50:55,740 INFO L226 Difference]: Without dead ends: 84 [2018-09-14 15:50:55,741 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 147 GetRequests, 123 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-09-14 15:50:55,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2018-09-14 15:50:55,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 40. [2018-09-14 15:50:55,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40 states. [2018-09-14 15:50:55,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 41 transitions. [2018-09-14 15:50:55,749 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 41 transitions. Word has length 34 [2018-09-14 15:50:55,749 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:50:55,749 INFO L480 AbstractCegarLoop]: Abstraction has 40 states and 41 transitions. [2018-09-14 15:50:55,750 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-09-14 15:50:55,750 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 41 transitions. [2018-09-14 15:50:55,750 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-09-14 15:50:55,750 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:50:55,751 INFO L376 BasicCegarLoop]: trace histogram [12, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:50:55,751 INFO L423 AbstractCegarLoop]: === Iteration 12 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:50:55,751 INFO L82 PathProgramCache]: Analyzing trace with hash 247465844, now seen corresponding path program 10 times [2018-09-14 15:50:55,751 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:50:55,752 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:55,752 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:50:55,752 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:55,752 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:50:55,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:50:56,015 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:56,015 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:50:56,015 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:50:56,023 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:50:56,023 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:50:56,040 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:50:56,040 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:50:56,041 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:50:56,096 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:56,096 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:50:56,501 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:56,522 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:50:56,522 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:50:56,537 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:50:56,537 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:50:56,642 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:50:56,642 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:50:56,646 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:50:56,676 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:56,676 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:50:56,732 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:56,735 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:50:56,735 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 26 [2018-09-14 15:50:56,735 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:50:56,735 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-09-14 15:50:56,736 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-09-14 15:50:56,736 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-09-14 15:50:56,737 INFO L87 Difference]: Start difference. First operand 40 states and 41 transitions. Second operand 14 states. [2018-09-14 15:50:57,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:50:57,400 INFO L93 Difference]: Finished difference Result 101 states and 115 transitions. [2018-09-14 15:50:57,401 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-09-14 15:50:57,401 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 36 [2018-09-14 15:50:57,402 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:50:57,402 INFO L225 Difference]: With dead ends: 101 [2018-09-14 15:50:57,403 INFO L226 Difference]: Without dead ends: 90 [2018-09-14 15:50:57,403 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 130 SyntacticMatches, 2 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-09-14 15:50:57,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states. [2018-09-14 15:50:57,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 42. [2018-09-14 15:50:57,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2018-09-14 15:50:57,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 43 transitions. [2018-09-14 15:50:57,410 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 43 transitions. Word has length 36 [2018-09-14 15:50:57,411 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:50:57,411 INFO L480 AbstractCegarLoop]: Abstraction has 42 states and 43 transitions. [2018-09-14 15:50:57,411 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-09-14 15:50:57,411 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 43 transitions. [2018-09-14 15:50:57,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-09-14 15:50:57,412 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:50:57,412 INFO L376 BasicCegarLoop]: trace histogram [13, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:50:57,412 INFO L423 AbstractCegarLoop]: === Iteration 13 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:50:57,412 INFO L82 PathProgramCache]: Analyzing trace with hash 1638640046, now seen corresponding path program 11 times [2018-09-14 15:50:57,412 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:50:57,413 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:57,413 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:50:57,413 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:50:57,413 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:50:57,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:50:57,744 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:57,745 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:50:57,745 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:50:57,754 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:50:57,754 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:50:57,965 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2018-09-14 15:50:57,965 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:50:57,967 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:50:57,999 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:57,999 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:50:58,445 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:58,467 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:50:58,467 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:50:58,483 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:50:58,483 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:50:59,557 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2018-09-14 15:50:59,557 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:50:59,561 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:50:59,575 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:59,575 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:50:59,590 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:50:59,591 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:50:59,592 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 28 [2018-09-14 15:50:59,592 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:50:59,592 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-09-14 15:50:59,592 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-09-14 15:50:59,593 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-09-14 15:50:59,593 INFO L87 Difference]: Start difference. First operand 42 states and 43 transitions. Second operand 15 states. [2018-09-14 15:51:00,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:00,413 INFO L93 Difference]: Finished difference Result 107 states and 122 transitions. [2018-09-14 15:51:00,416 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-09-14 15:51:00,416 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 38 [2018-09-14 15:51:00,416 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:00,417 INFO L225 Difference]: With dead ends: 107 [2018-09-14 15:51:00,417 INFO L226 Difference]: Without dead ends: 96 [2018-09-14 15:51:00,418 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 165 GetRequests, 137 SyntacticMatches, 2 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-09-14 15:51:00,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-09-14 15:51:00,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 44. [2018-09-14 15:51:00,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2018-09-14 15:51:00,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 45 transitions. [2018-09-14 15:51:00,425 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 45 transitions. Word has length 38 [2018-09-14 15:51:00,426 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:00,426 INFO L480 AbstractCegarLoop]: Abstraction has 44 states and 45 transitions. [2018-09-14 15:51:00,426 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-09-14 15:51:00,426 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 45 transitions. [2018-09-14 15:51:00,427 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-09-14 15:51:00,427 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:00,427 INFO L376 BasicCegarLoop]: trace histogram [14, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:00,427 INFO L423 AbstractCegarLoop]: === Iteration 14 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:00,427 INFO L82 PathProgramCache]: Analyzing trace with hash -1472748184, now seen corresponding path program 12 times [2018-09-14 15:51:00,427 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:00,428 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:00,428 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:00,428 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:00,428 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:00,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:00,783 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:00,783 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:00,783 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:00,792 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:51:00,792 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:51:01,075 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 14 check-sat command(s) [2018-09-14 15:51:01,075 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:01,079 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:01,107 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:01,107 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:01,712 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:01,732 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:01,732 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:01,747 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:51:01,747 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:51:16,482 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 14 check-sat command(s) [2018-09-14 15:51:16,482 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:16,488 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:16,507 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:16,507 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:16,520 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:16,522 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:16,523 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 30 [2018-09-14 15:51:16,523 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:16,523 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-09-14 15:51:16,524 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-09-14 15:51:16,525 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-09-14 15:51:16,525 INFO L87 Difference]: Start difference. First operand 44 states and 45 transitions. Second operand 16 states. [2018-09-14 15:51:17,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:17,192 INFO L93 Difference]: Finished difference Result 113 states and 129 transitions. [2018-09-14 15:51:17,194 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-09-14 15:51:17,194 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 40 [2018-09-14 15:51:17,194 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:17,195 INFO L225 Difference]: With dead ends: 113 [2018-09-14 15:51:17,195 INFO L226 Difference]: Without dead ends: 102 [2018-09-14 15:51:17,196 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 174 GetRequests, 144 SyntacticMatches, 2 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-09-14 15:51:17,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states. [2018-09-14 15:51:17,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 46. [2018-09-14 15:51:17,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-09-14 15:51:17,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 47 transitions. [2018-09-14 15:51:17,202 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 47 transitions. Word has length 40 [2018-09-14 15:51:17,203 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:17,203 INFO L480 AbstractCegarLoop]: Abstraction has 46 states and 47 transitions. [2018-09-14 15:51:17,203 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-09-14 15:51:17,203 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 47 transitions. [2018-09-14 15:51:17,203 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-09-14 15:51:17,204 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:17,204 INFO L376 BasicCegarLoop]: trace histogram [15, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:17,204 INFO L423 AbstractCegarLoop]: === Iteration 15 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:17,204 INFO L82 PathProgramCache]: Analyzing trace with hash 2075368098, now seen corresponding path program 13 times [2018-09-14 15:51:17,204 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:17,205 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:17,205 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:17,205 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:17,205 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:17,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:18,430 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:18,430 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:18,430 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:18,439 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:18,439 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:51:18,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:18,458 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:18,483 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:18,483 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:19,137 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:19,158 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:19,158 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:19,173 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:19,173 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-09-14 15:51:19,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:19,278 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:19,292 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:19,292 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:19,298 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:19,300 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:19,301 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 32 [2018-09-14 15:51:19,301 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:19,301 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-09-14 15:51:19,301 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-09-14 15:51:19,302 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-09-14 15:51:19,302 INFO L87 Difference]: Start difference. First operand 46 states and 47 transitions. Second operand 17 states. [2018-09-14 15:51:20,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:20,228 INFO L93 Difference]: Finished difference Result 119 states and 136 transitions. [2018-09-14 15:51:20,228 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-09-14 15:51:20,228 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 42 [2018-09-14 15:51:20,228 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:20,229 INFO L225 Difference]: With dead ends: 119 [2018-09-14 15:51:20,229 INFO L226 Difference]: Without dead ends: 108 [2018-09-14 15:51:20,230 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 183 GetRequests, 151 SyntacticMatches, 2 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-09-14 15:51:20,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108 states. [2018-09-14 15:51:20,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108 to 48. [2018-09-14 15:51:20,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-09-14 15:51:20,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 49 transitions. [2018-09-14 15:51:20,237 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 49 transitions. Word has length 42 [2018-09-14 15:51:20,237 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:20,237 INFO L480 AbstractCegarLoop]: Abstraction has 48 states and 49 transitions. [2018-09-14 15:51:20,237 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-09-14 15:51:20,237 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 49 transitions. [2018-09-14 15:51:20,238 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-09-14 15:51:20,238 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:20,238 INFO L376 BasicCegarLoop]: trace histogram [16, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:20,238 INFO L423 AbstractCegarLoop]: === Iteration 16 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:20,239 INFO L82 PathProgramCache]: Analyzing trace with hash 1611082076, now seen corresponding path program 14 times [2018-09-14 15:51:20,239 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:20,239 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:20,240 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-09-14 15:51:20,240 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:20,240 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:20,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:21,265 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:21,265 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:21,266 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:21,278 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:51:21,278 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:51:21,302 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:51:21,302 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:21,303 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:21,321 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:21,321 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:22,017 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:22,038 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:22,038 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:22,053 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-09-14 15:51:22,053 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:51:22,145 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-09-14 15:51:22,145 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:22,150 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:22,183 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:22,184 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:22,241 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (29)] Exception during sending of exit command (exit): Broken pipe [2018-09-14 15:51:22,243 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:51:22,243 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 34 [2018-09-14 15:51:22,243 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:51:22,244 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-09-14 15:51:22,244 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-09-14 15:51:22,244 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-09-14 15:51:22,245 INFO L87 Difference]: Start difference. First operand 48 states and 49 transitions. Second operand 18 states. [2018-09-14 15:51:23,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:51:23,192 INFO L93 Difference]: Finished difference Result 125 states and 143 transitions. [2018-09-14 15:51:23,192 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-09-14 15:51:23,192 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 44 [2018-09-14 15:51:23,193 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:51:23,194 INFO L225 Difference]: With dead ends: 125 [2018-09-14 15:51:23,194 INFO L226 Difference]: Without dead ends: 114 [2018-09-14 15:51:23,196 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 192 GetRequests, 158 SyntacticMatches, 2 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-09-14 15:51:23,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-09-14 15:51:23,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 50. [2018-09-14 15:51:23,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-09-14 15:51:23,201 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 51 transitions. [2018-09-14 15:51:23,201 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 51 transitions. Word has length 44 [2018-09-14 15:51:23,201 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:51:23,202 INFO L480 AbstractCegarLoop]: Abstraction has 50 states and 51 transitions. [2018-09-14 15:51:23,202 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-09-14 15:51:23,202 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 51 transitions. [2018-09-14 15:51:23,203 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-09-14 15:51:23,203 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:51:23,203 INFO L376 BasicCegarLoop]: trace histogram [17, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:51:23,203 INFO L423 AbstractCegarLoop]: === Iteration 17 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:51:23,203 INFO L82 PathProgramCache]: Analyzing trace with hash 2108813718, now seen corresponding path program 15 times [2018-09-14 15:51:23,203 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:51:23,204 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:23,204 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:51:23,204 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:51:23,205 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:51:23,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:51:23,506 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:23,506 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:23,506 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:51:23,513 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:51:23,513 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:51:32,863 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 17 check-sat command(s) [2018-09-14 15:51:32,864 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:51:32,891 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:51:32,905 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:32,905 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:51:33,665 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:51:33,686 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:51:33,686 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:51:33,701 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-09-14 15:51:33,701 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-09-14 15:52:52,847 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 17 check-sat command(s) [2018-09-14 15:52:52,847 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:52,854 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:52,879 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:52,879 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:52,903 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:52,906 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:52,906 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 36 [2018-09-14 15:52:52,906 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:52,907 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-09-14 15:52:52,907 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-09-14 15:52:52,908 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-09-14 15:52:52,908 INFO L87 Difference]: Start difference. First operand 50 states and 51 transitions. Second operand 19 states. [2018-09-14 15:52:53,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:53,833 INFO L93 Difference]: Finished difference Result 131 states and 150 transitions. [2018-09-14 15:52:53,834 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-09-14 15:52:53,834 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 46 [2018-09-14 15:52:53,834 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:53,836 INFO L225 Difference]: With dead ends: 131 [2018-09-14 15:52:53,836 INFO L226 Difference]: Without dead ends: 120 [2018-09-14 15:52:53,837 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 201 GetRequests, 165 SyntacticMatches, 2 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-09-14 15:52:53,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states. [2018-09-14 15:52:53,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 52. [2018-09-14 15:52:53,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. [2018-09-14 15:52:53,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 53 transitions. [2018-09-14 15:52:53,844 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 53 transitions. Word has length 46 [2018-09-14 15:52:53,844 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:53,844 INFO L480 AbstractCegarLoop]: Abstraction has 52 states and 53 transitions. [2018-09-14 15:52:53,844 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-09-14 15:52:53,845 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 53 transitions. [2018-09-14 15:52:53,845 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-09-14 15:52:53,846 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:53,846 INFO L376 BasicCegarLoop]: trace histogram [18, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:53,846 INFO L423 AbstractCegarLoop]: === Iteration 18 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:53,846 INFO L82 PathProgramCache]: Analyzing trace with hash -607415472, now seen corresponding path program 16 times [2018-09-14 15:52:53,846 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:53,847 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:53,847 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:53,847 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:53,848 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:53,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:54,249 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:54,250 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:54,250 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:54,258 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:54,258 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:54,284 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:54,284 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:54,286 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:54,296 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:54,296 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:55,180 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:55,200 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:55,200 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:55,217 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-09-14 15:52:55,218 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-09-14 15:52:55,358 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-09-14 15:52:55,358 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:55,363 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:55,372 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:55,372 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:55,400 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:55,402 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:52:55,402 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 38 [2018-09-14 15:52:55,402 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:52:55,403 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-09-14 15:52:55,403 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-09-14 15:52:55,404 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-09-14 15:52:55,404 INFO L87 Difference]: Start difference. First operand 52 states and 53 transitions. Second operand 20 states. [2018-09-14 15:52:56,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:52:56,562 INFO L93 Difference]: Finished difference Result 137 states and 157 transitions. [2018-09-14 15:52:56,563 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-09-14 15:52:56,563 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 48 [2018-09-14 15:52:56,563 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:52:56,565 INFO L225 Difference]: With dead ends: 137 [2018-09-14 15:52:56,565 INFO L226 Difference]: Without dead ends: 126 [2018-09-14 15:52:56,566 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 210 GetRequests, 172 SyntacticMatches, 2 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-09-14 15:52:56,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-09-14 15:52:56,574 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 54. [2018-09-14 15:52:56,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-09-14 15:52:56,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 55 transitions. [2018-09-14 15:52:56,578 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 55 transitions. Word has length 48 [2018-09-14 15:52:56,578 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:52:56,578 INFO L480 AbstractCegarLoop]: Abstraction has 54 states and 55 transitions. [2018-09-14 15:52:56,578 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-09-14 15:52:56,578 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 55 transitions. [2018-09-14 15:52:56,579 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-09-14 15:52:56,579 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:52:56,579 INFO L376 BasicCegarLoop]: trace histogram [19, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:52:56,579 INFO L423 AbstractCegarLoop]: === Iteration 19 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:52:56,580 INFO L82 PathProgramCache]: Analyzing trace with hash 436448906, now seen corresponding path program 17 times [2018-09-14 15:52:56,580 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:52:56,583 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:56,584 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:52:56,584 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:52:56,584 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:52:56,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:52:57,187 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:57,187 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:57,187 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:52:57,196 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:57,196 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:52:58,589 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2018-09-14 15:52:58,590 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:52:58,592 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:52:58,600 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:58,600 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:52:59,808 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:52:59,829 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:52:59,830 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:52:59,846 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-09-14 15:52:59,847 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-09-14 15:53:06,167 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2018-09-14 15:53:06,167 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:06,174 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:06,187 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:53:06,187 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:06,200 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:53:06,202 INFO L313 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-09-14 15:53:06,202 INFO L328 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 40 [2018-09-14 15:53:06,203 INFO L258 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-09-14 15:53:06,203 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-09-14 15:53:06,204 INFO L147 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-09-14 15:53:06,205 INFO L148 InterpolantAutomaton]: CoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-09-14 15:53:06,205 INFO L87 Difference]: Start difference. First operand 54 states and 55 transitions. Second operand 21 states. [2018-09-14 15:53:07,401 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-09-14 15:53:07,401 INFO L93 Difference]: Finished difference Result 143 states and 164 transitions. [2018-09-14 15:53:07,401 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-09-14 15:53:07,401 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 50 [2018-09-14 15:53:07,402 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-09-14 15:53:07,403 INFO L225 Difference]: With dead ends: 143 [2018-09-14 15:53:07,403 INFO L226 Difference]: Without dead ends: 132 [2018-09-14 15:53:07,404 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 219 GetRequests, 179 SyntacticMatches, 2 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-09-14 15:53:07,404 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-09-14 15:53:07,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 56. [2018-09-14 15:53:07,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56 states. [2018-09-14 15:53:07,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 57 transitions. [2018-09-14 15:53:07,410 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 57 transitions. Word has length 50 [2018-09-14 15:53:07,410 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-09-14 15:53:07,410 INFO L480 AbstractCegarLoop]: Abstraction has 56 states and 57 transitions. [2018-09-14 15:53:07,410 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-09-14 15:53:07,410 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 57 transitions. [2018-09-14 15:53:07,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-09-14 15:53:07,411 INFO L368 BasicCegarLoop]: Found error trace [2018-09-14 15:53:07,411 INFO L376 BasicCegarLoop]: trace histogram [20, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-09-14 15:53:07,411 INFO L423 AbstractCegarLoop]: === Iteration 20 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-09-14 15:53:07,411 INFO L82 PathProgramCache]: Analyzing trace with hash -1432231100, now seen corresponding path program 18 times [2018-09-14 15:53:07,412 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-09-14 15:53:07,412 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:07,412 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-09-14 15:53:07,412 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-09-14 15:53:07,413 INFO L295 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-09-14 15:53:07,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-09-14 15:53:07,806 INFO L134 CoverageAnalysis]: Checked inductivity of 380 backedges. 0 proven. 380 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:53:07,807 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:53:07,807 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-09-14 15:53:07,814 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:53:07,815 INFO L295 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-09-14 15:53:32,779 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 20 check-sat command(s) [2018-09-14 15:53:32,779 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-09-14 15:53:32,791 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-09-14 15:53:32,861 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-09-14 15:53:32,861 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:32,867 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-09-14 15:53:32,867 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-09-14 15:53:32,995 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-09-14 15:53:32,995 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:33,002 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-09-14 15:53:33,003 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:15, output treesize:9 [2018-09-14 15:53:33,053 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-09-14 15:53:33,053 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:33,075 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-09-14 15:53:33,075 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:15, output treesize:9 [2018-09-14 15:53:33,120 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-09-14 15:53:33,121 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:33,127 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-09-14 15:53:33,128 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:15, output treesize:9 [2018-09-14 15:53:33,157 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-09-14 15:53:33,157 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:33,160 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-09-14 15:53:33,160 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:12, output treesize:5 [2018-09-14 15:53:33,529 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 16 treesize of output 23 [2018-09-14 15:53:33,530 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 2 xjuncts. [2018-09-14 15:53:33,546 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-09-14 15:53:33,547 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:23, output treesize:29 [2018-09-14 15:53:33,618 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2018-09-14 15:53:33,619 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:33,682 INFO L700 Elim1Store]: detected not equals via solver [2018-09-14 15:53:33,684 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 37 [2018-09-14 15:53:33,685 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:33,717 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-09-14 15:53:33,717 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:56, output treesize:29 [2018-09-14 15:53:33,824 INFO L700 Elim1Store]: detected not equals via solver [2018-09-14 15:53:33,826 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 45 [2018-09-14 15:53:33,826 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:33,863 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 17 [2018-09-14 15:53:33,863 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:33,887 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-09-14 15:53:33,887 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:64, output treesize:37 [2018-09-14 15:53:34,078 INFO L700 Elim1Store]: detected not equals via solver [2018-09-14 15:53:34,080 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 53 [2018-09-14 15:53:34,081 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:34,128 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 17 [2018-09-14 15:53:34,129 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:34,171 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-09-14 15:53:34,172 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:72, output treesize:45 [2018-09-14 15:53:34,364 INFO L700 Elim1Store]: detected not equals via solver [2018-09-14 15:53:34,367 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 54 treesize of output 61 [2018-09-14 15:53:34,368 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:34,435 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 17 [2018-09-14 15:53:34,436 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:34,488 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-09-14 15:53:34,488 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:80, output treesize:53 [2018-09-14 15:53:34,703 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2018-09-14 15:53:34,704 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:34,804 INFO L700 Elim1Store]: detected not equals via solver [2018-09-14 15:53:34,808 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 62 treesize of output 69 [2018-09-14 15:53:34,809 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:34,913 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-09-14 15:53:34,913 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:88, output treesize:61 [2018-09-14 15:53:35,198 INFO L700 Elim1Store]: detected not equals via solver [2018-09-14 15:53:35,203 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 70 treesize of output 77 [2018-09-14 15:53:35,204 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:35,343 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 17 [2018-09-14 15:53:35,343 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:35,466 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-09-14 15:53:35,467 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:96, output treesize:69 [2018-09-14 15:53:35,809 INFO L700 Elim1Store]: detected not equals via solver [2018-09-14 15:53:35,817 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 78 treesize of output 85 [2018-09-14 15:53:35,818 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:36,057 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 17 [2018-09-14 15:53:36,057 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:36,227 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-09-14 15:53:36,227 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:104, output treesize:77 [2018-09-14 15:53:36,864 WARN L178 SmtUtils]: Spent 145.00 ms on a formula simplification that was a NOOP. DAG size: 49 [2018-09-14 15:53:36,878 INFO L700 Elim1Store]: detected not equals via solver [2018-09-14 15:53:36,887 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 79 treesize of output 86 [2018-09-14 15:53:36,888 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:37,131 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 17 [2018-09-14 15:53:37,131 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:37,397 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-09-14 15:53:37,397 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:98, output treesize:77 [2018-09-14 15:53:38,011 WARN L178 SmtUtils]: Spent 160.00 ms on a formula simplification that was a NOOP. DAG size: 49 [2018-09-14 15:53:38,025 INFO L700 Elim1Store]: detected not equals via solver [2018-09-14 15:53:38,035 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 79 treesize of output 86 [2018-09-14 15:53:38,035 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:38,266 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 17 [2018-09-14 15:53:38,266 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:39,254 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-09-14 15:53:39,254 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:98, output treesize:77 [2018-09-14 15:53:41,958 WARN L178 SmtUtils]: Spent 133.00 ms on a formula simplification that was a NOOP. DAG size: 49 [2018-09-14 15:53:41,973 INFO L700 Elim1Store]: detected not equals via solver [2018-09-14 15:53:41,985 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 79 treesize of output 86 [2018-09-14 15:53:41,985 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:42,221 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 17 [2018-09-14 15:53:42,221 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:42,441 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-09-14 15:53:42,441 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:98, output treesize:77 [2018-09-14 15:53:43,398 WARN L178 SmtUtils]: Spent 230.00 ms on a formula simplification that was a NOOP. DAG size: 49 [2018-09-14 15:53:43,404 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 17 [2018-09-14 15:53:43,404 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:45,694 INFO L700 Elim1Store]: detected not equals via solver [2018-09-14 15:53:45,703 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 79 treesize of output 86 [2018-09-14 15:53:45,704 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:45,885 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-09-14 15:53:45,885 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:98, output treesize:77 [2018-09-14 15:53:46,866 WARN L178 SmtUtils]: Spent 266.00 ms on a formula simplification that was a NOOP. DAG size: 49 [2018-09-14 15:53:46,872 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 17 [2018-09-14 15:53:46,873 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:47,071 INFO L700 Elim1Store]: detected not equals via solver [2018-09-14 15:53:47,085 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 79 treesize of output 86 [2018-09-14 15:53:47,086 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:47,272 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-09-14 15:53:47,273 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:98, output treesize:77 [2018-09-14 15:53:47,779 WARN L178 SmtUtils]: Spent 151.00 ms on a formula simplification that was a NOOP. DAG size: 49 [2018-09-14 15:53:47,793 INFO L700 Elim1Store]: detected not equals via solver [2018-09-14 15:53:47,801 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 79 treesize of output 86 [2018-09-14 15:53:47,802 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:47,994 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 17 [2018-09-14 15:53:47,995 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-09-14 15:53:48,228 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-09-14 15:53:48,229 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:98, output treesize:77 [2018-09-14 15:53:51,661 WARN L178 SmtUtils]: Spent 2.14 s on a formula simplification that was a NOOP. DAG size: 49 [2018-09-14 15:53:51,987 INFO L134 CoverageAnalysis]: Checked inductivity of 380 backedges. 0 proven. 380 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:53:51,988 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-09-14 15:53:55,242 WARN L178 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 53 [2018-09-14 15:53:56,386 WARN L178 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 58 [2018-09-14 15:53:57,034 WARN L178 SmtUtils]: Spent 120.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 63 [2018-09-14 15:53:57,937 WARN L178 SmtUtils]: Spent 169.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 68 [2018-09-14 15:53:58,915 WARN L178 SmtUtils]: Spent 156.00 ms on a formula simplification. DAG size of input: 74 DAG size of output: 73 [2018-09-14 15:54:00,172 WARN L178 SmtUtils]: Spent 215.00 ms on a formula simplification. DAG size of input: 79 DAG size of output: 78 [2018-09-14 15:54:02,613 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 44 [2018-09-14 15:54:02,637 INFO L682 Elim1Store]: detected equality via solver [2018-09-14 15:54:02,640 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 56 [2018-09-14 15:54:02,644 INFO L682 Elim1Store]: detected equality via solver [2018-09-14 15:54:02,645 INFO L682 Elim1Store]: detected equality via solver [2018-09-14 15:54:02,652 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 79 [2018-09-14 15:54:02,657 INFO L682 Elim1Store]: detected equality via solver [2018-09-14 15:54:02,658 INFO L682 Elim1Store]: detected equality via solver [2018-09-14 15:54:02,658 INFO L682 Elim1Store]: detected equality via solver [2018-09-14 15:54:02,675 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 50 treesize of output 113 [2018-09-14 15:54:02,761 WARN L307 Elim1Store]: Array PQE input equivalent to true [2018-09-14 15:54:02,761 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-09-14 15:54:02,766 INFO L682 Elim1Store]: detected equality via solver [2018-09-14 15:54:02,767 INFO L682 Elim1Store]: detected equality via solver [2018-09-14 15:54:02,767 INFO L682 Elim1Store]: detected equality via solver [2018-09-14 15:54:02,768 INFO L682 Elim1Store]: detected equality via solver [2018-09-14 15:54:02,775 INFO L682 Elim1Store]: detected equality via solver [2018-09-14 15:54:02,813 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 8 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 46 treesize of output 102 [2018-09-14 15:54:02,815 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 4 xjuncts. [2018-09-14 15:54:02,938 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 3 xjuncts. [2018-09-14 15:54:02,969 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 3 xjuncts. [2018-09-14 15:54:02,995 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 3 xjuncts. [2018-09-14 15:54:03,017 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 3 xjuncts. [2018-09-14 15:54:03,049 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 1 dim-1 vars, End of recursive call: and 3 xjuncts. [2018-09-14 15:54:03,049 INFO L202 ElimStorePlain]: Needed 7 recursive calls to eliminate 5 variables, input treesize:55, output treesize:75 [2018-09-14 15:54:03,702 INFO L134 CoverageAnalysis]: Checked inductivity of 380 backedges. 10 proven. 370 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-09-14 15:54:03,723 INFO L301 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-09-14 15:54:03,723 INFO L197 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-09-14 15:54:03,738 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-09-14 15:54:03,738 INFO L295 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) Received shutdown request... Cannot interrupt operation gracefully because timeout expired. Forcing shutdown