/root/.sdkman/candidates/java/21.0.5-tem/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata ./data -s ../../../trunk/examples/settings/buchiAutomizer/concurrent-automaton-noLbe.epf -tc ../../../trunk/examples/toolchains/BuchiAutomizerBplInline.xml -i ../../../trunk/examples/concurrent/bpl/regression/ForkInLoop02-Incrementer.bpl -------------------------------------------------------------------------------- This is Ultimate 0.3.0-wip.dk.ample-buchi-a4216cd-m [2025-04-26 16:20:10,987 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-04-26 16:20:11,036 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/../../../trunk/examples/settings/buchiAutomizer/concurrent-automaton-noLbe.epf [2025-04-26 16:20:11,040 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-04-26 16:20:11,040 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-04-26 16:20:11,062 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-04-26 16:20:11,062 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-04-26 16:20:11,062 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-04-26 16:20:11,063 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-04-26 16:20:11,063 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-04-26 16:20:11,063 INFO L153 SettingsManager]: * Use SBE=true [2025-04-26 16:20:11,063 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-04-26 16:20:11,063 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-04-26 16:20:11,063 INFO L153 SettingsManager]: * Use old map elimination=false [2025-04-26 16:20:11,063 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-04-26 16:20:11,063 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-04-26 16:20:11,063 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-04-26 16:20:11,063 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-04-26 16:20:11,063 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-04-26 16:20:11,063 INFO L153 SettingsManager]: * sizeof long=4 [2025-04-26 16:20:11,064 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-04-26 16:20:11,064 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-04-26 16:20:11,064 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-04-26 16:20:11,064 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-04-26 16:20:11,064 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-04-26 16:20:11,064 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-04-26 16:20:11,064 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-04-26 16:20:11,064 INFO L153 SettingsManager]: * sizeof long double=12 [2025-04-26 16:20:11,064 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-04-26 16:20:11,064 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-04-26 16:20:11,064 INFO L153 SettingsManager]: * Use constant arrays=true [2025-04-26 16:20:11,064 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2025-04-26 16:20:11,064 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-04-26 16:20:11,065 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-04-26 16:20:11,065 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-04-26 16:20:11,065 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-04-26 16:20:11,065 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR [2025-04-26 16:20:11,288 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-04-26 16:20:11,295 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-04-26 16:20:11,297 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-04-26 16:20:11,298 INFO L270 PluginConnector]: Initializing Boogie PL CUP Parser... [2025-04-26 16:20:11,298 INFO L274 PluginConnector]: Boogie PL CUP Parser initialized [2025-04-26 16:20:11,300 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/../../../trunk/examples/concurrent/bpl/regression/ForkInLoop02-Incrementer.bpl [2025-04-26 16:20:11,300 INFO L110 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/../../../trunk/examples/concurrent/bpl/regression/ForkInLoop02-Incrementer.bpl' [2025-04-26 16:20:11,311 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-04-26 16:20:11,311 INFO L133 ToolchainWalker]: Walking toolchain with 4 elements. [2025-04-26 16:20:11,312 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-04-26 16:20:11,312 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-04-26 16:20:11,312 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-04-26 16:20:11,318 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "ForkInLoop02-Incrementer.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 04:20:11" (1/1) ... [2025-04-26 16:20:11,333 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "ForkInLoop02-Incrementer.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 04:20:11" (1/1) ... [2025-04-26 16:20:11,337 INFO L138 Inliner]: procedures = 2, calls = 1, calls flagged for inlining = 0, calls inlined = 0, statements flattened = 0 [2025-04-26 16:20:11,338 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-04-26 16:20:11,339 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-04-26 16:20:11,339 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-04-26 16:20:11,339 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-04-26 16:20:11,344 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "ForkInLoop02-Incrementer.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 04:20:11" (1/1) ... [2025-04-26 16:20:11,344 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "ForkInLoop02-Incrementer.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 04:20:11" (1/1) ... [2025-04-26 16:20:11,344 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "ForkInLoop02-Incrementer.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 04:20:11" (1/1) ... [2025-04-26 16:20:11,344 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "ForkInLoop02-Incrementer.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 04:20:11" (1/1) ... [2025-04-26 16:20:11,346 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "ForkInLoop02-Incrementer.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 04:20:11" (1/1) ... [2025-04-26 16:20:11,347 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "ForkInLoop02-Incrementer.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 04:20:11" (1/1) ... [2025-04-26 16:20:11,348 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "ForkInLoop02-Incrementer.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 04:20:11" (1/1) ... [2025-04-26 16:20:11,348 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "ForkInLoop02-Incrementer.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 04:20:11" (1/1) ... [2025-04-26 16:20:11,349 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "ForkInLoop02-Incrementer.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 04:20:11" (1/1) ... [2025-04-26 16:20:11,358 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-04-26 16:20:11,359 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2025-04-26 16:20:11,359 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2025-04-26 16:20:11,359 INFO L274 PluginConnector]: RCFGBuilder initialized [2025-04-26 16:20:11,359 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "ForkInLoop02-Incrementer.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 04:20:11" (1/1) ... [2025-04-26 16:20:11,363 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 16:20:11,370 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 16:20:11,379 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 16:20:11,381 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-04-26 16:20:11,400 INFO L124 BoogieDeclarations]: Specification and implementation of procedure foo given in one single declaration [2025-04-26 16:20:11,401 INFO L130 BoogieDeclarations]: Found specification of procedure foo [2025-04-26 16:20:11,401 INFO L138 BoogieDeclarations]: Found implementation of procedure foo [2025-04-26 16:20:11,401 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-04-26 16:20:11,401 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-04-26 16:20:11,402 WARN L203 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to OneNontrivialStatement. [2025-04-26 16:20:11,433 INFO L234 CfgBuilder]: Building ICFG [2025-04-26 16:20:11,435 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2025-04-26 16:20:11,474 INFO L279 CfgBuilder]: Omitted future-live optimization because the input is a concurrent program. [2025-04-26 16:20:11,474 INFO L283 CfgBuilder]: Performing block encoding [2025-04-26 16:20:11,481 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-04-26 16:20:11,481 INFO L312 CfgBuilder]: Removed 1 assume(true) statements. [2025-04-26 16:20:11,481 INFO L201 PluginConnector]: Adding new model ForkInLoop02-Incrementer.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.04 04:20:11 BoogieIcfgContainer [2025-04-26 16:20:11,481 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2025-04-26 16:20:11,482 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-04-26 16:20:11,482 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-04-26 16:20:11,487 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-04-26 16:20:11,488 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-04-26 16:20:11,488 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "ForkInLoop02-Incrementer.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 04:20:11" (1/2) ... [2025-04-26 16:20:11,489 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3434a8df and model type ForkInLoop02-Incrementer.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.04 04:20:11, skipping insertion in model container [2025-04-26 16:20:11,489 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-04-26 16:20:11,489 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "ForkInLoop02-Incrementer.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.04 04:20:11" (2/2) ... [2025-04-26 16:20:11,490 INFO L376 chiAutomizerObserver]: Analyzing ICFG ForkInLoop02-Incrementer.bpl [2025-04-26 16:20:11,515 INFO L143 ThreadInstanceAdder]: Constructed 0 joinOtherThreadTransitions. [2025-04-26 16:20:11,543 INFO L73 FinitePrefix]: Start finitePrefix. Operand has 13 places, 11 transitions, 26 flow [2025-04-26 16:20:11,556 INFO L116 PetriNetUnfolderBase]: 1/12 cut-off events. [2025-04-26 16:20:11,557 INFO L117 PetriNetUnfolderBase]: For 0/0 co-relation queries the response was YES. [2025-04-26 16:20:11,559 INFO L83 FinitePrefix]: Finished finitePrefix Result has 16 conditions, 12 events. 1/12 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 4. Compared 11 event pairs, 0 based on Foata normal form. 0/11 useless extension candidates. Maximal degree in co-relation 4. Up to 2 conditions per place. [2025-04-26 16:20:11,560 INFO L82 GeneralOperation]: Start removeDead. Operand has 13 places, 11 transitions, 26 flow [2025-04-26 16:20:11,565 INFO L88 GeneralOperation]: Finished RemoveDead, result has has 13 places, 11 transitions, 26 flow [2025-04-26 16:20:11,565 INFO L84 lAbstractionProvider]: Constructed initial Petri net abstraction that has has 13 places, 11 transitions, 26 flow [2025-04-26 16:20:11,574 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-04-26 16:20:11,574 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-04-26 16:20:11,574 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-04-26 16:20:11,574 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-04-26 16:20:11,574 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-04-26 16:20:11,574 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-04-26 16:20:11,575 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-04-26 16:20:11,575 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-04-26 16:20:11,576 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand currently 0 states, but on-demand construction may add more states [2025-04-26 16:20:11,599 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 5 [2025-04-26 16:20:11,599 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 16:20:11,599 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 16:20:11,606 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2025-04-26 16:20:11,606 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-04-26 16:20:11,606 INFO L340 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-04-26 16:20:11,606 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand currently 23 states, but on-demand construction may add more states [2025-04-26 16:20:11,607 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 5 [2025-04-26 16:20:11,607 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 16:20:11,607 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 16:20:11,607 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2025-04-26 16:20:11,607 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-04-26 16:20:11,611 INFO L752 eck$LassoCheckResult]: Stem: "[18] $Ultimate##0-->L18: Formula: (= v_ULTIMATE.start_newid_1 0) InVars {} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_1} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[14] L18-->L20-1: Formula: (= v_n_5 0) InVars {} OutVars{n=v_n_5} AuxVars[] AssignedVars[n]" "[28] L20-1-->$Ultimate##0: Formula: (= v_fooThread1of1ForFork0_thidvar0_2 v_ULTIMATE.start_newid_5) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_5} OutVars{fooThread1of1ForFork0_thidvar0=v_fooThread1of1ForFork0_thidvar0_2, ULTIMATE.start_newid=v_ULTIMATE.start_newid_5} AuxVars[] AssignedVars[fooThread1of1ForFork0_thidvar0]" "[17] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[26] L20-1-->ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]" [2025-04-26 16:20:11,611 INFO L754 eck$LassoCheckResult]: Loop: "[27] ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES-->ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]" [2025-04-26 16:20:11,616 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 16:20:11,618 INFO L85 PathProgramCache]: Analyzing trace with hash 45697064, now seen corresponding path program 1 times [2025-04-26 16:20:11,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 16:20:11,623 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1622415218] [2025-04-26 16:20:11,623 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 16:20:11,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 16:20:11,663 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 16:20:11,670 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 16:20:11,670 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:11,671 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:11,671 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:11,672 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 16:20:11,674 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 16:20:11,674 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:11,674 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:11,681 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 16:20:11,683 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 16:20:11,683 INFO L85 PathProgramCache]: Analyzing trace with hash 58, now seen corresponding path program 1 times [2025-04-26 16:20:11,684 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 16:20:11,684 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1260868289] [2025-04-26 16:20:11,684 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 16:20:11,684 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 16:20:11,685 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-04-26 16:20:11,686 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-04-26 16:20:11,686 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:11,686 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:11,686 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:11,686 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-04-26 16:20:11,687 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-04-26 16:20:11,687 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:11,687 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:11,687 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 16:20:11,688 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 16:20:11,688 INFO L85 PathProgramCache]: Analyzing trace with hash 1416609011, now seen corresponding path program 1 times [2025-04-26 16:20:11,688 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 16:20:11,688 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1344443599] [2025-04-26 16:20:11,688 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 16:20:11,688 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 16:20:11,690 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-04-26 16:20:11,691 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-04-26 16:20:11,692 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:11,692 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:11,692 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:11,693 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-04-26 16:20:11,694 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-04-26 16:20:11,694 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:11,694 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:11,695 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 16:20:11,775 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 16:20:11,778 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 16:20:11,778 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:11,778 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:11,779 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:11,781 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 16:20:11,782 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 16:20:11,783 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:11,783 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:11,789 WARN L166 chiAutomizerObserver]: 1 thread instances were not sufficient, I will increase this number and restart the analysis [2025-04-26 16:20:11,793 INFO L143 ThreadInstanceAdder]: Constructed 0 joinOtherThreadTransitions. [2025-04-26 16:20:11,797 INFO L73 FinitePrefix]: Start finitePrefix. Operand has 20 places, 16 transitions, 42 flow [2025-04-26 16:20:11,804 INFO L116 PetriNetUnfolderBase]: 1/19 cut-off events. [2025-04-26 16:20:11,804 INFO L117 PetriNetUnfolderBase]: For 2/2 co-relation queries the response was YES. [2025-04-26 16:20:11,804 INFO L83 FinitePrefix]: Finished finitePrefix Result has 27 conditions, 19 events. 1/19 cut-off events. For 2/2 co-relation queries the response was YES. Maximal size of possible extension queue 4. Compared 24 event pairs, 0 based on Foata normal form. 0/17 useless extension candidates. Maximal degree in co-relation 14. Up to 3 conditions per place. [2025-04-26 16:20:11,804 INFO L82 GeneralOperation]: Start removeDead. Operand has 20 places, 16 transitions, 42 flow [2025-04-26 16:20:11,806 INFO L88 GeneralOperation]: Finished RemoveDead, result has has 20 places, 16 transitions, 42 flow [2025-04-26 16:20:11,806 INFO L84 lAbstractionProvider]: Constructed initial Petri net abstraction that has has 20 places, 16 transitions, 42 flow [2025-04-26 16:20:11,806 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-04-26 16:20:11,806 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-04-26 16:20:11,806 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-04-26 16:20:11,806 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-04-26 16:20:11,806 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-04-26 16:20:11,806 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-04-26 16:20:11,806 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-04-26 16:20:11,806 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-04-26 16:20:11,806 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand currently 0 states, but on-demand construction may add more states [2025-04-26 16:20:11,838 INFO L131 ngComponentsAnalysis]: Automaton has 25 accepting balls. 25 [2025-04-26 16:20:11,838 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 16:20:11,838 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 16:20:11,839 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1] [2025-04-26 16:20:11,839 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-04-26 16:20:11,839 INFO L340 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-04-26 16:20:11,839 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand currently 118 states, but on-demand construction may add more states [2025-04-26 16:20:11,849 INFO L131 ngComponentsAnalysis]: Automaton has 25 accepting balls. 25 [2025-04-26 16:20:11,849 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 16:20:11,849 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 16:20:11,850 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1] [2025-04-26 16:20:11,850 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-04-26 16:20:11,850 INFO L752 eck$LassoCheckResult]: Stem: "[34] $Ultimate##0-->L18: Formula: (= v_ULTIMATE.start_newid_1 0) InVars {} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_1} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[30] L18-->L20-1: Formula: (= v_n_5 0) InVars {} OutVars{n=v_n_5} AuxVars[] AssignedVars[n]" "[48] L20-1-->$Ultimate##0: Formula: (= v_ULTIMATE.start_newid_9 v_fooThread1of2ForFork0_thidvar0_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_9} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_9, fooThread1of2ForFork0_thidvar0=v_fooThread1of2ForFork0_thidvar0_2} AuxVars[] AssignedVars[fooThread1of2ForFork0_thidvar0]" "[33] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[49] L20-1-->$Ultimate##0: Formula: (= v_fooThread2of2ForFork0_thidvar0_2 v_ULTIMATE.start_newid_11) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_11} OutVars{fooThread2of2ForFork0_thidvar0=v_fooThread2of2ForFork0_thidvar0_2, ULTIMATE.start_newid=v_ULTIMATE.start_newid_11} AuxVars[] AssignedVars[fooThread2of2ForFork0_thidvar0]" "[33] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[46] L20-1-->ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]" [2025-04-26 16:20:11,850 INFO L754 eck$LassoCheckResult]: Loop: "[47] ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES-->ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]" [2025-04-26 16:20:11,852 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 16:20:11,852 INFO L85 PathProgramCache]: Analyzing trace with hash -1537568080, now seen corresponding path program 1 times [2025-04-26 16:20:11,852 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 16:20:11,852 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1568962622] [2025-04-26 16:20:11,852 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 16:20:11,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 16:20:11,855 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-04-26 16:20:11,860 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-04-26 16:20:11,861 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:11,861 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:11,861 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:11,862 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-04-26 16:20:11,866 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-04-26 16:20:11,866 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:11,866 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:11,867 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 16:20:11,868 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 16:20:11,868 INFO L85 PathProgramCache]: Analyzing trace with hash 78, now seen corresponding path program 1 times [2025-04-26 16:20:11,868 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 16:20:11,868 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1893500512] [2025-04-26 16:20:11,868 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 16:20:11,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 16:20:11,872 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-04-26 16:20:11,872 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-04-26 16:20:11,872 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:11,872 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:11,872 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:11,873 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-04-26 16:20:11,873 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-04-26 16:20:11,873 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:11,873 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:11,873 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 16:20:11,874 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 16:20:11,874 INFO L85 PathProgramCache]: Analyzing trace with hash -419970177, now seen corresponding path program 1 times [2025-04-26 16:20:11,874 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 16:20:11,874 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1708710861] [2025-04-26 16:20:11,874 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 16:20:11,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 16:20:11,879 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-04-26 16:20:11,883 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-04-26 16:20:11,885 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:11,885 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:11,885 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:11,886 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-04-26 16:20:11,889 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-04-26 16:20:11,889 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:11,890 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:11,891 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 16:20:11,949 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-04-26 16:20:11,951 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-04-26 16:20:11,951 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:11,951 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:11,951 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:11,956 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-04-26 16:20:11,957 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-04-26 16:20:11,957 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:11,957 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:11,960 WARN L166 chiAutomizerObserver]: 2 thread instances were not sufficient, I will increase this number and restart the analysis [2025-04-26 16:20:11,966 INFO L143 ThreadInstanceAdder]: Constructed 0 joinOtherThreadTransitions. [2025-04-26 16:20:11,973 INFO L73 FinitePrefix]: Start finitePrefix. Operand has 27 places, 21 transitions, 60 flow [2025-04-26 16:20:11,978 INFO L116 PetriNetUnfolderBase]: 1/26 cut-off events. [2025-04-26 16:20:11,978 INFO L117 PetriNetUnfolderBase]: For 7/7 co-relation queries the response was YES. [2025-04-26 16:20:11,978 INFO L83 FinitePrefix]: Finished finitePrefix Result has 39 conditions, 26 events. 1/26 cut-off events. For 7/7 co-relation queries the response was YES. Maximal size of possible extension queue 5. Compared 46 event pairs, 0 based on Foata normal form. 0/23 useless extension candidates. Maximal degree in co-relation 25. Up to 4 conditions per place. [2025-04-26 16:20:11,979 INFO L82 GeneralOperation]: Start removeDead. Operand has 27 places, 21 transitions, 60 flow [2025-04-26 16:20:11,979 INFO L88 GeneralOperation]: Finished RemoveDead, result has has 27 places, 21 transitions, 60 flow [2025-04-26 16:20:11,979 INFO L84 lAbstractionProvider]: Constructed initial Petri net abstraction that has has 27 places, 21 transitions, 60 flow [2025-04-26 16:20:11,980 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-04-26 16:20:11,980 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-04-26 16:20:11,980 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-04-26 16:20:11,980 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-04-26 16:20:11,980 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-04-26 16:20:11,980 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-04-26 16:20:11,980 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-04-26 16:20:11,980 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-04-26 16:20:11,980 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand currently 0 states, but on-demand construction may add more states [2025-04-26 16:20:12,099 INFO L131 ngComponentsAnalysis]: Automaton has 125 accepting balls. 125 [2025-04-26 16:20:12,100 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 16:20:12,100 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 16:20:12,100 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 1, 1, 1, 1, 1, 1] [2025-04-26 16:20:12,100 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-04-26 16:20:12,100 INFO L340 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-04-26 16:20:12,100 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand currently 593 states, but on-demand construction may add more states [2025-04-26 16:20:12,115 INFO L131 ngComponentsAnalysis]: Automaton has 125 accepting balls. 125 [2025-04-26 16:20:12,116 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 16:20:12,116 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 16:20:12,116 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 1, 1, 1, 1, 1, 1] [2025-04-26 16:20:12,116 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-04-26 16:20:12,117 INFO L752 eck$LassoCheckResult]: Stem: "[55] $Ultimate##0-->L18: Formula: (= v_ULTIMATE.start_newid_1 0) InVars {} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_1} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[51] L18-->L20-1: Formula: (= v_n_5 0) InVars {} OutVars{n=v_n_5} AuxVars[] AssignedVars[n]" "[73] L20-1-->$Ultimate##0: Formula: (= v_ULTIMATE.start_newid_16 v_fooThread1of3ForFork0_thidvar0_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_16} OutVars{fooThread1of3ForFork0_thidvar0=v_fooThread1of3ForFork0_thidvar0_2, ULTIMATE.start_newid=v_ULTIMATE.start_newid_16} AuxVars[] AssignedVars[fooThread1of3ForFork0_thidvar0]" "[54] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[74] L20-1-->$Ultimate##0: Formula: (= v_fooThread2of3ForFork0_thidvar0_2 v_ULTIMATE.start_newid_18) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_18} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_18, fooThread2of3ForFork0_thidvar0=v_fooThread2of3ForFork0_thidvar0_2} AuxVars[] AssignedVars[fooThread2of3ForFork0_thidvar0]" "[54] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[75] L20-1-->$Ultimate##0: Formula: (= v_fooThread3of3ForFork0_thidvar0_2 v_ULTIMATE.start_newid_20) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_20} OutVars{fooThread3of3ForFork0_thidvar0=v_fooThread3of3ForFork0_thidvar0_2, ULTIMATE.start_newid=v_ULTIMATE.start_newid_20} AuxVars[] AssignedVars[fooThread3of3ForFork0_thidvar0]" "[54] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[71] L20-1-->ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]" [2025-04-26 16:20:12,117 INFO L754 eck$LassoCheckResult]: Loop: "[72] ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES-->ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]" [2025-04-26 16:20:12,117 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 16:20:12,117 INFO L85 PathProgramCache]: Analyzing trace with hash -153990778, now seen corresponding path program 1 times [2025-04-26 16:20:12,117 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 16:20:12,117 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [870153732] [2025-04-26 16:20:12,117 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 16:20:12,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 16:20:12,122 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-04-26 16:20:12,124 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-04-26 16:20:12,124 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:12,124 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:12,124 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:12,127 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-04-26 16:20:12,134 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-04-26 16:20:12,134 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:12,134 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:12,135 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 16:20:12,135 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 16:20:12,135 INFO L85 PathProgramCache]: Analyzing trace with hash 103, now seen corresponding path program 1 times [2025-04-26 16:20:12,137 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 16:20:12,137 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [321957177] [2025-04-26 16:20:12,137 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 16:20:12,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 16:20:12,139 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-04-26 16:20:12,139 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-04-26 16:20:12,139 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:12,139 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:12,139 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:12,140 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-04-26 16:20:12,140 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-04-26 16:20:12,140 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:12,140 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:12,142 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 16:20:12,142 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 16:20:12,142 INFO L85 PathProgramCache]: Analyzing trace with hash -478746750, now seen corresponding path program 1 times [2025-04-26 16:20:12,142 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 16:20:12,142 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1559019811] [2025-04-26 16:20:12,142 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 16:20:12,142 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 16:20:12,146 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-04-26 16:20:12,149 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-04-26 16:20:12,149 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:12,149 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:12,149 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:12,150 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-04-26 16:20:12,154 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-04-26 16:20:12,154 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:12,154 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:12,155 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 16:20:12,219 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-04-26 16:20:12,221 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-04-26 16:20:12,221 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:12,221 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:12,221 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:12,223 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-04-26 16:20:12,225 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-04-26 16:20:12,226 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:12,226 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:12,229 WARN L166 chiAutomizerObserver]: 3 thread instances were not sufficient, I will increase this number and restart the analysis [2025-04-26 16:20:12,235 INFO L143 ThreadInstanceAdder]: Constructed 0 joinOtherThreadTransitions. [2025-04-26 16:20:12,240 INFO L73 FinitePrefix]: Start finitePrefix. Operand has 34 places, 26 transitions, 80 flow [2025-04-26 16:20:12,246 INFO L116 PetriNetUnfolderBase]: 1/33 cut-off events. [2025-04-26 16:20:12,246 INFO L117 PetriNetUnfolderBase]: For 16/16 co-relation queries the response was YES. [2025-04-26 16:20:12,246 INFO L83 FinitePrefix]: Finished finitePrefix Result has 52 conditions, 33 events. 1/33 cut-off events. For 16/16 co-relation queries the response was YES. Maximal size of possible extension queue 5. Compared 64 event pairs, 0 based on Foata normal form. 0/29 useless extension candidates. Maximal degree in co-relation 37. Up to 5 conditions per place. [2025-04-26 16:20:12,246 INFO L82 GeneralOperation]: Start removeDead. Operand has 34 places, 26 transitions, 80 flow [2025-04-26 16:20:12,246 INFO L88 GeneralOperation]: Finished RemoveDead, result has has 34 places, 26 transitions, 80 flow [2025-04-26 16:20:12,247 INFO L84 lAbstractionProvider]: Constructed initial Petri net abstraction that has has 34 places, 26 transitions, 80 flow [2025-04-26 16:20:12,247 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-04-26 16:20:12,247 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-04-26 16:20:12,247 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-04-26 16:20:12,247 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-04-26 16:20:12,247 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-04-26 16:20:12,247 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-04-26 16:20:12,247 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-04-26 16:20:12,247 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-04-26 16:20:12,247 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand currently 0 states, but on-demand construction may add more states [2025-04-26 16:20:12,476 INFO L131 ngComponentsAnalysis]: Automaton has 625 accepting balls. 625 [2025-04-26 16:20:12,476 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 16:20:12,477 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 16:20:12,479 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 1, 1, 1, 1, 1, 1, 1] [2025-04-26 16:20:12,479 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-04-26 16:20:12,479 INFO L340 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-04-26 16:20:12,479 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand currently 2968 states, but on-demand construction may add more states [2025-04-26 16:20:12,537 INFO L131 ngComponentsAnalysis]: Automaton has 625 accepting balls. 625 [2025-04-26 16:20:12,538 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 16:20:12,538 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 16:20:12,539 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 1, 1, 1, 1, 1, 1, 1] [2025-04-26 16:20:12,539 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-04-26 16:20:12,540 INFO L752 eck$LassoCheckResult]: Stem: "[81] $Ultimate##0-->L18: Formula: (= v_ULTIMATE.start_newid_1 0) InVars {} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_1} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[77] L18-->L20-1: Formula: (= v_n_5 0) InVars {} OutVars{n=v_n_5} AuxVars[] AssignedVars[n]" "[103] L20-1-->$Ultimate##0: Formula: (= v_ULTIMATE.start_newid_26 v_fooThread1of4ForFork0_thidvar0_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_26} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_26, fooThread1of4ForFork0_thidvar0=v_fooThread1of4ForFork0_thidvar0_2} AuxVars[] AssignedVars[fooThread1of4ForFork0_thidvar0]" "[80] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[104] L20-1-->$Ultimate##0: Formula: (= v_fooThread2of4ForFork0_thidvar0_2 v_ULTIMATE.start_newid_28) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_28} OutVars{fooThread2of4ForFork0_thidvar0=v_fooThread2of4ForFork0_thidvar0_2, ULTIMATE.start_newid=v_ULTIMATE.start_newid_28} AuxVars[] AssignedVars[fooThread2of4ForFork0_thidvar0]" "[80] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[105] L20-1-->$Ultimate##0: Formula: (= v_fooThread3of4ForFork0_thidvar0_2 v_ULTIMATE.start_newid_30) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_30} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_30, fooThread3of4ForFork0_thidvar0=v_fooThread3of4ForFork0_thidvar0_2} AuxVars[] AssignedVars[fooThread3of4ForFork0_thidvar0]" "[80] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[106] L20-1-->$Ultimate##0: Formula: (= v_fooThread4of4ForFork0_thidvar0_2 v_ULTIMATE.start_newid_32) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_32} OutVars{fooThread4of4ForFork0_thidvar0=v_fooThread4of4ForFork0_thidvar0_2, ULTIMATE.start_newid=v_ULTIMATE.start_newid_32} AuxVars[] AssignedVars[fooThread4of4ForFork0_thidvar0]" "[80] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[101] L20-1-->ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]" [2025-04-26 16:20:12,541 INFO L754 eck$LassoCheckResult]: Loop: "[102] ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES-->ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]" [2025-04-26 16:20:12,541 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 16:20:12,541 INFO L85 PathProgramCache]: Analyzing trace with hash -939178102, now seen corresponding path program 1 times [2025-04-26 16:20:12,541 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 16:20:12,541 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1381777283] [2025-04-26 16:20:12,541 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 16:20:12,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 16:20:12,544 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-04-26 16:20:12,549 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-04-26 16:20:12,549 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:12,549 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:12,549 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:12,550 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-04-26 16:20:12,552 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-04-26 16:20:12,552 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:12,552 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:12,554 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 16:20:12,554 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 16:20:12,554 INFO L85 PathProgramCache]: Analyzing trace with hash 133, now seen corresponding path program 1 times [2025-04-26 16:20:12,554 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 16:20:12,554 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [558167753] [2025-04-26 16:20:12,554 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 16:20:12,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 16:20:12,557 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-04-26 16:20:12,557 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-04-26 16:20:12,557 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:12,557 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:12,557 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:12,558 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-04-26 16:20:12,558 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-04-26 16:20:12,558 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:12,558 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:12,558 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 16:20:12,559 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 16:20:12,559 INFO L85 PathProgramCache]: Analyzing trace with hash 950250012, now seen corresponding path program 1 times [2025-04-26 16:20:12,559 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 16:20:12,559 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1321386049] [2025-04-26 16:20:12,559 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 16:20:12,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 16:20:12,562 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 12 statements into 1 equivalence classes. [2025-04-26 16:20:12,567 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 12 of 12 statements. [2025-04-26 16:20:12,567 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:12,567 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:12,567 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:12,568 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 12 statements into 1 equivalence classes. [2025-04-26 16:20:12,570 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 12 of 12 statements. [2025-04-26 16:20:12,570 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:12,570 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:12,571 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 16:20:12,644 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-04-26 16:20:12,646 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-04-26 16:20:12,646 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:12,646 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:12,647 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:12,650 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-04-26 16:20:12,653 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-04-26 16:20:12,653 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:12,653 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:12,660 WARN L166 chiAutomizerObserver]: 4 thread instances were not sufficient, I will increase this number and restart the analysis [2025-04-26 16:20:12,665 INFO L143 ThreadInstanceAdder]: Constructed 0 joinOtherThreadTransitions. [2025-04-26 16:20:12,668 INFO L73 FinitePrefix]: Start finitePrefix. Operand has 41 places, 31 transitions, 102 flow [2025-04-26 16:20:12,673 INFO L116 PetriNetUnfolderBase]: 1/40 cut-off events. [2025-04-26 16:20:12,673 INFO L117 PetriNetUnfolderBase]: For 30/30 co-relation queries the response was YES. [2025-04-26 16:20:12,673 INFO L83 FinitePrefix]: Finished finitePrefix Result has 66 conditions, 40 events. 1/40 cut-off events. For 30/30 co-relation queries the response was YES. Maximal size of possible extension queue 4. Compared 67 event pairs, 0 based on Foata normal form. 0/35 useless extension candidates. Maximal degree in co-relation 50. Up to 6 conditions per place. [2025-04-26 16:20:12,673 INFO L82 GeneralOperation]: Start removeDead. Operand has 41 places, 31 transitions, 102 flow [2025-04-26 16:20:12,674 INFO L88 GeneralOperation]: Finished RemoveDead, result has has 41 places, 31 transitions, 102 flow [2025-04-26 16:20:12,674 INFO L84 lAbstractionProvider]: Constructed initial Petri net abstraction that has has 41 places, 31 transitions, 102 flow [2025-04-26 16:20:12,674 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-04-26 16:20:12,674 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-04-26 16:20:12,674 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-04-26 16:20:12,674 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-04-26 16:20:12,674 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-04-26 16:20:12,674 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-04-26 16:20:12,674 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-04-26 16:20:12,674 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-04-26 16:20:12,674 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand currently 0 states, but on-demand construction may add more states [2025-04-26 16:20:13,694 INFO L131 ngComponentsAnalysis]: Automaton has 3125 accepting balls. 3125 [2025-04-26 16:20:13,694 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 16:20:13,694 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 16:20:13,695 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 1, 1, 1, 1, 1, 1, 1, 1] [2025-04-26 16:20:13,695 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-04-26 16:20:13,695 INFO L340 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-04-26 16:20:13,695 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand currently 14843 states, but on-demand construction may add more states [2025-04-26 16:20:14,022 INFO L131 ngComponentsAnalysis]: Automaton has 3125 accepting balls. 3125 [2025-04-26 16:20:14,023 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 16:20:14,023 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 16:20:14,024 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 1, 1, 1, 1, 1, 1, 1, 1] [2025-04-26 16:20:14,024 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-04-26 16:20:14,024 INFO L752 eck$LassoCheckResult]: Stem: "[112] $Ultimate##0-->L18: Formula: (= v_ULTIMATE.start_newid_1 0) InVars {} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_1} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[108] L18-->L20-1: Formula: (= v_n_5 0) InVars {} OutVars{n=v_n_5} AuxVars[] AssignedVars[n]" "[138] L20-1-->$Ultimate##0: Formula: (= v_fooThread1of5ForFork0_thidvar0_2 v_ULTIMATE.start_newid_39) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_39} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_39, fooThread1of5ForFork0_thidvar0=v_fooThread1of5ForFork0_thidvar0_2} AuxVars[] AssignedVars[fooThread1of5ForFork0_thidvar0]" "[111] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[139] L20-1-->$Ultimate##0: Formula: (= v_ULTIMATE.start_newid_41 v_fooThread2of5ForFork0_thidvar0_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_41} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_41, fooThread2of5ForFork0_thidvar0=v_fooThread2of5ForFork0_thidvar0_2} AuxVars[] AssignedVars[fooThread2of5ForFork0_thidvar0]" "[111] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[140] L20-1-->$Ultimate##0: Formula: (= v_fooThread3of5ForFork0_thidvar0_2 v_ULTIMATE.start_newid_43) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_43} OutVars{fooThread3of5ForFork0_thidvar0=v_fooThread3of5ForFork0_thidvar0_2, ULTIMATE.start_newid=v_ULTIMATE.start_newid_43} AuxVars[] AssignedVars[fooThread3of5ForFork0_thidvar0]" "[111] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[141] L20-1-->$Ultimate##0: Formula: (= v_fooThread4of5ForFork0_thidvar0_2 v_ULTIMATE.start_newid_45) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_45} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_45, fooThread4of5ForFork0_thidvar0=v_fooThread4of5ForFork0_thidvar0_2} AuxVars[] AssignedVars[fooThread4of5ForFork0_thidvar0]" "[111] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[142] L20-1-->$Ultimate##0: Formula: (= v_ULTIMATE.start_newid_47 v_fooThread5of5ForFork0_thidvar0_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_47} OutVars{fooThread5of5ForFork0_thidvar0=v_fooThread5of5ForFork0_thidvar0_2, ULTIMATE.start_newid=v_ULTIMATE.start_newid_47} AuxVars[] AssignedVars[fooThread5of5ForFork0_thidvar0]" "[111] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[136] L20-1-->ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]" [2025-04-26 16:20:14,024 INFO L754 eck$LassoCheckResult]: Loop: "[137] ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES-->ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]" [2025-04-26 16:20:14,024 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 16:20:14,024 INFO L85 PathProgramCache]: Analyzing trace with hash -396925028, now seen corresponding path program 1 times [2025-04-26 16:20:14,025 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 16:20:14,025 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [228723853] [2025-04-26 16:20:14,025 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 16:20:14,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 16:20:14,030 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes. [2025-04-26 16:20:14,036 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements. [2025-04-26 16:20:14,036 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:14,036 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:14,036 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:14,038 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes. [2025-04-26 16:20:14,043 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements. [2025-04-26 16:20:14,044 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:14,044 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:14,045 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 16:20:14,045 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 16:20:14,045 INFO L85 PathProgramCache]: Analyzing trace with hash 168, now seen corresponding path program 1 times [2025-04-26 16:20:14,046 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 16:20:14,046 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [576633111] [2025-04-26 16:20:14,046 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 16:20:14,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 16:20:14,047 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-04-26 16:20:14,047 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-04-26 16:20:14,047 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:14,047 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:14,047 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:14,048 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-04-26 16:20:14,048 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-04-26 16:20:14,048 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:14,048 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:14,049 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 16:20:14,049 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 16:20:14,049 INFO L85 PathProgramCache]: Analyzing trace with hash 580226157, now seen corresponding path program 1 times [2025-04-26 16:20:14,049 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 16:20:14,049 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [107386771] [2025-04-26 16:20:14,049 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 16:20:14,049 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 16:20:14,053 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 14 statements into 1 equivalence classes. [2025-04-26 16:20:14,055 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 14 of 14 statements. [2025-04-26 16:20:14,055 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:14,055 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:14,055 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:14,059 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 14 statements into 1 equivalence classes. [2025-04-26 16:20:14,062 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 14 of 14 statements. [2025-04-26 16:20:14,062 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:14,063 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:14,064 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 16:20:14,147 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes. [2025-04-26 16:20:14,149 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements. [2025-04-26 16:20:14,149 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:14,149 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:14,149 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:14,152 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes. [2025-04-26 16:20:14,154 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements. [2025-04-26 16:20:14,154 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:14,154 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:14,157 WARN L166 chiAutomizerObserver]: 5 thread instances were not sufficient, I will increase this number and restart the analysis [2025-04-26 16:20:14,163 INFO L143 ThreadInstanceAdder]: Constructed 0 joinOtherThreadTransitions. [2025-04-26 16:20:14,168 INFO L73 FinitePrefix]: Start finitePrefix. Operand has 48 places, 36 transitions, 126 flow [2025-04-26 16:20:14,177 INFO L116 PetriNetUnfolderBase]: 1/47 cut-off events. [2025-04-26 16:20:14,178 INFO L117 PetriNetUnfolderBase]: For 50/50 co-relation queries the response was YES. [2025-04-26 16:20:14,178 INFO L83 FinitePrefix]: Finished finitePrefix Result has 81 conditions, 47 events. 1/47 cut-off events. For 50/50 co-relation queries the response was YES. Maximal size of possible extension queue 5. Compared 90 event pairs, 0 based on Foata normal form. 0/41 useless extension candidates. Maximal degree in co-relation 64. Up to 7 conditions per place. [2025-04-26 16:20:14,178 INFO L82 GeneralOperation]: Start removeDead. Operand has 48 places, 36 transitions, 126 flow [2025-04-26 16:20:14,179 INFO L88 GeneralOperation]: Finished RemoveDead, result has has 48 places, 36 transitions, 126 flow [2025-04-26 16:20:14,179 INFO L84 lAbstractionProvider]: Constructed initial Petri net abstraction that has has 48 places, 36 transitions, 126 flow [2025-04-26 16:20:14,179 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-04-26 16:20:14,179 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-04-26 16:20:14,179 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-04-26 16:20:14,179 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-04-26 16:20:14,179 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-04-26 16:20:14,179 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-04-26 16:20:14,179 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-04-26 16:20:14,179 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-04-26 16:20:14,179 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand currently 0 states, but on-demand construction may add more states [2025-04-26 16:20:19,319 INFO L131 ngComponentsAnalysis]: Automaton has 15625 accepting balls. 15625 [2025-04-26 16:20:19,319 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 16:20:19,319 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 16:20:19,324 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-04-26 16:20:19,324 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-04-26 16:20:19,324 INFO L340 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-04-26 16:20:19,324 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand currently 74218 states, but on-demand construction may add more states [2025-04-26 16:20:20,883 INFO L131 ngComponentsAnalysis]: Automaton has 15625 accepting balls. 15625 [2025-04-26 16:20:20,884 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 16:20:20,884 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 16:20:20,890 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-04-26 16:20:20,890 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-04-26 16:20:20,891 INFO L752 eck$LassoCheckResult]: Stem: "[148] $Ultimate##0-->L18: Formula: (= v_ULTIMATE.start_newid_1 0) InVars {} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_1} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[144] L18-->L20-1: Formula: (= v_n_5 0) InVars {} OutVars{n=v_n_5} AuxVars[] AssignedVars[n]" "[178] L20-1-->$Ultimate##0: Formula: (= v_fooThread1of6ForFork0_thidvar0_2 v_ULTIMATE.start_newid_55) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_55} OutVars{fooThread1of6ForFork0_thidvar0=v_fooThread1of6ForFork0_thidvar0_2, ULTIMATE.start_newid=v_ULTIMATE.start_newid_55} AuxVars[] AssignedVars[fooThread1of6ForFork0_thidvar0]" "[147] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[179] L20-1-->$Ultimate##0: Formula: (= v_ULTIMATE.start_newid_57 v_fooThread2of6ForFork0_thidvar0_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_57} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_57, fooThread2of6ForFork0_thidvar0=v_fooThread2of6ForFork0_thidvar0_2} AuxVars[] AssignedVars[fooThread2of6ForFork0_thidvar0]" "[147] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[180] L20-1-->$Ultimate##0: Formula: (= v_fooThread3of6ForFork0_thidvar0_2 v_ULTIMATE.start_newid_59) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_59} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_59, fooThread3of6ForFork0_thidvar0=v_fooThread3of6ForFork0_thidvar0_2} AuxVars[] AssignedVars[fooThread3of6ForFork0_thidvar0]" "[147] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[181] L20-1-->$Ultimate##0: Formula: (= v_fooThread4of6ForFork0_thidvar0_2 v_ULTIMATE.start_newid_61) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_61} OutVars{fooThread4of6ForFork0_thidvar0=v_fooThread4of6ForFork0_thidvar0_2, ULTIMATE.start_newid=v_ULTIMATE.start_newid_61} AuxVars[] AssignedVars[fooThread4of6ForFork0_thidvar0]" "[147] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[182] L20-1-->$Ultimate##0: Formula: (= v_ULTIMATE.start_newid_63 v_fooThread5of6ForFork0_thidvar0_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_63} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_63, fooThread5of6ForFork0_thidvar0=v_fooThread5of6ForFork0_thidvar0_2} AuxVars[] AssignedVars[fooThread5of6ForFork0_thidvar0]" "[147] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[183] L20-1-->$Ultimate##0: Formula: (= v_fooThread6of6ForFork0_thidvar0_2 v_ULTIMATE.start_newid_65) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_65} OutVars{fooThread6of6ForFork0_thidvar0=v_fooThread6of6ForFork0_thidvar0_2, ULTIMATE.start_newid=v_ULTIMATE.start_newid_65} AuxVars[] AssignedVars[fooThread6of6ForFork0_thidvar0]" "[147] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[176] L20-1-->ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]" [2025-04-26 16:20:20,891 INFO L754 eck$LassoCheckResult]: Loop: "[177] ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES-->ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]" [2025-04-26 16:20:20,892 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 16:20:20,892 INFO L85 PathProgramCache]: Analyzing trace with hash -676100964, now seen corresponding path program 1 times [2025-04-26 16:20:20,892 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 16:20:20,892 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [509130530] [2025-04-26 16:20:20,892 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 16:20:20,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 16:20:20,895 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 15 statements into 1 equivalence classes. [2025-04-26 16:20:20,898 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 15 of 15 statements. [2025-04-26 16:20:20,898 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:20,898 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:20,898 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:20,899 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 15 statements into 1 equivalence classes. [2025-04-26 16:20:20,901 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 15 of 15 statements. [2025-04-26 16:20:20,901 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:20,902 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:20,903 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 16:20:20,903 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 16:20:20,903 INFO L85 PathProgramCache]: Analyzing trace with hash 208, now seen corresponding path program 1 times [2025-04-26 16:20:20,903 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 16:20:20,903 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1590669218] [2025-04-26 16:20:20,903 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 16:20:20,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 16:20:20,905 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-04-26 16:20:20,905 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-04-26 16:20:20,905 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:20,905 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:20,905 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:20,906 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-04-26 16:20:20,906 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-04-26 16:20:20,906 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:20,906 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:20,906 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 16:20:20,907 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 16:20:20,907 INFO L85 PathProgramCache]: Analyzing trace with hash 515706773, now seen corresponding path program 1 times [2025-04-26 16:20:20,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 16:20:20,907 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [86292907] [2025-04-26 16:20:20,907 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 16:20:20,907 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 16:20:20,909 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 16 statements into 1 equivalence classes. [2025-04-26 16:20:20,915 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 16 of 16 statements. [2025-04-26 16:20:20,915 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:20,915 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:20,915 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:20,916 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 16 statements into 1 equivalence classes. [2025-04-26 16:20:20,919 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 16 of 16 statements. [2025-04-26 16:20:20,919 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:20,919 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:20,920 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 16:20:21,011 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 15 statements into 1 equivalence classes. [2025-04-26 16:20:21,013 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 15 of 15 statements. [2025-04-26 16:20:21,013 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:21,013 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:21,013 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:20:21,017 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 15 statements into 1 equivalence classes. [2025-04-26 16:20:21,021 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 15 of 15 statements. [2025-04-26 16:20:21,021 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:20:21,022 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:20:21,030 WARN L166 chiAutomizerObserver]: 6 thread instances were not sufficient, I will increase this number and restart the analysis [2025-04-26 16:20:21,037 INFO L143 ThreadInstanceAdder]: Constructed 0 joinOtherThreadTransitions. [2025-04-26 16:20:21,041 INFO L73 FinitePrefix]: Start finitePrefix. Operand has 55 places, 41 transitions, 152 flow [2025-04-26 16:20:21,052 INFO L116 PetriNetUnfolderBase]: 1/54 cut-off events. [2025-04-26 16:20:21,052 INFO L117 PetriNetUnfolderBase]: For 77/77 co-relation queries the response was YES. [2025-04-26 16:20:21,052 INFO L83 FinitePrefix]: Finished finitePrefix Result has 97 conditions, 54 events. 1/54 cut-off events. For 77/77 co-relation queries the response was YES. Maximal size of possible extension queue 5. Compared 106 event pairs, 0 based on Foata normal form. 0/47 useless extension candidates. Maximal degree in co-relation 79. Up to 8 conditions per place. [2025-04-26 16:20:21,052 INFO L82 GeneralOperation]: Start removeDead. Operand has 55 places, 41 transitions, 152 flow [2025-04-26 16:20:21,053 INFO L88 GeneralOperation]: Finished RemoveDead, result has has 55 places, 41 transitions, 152 flow [2025-04-26 16:20:21,053 INFO L84 lAbstractionProvider]: Constructed initial Petri net abstraction that has has 55 places, 41 transitions, 152 flow [2025-04-26 16:20:21,054 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-04-26 16:20:21,054 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-04-26 16:20:21,054 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-04-26 16:20:21,054 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-04-26 16:20:21,054 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-04-26 16:20:21,054 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-04-26 16:20:21,054 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-04-26 16:20:21,054 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-04-26 16:20:21,054 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand currently 0 states, but on-demand construction may add more states [2025-04-26 16:20:54,018 INFO L131 ngComponentsAnalysis]: Automaton has 78125 accepting balls. 78125 [2025-04-26 16:20:54,018 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 16:20:54,018 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 16:20:54,041 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-04-26 16:20:54,041 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-04-26 16:20:54,042 INFO L340 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-04-26 16:20:54,042 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand currently 371093 states, but on-demand construction may add more states [2025-04-26 16:21:07,026 INFO L131 ngComponentsAnalysis]: Automaton has 78125 accepting balls. 78125 [2025-04-26 16:21:07,027 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 16:21:07,027 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 16:21:07,041 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-04-26 16:21:07,041 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-04-26 16:21:07,045 INFO L752 eck$LassoCheckResult]: Stem: "[189] $Ultimate##0-->L18: Formula: (= v_ULTIMATE.start_newid_1 0) InVars {} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_1} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[185] L18-->L20-1: Formula: (= v_n_5 0) InVars {} OutVars{n=v_n_5} AuxVars[] AssignedVars[n]" "[223] L20-1-->$Ultimate##0: Formula: (= v_fooThread1of7ForFork0_thidvar0_2 v_ULTIMATE.start_newid_74) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_74} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_74, fooThread1of7ForFork0_thidvar0=v_fooThread1of7ForFork0_thidvar0_2} AuxVars[] AssignedVars[fooThread1of7ForFork0_thidvar0]" "[188] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[224] L20-1-->$Ultimate##0: Formula: (= v_ULTIMATE.start_newid_76 v_fooThread2of7ForFork0_thidvar0_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_76} OutVars{fooThread2of7ForFork0_thidvar0=v_fooThread2of7ForFork0_thidvar0_2, ULTIMATE.start_newid=v_ULTIMATE.start_newid_76} AuxVars[] AssignedVars[fooThread2of7ForFork0_thidvar0]" "[188] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[225] L20-1-->$Ultimate##0: Formula: (= v_fooThread3of7ForFork0_thidvar0_2 v_ULTIMATE.start_newid_78) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_78} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_78, fooThread3of7ForFork0_thidvar0=v_fooThread3of7ForFork0_thidvar0_2} AuxVars[] AssignedVars[fooThread3of7ForFork0_thidvar0]" "[188] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[226] L20-1-->$Ultimate##0: Formula: (= v_fooThread4of7ForFork0_thidvar0_2 v_ULTIMATE.start_newid_80) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_80} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_80, fooThread4of7ForFork0_thidvar0=v_fooThread4of7ForFork0_thidvar0_2} AuxVars[] AssignedVars[fooThread4of7ForFork0_thidvar0]" "[188] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[227] L20-1-->$Ultimate##0: Formula: (= v_fooThread5of7ForFork0_thidvar0_2 v_ULTIMATE.start_newid_82) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_82} OutVars{fooThread5of7ForFork0_thidvar0=v_fooThread5of7ForFork0_thidvar0_2, ULTIMATE.start_newid=v_ULTIMATE.start_newid_82} AuxVars[] AssignedVars[fooThread5of7ForFork0_thidvar0]" "[188] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[228] L20-1-->$Ultimate##0: Formula: (= v_ULTIMATE.start_newid_84 v_fooThread6of7ForFork0_thidvar0_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_84} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_84, fooThread6of7ForFork0_thidvar0=v_fooThread6of7ForFork0_thidvar0_2} AuxVars[] AssignedVars[fooThread6of7ForFork0_thidvar0]" "[188] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[229] L20-1-->$Ultimate##0: Formula: (= v_fooThread7of7ForFork0_thidvar0_2 v_ULTIMATE.start_newid_86) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_86} OutVars{fooThread7of7ForFork0_thidvar0=v_fooThread7of7ForFork0_thidvar0_2, ULTIMATE.start_newid=v_ULTIMATE.start_newid_86} AuxVars[] AssignedVars[fooThread7of7ForFork0_thidvar0]" "[188] L21-->L20-1: Formula: (= (+ v_ULTIMATE.start_newid_3 1) v_ULTIMATE.start_newid_2) InVars {ULTIMATE.start_newid=v_ULTIMATE.start_newid_3} OutVars{ULTIMATE.start_newid=v_ULTIMATE.start_newid_2} AuxVars[] AssignedVars[ULTIMATE.start_newid]" "[221] L20-1-->ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]" [2025-04-26 16:21:07,045 INFO L754 eck$LassoCheckResult]: Loop: "[222] ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES-->ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]" [2025-04-26 16:21:07,046 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 16:21:07,046 INFO L85 PathProgramCache]: Analyzing trace with hash 2031319402, now seen corresponding path program 1 times [2025-04-26 16:21:07,046 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 16:21:07,046 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1903723474] [2025-04-26 16:21:07,046 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 16:21:07,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 16:21:07,059 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 17 statements into 1 equivalence classes. [2025-04-26 16:21:07,063 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 17 of 17 statements. [2025-04-26 16:21:07,063 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:21:07,063 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:21:07,063 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:21:07,064 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 17 statements into 1 equivalence classes. [2025-04-26 16:21:07,070 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 17 of 17 statements. [2025-04-26 16:21:07,070 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:21:07,070 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:21:07,076 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 16:21:07,076 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 16:21:07,076 INFO L85 PathProgramCache]: Analyzing trace with hash 253, now seen corresponding path program 1 times [2025-04-26 16:21:07,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 16:21:07,077 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023832539] [2025-04-26 16:21:07,077 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 16:21:07,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 16:21:07,082 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-04-26 16:21:07,083 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-04-26 16:21:07,083 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:21:07,083 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:21:07,083 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:21:07,083 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-04-26 16:21:07,083 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-04-26 16:21:07,083 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:21:07,083 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:21:07,084 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 16:21:07,084 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 16:21:07,088 INFO L85 PathProgramCache]: Analyzing trace with hash -1453607756, now seen corresponding path program 1 times [2025-04-26 16:21:07,089 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 16:21:07,089 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1403098310] [2025-04-26 16:21:07,089 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 16:21:07,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 16:21:07,091 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 18 statements into 1 equivalence classes. [2025-04-26 16:21:07,098 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 18 of 18 statements. [2025-04-26 16:21:07,098 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:21:07,098 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:21:07,098 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:21:07,099 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 18 statements into 1 equivalence classes. [2025-04-26 16:21:07,105 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 18 of 18 statements. [2025-04-26 16:21:07,105 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:21:07,105 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:21:07,106 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 16:21:07,184 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 17 statements into 1 equivalence classes. [2025-04-26 16:21:07,186 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 17 of 17 statements. [2025-04-26 16:21:07,186 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:21:07,186 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:21:07,186 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 16:21:07,188 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 17 statements into 1 equivalence classes. [2025-04-26 16:21:07,190 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 17 of 17 statements. [2025-04-26 16:21:07,190 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 16:21:07,190 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 16:21:07,194 WARN L166 chiAutomizerObserver]: 7 thread instances were not sufficient, I will increase this number and restart the analysis [2025-04-26 16:21:07,200 INFO L143 ThreadInstanceAdder]: Constructed 0 joinOtherThreadTransitions. [2025-04-26 16:21:07,206 INFO L73 FinitePrefix]: Start finitePrefix. Operand has 62 places, 46 transitions, 180 flow [2025-04-26 16:21:07,212 INFO L116 PetriNetUnfolderBase]: 1/61 cut-off events. [2025-04-26 16:21:07,212 INFO L117 PetriNetUnfolderBase]: For 112/112 co-relation queries the response was YES. [2025-04-26 16:21:07,212 INFO L83 FinitePrefix]: Finished finitePrefix Result has 114 conditions, 61 events. 1/61 cut-off events. For 112/112 co-relation queries the response was YES. Maximal size of possible extension queue 5. Compared 132 event pairs, 0 based on Foata normal form. 0/53 useless extension candidates. Maximal degree in co-relation 95. Up to 9 conditions per place. [2025-04-26 16:21:07,212 INFO L82 GeneralOperation]: Start removeDead. Operand has 62 places, 46 transitions, 180 flow [2025-04-26 16:21:07,213 INFO L88 GeneralOperation]: Finished RemoveDead, result has has 62 places, 46 transitions, 180 flow [2025-04-26 16:21:07,213 INFO L84 lAbstractionProvider]: Constructed initial Petri net abstraction that has has 62 places, 46 transitions, 180 flow [2025-04-26 16:21:07,213 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-04-26 16:21:07,213 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-04-26 16:21:07,213 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-04-26 16:21:07,213 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-04-26 16:21:07,213 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-04-26 16:21:07,213 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-04-26 16:21:07,213 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-04-26 16:21:07,213 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-04-26 16:21:07,213 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand currently 0 states, but on-demand construction may add more states