/root/.sdkman/candidates/java/21.0.5-tem/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata ./data -s ../../../trunk/examples/settings/gemcutter/Termination.epf -tc ../../../trunk/examples/toolchains/BuchiAutomizerBplInline.xml -i ../../../trunk/examples/concurrent/bpl/weaver-benchmarks/generated/popl20-bad/ring-nondet.wvr.bpl -------------------------------------------------------------------------------- This is Ultimate 0.3.0-wip.dk.ample-buchi-a4216cd-m [2025-04-26 18:40:50,448 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-04-26 18:40:50,518 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/../../../trunk/examples/settings/gemcutter/Termination.epf [2025-04-26 18:40:50,526 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-04-26 18:40:50,526 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-04-26 18:40:50,526 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.Check unreachability of error function in SV-COMP mode [2025-04-26 18:40:50,526 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.Translation Mode: [2025-04-26 18:40:50,554 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-04-26 18:40:50,554 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-04-26 18:40:50,554 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-04-26 18:40:50,555 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-04-26 18:40:50,555 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-04-26 18:40:50,555 INFO L153 SettingsManager]: * Use SBE=true [2025-04-26 18:40:50,555 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-04-26 18:40:50,555 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-04-26 18:40:50,555 INFO L153 SettingsManager]: * Use old map elimination=false [2025-04-26 18:40:50,555 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-04-26 18:40:50,555 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-04-26 18:40:50,555 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-04-26 18:40:50,555 INFO L153 SettingsManager]: * Automaton type for concurrent programs=PARTIAL_ORDER_BA [2025-04-26 18:40:50,555 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-04-26 18:40:50,555 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-04-26 18:40:50,555 INFO L153 SettingsManager]: * sizeof long=4 [2025-04-26 18:40:50,555 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-04-26 18:40:50,555 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-04-26 18:40:50,556 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-04-26 18:40:50,556 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-04-26 18:40:50,556 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-04-26 18:40:50,556 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-04-26 18:40:50,556 INFO L153 SettingsManager]: * sizeof long double=12 [2025-04-26 18:40:50,556 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-04-26 18:40:50,556 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-04-26 18:40:50,556 INFO L153 SettingsManager]: * Use constant arrays=true [2025-04-26 18:40:50,559 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2025-04-26 18:40:50,560 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-04-26 18:40:50,560 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -smt2 -in -t:4000 [2025-04-26 18:40:50,560 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-04-26 18:40:50,560 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-04-26 18:40:50,560 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2025-04-26 18:40:50,560 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2025-04-26 18:40:50,560 INFO L153 SettingsManager]: * Use conditional POR in concurrent analysis=false [2025-04-26 18:40:50,560 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-04-26 18:40:50,560 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR [2025-04-26 18:40:50,793 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-04-26 18:40:50,799 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-04-26 18:40:50,800 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-04-26 18:40:50,801 INFO L270 PluginConnector]: Initializing Boogie PL CUP Parser... [2025-04-26 18:40:50,802 INFO L274 PluginConnector]: Boogie PL CUP Parser initialized [2025-04-26 18:40:50,802 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/../../../trunk/examples/concurrent/bpl/weaver-benchmarks/generated/popl20-bad/ring-nondet.wvr.bpl [2025-04-26 18:40:50,803 INFO L110 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/../../../trunk/examples/concurrent/bpl/weaver-benchmarks/generated/popl20-bad/ring-nondet.wvr.bpl' [2025-04-26 18:40:50,817 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-04-26 18:40:50,818 INFO L133 ToolchainWalker]: Walking toolchain with 4 elements. [2025-04-26 18:40:50,819 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-04-26 18:40:50,819 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-04-26 18:40:50,819 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-04-26 18:40:50,825 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "ring-nondet.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 06:40:50" (1/1) ... [2025-04-26 18:40:50,847 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "ring-nondet.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 06:40:50" (1/1) ... [2025-04-26 18:40:50,851 INFO L138 Inliner]: procedures = 4, calls = 3, calls flagged for inlining = 0, calls inlined = 0, statements flattened = 0 [2025-04-26 18:40:50,853 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-04-26 18:40:50,854 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-04-26 18:40:50,854 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-04-26 18:40:50,854 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-04-26 18:40:50,858 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "ring-nondet.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 06:40:50" (1/1) ... [2025-04-26 18:40:50,858 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "ring-nondet.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 06:40:50" (1/1) ... [2025-04-26 18:40:50,860 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "ring-nondet.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 06:40:50" (1/1) ... [2025-04-26 18:40:50,860 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "ring-nondet.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 06:40:50" (1/1) ... [2025-04-26 18:40:50,861 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "ring-nondet.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 06:40:50" (1/1) ... [2025-04-26 18:40:50,862 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "ring-nondet.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 06:40:50" (1/1) ... [2025-04-26 18:40:50,864 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "ring-nondet.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 06:40:50" (1/1) ... [2025-04-26 18:40:50,865 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "ring-nondet.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 06:40:50" (1/1) ... [2025-04-26 18:40:50,865 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "ring-nondet.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 06:40:50" (1/1) ... [2025-04-26 18:40:50,876 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-04-26 18:40:50,877 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2025-04-26 18:40:50,877 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2025-04-26 18:40:50,877 INFO L274 PluginConnector]: RCFGBuilder initialized [2025-04-26 18:40:50,878 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "ring-nondet.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 06:40:50" (1/1) ... [2025-04-26 18:40:50,883 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -smt2 -in -t:4000 [2025-04-26 18:40:50,893 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:50,904 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:50,908 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2025-04-26 18:40:50,929 INFO L124 BoogieDeclarations]: Specification and implementation of procedure thread1 given in one single declaration [2025-04-26 18:40:50,930 INFO L130 BoogieDeclarations]: Found specification of procedure thread1 [2025-04-26 18:40:50,930 INFO L138 BoogieDeclarations]: Found implementation of procedure thread1 [2025-04-26 18:40:50,930 INFO L124 BoogieDeclarations]: Specification and implementation of procedure thread2 given in one single declaration [2025-04-26 18:40:50,930 INFO L130 BoogieDeclarations]: Found specification of procedure thread2 [2025-04-26 18:40:50,930 INFO L138 BoogieDeclarations]: Found implementation of procedure thread2 [2025-04-26 18:40:50,930 INFO L124 BoogieDeclarations]: Specification and implementation of procedure ULTIMATE.start given in one single declaration [2025-04-26 18:40:50,930 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-04-26 18:40:50,930 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-04-26 18:40:50,930 INFO L124 BoogieDeclarations]: Specification and implementation of procedure thread3 given in one single declaration [2025-04-26 18:40:50,930 INFO L130 BoogieDeclarations]: Found specification of procedure thread3 [2025-04-26 18:40:50,930 INFO L138 BoogieDeclarations]: Found implementation of procedure thread3 [2025-04-26 18:40:50,931 WARN L203 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to OneNontrivialStatement. [2025-04-26 18:40:50,974 INFO L234 CfgBuilder]: Building ICFG [2025-04-26 18:40:50,976 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2025-04-26 18:40:51,086 INFO L279 CfgBuilder]: Omitted future-live optimization because the input is a concurrent program. [2025-04-26 18:40:51,086 INFO L283 CfgBuilder]: Performing block encoding [2025-04-26 18:40:51,125 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-04-26 18:40:51,125 INFO L312 CfgBuilder]: Removed 0 assume(true) statements. [2025-04-26 18:40:51,126 INFO L201 PluginConnector]: Adding new model ring-nondet.wvr.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.04 06:40:51 BoogieIcfgContainer [2025-04-26 18:40:51,126 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2025-04-26 18:40:51,127 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-04-26 18:40:51,127 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-04-26 18:40:51,132 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-04-26 18:40:51,132 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-04-26 18:40:51,132 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "ring-nondet.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 26.04 06:40:50" (1/2) ... [2025-04-26 18:40:51,134 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@b052c2e and model type ring-nondet.wvr.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.04 06:40:51, skipping insertion in model container [2025-04-26 18:40:51,134 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-04-26 18:40:51,134 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "ring-nondet.wvr.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.04 06:40:51" (2/2) ... [2025-04-26 18:40:51,135 INFO L376 chiAutomizerObserver]: Analyzing ICFG ring-nondet.wvr.bpl [2025-04-26 18:40:51,193 INFO L143 ThreadInstanceAdder]: Constructed 3 joinOtherThreadTransitions. [2025-04-26 18:40:51,238 INFO L125 denceProviderFactory]: Independence Relation #1: [IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2025-04-26 18:40:51,239 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 [2025-04-26 18:40:51,239 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:51,242 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:51,244 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (2)] Waiting until timeout for monitored process [2025-04-26 18:40:51,305 INFO L73 FinitePrefix]: Start finitePrefix. Operand has 40 places, 37 transitions, 95 flow [2025-04-26 18:40:51,324 INFO L116 PetriNetUnfolderBase]: 4/31 cut-off events. [2025-04-26 18:40:51,326 INFO L117 PetriNetUnfolderBase]: For 3/3 co-relation queries the response was YES. [2025-04-26 18:40:51,330 INFO L83 FinitePrefix]: Finished finitePrefix Result has 44 conditions, 31 events. 4/31 cut-off events. For 3/3 co-relation queries the response was YES. Maximal size of possible extension queue 5. Compared 55 event pairs, 0 based on Foata normal form. 0/26 useless extension candidates. Maximal degree in co-relation 26. Up to 3 conditions per place. [2025-04-26 18:40:51,330 INFO L82 GeneralOperation]: Start removeDead. Operand has 40 places, 37 transitions, 95 flow [2025-04-26 18:40:51,333 INFO L88 GeneralOperation]: Finished RemoveDead, result has has 37 places, 31 transitions, 80 flow [2025-04-26 18:40:51,333 INFO L84 lAbstractionProvider]: Constructed initial Petri net abstraction that has has 37 places, 31 transitions, 80 flow [2025-04-26 18:40:51,334 INFO L113 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 37 places, 31 transitions, 80 flow [2025-04-26 18:40:51,374 INFO L135 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result has 348 states, 346 states have (on average 3.106936416184971) internal successors, (in total 1075), 347 states have internal predecessors, (1075), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:51,375 INFO L171 actionProvider$Eager]: Constructed initial Büchi automaton abstraction (from Petri net) that has 348 states, 346 states have (on average 3.106936416184971) internal successors, (in total 1075), 347 states have internal predecessors, (1075), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:51,377 INFO L135 AmpleReduction]: Starting ample reduction [2025-04-26 18:40:51,498 WARN L140 AmpleReduction]: Number of pruned transitions: 320 [2025-04-26 18:40:51,498 WARN L141 AmpleReduction]: Loop nodes with "changing loop node status": 0 [2025-04-26 18:40:51,498 WARN L142 AmpleReduction]: Number of trivial sets caused by loops: 44 [2025-04-26 18:40:51,498 WARN L143 AmpleReduction]: Number of not loop caused trivial ample sets:30 [2025-04-26 18:40:51,498 WARN L144 AmpleReduction]: Number of initially assigned non-trivial ample sets:183 [2025-04-26 18:40:51,499 WARN L145 AmpleReduction]: Times succ was already a loop node:48 [2025-04-26 18:40:51,499 WARN L146 AmpleReduction]: Times some other node on the cycle already had a trivial ample set:49 [2025-04-26 18:40:51,499 INFO L149 AmpleReduction]: Finished ample reduction [2025-04-26 18:40:51,501 INFO L136 dAbstractionProvider]: Constructed initial ample set-reduced NBA abstraction that has 258 states, 256 states have (on average 1.59375) internal successors, (in total 408), 257 states have internal predecessors, (408), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:51,508 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-04-26 18:40:51,508 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-04-26 18:40:51,508 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-04-26 18:40:51,508 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-04-26 18:40:51,509 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-04-26 18:40:51,509 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-04-26 18:40:51,509 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-04-26 18:40:51,509 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-04-26 18:40:51,511 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 258 states, 256 states have (on average 1.59375) internal successors, (in total 408), 257 states have internal predecessors, (408), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:51,526 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 210 [2025-04-26 18:40:51,526 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:40:51,526 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:40:51,530 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-04-26 18:40:51,530 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:40:51,530 INFO L340 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-04-26 18:40:51,531 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 258 states, 256 states have (on average 1.59375) internal successors, (in total 408), 257 states have internal predecessors, (408), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:51,536 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 210 [2025-04-26 18:40:51,536 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:40:51,536 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:40:51,536 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-04-26 18:40:51,536 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:40:51,540 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" [2025-04-26 18:40:51,540 INFO L754 eck$LassoCheckResult]: Loop: "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" [2025-04-26 18:40:51,543 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:51,544 INFO L85 PathProgramCache]: Analyzing trace with hash 4058, now seen corresponding path program 1 times [2025-04-26 18:40:51,548 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:51,548 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1619701029] [2025-04-26 18:40:51,548 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:51,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:51,614 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:40:51,621 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:40:51,621 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:51,621 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:51,622 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:51,624 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:40:51,625 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:40:51,625 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:51,626 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:51,640 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:51,642 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:51,642 INFO L85 PathProgramCache]: Analyzing trace with hash 4163, now seen corresponding path program 1 times [2025-04-26 18:40:51,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:51,642 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [991063930] [2025-04-26 18:40:51,642 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:51,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:51,646 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:40:51,655 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:40:51,655 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:51,655 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:51,655 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:51,657 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:40:51,659 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:40:51,659 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:51,659 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:51,664 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:51,667 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:51,667 INFO L85 PathProgramCache]: Analyzing trace with hash 3902940, now seen corresponding path program 1 times [2025-04-26 18:40:51,668 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:51,668 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [582351270] [2025-04-26 18:40:51,668 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:51,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:51,671 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 4 statements into 1 equivalence classes. [2025-04-26 18:40:51,678 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 4 of 4 statements. [2025-04-26 18:40:51,678 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:51,678 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:51,785 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:51,785 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:40:51,792 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [582351270] [2025-04-26 18:40:51,793 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [582351270] provided 1 perfect and 0 imperfect interpolant sequences [2025-04-26 18:40:51,793 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-04-26 18:40:51,799 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2025-04-26 18:40:51,800 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [486587978] [2025-04-26 18:40:51,800 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-04-26 18:40:51,883 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:40:51,900 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-04-26 18:40:51,900 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-04-26 18:40:51,902 INFO L87 Difference]: Start difference. First operand has 258 states, 256 states have (on average 1.59375) internal successors, (in total 408), 257 states have internal predecessors, (408), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) Second operand has 3 states, 2 states have (on average 2.0) internal successors, (in total 4), 2 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:51,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:40:51,952 INFO L93 Difference]: Finished difference Result 416 states and 647 transitions. [2025-04-26 18:40:51,955 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 416 states and 647 transitions. [2025-04-26 18:40:51,960 INFO L131 ngComponentsAnalysis]: Automaton has 52 accepting balls. 319 [2025-04-26 18:40:51,968 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 416 states to 374 states and 576 transitions. [2025-04-26 18:40:51,969 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 374 [2025-04-26 18:40:51,970 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 374 [2025-04-26 18:40:51,970 INFO L74 IsDeterministic]: Start isDeterministic. Operand 374 states and 576 transitions. [2025-04-26 18:40:51,972 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-04-26 18:40:51,972 INFO L218 hiAutomatonCegarLoop]: Abstraction has 374 states and 576 transitions. [2025-04-26 18:40:51,982 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 374 states and 576 transitions. [2025-04-26 18:40:51,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 374 to 271. [2025-04-26 18:40:51,998 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 271 states, 271 states have (on average 1.6199261992619927) internal successors, (in total 439), 270 states have internal predecessors, (439), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:51,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 271 states to 271 states and 439 transitions. [2025-04-26 18:40:52,002 INFO L240 hiAutomatonCegarLoop]: Abstraction has 271 states and 439 transitions. [2025-04-26 18:40:52,003 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-04-26 18:40:52,005 INFO L438 stractBuchiCegarLoop]: Abstraction has 271 states and 439 transitions. [2025-04-26 18:40:52,005 INFO L340 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-04-26 18:40:52,006 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 271 states and 439 transitions. [2025-04-26 18:40:52,010 INFO L131 ngComponentsAnalysis]: Automaton has 37 accepting balls. 244 [2025-04-26 18:40:52,011 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:40:52,011 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:40:52,011 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-04-26 18:40:52,011 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:40:52,012 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" [2025-04-26 18:40:52,012 INFO L754 eck$LassoCheckResult]: Loop: "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" [2025-04-26 18:40:52,012 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:52,012 INFO L85 PathProgramCache]: Analyzing trace with hash 4058, now seen corresponding path program 2 times [2025-04-26 18:40:52,013 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:52,013 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [946981738] [2025-04-26 18:40:52,013 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-04-26 18:40:52,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:52,020 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:40:52,022 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:40:52,022 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-04-26 18:40:52,022 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:52,022 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:52,023 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:40:52,024 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:40:52,024 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:52,024 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:52,025 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:52,026 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:52,026 INFO L85 PathProgramCache]: Analyzing trace with hash 4164, now seen corresponding path program 1 times [2025-04-26 18:40:52,026 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:52,026 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1694484331] [2025-04-26 18:40:52,026 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:52,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:52,028 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:40:52,029 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:40:52,029 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:52,029 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:52,029 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:52,030 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:40:52,031 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:40:52,031 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:52,031 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:52,032 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:52,033 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:52,033 INFO L85 PathProgramCache]: Analyzing trace with hash 3902941, now seen corresponding path program 1 times [2025-04-26 18:40:52,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:52,033 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1677801010] [2025-04-26 18:40:52,033 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:52,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:52,035 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 4 statements into 1 equivalence classes. [2025-04-26 18:40:52,037 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 4 of 4 statements. [2025-04-26 18:40:52,037 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:52,037 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:52,037 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:52,038 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 4 statements into 1 equivalence classes. [2025-04-26 18:40:52,041 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 4 of 4 statements. [2025-04-26 18:40:52,041 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:52,041 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:52,044 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:52,197 INFO L206 LassoAnalysis]: Preferences: [2025-04-26 18:40:52,198 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-04-26 18:40:52,198 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-04-26 18:40:52,198 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-04-26 18:40:52,198 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-04-26 18:40:52,198 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:52,198 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-04-26 18:40:52,198 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-04-26 18:40:52,198 INFO L132 ssoRankerPreferences]: Filename of dumped script: ring-nondet.wvr.bpl_petrified1_Iteration2_Lasso [2025-04-26 18:40:52,198 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-04-26 18:40:52,198 INFO L243 LassoAnalysis]: Starting lasso preprocessing... [2025-04-26 18:40:52,209 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:52,214 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:52,218 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:52,222 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:52,232 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:52,234 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:52,237 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:52,251 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:52,253 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:52,257 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:52,361 INFO L261 LassoAnalysis]: Preprocessing complete. [2025-04-26 18:40:52,363 INFO L453 LassoAnalysis]: Using template 'affine'. [2025-04-26 18:40:52,364 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:52,365 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:52,371 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:52,371 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2025-04-26 18:40:52,372 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:52,384 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:52,385 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:52,385 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:52,385 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:52,390 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:52,390 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:52,394 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:40:52,403 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2025-04-26 18:40:52,403 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:52,403 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:52,405 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:52,407 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2025-04-26 18:40:52,408 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:52,419 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:52,419 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:52,419 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:52,419 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:52,421 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:52,421 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:52,424 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:40:52,430 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2025-04-26 18:40:52,430 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:52,430 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:52,432 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:52,433 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2025-04-26 18:40:52,435 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:52,444 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:52,444 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:52,444 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:52,444 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:52,447 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:52,447 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:52,450 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:40:52,456 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2025-04-26 18:40:52,457 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:52,457 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:52,458 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:52,460 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2025-04-26 18:40:52,461 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:52,471 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:52,471 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:52,471 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:52,471 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:52,474 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:52,474 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:52,479 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-04-26 18:40:52,488 INFO L436 ModelExtractionUtils]: Simplification made 7 calls to the SMT solver. [2025-04-26 18:40:52,488 INFO L437 ModelExtractionUtils]: 3 out of 10 variables were initially zero. Simplification set additionally 4 variables to zero. [2025-04-26 18:40:52,490 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:52,490 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:52,493 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:52,494 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2025-04-26 18:40:52,496 INFO L436 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-04-26 18:40:52,515 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2025-04-26 18:40:52,516 INFO L439 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2025-04-26 18:40:52,516 INFO L476 LassoAnalysis]: Proved termination. [2025-04-26 18:40:52,516 INFO L478 LassoAnalysis]: Termination argument consisting of: Ranking function f(N, i) = 1*N - 1*i Supporting invariants [] [2025-04-26 18:40:52,523 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2025-04-26 18:40:52,524 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2025-04-26 18:40:52,543 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:52,552 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:40:52,555 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:40:52,555 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:52,555 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:52,557 INFO L256 TraceCheckSpWp]: Trace formula consists of 21 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-04-26 18:40:52,557 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:52,568 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:40:52,569 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:40:52,570 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:52,570 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:52,572 INFO L256 TraceCheckSpWp]: Trace formula consists of 9 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-04-26 18:40:52,573 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:52,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:52,592 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2025-04-26 18:40:52,593 INFO L70 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 271 states and 439 transitions. cyclomatic complexity: 205 Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (in total 4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:52,683 INFO L74 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 271 states and 439 transitions. cyclomatic complexity: 205. Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (in total 4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) Result 783 states and 1287 transitions. Complement of second has 7 states. [2025-04-26 18:40:52,683 INFO L140 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2025-04-26 18:40:52,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (in total 4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:52,686 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 70 transitions. [2025-04-26 18:40:52,688 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 5 states and 70 transitions. Stem has 2 letters. Loop has 2 letters. [2025-04-26 18:40:52,688 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:40:52,689 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 5 states and 70 transitions. Stem has 4 letters. Loop has 2 letters. [2025-04-26 18:40:52,689 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:40:52,689 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 5 states and 70 transitions. Stem has 2 letters. Loop has 4 letters. [2025-04-26 18:40:52,689 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:40:52,689 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 783 states and 1287 transitions. [2025-04-26 18:40:52,694 INFO L131 ngComponentsAnalysis]: Automaton has 29 accepting balls. 210 [2025-04-26 18:40:52,697 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 783 states to 418 states and 714 transitions. [2025-04-26 18:40:52,697 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 239 [2025-04-26 18:40:52,698 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 294 [2025-04-26 18:40:52,698 INFO L74 IsDeterministic]: Start isDeterministic. Operand 418 states and 714 transitions. [2025-04-26 18:40:52,698 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:40:52,698 INFO L218 hiAutomatonCegarLoop]: Abstraction has 418 states and 714 transitions. [2025-04-26 18:40:52,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 418 states and 714 transitions. [2025-04-26 18:40:52,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 418 to 370. [2025-04-26 18:40:52,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 370 states, 370 states have (on average 1.7243243243243243) internal successors, (in total 638), 369 states have internal predecessors, (638), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:52,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 370 states to 370 states and 638 transitions. [2025-04-26 18:40:52,711 INFO L240 hiAutomatonCegarLoop]: Abstraction has 370 states and 638 transitions. [2025-04-26 18:40:52,711 INFO L438 stractBuchiCegarLoop]: Abstraction has 370 states and 638 transitions. [2025-04-26 18:40:52,711 INFO L340 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-04-26 18:40:52,711 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 370 states and 638 transitions. [2025-04-26 18:40:52,712 INFO L131 ngComponentsAnalysis]: Automaton has 29 accepting balls. 210 [2025-04-26 18:40:52,712 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:40:52,712 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:40:52,713 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2025-04-26 18:40:52,713 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2025-04-26 18:40:52,713 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" [2025-04-26 18:40:52,713 INFO L754 eck$LassoCheckResult]: Loop: "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" [2025-04-26 18:40:52,713 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:52,713 INFO L85 PathProgramCache]: Analyzing trace with hash 3902962, now seen corresponding path program 1 times [2025-04-26 18:40:52,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:52,714 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1736327688] [2025-04-26 18:40:52,714 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:52,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:52,716 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 4 statements into 1 equivalence classes. [2025-04-26 18:40:52,718 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 4 of 4 statements. [2025-04-26 18:40:52,718 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:52,718 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:52,718 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:52,719 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 4 statements into 1 equivalence classes. [2025-04-26 18:40:52,721 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 4 of 4 statements. [2025-04-26 18:40:52,721 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:52,721 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:52,723 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:52,724 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:52,724 INFO L85 PathProgramCache]: Analyzing trace with hash 129848075, now seen corresponding path program 1 times [2025-04-26 18:40:52,724 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:52,724 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [943943031] [2025-04-26 18:40:52,724 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:52,724 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:52,728 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:40:52,731 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:52,731 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:52,731 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:52,732 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:52,733 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:40:52,741 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:52,741 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:52,741 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:52,743 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:52,743 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:52,743 INFO L85 PathProgramCache]: Analyzing trace with hash 720491450, now seen corresponding path program 1 times [2025-04-26 18:40:52,743 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:52,743 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [786761054] [2025-04-26 18:40:52,743 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:52,743 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:52,747 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-04-26 18:40:52,751 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-04-26 18:40:52,751 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:52,751 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:52,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:52,784 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:40:52,784 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [786761054] [2025-04-26 18:40:52,784 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [786761054] provided 1 perfect and 0 imperfect interpolant sequences [2025-04-26 18:40:52,784 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-04-26 18:40:52,784 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-04-26 18:40:52,784 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [153178860] [2025-04-26 18:40:52,785 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-04-26 18:40:52,862 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:40:52,863 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-04-26 18:40:52,863 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-04-26 18:40:52,863 INFO L87 Difference]: Start difference. First operand 370 states and 638 transitions. cyclomatic complexity: 312 Second operand has 3 states, 3 states have (on average 3.0) internal successors, (in total 9), 2 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:52,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:40:52,891 INFO L93 Difference]: Finished difference Result 428 states and 721 transitions. [2025-04-26 18:40:52,891 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 428 states and 721 transitions. [2025-04-26 18:40:52,893 INFO L131 ngComponentsAnalysis]: Automaton has 35 accepting balls. 230 [2025-04-26 18:40:52,895 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 428 states to 428 states and 721 transitions. [2025-04-26 18:40:52,895 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 285 [2025-04-26 18:40:52,896 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 285 [2025-04-26 18:40:52,896 INFO L74 IsDeterministic]: Start isDeterministic. Operand 428 states and 721 transitions. [2025-04-26 18:40:52,896 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:40:52,896 INFO L218 hiAutomatonCegarLoop]: Abstraction has 428 states and 721 transitions. [2025-04-26 18:40:52,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 428 states and 721 transitions. [2025-04-26 18:40:52,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 428 to 400. [2025-04-26 18:40:52,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 400 states, 400 states have (on average 1.7075) internal successors, (in total 683), 399 states have internal predecessors, (683), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:52,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 400 states to 400 states and 683 transitions. [2025-04-26 18:40:52,905 INFO L240 hiAutomatonCegarLoop]: Abstraction has 400 states and 683 transitions. [2025-04-26 18:40:52,905 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-04-26 18:40:52,906 INFO L438 stractBuchiCegarLoop]: Abstraction has 400 states and 683 transitions. [2025-04-26 18:40:52,906 INFO L340 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-04-26 18:40:52,906 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 400 states and 683 transitions. [2025-04-26 18:40:52,907 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 220 [2025-04-26 18:40:52,908 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:40:52,908 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:40:52,908 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2025-04-26 18:40:52,908 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2025-04-26 18:40:52,908 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[99] L41-->L49: Formula: (<= v_N_2 v_i_4) InVars {i=v_i_4, N=v_N_2} OutVars{i=v_i_4, N=v_N_2} AuxVars[] AssignedVars[]" "[101] L49-->thread1FINAL: Formula: (and (= (select v_q1_4 v_q1_back_10) 0) (= v_q1_back_9 (+ 1 v_q1_back_10))) InVars {q1=v_q1_4, q1_back=v_q1_back_10} OutVars{q1=v_q1_4, q1_back=v_q1_back_9} AuxVars[] AssignedVars[q1_back]" "[104] thread1FINAL-->thread1EXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" [2025-04-26 18:40:52,908 INFO L754 eck$LassoCheckResult]: Loop: "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" [2025-04-26 18:40:52,911 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:52,911 INFO L85 PathProgramCache]: Analyzing trace with hash -544269360, now seen corresponding path program 1 times [2025-04-26 18:40:52,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:52,911 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1806040371] [2025-04-26 18:40:52,911 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:52,911 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:52,914 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-04-26 18:40:52,919 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-04-26 18:40:52,919 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:52,919 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:52,920 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:52,922 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-04-26 18:40:52,925 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-04-26 18:40:52,926 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:52,926 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:52,927 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:52,927 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:52,927 INFO L85 PathProgramCache]: Analyzing trace with hash 129848075, now seen corresponding path program 2 times [2025-04-26 18:40:52,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:52,928 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1975036677] [2025-04-26 18:40:52,928 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-04-26 18:40:52,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:52,930 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:40:52,932 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:52,932 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-04-26 18:40:52,932 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:52,934 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:52,937 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:40:52,942 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:52,943 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:52,943 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:52,944 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:52,944 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:52,944 INFO L85 PathProgramCache]: Analyzing trace with hash -39698276, now seen corresponding path program 1 times [2025-04-26 18:40:52,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:52,945 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [994948919] [2025-04-26 18:40:52,945 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:52,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:52,949 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-04-26 18:40:52,958 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-04-26 18:40:52,958 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:52,958 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:52,958 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:52,961 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-04-26 18:40:52,992 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-04-26 18:40:52,992 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:52,992 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:52,994 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:53,194 INFO L206 LassoAnalysis]: Preferences: [2025-04-26 18:40:53,194 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-04-26 18:40:53,194 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-04-26 18:40:53,194 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-04-26 18:40:53,194 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-04-26 18:40:53,194 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:53,194 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-04-26 18:40:53,195 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-04-26 18:40:53,195 INFO L132 ssoRankerPreferences]: Filename of dumped script: ring-nondet.wvr.bpl_petrified1_Iteration4_Lasso [2025-04-26 18:40:53,195 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-04-26 18:40:53,195 INFO L243 LassoAnalysis]: Starting lasso preprocessing... [2025-04-26 18:40:53,196 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:53,256 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:53,258 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:53,260 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:53,262 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:53,264 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:53,266 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:53,268 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:53,270 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:53,272 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:53,455 INFO L261 LassoAnalysis]: Preprocessing complete. [2025-04-26 18:40:53,455 INFO L453 LassoAnalysis]: Using template 'affine'. [2025-04-26 18:40:53,455 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:53,456 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:53,457 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:53,459 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2025-04-26 18:40:53,459 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:53,469 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:53,469 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:53,470 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2025-04-26 18:40:53,470 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:53,482 INFO L402 nArgumentSynthesizer]: We have 16 Motzkin's Theorem applications. [2025-04-26 18:40:53,483 INFO L403 nArgumentSynthesizer]: A total of 4 supporting invariants were added. [2025-04-26 18:40:53,498 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:40:53,504 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2025-04-26 18:40:53,505 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:53,505 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:53,507 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:53,508 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2025-04-26 18:40:53,509 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:53,519 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:53,520 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:53,520 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:53,520 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:53,522 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:53,522 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:53,525 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:40:53,531 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2025-04-26 18:40:53,531 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:53,531 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:53,533 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:53,534 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2025-04-26 18:40:53,536 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:53,546 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:53,546 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:53,546 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:53,546 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:53,548 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:53,549 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:53,553 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-04-26 18:40:53,562 INFO L436 ModelExtractionUtils]: Simplification made 7 calls to the SMT solver. [2025-04-26 18:40:53,562 INFO L437 ModelExtractionUtils]: 1 out of 10 variables were initially zero. Simplification set additionally 6 variables to zero. [2025-04-26 18:40:53,562 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:53,562 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:53,564 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:53,566 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2025-04-26 18:40:53,566 INFO L436 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-04-26 18:40:53,584 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Ended with exit code 0 [2025-04-26 18:40:53,584 INFO L439 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2025-04-26 18:40:53,584 INFO L476 LassoAnalysis]: Proved termination. [2025-04-26 18:40:53,584 INFO L478 LassoAnalysis]: Termination argument consisting of: Ranking function f(q1_front, q1_back) = -1*q1_front + 1*q1_back Supporting invariants [] [2025-04-26 18:40:53,590 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2025-04-26 18:40:53,591 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2025-04-26 18:40:53,600 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:53,604 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-04-26 18:40:53,610 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-04-26 18:40:53,610 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:53,610 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:53,610 INFO L256 TraceCheckSpWp]: Trace formula consists of 31 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-04-26 18:40:53,611 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:53,622 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:40:53,624 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:53,624 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:53,624 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:53,624 INFO L256 TraceCheckSpWp]: Trace formula consists of 15 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-04-26 18:40:53,624 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:53,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:53,660 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2025-04-26 18:40:53,660 INFO L70 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 400 states and 683 transitions. cyclomatic complexity: 333 Second operand has 4 states, 4 states have (on average 2.75) internal successors, (in total 11), 4 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:53,700 INFO L74 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 400 states and 683 transitions. cyclomatic complexity: 333. Second operand has 4 states, 4 states have (on average 2.75) internal successors, (in total 11), 4 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) Result 895 states and 1433 transitions. Complement of second has 5 states. [2025-04-26 18:40:53,703 INFO L140 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-04-26 18:40:53,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 2.75) internal successors, (in total 11), 4 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:53,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 36 transitions. [2025-04-26 18:40:53,704 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 36 transitions. Stem has 6 letters. Loop has 5 letters. [2025-04-26 18:40:53,704 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:40:53,704 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 36 transitions. Stem has 11 letters. Loop has 5 letters. [2025-04-26 18:40:53,705 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:40:53,705 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 36 transitions. Stem has 6 letters. Loop has 10 letters. [2025-04-26 18:40:53,705 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:40:53,705 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 895 states and 1433 transitions. [2025-04-26 18:40:53,710 INFO L131 ngComponentsAnalysis]: Automaton has 54 accepting balls. 291 [2025-04-26 18:40:53,714 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 895 states to 740 states and 1205 transitions. [2025-04-26 18:40:53,714 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 383 [2025-04-26 18:40:53,714 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 405 [2025-04-26 18:40:53,715 INFO L74 IsDeterministic]: Start isDeterministic. Operand 740 states and 1205 transitions. [2025-04-26 18:40:53,715 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:40:53,715 INFO L218 hiAutomatonCegarLoop]: Abstraction has 740 states and 1205 transitions. [2025-04-26 18:40:53,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 740 states and 1205 transitions. [2025-04-26 18:40:53,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 740 to 629. [2025-04-26 18:40:53,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 629 states, 629 states have (on average 1.6645468998410176) internal successors, (in total 1047), 628 states have internal predecessors, (1047), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:53,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 629 states to 629 states and 1047 transitions. [2025-04-26 18:40:53,729 INFO L240 hiAutomatonCegarLoop]: Abstraction has 629 states and 1047 transitions. [2025-04-26 18:40:53,729 INFO L438 stractBuchiCegarLoop]: Abstraction has 629 states and 1047 transitions. [2025-04-26 18:40:53,729 INFO L340 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-04-26 18:40:53,729 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 629 states and 1047 transitions. [2025-04-26 18:40:53,731 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 236 [2025-04-26 18:40:53,731 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:40:53,731 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:40:53,731 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1] [2025-04-26 18:40:53,731 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2025-04-26 18:40:53,732 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:40:53,732 INFO L754 eck$LassoCheckResult]: Loop: "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" [2025-04-26 18:40:53,732 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:53,732 INFO L85 PathProgramCache]: Analyzing trace with hash 309129109, now seen corresponding path program 1 times [2025-04-26 18:40:53,732 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:53,732 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [226383066] [2025-04-26 18:40:53,732 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:53,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:53,736 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-04-26 18:40:53,740 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-04-26 18:40:53,740 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:53,740 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:53,740 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:53,741 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-04-26 18:40:53,745 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-04-26 18:40:53,747 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:53,747 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:53,749 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:53,749 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:53,750 INFO L85 PathProgramCache]: Analyzing trace with hash 131725895, now seen corresponding path program 3 times [2025-04-26 18:40:53,750 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:53,750 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [130148230] [2025-04-26 18:40:53,750 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-04-26 18:40:53,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:53,753 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:40:53,755 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:53,755 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-04-26 18:40:53,755 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:53,755 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:53,756 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:40:53,757 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:53,757 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:53,757 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:53,761 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:53,761 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:53,762 INFO L85 PathProgramCache]: Analyzing trace with hash 1807198003, now seen corresponding path program 1 times [2025-04-26 18:40:53,762 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:53,762 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [731510930] [2025-04-26 18:40:53,762 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:53,762 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:53,764 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 12 statements into 1 equivalence classes. [2025-04-26 18:40:53,771 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 12 of 12 statements. [2025-04-26 18:40:53,771 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:53,771 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:53,771 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:53,772 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 12 statements into 1 equivalence classes. [2025-04-26 18:40:53,775 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 12 of 12 statements. [2025-04-26 18:40:53,775 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:53,775 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:53,776 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:53,966 INFO L206 LassoAnalysis]: Preferences: [2025-04-26 18:40:53,966 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-04-26 18:40:53,966 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-04-26 18:40:53,966 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-04-26 18:40:53,966 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-04-26 18:40:53,966 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:53,966 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-04-26 18:40:53,966 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-04-26 18:40:53,966 INFO L132 ssoRankerPreferences]: Filename of dumped script: ring-nondet.wvr.bpl_petrified1_Iteration5_Lasso [2025-04-26 18:40:53,966 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-04-26 18:40:53,966 INFO L243 LassoAnalysis]: Starting lasso preprocessing... [2025-04-26 18:40:53,967 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:53,970 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:53,972 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:53,995 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:53,997 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:53,999 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:54,001 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:54,004 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:54,007 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:54,009 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:54,012 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:54,149 INFO L261 LassoAnalysis]: Preprocessing complete. [2025-04-26 18:40:54,149 INFO L453 LassoAnalysis]: Using template 'affine'. [2025-04-26 18:40:54,149 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:54,149 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:54,153 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:54,155 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2025-04-26 18:40:54,157 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:54,167 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:54,168 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:54,168 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:54,168 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:54,169 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:54,170 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:54,177 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:40:54,183 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2025-04-26 18:40:54,184 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:54,184 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:54,185 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:54,186 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2025-04-26 18:40:54,187 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:54,197 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:54,197 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:54,197 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:54,197 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:54,198 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:54,199 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:54,204 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:40:54,216 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2025-04-26 18:40:54,217 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:54,217 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:54,219 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:54,224 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2025-04-26 18:40:54,225 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:54,235 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:54,235 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:54,235 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:54,235 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:54,237 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:54,237 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:54,240 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:40:54,246 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2025-04-26 18:40:54,247 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:54,247 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:54,248 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:54,250 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2025-04-26 18:40:54,252 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:54,262 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:54,262 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:54,262 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:54,262 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:54,264 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:54,264 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:54,268 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-04-26 18:40:54,275 INFO L436 ModelExtractionUtils]: Simplification made 6 calls to the SMT solver. [2025-04-26 18:40:54,275 INFO L437 ModelExtractionUtils]: 4 out of 10 variables were initially zero. Simplification set additionally 3 variables to zero. [2025-04-26 18:40:54,276 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:54,276 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:54,278 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:54,279 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2025-04-26 18:40:54,280 INFO L436 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-04-26 18:40:54,297 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2025-04-26 18:40:54,297 INFO L439 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2025-04-26 18:40:54,297 INFO L476 LassoAnalysis]: Proved termination. [2025-04-26 18:40:54,297 INFO L478 LassoAnalysis]: Termination argument consisting of: Ranking function f(q1_back, q1_front) = 1*q1_back - 1*q1_front Supporting invariants [] [2025-04-26 18:40:54,303 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2025-04-26 18:40:54,304 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2025-04-26 18:40:54,311 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:54,320 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-04-26 18:40:54,323 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-04-26 18:40:54,323 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:54,323 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:54,324 INFO L256 TraceCheckSpWp]: Trace formula consists of 34 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-04-26 18:40:54,324 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:54,334 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:40:54,335 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:54,335 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:54,335 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:54,336 INFO L256 TraceCheckSpWp]: Trace formula consists of 15 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-04-26 18:40:54,336 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:54,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:54,355 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2025-04-26 18:40:54,355 INFO L70 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 629 states and 1047 transitions. cyclomatic complexity: 497 Second operand has 3 states, 3 states have (on average 4.0) internal successors, (in total 12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:54,385 INFO L74 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 629 states and 1047 transitions. cyclomatic complexity: 497. Second operand has 3 states, 3 states have (on average 4.0) internal successors, (in total 12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) Result 862 states and 1366 transitions. Complement of second has 5 states. [2025-04-26 18:40:54,386 INFO L140 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-04-26 18:40:54,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.0) internal successors, (in total 12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:54,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 36 transitions. [2025-04-26 18:40:54,388 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 36 transitions. Stem has 7 letters. Loop has 5 letters. [2025-04-26 18:40:54,388 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:40:54,388 INFO L699 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2025-04-26 18:40:54,405 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:54,409 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-04-26 18:40:54,412 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-04-26 18:40:54,412 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:54,412 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:54,413 INFO L256 TraceCheckSpWp]: Trace formula consists of 34 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-04-26 18:40:54,413 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:54,424 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:40:54,426 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:54,426 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:54,426 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:54,426 INFO L256 TraceCheckSpWp]: Trace formula consists of 15 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-04-26 18:40:54,427 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:54,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:54,445 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and with honda bouncer for loop.1 stem predicates 2 loop predicates [2025-04-26 18:40:54,445 INFO L70 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 629 states and 1047 transitions. cyclomatic complexity: 497 Second operand has 3 states, 3 states have (on average 4.0) internal successors, (in total 12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:54,476 INFO L74 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 629 states and 1047 transitions. cyclomatic complexity: 497. Second operand has 3 states, 3 states have (on average 4.0) internal successors, (in total 12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) Result 862 states and 1366 transitions. Complement of second has 5 states. [2025-04-26 18:40:54,477 INFO L140 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-04-26 18:40:54,478 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.0) internal successors, (in total 12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:54,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 36 transitions. [2025-04-26 18:40:54,478 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 36 transitions. Stem has 7 letters. Loop has 5 letters. [2025-04-26 18:40:54,478 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:40:54,478 INFO L699 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2025-04-26 18:40:54,487 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:54,494 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-04-26 18:40:54,497 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-04-26 18:40:54,497 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:54,497 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:54,498 INFO L256 TraceCheckSpWp]: Trace formula consists of 34 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-04-26 18:40:54,498 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:54,508 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:40:54,510 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:54,510 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:54,510 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:54,511 INFO L256 TraceCheckSpWp]: Trace formula consists of 15 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-04-26 18:40:54,511 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:54,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:54,531 INFO L141 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2025-04-26 18:40:54,531 INFO L70 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 629 states and 1047 transitions. cyclomatic complexity: 497 Second operand has 3 states, 3 states have (on average 4.0) internal successors, (in total 12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:54,569 INFO L74 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 629 states and 1047 transitions. cyclomatic complexity: 497. Second operand has 3 states, 3 states have (on average 4.0) internal successors, (in total 12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) Result 1165 states and 2041 transitions. Complement of second has 7 states. [2025-04-26 18:40:54,570 INFO L140 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-04-26 18:40:54,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.0) internal successors, (in total 12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:54,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 59 transitions. [2025-04-26 18:40:54,571 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 59 transitions. Stem has 7 letters. Loop has 5 letters. [2025-04-26 18:40:54,571 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:40:54,571 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 59 transitions. Stem has 12 letters. Loop has 5 letters. [2025-04-26 18:40:54,571 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:40:54,571 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 59 transitions. Stem has 7 letters. Loop has 10 letters. [2025-04-26 18:40:54,572 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:40:54,572 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1165 states and 2041 transitions. [2025-04-26 18:40:54,579 INFO L131 ngComponentsAnalysis]: Automaton has 46 accepting balls. 234 [2025-04-26 18:40:54,584 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1165 states to 909 states and 1589 transitions. [2025-04-26 18:40:54,584 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 363 [2025-04-26 18:40:54,585 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 426 [2025-04-26 18:40:54,585 INFO L74 IsDeterministic]: Start isDeterministic. Operand 909 states and 1589 transitions. [2025-04-26 18:40:54,585 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:40:54,585 INFO L218 hiAutomatonCegarLoop]: Abstraction has 909 states and 1589 transitions. [2025-04-26 18:40:54,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 909 states and 1589 transitions. [2025-04-26 18:40:54,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 909 to 579. [2025-04-26 18:40:54,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 579 states, 579 states have (on average 1.7512953367875648) internal successors, (in total 1014), 578 states have internal predecessors, (1014), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:54,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 579 states to 579 states and 1014 transitions. [2025-04-26 18:40:54,598 INFO L240 hiAutomatonCegarLoop]: Abstraction has 579 states and 1014 transitions. [2025-04-26 18:40:54,598 INFO L438 stractBuchiCegarLoop]: Abstraction has 579 states and 1014 transitions. [2025-04-26 18:40:54,598 INFO L340 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-04-26 18:40:54,599 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 579 states and 1014 transitions. [2025-04-26 18:40:54,601 INFO L131 ngComponentsAnalysis]: Automaton has 35 accepting balls. 196 [2025-04-26 18:40:54,601 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:40:54,601 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:40:54,601 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-04-26 18:40:54,601 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2025-04-26 18:40:54,602 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[105] L58-->thread2FINAL: Formula: (not v_f_3) InVars {f=v_f_3} OutVars{f=v_f_3} AuxVars[] AssignedVars[]" "[107] thread2FINAL-->thread2EXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" [2025-04-26 18:40:54,602 INFO L754 eck$LassoCheckResult]: Loop: "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" [2025-04-26 18:40:54,602 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:54,603 INFO L85 PathProgramCache]: Analyzing trace with hash 993042790, now seen corresponding path program 1 times [2025-04-26 18:40:54,603 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:54,603 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [919960584] [2025-04-26 18:40:54,603 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:54,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:54,606 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-04-26 18:40:54,608 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-04-26 18:40:54,609 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:54,609 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:54,629 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:54,629 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:40:54,629 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [919960584] [2025-04-26 18:40:54,629 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [919960584] provided 1 perfect and 0 imperfect interpolant sequences [2025-04-26 18:40:54,629 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-04-26 18:40:54,629 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-04-26 18:40:54,630 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [464994340] [2025-04-26 18:40:54,630 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-04-26 18:40:54,630 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:40:54,630 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:54,630 INFO L85 PathProgramCache]: Analyzing trace with hash 138406030, now seen corresponding path program 1 times [2025-04-26 18:40:54,630 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:54,630 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1381044983] [2025-04-26 18:40:54,630 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:54,630 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:54,632 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:40:54,637 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:54,637 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:54,637 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:54,637 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:54,638 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:40:54,639 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:54,639 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:54,639 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:54,640 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:54,706 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:40:54,706 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-04-26 18:40:54,706 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-04-26 18:40:54,706 INFO L87 Difference]: Start difference. First operand 579 states and 1014 transitions. cyclomatic complexity: 493 Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (in total 8), 2 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:54,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:40:54,728 INFO L93 Difference]: Finished difference Result 583 states and 1017 transitions. [2025-04-26 18:40:54,728 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 583 states and 1017 transitions. [2025-04-26 18:40:54,730 INFO L131 ngComponentsAnalysis]: Automaton has 35 accepting balls. 196 [2025-04-26 18:40:54,733 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 583 states to 583 states and 1017 transitions. [2025-04-26 18:40:54,733 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 304 [2025-04-26 18:40:54,733 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 304 [2025-04-26 18:40:54,733 INFO L74 IsDeterministic]: Start isDeterministic. Operand 583 states and 1017 transitions. [2025-04-26 18:40:54,733 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:40:54,733 INFO L218 hiAutomatonCegarLoop]: Abstraction has 583 states and 1017 transitions. [2025-04-26 18:40:54,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 583 states and 1017 transitions. [2025-04-26 18:40:54,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 583 to 581. [2025-04-26 18:40:54,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 581 states, 581 states have (on average 1.7469879518072289) internal successors, (in total 1015), 580 states have internal predecessors, (1015), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:54,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 581 states to 581 states and 1015 transitions. [2025-04-26 18:40:54,748 INFO L240 hiAutomatonCegarLoop]: Abstraction has 581 states and 1015 transitions. [2025-04-26 18:40:54,750 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-04-26 18:40:54,752 INFO L438 stractBuchiCegarLoop]: Abstraction has 581 states and 1015 transitions. [2025-04-26 18:40:54,752 INFO L340 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-04-26 18:40:54,753 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 581 states and 1015 transitions. [2025-04-26 18:40:54,754 INFO L131 ngComponentsAnalysis]: Automaton has 35 accepting balls. 196 [2025-04-26 18:40:54,754 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:40:54,754 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:40:54,755 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-04-26 18:40:54,755 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2025-04-26 18:40:54,755 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[99] L41-->L49: Formula: (<= v_N_2 v_i_4) InVars {i=v_i_4, N=v_N_2} OutVars{i=v_i_4, N=v_N_2} AuxVars[] AssignedVars[]" "[101] L49-->thread1FINAL: Formula: (and (= (select v_q1_4 v_q1_back_10) 0) (= v_q1_back_9 (+ 1 v_q1_back_10))) InVars {q1=v_q1_4, q1_back=v_q1_back_10} OutVars{q1=v_q1_4, q1_back=v_q1_back_9} AuxVars[] AssignedVars[q1_back]" [2025-04-26 18:40:54,755 INFO L754 eck$LassoCheckResult]: Loop: "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" [2025-04-26 18:40:54,756 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:54,756 INFO L85 PathProgramCache]: Analyzing trace with hash 993067857, now seen corresponding path program 1 times [2025-04-26 18:40:54,756 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:54,756 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1106764551] [2025-04-26 18:40:54,756 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:54,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:54,758 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-04-26 18:40:54,762 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-04-26 18:40:54,762 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:54,762 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:54,762 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:54,763 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-04-26 18:40:54,766 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-04-26 18:40:54,766 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:54,766 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:54,767 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:54,768 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:54,768 INFO L85 PathProgramCache]: Analyzing trace with hash 131725895, now seen corresponding path program 4 times [2025-04-26 18:40:54,768 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:54,768 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [981224764] [2025-04-26 18:40:54,768 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-04-26 18:40:54,768 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:54,771 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 5 statements into 2 equivalence classes. [2025-04-26 18:40:54,776 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:54,776 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-04-26 18:40:54,776 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:54,776 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:54,777 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:40:54,778 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:54,778 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:54,778 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:54,778 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:54,779 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:54,779 INFO L85 PathProgramCache]: Analyzing trace with hash -900298505, now seen corresponding path program 1 times [2025-04-26 18:40:54,779 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:54,779 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [12460503] [2025-04-26 18:40:54,779 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:54,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:54,781 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes. [2025-04-26 18:40:54,784 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements. [2025-04-26 18:40:54,784 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:54,784 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:54,784 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:54,785 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes. [2025-04-26 18:40:54,787 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements. [2025-04-26 18:40:54,788 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:54,788 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:54,789 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:54,955 INFO L206 LassoAnalysis]: Preferences: [2025-04-26 18:40:54,955 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-04-26 18:40:54,955 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-04-26 18:40:54,955 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-04-26 18:40:54,955 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-04-26 18:40:54,955 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:54,955 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-04-26 18:40:54,956 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-04-26 18:40:54,956 INFO L132 ssoRankerPreferences]: Filename of dumped script: ring-nondet.wvr.bpl_petrified1_Iteration7_Lasso [2025-04-26 18:40:54,956 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-04-26 18:40:54,956 INFO L243 LassoAnalysis]: Starting lasso preprocessing... [2025-04-26 18:40:54,957 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:54,959 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:54,960 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:54,962 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:54,964 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:54,966 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:54,968 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:54,971 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:55,001 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:55,006 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:55,009 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:55,138 INFO L261 LassoAnalysis]: Preprocessing complete. [2025-04-26 18:40:55,138 INFO L453 LassoAnalysis]: Using template 'affine'. [2025-04-26 18:40:55,139 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:55,139 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:55,140 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:55,144 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2025-04-26 18:40:55,144 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:55,154 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:55,155 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:55,155 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:55,155 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:55,156 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:55,156 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:55,159 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:40:55,164 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2025-04-26 18:40:55,165 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:55,165 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:55,167 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:55,169 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2025-04-26 18:40:55,170 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:55,180 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:55,181 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:55,181 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:55,181 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:55,182 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:55,182 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:55,184 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:40:55,190 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Ended with exit code 0 [2025-04-26 18:40:55,191 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:55,191 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:55,193 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:55,198 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2025-04-26 18:40:55,198 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:55,211 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:55,211 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:55,211 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:55,211 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:55,213 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:55,213 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:55,215 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:40:55,221 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2025-04-26 18:40:55,222 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:55,222 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:55,223 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:55,224 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2025-04-26 18:40:55,226 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:55,236 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:55,236 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:55,236 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:55,236 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:55,237 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:55,237 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:55,240 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:40:55,245 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Ended with exit code 0 [2025-04-26 18:40:55,245 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:55,245 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:55,247 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:55,250 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2025-04-26 18:40:55,251 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:55,260 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:55,261 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:55,261 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:55,261 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:55,262 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:55,262 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:55,264 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:40:55,269 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2025-04-26 18:40:55,270 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:55,270 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:55,272 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:55,272 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2025-04-26 18:40:55,274 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:55,283 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:55,284 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:55,284 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:55,284 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:55,285 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:55,285 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:55,289 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:40:55,295 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Ended with exit code 0 [2025-04-26 18:40:55,295 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:55,295 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:55,297 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:55,297 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2025-04-26 18:40:55,300 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:55,309 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:55,309 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:55,309 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:55,309 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:55,310 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:55,310 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:55,313 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:40:55,318 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Forceful destruction successful, exit code 0 [2025-04-26 18:40:55,319 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:55,319 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:55,320 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:55,322 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2025-04-26 18:40:55,322 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:55,332 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:55,332 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:55,332 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:55,332 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:55,337 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:55,337 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:55,341 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-04-26 18:40:55,348 INFO L436 ModelExtractionUtils]: Simplification made 8 calls to the SMT solver. [2025-04-26 18:40:55,348 INFO L437 ModelExtractionUtils]: 1 out of 10 variables were initially zero. Simplification set additionally 6 variables to zero. [2025-04-26 18:40:55,348 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:55,349 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:55,350 INFO L229 MonitoredProcess]: Starting monitored process 25 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:55,352 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2025-04-26 18:40:55,353 INFO L436 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-04-26 18:40:55,368 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Forceful destruction successful, exit code 0 [2025-04-26 18:40:55,369 INFO L439 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2025-04-26 18:40:55,369 INFO L476 LassoAnalysis]: Proved termination. [2025-04-26 18:40:55,369 INFO L478 LassoAnalysis]: Termination argument consisting of: Ranking function f(q1_front, q1_back) = -1*q1_front + 1*q1_back Supporting invariants [] [2025-04-26 18:40:55,374 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Ended with exit code 0 [2025-04-26 18:40:55,376 INFO L156 tatePredicateManager]: 1 out of 1 supporting invariants were superfluous and have been removed [2025-04-26 18:40:55,383 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:55,388 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-04-26 18:40:55,391 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-04-26 18:40:55,391 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:55,391 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:55,391 INFO L256 TraceCheckSpWp]: Trace formula consists of 38 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-04-26 18:40:55,392 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:55,403 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:40:55,407 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:55,407 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:55,407 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:55,407 INFO L256 TraceCheckSpWp]: Trace formula consists of 15 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-04-26 18:40:55,408 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:55,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:55,430 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2025-04-26 18:40:55,430 INFO L70 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 581 states and 1015 transitions. cyclomatic complexity: 492 Second operand has 3 states, 3 states have (on average 4.333333333333333) internal successors, (in total 13), 3 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:55,459 INFO L74 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 581 states and 1015 transitions. cyclomatic complexity: 492. Second operand has 3 states, 3 states have (on average 4.333333333333333) internal successors, (in total 13), 3 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) Result 845 states and 1398 transitions. Complement of second has 4 states. [2025-04-26 18:40:55,460 INFO L140 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-04-26 18:40:55,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.333333333333333) internal successors, (in total 13), 3 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:55,460 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 55 transitions. [2025-04-26 18:40:55,460 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 55 transitions. Stem has 8 letters. Loop has 5 letters. [2025-04-26 18:40:55,461 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:40:55,461 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 55 transitions. Stem has 13 letters. Loop has 5 letters. [2025-04-26 18:40:55,461 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:40:55,461 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 55 transitions. Stem has 8 letters. Loop has 10 letters. [2025-04-26 18:40:55,461 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:40:55,461 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 845 states and 1398 transitions. [2025-04-26 18:40:55,466 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 81 [2025-04-26 18:40:55,469 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 845 states to 579 states and 966 transitions. [2025-04-26 18:40:55,469 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 204 [2025-04-26 18:40:55,469 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 240 [2025-04-26 18:40:55,469 INFO L74 IsDeterministic]: Start isDeterministic. Operand 579 states and 966 transitions. [2025-04-26 18:40:55,469 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:40:55,469 INFO L218 hiAutomatonCegarLoop]: Abstraction has 579 states and 966 transitions. [2025-04-26 18:40:55,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 579 states and 966 transitions. [2025-04-26 18:40:55,477 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 579 to 471. [2025-04-26 18:40:55,478 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 471 states, 471 states have (on average 1.7367303609341826) internal successors, (in total 818), 470 states have internal predecessors, (818), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:55,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 471 states to 471 states and 818 transitions. [2025-04-26 18:40:55,479 INFO L240 hiAutomatonCegarLoop]: Abstraction has 471 states and 818 transitions. [2025-04-26 18:40:55,479 INFO L438 stractBuchiCegarLoop]: Abstraction has 471 states and 818 transitions. [2025-04-26 18:40:55,479 INFO L340 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-04-26 18:40:55,479 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 471 states and 818 transitions. [2025-04-26 18:40:55,481 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 81 [2025-04-26 18:40:55,481 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:40:55,481 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:40:55,481 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-04-26 18:40:55,481 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2025-04-26 18:40:55,481 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" [2025-04-26 18:40:55,481 INFO L754 eck$LassoCheckResult]: Loop: "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" [2025-04-26 18:40:55,482 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:55,482 INFO L85 PathProgramCache]: Analyzing trace with hash 993091369, now seen corresponding path program 1 times [2025-04-26 18:40:55,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:55,482 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [293405407] [2025-04-26 18:40:55,482 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:55,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:55,484 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-04-26 18:40:55,487 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-04-26 18:40:55,487 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:55,487 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:55,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:55,508 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:40:55,508 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [293405407] [2025-04-26 18:40:55,508 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [293405407] provided 1 perfect and 0 imperfect interpolant sequences [2025-04-26 18:40:55,508 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-04-26 18:40:55,508 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2025-04-26 18:40:55,508 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [62144638] [2025-04-26 18:40:55,508 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-04-26 18:40:55,508 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:40:55,509 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:55,509 INFO L85 PathProgramCache]: Analyzing trace with hash 139360150, now seen corresponding path program 2 times [2025-04-26 18:40:55,509 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:55,509 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [582047573] [2025-04-26 18:40:55,509 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-04-26 18:40:55,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:55,510 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:40:55,511 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:55,511 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-04-26 18:40:55,511 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:55,512 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:55,512 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:40:55,513 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:55,513 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:55,513 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:55,514 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:55,562 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:40:55,562 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-04-26 18:40:55,562 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-04-26 18:40:55,562 INFO L87 Difference]: Start difference. First operand 471 states and 818 transitions. cyclomatic complexity: 394 Second operand has 3 states, 2 states have (on average 4.0) internal successors, (in total 8), 2 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:55,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:40:55,579 INFO L93 Difference]: Finished difference Result 504 states and 870 transitions. [2025-04-26 18:40:55,579 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 870 transitions. [2025-04-26 18:40:55,581 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 81 [2025-04-26 18:40:55,583 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 499 states and 863 transitions. [2025-04-26 18:40:55,583 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 194 [2025-04-26 18:40:55,584 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 194 [2025-04-26 18:40:55,584 INFO L74 IsDeterministic]: Start isDeterministic. Operand 499 states and 863 transitions. [2025-04-26 18:40:55,584 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:40:55,584 INFO L218 hiAutomatonCegarLoop]: Abstraction has 499 states and 863 transitions. [2025-04-26 18:40:55,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 499 states and 863 transitions. [2025-04-26 18:40:55,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 499 to 486. [2025-04-26 18:40:55,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 486 states, 486 states have (on average 1.7345679012345678) internal successors, (in total 843), 485 states have internal predecessors, (843), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:55,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 486 states and 843 transitions. [2025-04-26 18:40:55,592 INFO L240 hiAutomatonCegarLoop]: Abstraction has 486 states and 843 transitions. [2025-04-26 18:40:55,592 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-04-26 18:40:55,592 INFO L438 stractBuchiCegarLoop]: Abstraction has 486 states and 843 transitions. [2025-04-26 18:40:55,592 INFO L340 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-04-26 18:40:55,592 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 486 states and 843 transitions. [2025-04-26 18:40:55,594 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 81 [2025-04-26 18:40:55,594 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:40:55,594 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:40:55,594 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-04-26 18:40:55,594 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2025-04-26 18:40:55,595 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[99] L41-->L49: Formula: (<= v_N_2 v_i_4) InVars {i=v_i_4, N=v_N_2} OutVars{i=v_i_4, N=v_N_2} AuxVars[] AssignedVars[]" "[101] L49-->thread1FINAL: Formula: (and (= (select v_q1_4 v_q1_back_10) 0) (= v_q1_back_9 (+ 1 v_q1_back_10))) InVars {q1=v_q1_4, q1_back=v_q1_back_10} OutVars{q1=v_q1_4, q1_back=v_q1_back_9} AuxVars[] AssignedVars[q1_back]" "[104] thread1FINAL-->thread1EXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[105] L58-->thread2FINAL: Formula: (not v_f_3) InVars {f=v_f_3} OutVars{f=v_f_3} AuxVars[] AssignedVars[]" [2025-04-26 18:40:55,595 INFO L754 eck$LassoCheckResult]: Loop: "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" [2025-04-26 18:40:55,595 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:55,595 INFO L85 PathProgramCache]: Analyzing trace with hash 504681350, now seen corresponding path program 1 times [2025-04-26 18:40:55,595 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:55,595 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1424907438] [2025-04-26 18:40:55,595 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:55,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:55,598 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes. [2025-04-26 18:40:55,600 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements. [2025-04-26 18:40:55,601 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:55,601 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:55,601 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:55,602 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes. [2025-04-26 18:40:55,604 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements. [2025-04-26 18:40:55,604 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:55,604 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:55,606 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:55,606 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:55,606 INFO L85 PathProgramCache]: Analyzing trace with hash 136528210, now seen corresponding path program 3 times [2025-04-26 18:40:55,606 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:55,606 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1168932820] [2025-04-26 18:40:55,606 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-04-26 18:40:55,606 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:55,608 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:40:55,609 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:55,609 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-04-26 18:40:55,609 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:55,609 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:55,610 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:40:55,611 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:55,611 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:55,611 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:55,613 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:55,613 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:55,613 INFO L85 PathProgramCache]: Analyzing trace with hash -2012292883, now seen corresponding path program 1 times [2025-04-26 18:40:55,613 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:55,613 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [724663464] [2025-04-26 18:40:55,614 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:55,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:55,616 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 18 statements into 1 equivalence classes. [2025-04-26 18:40:55,629 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 18 of 18 statements. [2025-04-26 18:40:55,629 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:55,629 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:55,629 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:55,631 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 18 statements into 1 equivalence classes. [2025-04-26 18:40:55,637 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 18 of 18 statements. [2025-04-26 18:40:55,637 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:55,637 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:55,640 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:55,896 INFO L206 LassoAnalysis]: Preferences: [2025-04-26 18:40:55,896 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-04-26 18:40:55,896 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-04-26 18:40:55,896 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-04-26 18:40:55,896 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-04-26 18:40:55,896 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:55,896 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-04-26 18:40:55,896 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-04-26 18:40:55,896 INFO L132 ssoRankerPreferences]: Filename of dumped script: ring-nondet.wvr.bpl_petrified1_Iteration9_Lasso [2025-04-26 18:40:55,896 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-04-26 18:40:55,896 INFO L243 LassoAnalysis]: Starting lasso preprocessing... [2025-04-26 18:40:55,898 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:55,989 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:55,994 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:55,996 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:55,998 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:56,000 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:56,002 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:56,003 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:56,005 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:56,009 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:56,011 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:56,241 INFO L261 LassoAnalysis]: Preprocessing complete. [2025-04-26 18:40:56,241 INFO L453 LassoAnalysis]: Using template 'affine'. [2025-04-26 18:40:56,241 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:56,241 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:56,243 INFO L229 MonitoredProcess]: Starting monitored process 26 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:56,245 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2025-04-26 18:40:56,247 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:56,257 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:56,257 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:56,257 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:56,257 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:56,258 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:56,259 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:56,262 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:40:56,267 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Ended with exit code 0 [2025-04-26 18:40:56,268 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:56,268 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:56,269 INFO L229 MonitoredProcess]: Starting monitored process 27 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:56,270 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2025-04-26 18:40:56,271 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:56,281 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:56,281 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:56,281 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2025-04-26 18:40:56,281 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:56,299 INFO L402 nArgumentSynthesizer]: We have 16 Motzkin's Theorem applications. [2025-04-26 18:40:56,299 INFO L403 nArgumentSynthesizer]: A total of 4 supporting invariants were added. [2025-04-26 18:40:56,321 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:40:56,328 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Ended with exit code 0 [2025-04-26 18:40:56,328 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:56,329 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:56,330 INFO L229 MonitoredProcess]: Starting monitored process 28 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:56,332 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2025-04-26 18:40:56,333 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:56,343 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:56,343 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:56,343 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:56,343 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:56,345 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:56,345 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:56,349 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-04-26 18:40:56,357 INFO L436 ModelExtractionUtils]: Simplification made 6 calls to the SMT solver. [2025-04-26 18:40:56,358 INFO L437 ModelExtractionUtils]: 4 out of 10 variables were initially zero. Simplification set additionally 3 variables to zero. [2025-04-26 18:40:56,358 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:56,358 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:56,360 INFO L229 MonitoredProcess]: Starting monitored process 29 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:56,361 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2025-04-26 18:40:56,363 INFO L436 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-04-26 18:40:56,380 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Forceful destruction successful, exit code 0 [2025-04-26 18:40:56,381 INFO L439 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2025-04-26 18:40:56,381 INFO L476 LassoAnalysis]: Proved termination. [2025-04-26 18:40:56,381 INFO L478 LassoAnalysis]: Termination argument consisting of: Ranking function f(q2_back, q2_front) = 1*q2_back - 1*q2_front Supporting invariants [] [2025-04-26 18:40:56,387 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Ended with exit code 0 [2025-04-26 18:40:56,397 INFO L156 tatePredicateManager]: 1 out of 1 supporting invariants were superfluous and have been removed [2025-04-26 18:40:56,405 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:56,409 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes. [2025-04-26 18:40:56,415 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements. [2025-04-26 18:40:56,415 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:56,415 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:56,416 INFO L256 TraceCheckSpWp]: Trace formula consists of 51 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-04-26 18:40:56,416 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:56,432 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:40:56,434 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:56,434 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:56,434 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:56,435 INFO L256 TraceCheckSpWp]: Trace formula consists of 15 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-04-26 18:40:56,435 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:56,454 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:56,455 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2025-04-26 18:40:56,455 INFO L70 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 486 states and 843 transitions. cyclomatic complexity: 406 Second operand has 4 states, 4 states have (on average 4.5) internal successors, (in total 18), 4 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:56,480 INFO L74 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 486 states and 843 transitions. cyclomatic complexity: 406. Second operand has 4 states, 4 states have (on average 4.5) internal successors, (in total 18), 4 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) Result 615 states and 1063 transitions. Complement of second has 4 states. [2025-04-26 18:40:56,481 INFO L140 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-04-26 18:40:56,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 4.5) internal successors, (in total 18), 4 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:56,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 51 transitions. [2025-04-26 18:40:56,482 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 51 transitions. Stem has 13 letters. Loop has 5 letters. [2025-04-26 18:40:56,482 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:40:56,482 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 51 transitions. Stem has 18 letters. Loop has 5 letters. [2025-04-26 18:40:56,482 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:40:56,482 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 51 transitions. Stem has 13 letters. Loop has 10 letters. [2025-04-26 18:40:56,482 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:40:56,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 615 states and 1063 transitions. [2025-04-26 18:40:56,485 INFO L131 ngComponentsAnalysis]: Automaton has 17 accepting balls. 38 [2025-04-26 18:40:56,486 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 615 states to 324 states and 612 transitions. [2025-04-26 18:40:56,486 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 86 [2025-04-26 18:40:56,486 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 90 [2025-04-26 18:40:56,486 INFO L74 IsDeterministic]: Start isDeterministic. Operand 324 states and 612 transitions. [2025-04-26 18:40:56,486 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:40:56,487 INFO L218 hiAutomatonCegarLoop]: Abstraction has 324 states and 612 transitions. [2025-04-26 18:40:56,487 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 324 states and 612 transitions. [2025-04-26 18:40:56,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 324 to 315. [2025-04-26 18:40:56,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 315 states, 315 states have (on average 1.9015873015873015) internal successors, (in total 599), 314 states have internal predecessors, (599), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:56,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 315 states to 315 states and 599 transitions. [2025-04-26 18:40:56,491 INFO L240 hiAutomatonCegarLoop]: Abstraction has 315 states and 599 transitions. [2025-04-26 18:40:56,491 INFO L438 stractBuchiCegarLoop]: Abstraction has 315 states and 599 transitions. [2025-04-26 18:40:56,491 INFO L340 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-04-26 18:40:56,491 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 315 states and 599 transitions. [2025-04-26 18:40:56,493 INFO L131 ngComponentsAnalysis]: Automaton has 17 accepting balls. 38 [2025-04-26 18:40:56,493 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:40:56,493 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:40:56,494 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-04-26 18:40:56,494 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2025-04-26 18:40:56,494 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" [2025-04-26 18:40:56,494 INFO L754 eck$LassoCheckResult]: Loop: "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" [2025-04-26 18:40:56,494 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:56,494 INFO L85 PathProgramCache]: Analyzing trace with hash -1784794354, now seen corresponding path program 1 times [2025-04-26 18:40:56,495 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:56,495 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [729300705] [2025-04-26 18:40:56,495 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:56,495 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:56,501 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 15 statements into 1 equivalence classes. [2025-04-26 18:40:56,505 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 15 of 15 statements. [2025-04-26 18:40:56,505 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:56,505 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:56,505 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:56,509 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 15 statements into 1 equivalence classes. [2025-04-26 18:40:56,513 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 15 of 15 statements. [2025-04-26 18:40:56,513 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:56,513 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:56,516 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:56,517 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:56,517 INFO L85 PathProgramCache]: Analyzing trace with hash 139360150, now seen corresponding path program 4 times [2025-04-26 18:40:56,517 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:56,517 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981993286] [2025-04-26 18:40:56,517 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-04-26 18:40:56,517 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:56,520 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 5 statements into 2 equivalence classes. [2025-04-26 18:40:56,521 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:56,521 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-04-26 18:40:56,521 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:56,521 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:56,522 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:40:56,522 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:56,522 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:56,522 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:56,525 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:56,526 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:56,526 INFO L85 PathProgramCache]: Analyzing trace with hash 1657218217, now seen corresponding path program 1 times [2025-04-26 18:40:56,526 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:56,526 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1157958347] [2025-04-26 18:40:56,526 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:56,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:56,528 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 20 statements into 1 equivalence classes. [2025-04-26 18:40:56,535 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 20 of 20 statements. [2025-04-26 18:40:56,536 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:56,536 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:56,604 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2025-04-26 18:40:56,604 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:40:56,604 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1157958347] [2025-04-26 18:40:56,604 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1157958347] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:40:56,604 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [287653795] [2025-04-26 18:40:56,604 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:56,605 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:40:56,605 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:56,606 INFO L229 MonitoredProcess]: Starting monitored process 30 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:40:56,608 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2025-04-26 18:40:56,628 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 20 statements into 1 equivalence classes. [2025-04-26 18:40:56,635 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 20 of 20 statements. [2025-04-26 18:40:56,635 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:56,635 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:56,636 INFO L256 TraceCheckSpWp]: Trace formula consists of 72 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-04-26 18:40:56,636 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:56,663 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2025-04-26 18:40:56,663 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:40:56,696 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2025-04-26 18:40:56,696 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [287653795] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:40:56,697 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:40:56,697 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 3 [2025-04-26 18:40:56,697 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2026453787] [2025-04-26 18:40:56,697 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:40:56,749 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:40:56,749 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-04-26 18:40:56,749 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2025-04-26 18:40:56,749 INFO L87 Difference]: Start difference. First operand 315 states and 599 transitions. cyclomatic complexity: 325 Second operand has 5 states, 4 states have (on average 6.75) internal successors, (in total 27), 4 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:56,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:40:56,774 INFO L93 Difference]: Finished difference Result 701 states and 1350 transitions. [2025-04-26 18:40:56,775 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 701 states and 1350 transitions. [2025-04-26 18:40:56,778 INFO L131 ngComponentsAnalysis]: Automaton has 43 accepting balls. 90 [2025-04-26 18:40:56,781 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 701 states to 677 states and 1313 transitions. [2025-04-26 18:40:56,781 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 190 [2025-04-26 18:40:56,782 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195 [2025-04-26 18:40:56,782 INFO L74 IsDeterministic]: Start isDeterministic. Operand 677 states and 1313 transitions. [2025-04-26 18:40:56,782 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:40:56,782 INFO L218 hiAutomatonCegarLoop]: Abstraction has 677 states and 1313 transitions. [2025-04-26 18:40:56,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 677 states and 1313 transitions. [2025-04-26 18:40:56,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 677 to 428. [2025-04-26 18:40:56,788 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 428 states, 428 states have (on average 1.808411214953271) internal successors, (in total 774), 427 states have internal predecessors, (774), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:56,789 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 428 states to 428 states and 774 transitions. [2025-04-26 18:40:56,789 INFO L240 hiAutomatonCegarLoop]: Abstraction has 428 states and 774 transitions. [2025-04-26 18:40:56,789 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-04-26 18:40:56,790 INFO L438 stractBuchiCegarLoop]: Abstraction has 428 states and 774 transitions. [2025-04-26 18:40:56,790 INFO L340 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-04-26 18:40:56,790 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 428 states and 774 transitions. [2025-04-26 18:40:56,791 INFO L131 ngComponentsAnalysis]: Automaton has 19 accepting balls. 42 [2025-04-26 18:40:56,791 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:40:56,791 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:40:56,792 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-04-26 18:40:56,792 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:40:56,792 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[105] L58-->thread2FINAL: Formula: (not v_f_3) InVars {f=v_f_3} OutVars{f=v_f_3} AuxVars[] AssignedVars[]" "[107] thread2FINAL-->thread2EXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" [2025-04-26 18:40:56,792 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:40:56,792 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:56,792 INFO L85 PathProgramCache]: Analyzing trace with hash -560578295, now seen corresponding path program 1 times [2025-04-26 18:40:56,792 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:56,792 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [342004178] [2025-04-26 18:40:56,792 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:56,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:56,795 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 18 statements into 1 equivalence classes. [2025-04-26 18:40:56,797 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 18 of 18 statements. [2025-04-26 18:40:56,797 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:56,797 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:56,856 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:56,856 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:40:56,856 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [342004178] [2025-04-26 18:40:56,857 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [342004178] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:40:56,857 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [112999550] [2025-04-26 18:40:56,857 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:56,857 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:40:56,857 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:56,859 INFO L229 MonitoredProcess]: Starting monitored process 31 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:40:56,860 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2025-04-26 18:40:56,881 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 18 statements into 1 equivalence classes. [2025-04-26 18:40:56,887 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 18 of 18 statements. [2025-04-26 18:40:56,887 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:56,887 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:56,887 INFO L256 TraceCheckSpWp]: Trace formula consists of 66 conjuncts, 6 conjuncts are in the unsatisfiable core [2025-04-26 18:40:56,888 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:56,912 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:40:56,923 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:56,923 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:40:56,963 INFO L325 Elim1Store]: treesize reduction 5, result has 37.5 percent of original size [2025-04-26 18:40:56,963 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 11 treesize of output 10 [2025-04-26 18:40:56,967 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:56,967 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [112999550] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:40:56,967 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:40:56,967 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 9 [2025-04-26 18:40:56,968 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1119221083] [2025-04-26 18:40:56,968 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:40:56,968 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:40:56,968 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:56,968 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 2 times [2025-04-26 18:40:56,968 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:56,968 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [827823013] [2025-04-26 18:40:56,968 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-04-26 18:40:56,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:56,970 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:40:56,970 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:40:56,971 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-04-26 18:40:56,971 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:56,971 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:56,971 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:40:56,972 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:40:56,972 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:56,972 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:56,972 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:56,993 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:40:56,993 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-04-26 18:40:56,993 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2025-04-26 18:40:56,993 INFO L87 Difference]: Start difference. First operand 428 states and 774 transitions. cyclomatic complexity: 394 Second operand has 10 states, 10 states have (on average 3.4) internal successors, (in total 34), 9 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:57,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:40:57,063 INFO L93 Difference]: Finished difference Result 472 states and 852 transitions. [2025-04-26 18:40:57,064 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 472 states and 852 transitions. [2025-04-26 18:40:57,066 INFO L131 ngComponentsAnalysis]: Automaton has 22 accepting balls. 48 [2025-04-26 18:40:57,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 472 states to 472 states and 852 transitions. [2025-04-26 18:40:57,067 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 126 [2025-04-26 18:40:57,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 126 [2025-04-26 18:40:57,068 INFO L74 IsDeterministic]: Start isDeterministic. Operand 472 states and 852 transitions. [2025-04-26 18:40:57,068 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:40:57,068 INFO L218 hiAutomatonCegarLoop]: Abstraction has 472 states and 852 transitions. [2025-04-26 18:40:57,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 472 states and 852 transitions. [2025-04-26 18:40:57,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 472 to 417. [2025-04-26 18:40:57,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 417 states, 417 states have (on average 1.815347721822542) internal successors, (in total 757), 416 states have internal predecessors, (757), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:57,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 417 states to 417 states and 757 transitions. [2025-04-26 18:40:57,074 INFO L240 hiAutomatonCegarLoop]: Abstraction has 417 states and 757 transitions. [2025-04-26 18:40:57,074 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-04-26 18:40:57,074 INFO L438 stractBuchiCegarLoop]: Abstraction has 417 states and 757 transitions. [2025-04-26 18:40:57,074 INFO L340 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-04-26 18:40:57,074 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 417 states and 757 transitions. [2025-04-26 18:40:57,075 INFO L131 ngComponentsAnalysis]: Automaton has 19 accepting balls. 42 [2025-04-26 18:40:57,075 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:40:57,075 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:40:57,076 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-04-26 18:40:57,076 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:40:57,076 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:40:57,076 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:40:57,076 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:57,076 INFO L85 PathProgramCache]: Analyzing trace with hash 1716026633, now seen corresponding path program 1 times [2025-04-26 18:40:57,077 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:57,077 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1238727252] [2025-04-26 18:40:57,077 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:57,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:57,079 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 19 statements into 1 equivalence classes. [2025-04-26 18:40:57,081 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 19 of 19 statements. [2025-04-26 18:40:57,081 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:57,081 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:57,197 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:57,197 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:40:57,197 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1238727252] [2025-04-26 18:40:57,197 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1238727252] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:40:57,198 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [9856899] [2025-04-26 18:40:57,198 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:57,198 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:40:57,198 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:57,200 INFO L229 MonitoredProcess]: Starting monitored process 32 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:40:57,201 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2025-04-26 18:40:57,221 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 19 statements into 1 equivalence classes. [2025-04-26 18:40:57,227 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 19 of 19 statements. [2025-04-26 18:40:57,227 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:57,227 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:57,228 INFO L256 TraceCheckSpWp]: Trace formula consists of 67 conjuncts, 10 conjuncts are in the unsatisfiable core [2025-04-26 18:40:57,229 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:57,261 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:40:57,279 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:40:57,284 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:57,284 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:40:57,312 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:40:57,312 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 13 treesize of output 17 [2025-04-26 18:40:57,345 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:40:57,345 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 15 treesize of output 19 [2025-04-26 18:40:57,361 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:57,361 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [9856899] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:40:57,361 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:40:57,361 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6] total 9 [2025-04-26 18:40:57,361 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [657668080] [2025-04-26 18:40:57,362 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:40:57,362 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:40:57,362 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:57,362 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 3 times [2025-04-26 18:40:57,362 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:57,362 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1028291652] [2025-04-26 18:40:57,362 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-04-26 18:40:57,362 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:57,364 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:40:57,364 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:40:57,366 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-04-26 18:40:57,366 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:57,366 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:57,366 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:40:57,368 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:40:57,368 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:57,368 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:57,368 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:57,392 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:40:57,392 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2025-04-26 18:40:57,392 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=88, Unknown=0, NotChecked=0, Total=110 [2025-04-26 18:40:57,392 INFO L87 Difference]: Start difference. First operand 417 states and 757 transitions. cyclomatic complexity: 387 Second operand has 11 states, 10 states have (on average 2.7) internal successors, (in total 27), 10 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:57,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:40:57,523 INFO L93 Difference]: Finished difference Result 569 states and 984 transitions. [2025-04-26 18:40:57,523 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 569 states and 984 transitions. [2025-04-26 18:40:57,525 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 52 [2025-04-26 18:40:57,527 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 569 states to 567 states and 980 transitions. [2025-04-26 18:40:57,527 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 147 [2025-04-26 18:40:57,527 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 147 [2025-04-26 18:40:57,527 INFO L74 IsDeterministic]: Start isDeterministic. Operand 567 states and 980 transitions. [2025-04-26 18:40:57,527 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:40:57,528 INFO L218 hiAutomatonCegarLoop]: Abstraction has 567 states and 980 transitions. [2025-04-26 18:40:57,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 567 states and 980 transitions. [2025-04-26 18:40:57,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 567 to 475. [2025-04-26 18:40:57,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 475 states, 475 states have (on average 1.7326315789473685) internal successors, (in total 823), 474 states have internal predecessors, (823), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:57,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 475 states to 475 states and 823 transitions. [2025-04-26 18:40:57,535 INFO L240 hiAutomatonCegarLoop]: Abstraction has 475 states and 823 transitions. [2025-04-26 18:40:57,536 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-04-26 18:40:57,536 INFO L438 stractBuchiCegarLoop]: Abstraction has 475 states and 823 transitions. [2025-04-26 18:40:57,536 INFO L340 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-04-26 18:40:57,537 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 475 states and 823 transitions. [2025-04-26 18:40:57,538 INFO L131 ngComponentsAnalysis]: Automaton has 21 accepting balls. 46 [2025-04-26 18:40:57,538 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:40:57,538 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:40:57,539 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-04-26 18:40:57,539 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:40:57,539 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" [2025-04-26 18:40:57,539 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:40:57,539 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:57,539 INFO L85 PathProgramCache]: Analyzing trace with hash 1716026634, now seen corresponding path program 2 times [2025-04-26 18:40:57,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:57,539 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1197747104] [2025-04-26 18:40:57,539 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-04-26 18:40:57,540 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:57,541 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 19 statements into 2 equivalence classes. [2025-04-26 18:40:57,545 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 19 of 19 statements. [2025-04-26 18:40:57,546 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-04-26 18:40:57,546 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:57,546 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:57,551 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 19 statements into 1 equivalence classes. [2025-04-26 18:40:57,554 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 19 of 19 statements. [2025-04-26 18:40:57,554 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:57,554 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:57,556 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:57,556 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:57,556 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 4 times [2025-04-26 18:40:57,556 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:57,556 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [854728680] [2025-04-26 18:40:57,556 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-04-26 18:40:57,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:57,558 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-04-26 18:40:57,558 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:40:57,558 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-04-26 18:40:57,558 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:57,558 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:57,559 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:40:57,559 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:40:57,559 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:57,559 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:57,560 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:57,560 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:57,560 INFO L85 PathProgramCache]: Analyzing trace with hash -165843128, now seen corresponding path program 1 times [2025-04-26 18:40:57,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:57,560 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1801733676] [2025-04-26 18:40:57,560 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-04-26 18:40:57,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:57,562 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes. [2025-04-26 18:40:57,565 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-04-26 18:40:57,565 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:57,565 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:57,565 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:57,566 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes. [2025-04-26 18:40:57,588 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-04-26 18:40:57,588 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:57,589 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:57,590 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:57,885 INFO L206 LassoAnalysis]: Preferences: [2025-04-26 18:40:57,886 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-04-26 18:40:57,886 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-04-26 18:40:57,886 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-04-26 18:40:57,886 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-04-26 18:40:57,886 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:57,886 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-04-26 18:40:57,886 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-04-26 18:40:57,886 INFO L132 ssoRankerPreferences]: Filename of dumped script: ring-nondet.wvr.bpl_petrified1_Iteration13_Lasso [2025-04-26 18:40:57,886 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-04-26 18:40:57,886 INFO L243 LassoAnalysis]: Starting lasso preprocessing... [2025-04-26 18:40:57,887 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:57,890 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:57,891 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:57,893 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:57,894 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:57,972 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:57,976 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:57,979 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:57,980 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:57,982 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:40:58,172 INFO L261 LassoAnalysis]: Preprocessing complete. [2025-04-26 18:40:58,172 INFO L453 LassoAnalysis]: Using template 'affine'. [2025-04-26 18:40:58,173 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:58,173 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:58,174 INFO L229 MonitoredProcess]: Starting monitored process 33 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:58,175 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2025-04-26 18:40:58,176 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:58,186 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:58,186 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:58,186 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:58,186 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:58,187 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:58,187 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:58,189 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:40:58,195 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Ended with exit code 0 [2025-04-26 18:40:58,195 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:58,195 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:58,197 INFO L229 MonitoredProcess]: Starting monitored process 34 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:58,198 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2025-04-26 18:40:58,199 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:58,208 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:58,209 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:58,209 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:58,209 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:58,210 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:58,210 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:58,212 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:40:58,218 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Ended with exit code 0 [2025-04-26 18:40:58,218 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:58,218 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:58,220 INFO L229 MonitoredProcess]: Starting monitored process 35 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:58,221 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2025-04-26 18:40:58,222 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:58,232 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:58,232 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:58,232 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:58,232 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:58,233 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:58,233 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:58,235 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:40:58,240 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Ended with exit code 0 [2025-04-26 18:40:58,240 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:58,240 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:58,242 INFO L229 MonitoredProcess]: Starting monitored process 36 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:58,243 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2025-04-26 18:40:58,244 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:58,253 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:58,254 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:58,254 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:58,254 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:58,254 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:58,254 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:58,256 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:40:58,261 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Ended with exit code 0 [2025-04-26 18:40:58,262 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:58,262 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:58,263 INFO L229 MonitoredProcess]: Starting monitored process 37 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:58,264 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Waiting until timeout for monitored process [2025-04-26 18:40:58,265 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:58,274 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:58,274 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:58,274 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:58,274 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:58,276 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:58,276 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:58,283 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:40:58,288 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Ended with exit code 0 [2025-04-26 18:40:58,288 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:58,288 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:58,290 INFO L229 MonitoredProcess]: Starting monitored process 38 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:58,291 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Waiting until timeout for monitored process [2025-04-26 18:40:58,292 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:40:58,302 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:40:58,302 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:40:58,302 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:40:58,302 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:40:58,307 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:40:58,307 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:40:58,311 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-04-26 18:40:58,320 INFO L436 ModelExtractionUtils]: Simplification made 6 calls to the SMT solver. [2025-04-26 18:40:58,321 INFO L437 ModelExtractionUtils]: 0 out of 10 variables were initially zero. Simplification set additionally 7 variables to zero. [2025-04-26 18:40:58,321 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:40:58,321 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:58,324 INFO L229 MonitoredProcess]: Starting monitored process 39 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:40:58,324 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Waiting until timeout for monitored process [2025-04-26 18:40:58,325 INFO L436 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-04-26 18:40:58,340 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Forceful destruction successful, exit code 0 [2025-04-26 18:40:58,340 INFO L439 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2025-04-26 18:40:58,340 INFO L476 LassoAnalysis]: Proved termination. [2025-04-26 18:40:58,340 INFO L478 LassoAnalysis]: Termination argument consisting of: Ranking function f(q3_front, q3_back) = -1*q3_front + 1*q3_back Supporting invariants [] [2025-04-26 18:40:58,346 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Ended with exit code 0 [2025-04-26 18:40:58,353 INFO L156 tatePredicateManager]: 2 out of 2 supporting invariants were superfluous and have been removed [2025-04-26 18:40:58,362 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:58,370 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 19 statements into 1 equivalence classes. [2025-04-26 18:40:58,374 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 19 of 19 statements. [2025-04-26 18:40:58,374 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:58,374 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:58,374 INFO L256 TraceCheckSpWp]: Trace formula consists of 67 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-04-26 18:40:58,375 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:58,397 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:40:58,398 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:40:58,398 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:58,398 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:58,398 INFO L256 TraceCheckSpWp]: Trace formula consists of 10 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-04-26 18:40:58,398 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:58,406 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:58,407 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2025-04-26 18:40:58,407 INFO L70 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 475 states and 823 transitions. cyclomatic complexity: 399 Second operand has 3 states, 3 states have (on average 6.333333333333333) internal successors, (in total 19), 3 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:58,421 INFO L74 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 475 states and 823 transitions. cyclomatic complexity: 399. Second operand has 3 states, 3 states have (on average 6.333333333333333) internal successors, (in total 19), 3 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) Result 558 states and 947 transitions. Complement of second has 5 states. [2025-04-26 18:40:58,421 INFO L140 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-04-26 18:40:58,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 6.333333333333333) internal successors, (in total 19), 3 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:58,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 26 transitions. [2025-04-26 18:40:58,421 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 26 transitions. Stem has 19 letters. Loop has 2 letters. [2025-04-26 18:40:58,421 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:40:58,421 INFO L699 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2025-04-26 18:40:58,430 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:58,434 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 19 statements into 1 equivalence classes. [2025-04-26 18:40:58,438 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 19 of 19 statements. [2025-04-26 18:40:58,439 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:58,439 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:58,439 INFO L256 TraceCheckSpWp]: Trace formula consists of 67 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-04-26 18:40:58,440 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:58,459 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:40:58,460 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:40:58,460 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:58,460 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:58,460 INFO L256 TraceCheckSpWp]: Trace formula consists of 10 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-04-26 18:40:58,460 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:58,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:58,472 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and with honda bouncer for loop.1 stem predicates 2 loop predicates [2025-04-26 18:40:58,472 INFO L70 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 475 states and 823 transitions. cyclomatic complexity: 399 Second operand has 3 states, 3 states have (on average 6.333333333333333) internal successors, (in total 19), 3 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:58,494 INFO L74 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 475 states and 823 transitions. cyclomatic complexity: 399. Second operand has 3 states, 3 states have (on average 6.333333333333333) internal successors, (in total 19), 3 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) Result 558 states and 947 transitions. Complement of second has 5 states. [2025-04-26 18:40:58,494 INFO L140 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-04-26 18:40:58,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 6.333333333333333) internal successors, (in total 19), 3 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:58,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 26 transitions. [2025-04-26 18:40:58,495 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 26 transitions. Stem has 19 letters. Loop has 2 letters. [2025-04-26 18:40:58,495 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:40:58,495 INFO L699 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2025-04-26 18:40:58,503 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:58,508 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 19 statements into 1 equivalence classes. [2025-04-26 18:40:58,513 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 19 of 19 statements. [2025-04-26 18:40:58,514 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:58,514 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:58,514 INFO L256 TraceCheckSpWp]: Trace formula consists of 67 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-04-26 18:40:58,514 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:58,532 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:40:58,533 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:40:58,533 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:58,533 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:58,534 INFO L256 TraceCheckSpWp]: Trace formula consists of 10 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-04-26 18:40:58,534 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:58,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:58,544 INFO L141 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2025-04-26 18:40:58,544 INFO L70 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 475 states and 823 transitions. cyclomatic complexity: 399 Second operand has 3 states, 3 states have (on average 6.333333333333333) internal successors, (in total 19), 3 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:58,563 INFO L74 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 475 states and 823 transitions. cyclomatic complexity: 399. Second operand has 3 states, 3 states have (on average 6.333333333333333) internal successors, (in total 19), 3 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) Result 659 states and 1106 transitions. Complement of second has 4 states. [2025-04-26 18:40:58,563 INFO L140 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-04-26 18:40:58,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 6.333333333333333) internal successors, (in total 19), 3 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:58,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 37 transitions. [2025-04-26 18:40:58,564 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 37 transitions. Stem has 19 letters. Loop has 2 letters. [2025-04-26 18:40:58,564 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:40:58,564 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 37 transitions. Stem has 21 letters. Loop has 2 letters. [2025-04-26 18:40:58,564 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:40:58,564 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 37 transitions. Stem has 19 letters. Loop has 4 letters. [2025-04-26 18:40:58,564 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:40:58,564 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 659 states and 1106 transitions. [2025-04-26 18:40:58,566 INFO L131 ngComponentsAnalysis]: Automaton has 19 accepting balls. 45 [2025-04-26 18:40:58,568 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 659 states to 546 states and 939 transitions. [2025-04-26 18:40:58,568 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 118 [2025-04-26 18:40:58,568 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 122 [2025-04-26 18:40:58,568 INFO L74 IsDeterministic]: Start isDeterministic. Operand 546 states and 939 transitions. [2025-04-26 18:40:58,569 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:40:58,569 INFO L218 hiAutomatonCegarLoop]: Abstraction has 546 states and 939 transitions. [2025-04-26 18:40:58,569 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states and 939 transitions. [2025-04-26 18:40:58,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 531. [2025-04-26 18:40:58,588 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 531 states, 531 states have (on average 1.7250470809792844) internal successors, (in total 916), 530 states have internal predecessors, (916), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:58,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 531 states to 531 states and 916 transitions. [2025-04-26 18:40:58,589 INFO L240 hiAutomatonCegarLoop]: Abstraction has 531 states and 916 transitions. [2025-04-26 18:40:58,589 INFO L438 stractBuchiCegarLoop]: Abstraction has 531 states and 916 transitions. [2025-04-26 18:40:58,589 INFO L340 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-04-26 18:40:58,589 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 531 states and 916 transitions. [2025-04-26 18:40:58,590 INFO L131 ngComponentsAnalysis]: Automaton has 19 accepting balls. 44 [2025-04-26 18:40:58,590 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:40:58,590 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:40:58,590 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-04-26 18:40:58,590 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:40:58,591 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[105] L58-->thread2FINAL: Formula: (not v_f_3) InVars {f=v_f_3} OutVars{f=v_f_3} AuxVars[] AssignedVars[]" "[107] thread2FINAL-->thread2EXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" [2025-04-26 18:40:58,591 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:40:58,591 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:58,591 INFO L85 PathProgramCache]: Analyzing trace with hash -1931599061, now seen corresponding path program 2 times [2025-04-26 18:40:58,591 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:58,591 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1428245390] [2025-04-26 18:40:58,591 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-04-26 18:40:58,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:58,593 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 23 statements into 2 equivalence classes. [2025-04-26 18:40:58,597 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 23 of 23 statements. [2025-04-26 18:40:58,597 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-04-26 18:40:58,597 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:58,622 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 7 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:58,622 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:40:58,622 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1428245390] [2025-04-26 18:40:58,622 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1428245390] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:40:58,622 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1023343493] [2025-04-26 18:40:58,622 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-04-26 18:40:58,622 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:40:58,622 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:58,652 INFO L229 MonitoredProcess]: Starting monitored process 40 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:40:58,653 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2025-04-26 18:40:58,672 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 23 statements into 2 equivalence classes. [2025-04-26 18:40:58,680 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 23 of 23 statements. [2025-04-26 18:40:58,680 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-04-26 18:40:58,680 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:58,680 INFO L256 TraceCheckSpWp]: Trace formula consists of 79 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-04-26 18:40:58,681 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:58,693 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 7 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:58,693 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:40:58,715 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 7 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:58,715 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1023343493] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:40:58,715 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:40:58,715 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 3, 3] total 4 [2025-04-26 18:40:58,715 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1560532588] [2025-04-26 18:40:58,715 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:40:58,715 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:40:58,715 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:58,715 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 5 times [2025-04-26 18:40:58,715 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:58,715 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1132414616] [2025-04-26 18:40:58,715 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-04-26 18:40:58,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:58,717 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:40:58,718 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:40:58,718 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-04-26 18:40:58,718 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:58,718 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:58,719 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:40:58,719 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:40:58,719 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:58,719 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:58,720 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:58,739 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:40:58,739 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-04-26 18:40:58,740 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2025-04-26 18:40:58,740 INFO L87 Difference]: Start difference. First operand 531 states and 916 transitions. cyclomatic complexity: 438 Second operand has 5 states, 5 states have (on average 5.4) internal successors, (in total 27), 4 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:58,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:40:58,762 INFO L93 Difference]: Finished difference Result 1335 states and 2253 transitions. [2025-04-26 18:40:58,762 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1335 states and 2253 transitions. [2025-04-26 18:40:58,767 INFO L131 ngComponentsAnalysis]: Automaton has 57 accepting balls. 132 [2025-04-26 18:40:58,771 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1335 states to 1162 states and 2007 transitions. [2025-04-26 18:40:58,771 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 288 [2025-04-26 18:40:58,772 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 297 [2025-04-26 18:40:58,772 INFO L74 IsDeterministic]: Start isDeterministic. Operand 1162 states and 2007 transitions. [2025-04-26 18:40:58,772 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:40:58,772 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1162 states and 2007 transitions. [2025-04-26 18:40:58,773 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1162 states and 2007 transitions. [2025-04-26 18:40:58,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1162 to 815. [2025-04-26 18:40:58,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 815 states, 815 states have (on average 1.807361963190184) internal successors, (in total 1473), 814 states have internal predecessors, (1473), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:58,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 815 states to 815 states and 1473 transitions. [2025-04-26 18:40:58,784 INFO L240 hiAutomatonCegarLoop]: Abstraction has 815 states and 1473 transitions. [2025-04-26 18:40:58,784 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-04-26 18:40:58,784 INFO L438 stractBuchiCegarLoop]: Abstraction has 815 states and 1473 transitions. [2025-04-26 18:40:58,784 INFO L340 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-04-26 18:40:58,784 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 815 states and 1473 transitions. [2025-04-26 18:40:58,786 INFO L131 ngComponentsAnalysis]: Automaton has 19 accepting balls. 44 [2025-04-26 18:40:58,786 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:40:58,786 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:40:58,787 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-04-26 18:40:58,787 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:40:58,787 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[105] L58-->thread2FINAL: Formula: (not v_f_3) InVars {f=v_f_3} OutVars{f=v_f_3} AuxVars[] AssignedVars[]" "[107] thread2FINAL-->thread2EXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" [2025-04-26 18:40:58,787 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:40:58,787 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:58,787 INFO L85 PathProgramCache]: Analyzing trace with hash -185690872, now seen corresponding path program 3 times [2025-04-26 18:40:58,787 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:58,788 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [641317313] [2025-04-26 18:40:58,788 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-04-26 18:40:58,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:58,789 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 25 statements into 3 equivalence classes. [2025-04-26 18:40:58,801 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) and asserted 25 of 25 statements. [2025-04-26 18:40:58,801 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2025-04-26 18:40:58,801 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:58,955 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:58,955 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:40:58,955 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [641317313] [2025-04-26 18:40:58,955 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [641317313] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:40:58,955 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1304421354] [2025-04-26 18:40:58,955 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-04-26 18:40:58,955 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:40:58,955 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:40:58,957 INFO L229 MonitoredProcess]: Starting monitored process 41 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:40:58,959 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2025-04-26 18:40:58,980 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 25 statements into 3 equivalence classes. [2025-04-26 18:40:58,990 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) and asserted 25 of 25 statements. [2025-04-26 18:40:58,991 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2025-04-26 18:40:58,991 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:40:58,991 INFO L256 TraceCheckSpWp]: Trace formula consists of 86 conjuncts, 9 conjuncts are in the unsatisfiable core [2025-04-26 18:40:58,992 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:40:59,105 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:40:59,111 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:59,111 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:40:59,215 INFO L325 Elim1Store]: treesize reduction 5, result has 37.5 percent of original size [2025-04-26 18:40:59,216 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 11 treesize of output 10 [2025-04-26 18:40:59,241 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:40:59,241 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1304421354] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:40:59,241 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:40:59,242 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 15 [2025-04-26 18:40:59,242 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1988653544] [2025-04-26 18:40:59,242 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:40:59,242 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:40:59,242 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:59,242 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 6 times [2025-04-26 18:40:59,242 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:59,242 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1420973392] [2025-04-26 18:40:59,242 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-04-26 18:40:59,242 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:59,244 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:40:59,246 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:40:59,246 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-04-26 18:40:59,246 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:59,246 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:59,246 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:40:59,247 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:40:59,247 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:59,247 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:59,247 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:59,270 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:40:59,270 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2025-04-26 18:40:59,270 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=177, Unknown=0, NotChecked=0, Total=240 [2025-04-26 18:40:59,270 INFO L87 Difference]: Start difference. First operand 815 states and 1473 transitions. cyclomatic complexity: 732 Second operand has 16 states, 16 states have (on average 3.3125) internal successors, (in total 53), 15 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:59,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:40:59,687 INFO L93 Difference]: Finished difference Result 2506 states and 4473 transitions. [2025-04-26 18:40:59,687 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2506 states and 4473 transitions. [2025-04-26 18:40:59,697 INFO L131 ngComponentsAnalysis]: Automaton has 77 accepting balls. 196 [2025-04-26 18:40:59,707 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2506 states to 2368 states and 4269 transitions. [2025-04-26 18:40:59,707 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2025-04-26 18:40:59,708 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 508 [2025-04-26 18:40:59,708 INFO L74 IsDeterministic]: Start isDeterministic. Operand 2368 states and 4269 transitions. [2025-04-26 18:40:59,708 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:40:59,708 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2368 states and 4269 transitions. [2025-04-26 18:40:59,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2368 states and 4269 transitions. [2025-04-26 18:40:59,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2368 to 1074. [2025-04-26 18:40:59,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1074 states, 1074 states have (on average 1.809124767225326) internal successors, (in total 1943), 1073 states have internal predecessors, (1943), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:40:59,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1074 states to 1074 states and 1943 transitions. [2025-04-26 18:40:59,730 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1074 states and 1943 transitions. [2025-04-26 18:40:59,730 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-04-26 18:40:59,730 INFO L438 stractBuchiCegarLoop]: Abstraction has 1074 states and 1943 transitions. [2025-04-26 18:40:59,730 INFO L340 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-04-26 18:40:59,730 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1074 states and 1943 transitions. [2025-04-26 18:40:59,733 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 28 [2025-04-26 18:40:59,733 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:40:59,733 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:40:59,734 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2025-04-26 18:40:59,734 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2025-04-26 18:40:59,734 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" [2025-04-26 18:40:59,734 INFO L754 eck$LassoCheckResult]: Loop: "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" [2025-04-26 18:40:59,734 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:59,734 INFO L85 PathProgramCache]: Analyzing trace with hash 452634859, now seen corresponding path program 3 times [2025-04-26 18:40:59,735 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:59,735 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1357231131] [2025-04-26 18:40:59,735 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-04-26 18:40:59,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:59,737 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 26 statements into 3 equivalence classes. [2025-04-26 18:40:59,748 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) and asserted 26 of 26 statements. [2025-04-26 18:40:59,748 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2025-04-26 18:40:59,748 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:59,748 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:59,749 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-04-26 18:40:59,758 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-04-26 18:40:59,759 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:59,759 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:59,760 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:59,765 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:59,765 INFO L85 PathProgramCache]: Analyzing trace with hash 138406030, now seen corresponding path program 5 times [2025-04-26 18:40:59,765 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:59,765 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1612990420] [2025-04-26 18:40:59,765 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-04-26 18:40:59,765 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:59,766 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:40:59,767 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:59,767 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-04-26 18:40:59,768 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:59,768 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:59,769 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:40:59,769 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:40:59,770 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:59,770 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:59,770 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:40:59,771 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:40:59,771 INFO L85 PathProgramCache]: Analyzing trace with hash -151240220, now seen corresponding path program 4 times [2025-04-26 18:40:59,771 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:40:59,771 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1459533697] [2025-04-26 18:40:59,771 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-04-26 18:40:59,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:40:59,774 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 31 statements into 2 equivalence classes. [2025-04-26 18:40:59,787 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 31 of 31 statements. [2025-04-26 18:40:59,788 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-04-26 18:40:59,788 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:59,788 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:40:59,790 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-04-26 18:40:59,801 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-04-26 18:40:59,803 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:40:59,803 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:40:59,805 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:00,249 INFO L206 LassoAnalysis]: Preferences: [2025-04-26 18:41:00,250 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-04-26 18:41:00,250 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-04-26 18:41:00,250 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-04-26 18:41:00,250 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-04-26 18:41:00,250 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:41:00,250 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-04-26 18:41:00,250 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-04-26 18:41:00,250 INFO L132 ssoRankerPreferences]: Filename of dumped script: ring-nondet.wvr.bpl_petrified1_Iteration16_Lasso [2025-04-26 18:41:00,250 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-04-26 18:41:00,250 INFO L243 LassoAnalysis]: Starting lasso preprocessing... [2025-04-26 18:41:00,251 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:00,374 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:00,378 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:00,380 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:00,383 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:00,385 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:00,387 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:00,389 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:00,391 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:00,393 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:00,394 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:00,396 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:00,648 INFO L261 LassoAnalysis]: Preprocessing complete. [2025-04-26 18:41:00,649 INFO L453 LassoAnalysis]: Using template 'affine'. [2025-04-26 18:41:00,649 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:41:00,649 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:00,652 INFO L229 MonitoredProcess]: Starting monitored process 42 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:41:00,653 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Waiting until timeout for monitored process [2025-04-26 18:41:00,653 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:41:00,663 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:41:00,663 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:41:00,663 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:41:00,663 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:41:00,665 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:41:00,665 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:41:00,670 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-04-26 18:41:00,675 INFO L436 ModelExtractionUtils]: Simplification made 6 calls to the SMT solver. [2025-04-26 18:41:00,676 INFO L437 ModelExtractionUtils]: 1 out of 10 variables were initially zero. Simplification set additionally 6 variables to zero. [2025-04-26 18:41:00,676 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:41:00,676 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:00,678 INFO L229 MonitoredProcess]: Starting monitored process 43 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:41:00,679 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Waiting until timeout for monitored process [2025-04-26 18:41:00,679 INFO L436 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-04-26 18:41:00,695 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Ended with exit code 0 [2025-04-26 18:41:00,695 INFO L439 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2025-04-26 18:41:00,695 INFO L476 LassoAnalysis]: Proved termination. [2025-04-26 18:41:00,695 INFO L478 LassoAnalysis]: Termination argument consisting of: Ranking function f(q2_back, q2_front) = 1*q2_back - 1*q2_front Supporting invariants [] [2025-04-26 18:41:00,701 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Ended with exit code 0 [2025-04-26 18:41:00,708 INFO L156 tatePredicateManager]: 5 out of 5 supporting invariants were superfluous and have been removed [2025-04-26 18:41:00,715 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:00,722 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-04-26 18:41:00,729 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-04-26 18:41:00,729 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:00,729 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:00,730 INFO L256 TraceCheckSpWp]: Trace formula consists of 87 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-04-26 18:41:00,730 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:00,764 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:41:00,765 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:41:00,765 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:00,765 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:00,766 INFO L256 TraceCheckSpWp]: Trace formula consists of 15 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-04-26 18:41:00,766 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:00,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:00,782 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2025-04-26 18:41:00,782 INFO L70 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 1074 states and 1943 transitions. cyclomatic complexity: 938 Second operand has 3 states, 3 states have (on average 7.333333333333333) internal successors, (in total 22), 3 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:00,802 INFO L74 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 1074 states and 1943 transitions. cyclomatic complexity: 938. Second operand has 3 states, 3 states have (on average 7.333333333333333) internal successors, (in total 22), 3 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) Result 2058 states and 3707 transitions. Complement of second has 5 states. [2025-04-26 18:41:00,803 INFO L140 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-04-26 18:41:00,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 7.333333333333333) internal successors, (in total 22), 3 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:00,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 26 transitions. [2025-04-26 18:41:00,803 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 26 transitions. Stem has 26 letters. Loop has 5 letters. [2025-04-26 18:41:00,803 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:41:00,803 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 26 transitions. Stem has 31 letters. Loop has 5 letters. [2025-04-26 18:41:00,803 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:41:00,803 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 26 transitions. Stem has 26 letters. Loop has 10 letters. [2025-04-26 18:41:00,804 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:41:00,804 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2058 states and 3707 transitions. [2025-04-26 18:41:00,811 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 36 [2025-04-26 18:41:00,817 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2058 states to 1703 states and 3054 transitions. [2025-04-26 18:41:00,818 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 214 [2025-04-26 18:41:00,818 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 216 [2025-04-26 18:41:00,818 INFO L74 IsDeterministic]: Start isDeterministic. Operand 1703 states and 3054 transitions. [2025-04-26 18:41:00,818 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:41:00,818 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1703 states and 3054 transitions. [2025-04-26 18:41:00,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1703 states and 3054 transitions. [2025-04-26 18:41:00,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1703 to 1333. [2025-04-26 18:41:00,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1333 states, 1333 states have (on average 1.7944486121530383) internal successors, (in total 2392), 1332 states have internal predecessors, (2392), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:00,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1333 states to 1333 states and 2392 transitions. [2025-04-26 18:41:00,838 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1333 states and 2392 transitions. [2025-04-26 18:41:00,838 INFO L438 stractBuchiCegarLoop]: Abstraction has 1333 states and 2392 transitions. [2025-04-26 18:41:00,838 INFO L340 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-04-26 18:41:00,838 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1333 states and 2392 transitions. [2025-04-26 18:41:00,840 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 28 [2025-04-26 18:41:00,840 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:41:00,840 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:41:00,841 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2025-04-26 18:41:00,841 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2025-04-26 18:41:00,842 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" [2025-04-26 18:41:00,842 INFO L754 eck$LassoCheckResult]: Loop: "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" [2025-04-26 18:41:00,842 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:00,842 INFO L85 PathProgramCache]: Analyzing trace with hash 886049999, now seen corresponding path program 5 times [2025-04-26 18:41:00,842 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:00,842 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [520335512] [2025-04-26 18:41:00,842 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-04-26 18:41:00,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:00,845 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 26 statements into 3 equivalence classes. [2025-04-26 18:41:00,852 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 3 check-sat command(s) and asserted 26 of 26 statements. [2025-04-26 18:41:00,852 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 3 check-sat command(s) [2025-04-26 18:41:00,852 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:00,852 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:41:00,854 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-04-26 18:41:00,862 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-04-26 18:41:00,862 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:00,862 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:00,864 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:00,864 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:00,864 INFO L85 PathProgramCache]: Analyzing trace with hash 138406030, now seen corresponding path program 6 times [2025-04-26 18:41:00,864 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:00,864 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [479502509] [2025-04-26 18:41:00,864 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-04-26 18:41:00,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:00,866 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:41:00,866 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:41:00,866 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-04-26 18:41:00,866 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:00,867 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:41:00,868 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:41:00,868 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:41:00,868 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:00,868 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:00,869 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:00,869 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:00,869 INFO L85 PathProgramCache]: Analyzing trace with hash 790473856, now seen corresponding path program 6 times [2025-04-26 18:41:00,870 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:00,870 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [835951997] [2025-04-26 18:41:00,870 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-04-26 18:41:00,870 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:00,872 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 31 statements into 3 equivalence classes. [2025-04-26 18:41:00,879 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 3 check-sat command(s) and asserted 31 of 31 statements. [2025-04-26 18:41:00,880 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 3 check-sat command(s) [2025-04-26 18:41:00,880 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:00,880 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:41:00,881 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-04-26 18:41:00,893 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-04-26 18:41:00,894 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:00,894 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:00,896 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:01,316 INFO L206 LassoAnalysis]: Preferences: [2025-04-26 18:41:01,316 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-04-26 18:41:01,316 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-04-26 18:41:01,316 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-04-26 18:41:01,316 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-04-26 18:41:01,316 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:41:01,316 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-04-26 18:41:01,316 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-04-26 18:41:01,316 INFO L132 ssoRankerPreferences]: Filename of dumped script: ring-nondet.wvr.bpl_petrified1_Iteration17_Lasso [2025-04-26 18:41:01,316 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-04-26 18:41:01,316 INFO L243 LassoAnalysis]: Starting lasso preprocessing... [2025-04-26 18:41:01,317 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:01,324 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:01,326 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:01,328 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:01,330 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:01,332 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:01,335 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:01,337 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:01,339 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:01,340 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:01,342 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:01,346 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-04-26 18:41:01,715 INFO L261 LassoAnalysis]: Preprocessing complete. [2025-04-26 18:41:01,715 INFO L453 LassoAnalysis]: Using template 'affine'. [2025-04-26 18:41:01,715 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:41:01,715 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:01,717 INFO L229 MonitoredProcess]: Starting monitored process 44 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:41:01,718 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Waiting until timeout for monitored process [2025-04-26 18:41:01,719 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:41:01,729 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:41:01,729 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:41:01,729 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:41:01,729 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:41:01,730 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:41:01,730 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:41:01,732 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:41:01,738 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Ended with exit code 0 [2025-04-26 18:41:01,738 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:41:01,738 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:01,740 INFO L229 MonitoredProcess]: Starting monitored process 45 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:41:01,740 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Waiting until timeout for monitored process [2025-04-26 18:41:01,742 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:41:01,751 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:41:01,751 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:41:01,751 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:41:01,751 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:41:01,752 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:41:01,752 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:41:01,755 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:41:01,762 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Ended with exit code 0 [2025-04-26 18:41:01,763 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:41:01,763 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:01,765 INFO L229 MonitoredProcess]: Starting monitored process 46 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:41:01,766 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Waiting until timeout for monitored process [2025-04-26 18:41:01,766 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:41:01,776 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:41:01,776 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:41:01,776 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:41:01,776 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:41:01,777 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:41:01,777 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:41:01,779 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:41:01,784 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Ended with exit code 0 [2025-04-26 18:41:01,785 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:41:01,785 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:01,786 INFO L229 MonitoredProcess]: Starting monitored process 47 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:41:01,787 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Waiting until timeout for monitored process [2025-04-26 18:41:01,788 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:41:01,798 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:41:01,798 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:41:01,798 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:41:01,798 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:41:01,799 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:41:01,799 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:41:01,801 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:41:01,807 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Ended with exit code 0 [2025-04-26 18:41:01,807 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:41:01,807 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:01,809 INFO L229 MonitoredProcess]: Starting monitored process 48 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:41:01,811 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Waiting until timeout for monitored process [2025-04-26 18:41:01,811 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:41:01,821 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:41:01,821 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:41:01,821 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:41:01,821 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:41:01,822 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:41:01,822 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:41:01,824 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:41:01,830 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Forceful destruction successful, exit code 0 [2025-04-26 18:41:01,830 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:41:01,830 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:01,832 INFO L229 MonitoredProcess]: Starting monitored process 49 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:41:01,832 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Waiting until timeout for monitored process [2025-04-26 18:41:01,833 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:41:01,843 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:41:01,843 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:41:01,843 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:41:01,843 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:41:01,844 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:41:01,844 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:41:01,847 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:41:01,852 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Ended with exit code 0 [2025-04-26 18:41:01,852 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:41:01,852 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:01,854 INFO L229 MonitoredProcess]: Starting monitored process 50 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:41:01,855 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Waiting until timeout for monitored process [2025-04-26 18:41:01,856 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:41:01,866 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:41:01,866 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:41:01,866 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:41:01,866 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:41:01,867 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:41:01,867 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:41:01,869 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:41:01,874 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Forceful destruction successful, exit code 0 [2025-04-26 18:41:01,875 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:41:01,875 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:01,876 INFO L229 MonitoredProcess]: Starting monitored process 51 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:41:01,877 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Waiting until timeout for monitored process [2025-04-26 18:41:01,878 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:41:01,887 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:41:01,887 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:41:01,888 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:41:01,888 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:41:01,888 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:41:01,888 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:41:01,891 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:41:01,896 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Forceful destruction successful, exit code 0 [2025-04-26 18:41:01,897 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:41:01,897 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:01,898 INFO L229 MonitoredProcess]: Starting monitored process 52 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:41:01,899 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (52)] Waiting until timeout for monitored process [2025-04-26 18:41:01,900 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:41:01,909 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:41:01,909 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:41:01,909 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:41:01,910 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:41:01,910 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:41:01,910 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:41:01,912 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:41:01,918 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (52)] Ended with exit code 0 [2025-04-26 18:41:01,918 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:41:01,918 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:01,920 INFO L229 MonitoredProcess]: Starting monitored process 53 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:41:01,920 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (53)] Waiting until timeout for monitored process [2025-04-26 18:41:01,921 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:41:01,931 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:41:01,931 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:41:01,931 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:41:01,931 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:41:01,932 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:41:01,932 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:41:01,937 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:41:01,944 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (53)] Ended with exit code 0 [2025-04-26 18:41:01,944 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:41:01,944 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:01,948 INFO L229 MonitoredProcess]: Starting monitored process 54 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:41:01,959 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (54)] Waiting until timeout for monitored process [2025-04-26 18:41:01,960 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:41:01,969 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:41:01,970 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:41:01,970 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:41:01,970 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:41:01,970 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:41:01,970 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:41:01,972 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:41:01,978 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (54)] Ended with exit code 0 [2025-04-26 18:41:01,978 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:41:01,979 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:01,980 INFO L229 MonitoredProcess]: Starting monitored process 55 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:41:01,982 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (55)] Waiting until timeout for monitored process [2025-04-26 18:41:01,983 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:41:01,992 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:41:01,993 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:41:01,993 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:41:01,993 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:41:01,999 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:41:01,999 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:41:02,009 INFO L490 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-04-26 18:41:02,015 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (55)] Forceful destruction successful, exit code 0 [2025-04-26 18:41:02,015 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:41:02,015 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:02,017 INFO L229 MonitoredProcess]: Starting monitored process 56 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:41:02,018 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (56)] Waiting until timeout for monitored process [2025-04-26 18:41:02,018 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-04-26 18:41:02,028 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-04-26 18:41:02,028 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-04-26 18:41:02,028 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-04-26 18:41:02,028 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-04-26 18:41:02,030 INFO L402 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-04-26 18:41:02,030 INFO L403 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-04-26 18:41:02,034 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-04-26 18:41:02,041 INFO L436 ModelExtractionUtils]: Simplification made 8 calls to the SMT solver. [2025-04-26 18:41:02,041 INFO L437 ModelExtractionUtils]: 0 out of 10 variables were initially zero. Simplification set additionally 7 variables to zero. [2025-04-26 18:41:02,041 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-04-26 18:41:02,041 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:02,043 INFO L229 MonitoredProcess]: Starting monitored process 57 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-04-26 18:41:02,043 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (57)] Waiting until timeout for monitored process [2025-04-26 18:41:02,044 INFO L436 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-04-26 18:41:02,059 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (57)] Ended with exit code 0 [2025-04-26 18:41:02,060 INFO L439 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2025-04-26 18:41:02,060 INFO L476 LassoAnalysis]: Proved termination. [2025-04-26 18:41:02,060 INFO L478 LassoAnalysis]: Termination argument consisting of: Ranking function f(q2_back, q2_front) = 1*q2_back - 1*q2_front Supporting invariants [] [2025-04-26 18:41:02,065 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (56)] Ended with exit code 0 [2025-04-26 18:41:02,071 INFO L156 tatePredicateManager]: 4 out of 4 supporting invariants were superfluous and have been removed [2025-04-26 18:41:02,079 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:02,088 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-04-26 18:41:02,096 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-04-26 18:41:02,096 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:02,096 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:02,097 INFO L256 TraceCheckSpWp]: Trace formula consists of 87 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-04-26 18:41:02,097 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:02,121 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:41:02,122 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:41:02,122 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:02,122 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:02,123 INFO L256 TraceCheckSpWp]: Trace formula consists of 15 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-04-26 18:41:02,123 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:02,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:02,140 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2025-04-26 18:41:02,140 INFO L70 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 1333 states and 2392 transitions. cyclomatic complexity: 1154 Second operand has 3 states, 3 states have (on average 7.333333333333333) internal successors, (in total 22), 3 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:02,165 INFO L74 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 1333 states and 2392 transitions. cyclomatic complexity: 1154. Second operand has 3 states, 3 states have (on average 7.333333333333333) internal successors, (in total 22), 3 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) Result 2260 states and 3999 transitions. Complement of second has 5 states. [2025-04-26 18:41:02,168 INFO L140 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-04-26 18:41:02,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 7.333333333333333) internal successors, (in total 22), 3 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:02,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 26 transitions. [2025-04-26 18:41:02,168 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 26 transitions. Stem has 26 letters. Loop has 5 letters. [2025-04-26 18:41:02,168 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:41:02,168 INFO L699 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2025-04-26 18:41:02,177 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:02,182 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-04-26 18:41:02,191 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-04-26 18:41:02,192 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:02,192 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:02,192 INFO L256 TraceCheckSpWp]: Trace formula consists of 87 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-04-26 18:41:02,193 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:02,220 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:41:02,222 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:41:02,222 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:02,222 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:02,222 INFO L256 TraceCheckSpWp]: Trace formula consists of 15 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-04-26 18:41:02,222 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:02,240 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:02,240 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and with honda bouncer for loop.1 stem predicates 2 loop predicates [2025-04-26 18:41:02,240 INFO L70 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 1333 states and 2392 transitions. cyclomatic complexity: 1154 Second operand has 3 states, 3 states have (on average 7.333333333333333) internal successors, (in total 22), 3 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:02,270 INFO L74 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 1333 states and 2392 transitions. cyclomatic complexity: 1154. Second operand has 3 states, 3 states have (on average 7.333333333333333) internal successors, (in total 22), 3 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) Result 3034 states and 5845 transitions. Complement of second has 7 states. [2025-04-26 18:41:02,271 INFO L140 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2025-04-26 18:41:02,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 7.333333333333333) internal successors, (in total 22), 3 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:02,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 36 transitions. [2025-04-26 18:41:02,271 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 4 states and 36 transitions. Stem has 26 letters. Loop has 5 letters. [2025-04-26 18:41:02,271 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:41:02,271 INFO L699 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2025-04-26 18:41:02,277 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:02,282 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-04-26 18:41:02,293 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-04-26 18:41:02,293 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:02,293 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:02,293 INFO L256 TraceCheckSpWp]: Trace formula consists of 87 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-04-26 18:41:02,294 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:02,318 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-04-26 18:41:02,320 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-04-26 18:41:02,320 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:02,321 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:02,321 INFO L256 TraceCheckSpWp]: Trace formula consists of 15 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-04-26 18:41:02,321 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:02,343 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:02,344 INFO L141 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2025-04-26 18:41:02,344 INFO L70 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 1333 states and 2392 transitions. cyclomatic complexity: 1154 Second operand has 3 states, 3 states have (on average 7.333333333333333) internal successors, (in total 22), 3 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:02,370 INFO L74 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 1333 states and 2392 transitions. cyclomatic complexity: 1154. Second operand has 3 states, 3 states have (on average 7.333333333333333) internal successors, (in total 22), 3 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) Result 2418 states and 4373 transitions. Complement of second has 6 states. [2025-04-26 18:41:02,370 INFO L140 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-04-26 18:41:02,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 7.333333333333333) internal successors, (in total 22), 3 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:02,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 35 transitions. [2025-04-26 18:41:02,371 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 35 transitions. Stem has 26 letters. Loop has 5 letters. [2025-04-26 18:41:02,371 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:41:02,371 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 35 transitions. Stem has 31 letters. Loop has 5 letters. [2025-04-26 18:41:02,371 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:41:02,371 INFO L85 BuchiAccepts]: Start buchiAccepts Operand 3 states and 35 transitions. Stem has 26 letters. Loop has 10 letters. [2025-04-26 18:41:02,371 INFO L117 BuchiAccepts]: Finished buchiAccepts. [2025-04-26 18:41:02,371 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2418 states and 4373 transitions. [2025-04-26 18:41:02,378 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 28 [2025-04-26 18:41:02,384 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2418 states to 1801 states and 3250 transitions. [2025-04-26 18:41:02,385 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 217 [2025-04-26 18:41:02,385 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 220 [2025-04-26 18:41:02,385 INFO L74 IsDeterministic]: Start isDeterministic. Operand 1801 states and 3250 transitions. [2025-04-26 18:41:02,385 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:41:02,385 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 3250 transitions. [2025-04-26 18:41:02,386 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 3250 transitions. [2025-04-26 18:41:02,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1331. [2025-04-26 18:41:02,400 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1331 states, 1331 states have (on average 1.8054094665664913) internal successors, (in total 2403), 1330 states have internal predecessors, (2403), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:02,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1331 states to 1331 states and 2403 transitions. [2025-04-26 18:41:02,402 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1331 states and 2403 transitions. [2025-04-26 18:41:02,402 INFO L438 stractBuchiCegarLoop]: Abstraction has 1331 states and 2403 transitions. [2025-04-26 18:41:02,402 INFO L340 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-04-26 18:41:02,402 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1331 states and 2403 transitions. [2025-04-26 18:41:02,404 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:02,404 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:41:02,404 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:41:02,405 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1] [2025-04-26 18:41:02,405 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:41:02,405 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:41:02,405 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:41:02,405 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:02,406 INFO L85 PathProgramCache]: Analyzing trace with hash -151240221, now seen corresponding path program 2 times [2025-04-26 18:41:02,406 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:02,406 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [673211703] [2025-04-26 18:41:02,406 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-04-26 18:41:02,406 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:02,411 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 31 statements into 2 equivalence classes. [2025-04-26 18:41:02,425 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 31 of 31 statements. [2025-04-26 18:41:02,425 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-04-26 18:41:02,425 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:02,673 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:02,673 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:41:02,674 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [673211703] [2025-04-26 18:41:02,674 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [673211703] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:41:02,674 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [379609085] [2025-04-26 18:41:02,674 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-04-26 18:41:02,674 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:41:02,674 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:02,676 INFO L229 MonitoredProcess]: Starting monitored process 58 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:41:02,677 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Waiting until timeout for monitored process [2025-04-26 18:41:02,698 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 31 statements into 2 equivalence classes. [2025-04-26 18:41:02,706 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 31 of 31 statements. [2025-04-26 18:41:02,707 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-04-26 18:41:02,707 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:02,707 INFO L256 TraceCheckSpWp]: Trace formula consists of 100 conjuncts, 18 conjuncts are in the unsatisfiable core [2025-04-26 18:41:02,708 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:02,797 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:41:02,823 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:41:02,827 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:02,828 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:41:02,865 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:02,866 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 15 treesize of output 19 [2025-04-26 18:41:02,900 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:02,900 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 21 [2025-04-26 18:41:02,915 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:02,915 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [379609085] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:41:02,916 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:41:02,916 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 10] total 15 [2025-04-26 18:41:02,916 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [120399293] [2025-04-26 18:41:02,916 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:41:02,916 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:41:02,916 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:02,916 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 7 times [2025-04-26 18:41:02,916 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:02,916 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [150679118] [2025-04-26 18:41:02,916 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-04-26 18:41:02,916 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:02,918 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:02,919 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:02,919 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:02,919 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:02,919 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:41:02,919 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:02,919 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:02,919 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:02,919 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:02,920 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:02,940 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:41:02,941 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2025-04-26 18:41:02,941 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=232, Unknown=0, NotChecked=0, Total=272 [2025-04-26 18:41:02,941 INFO L87 Difference]: Start difference. First operand 1331 states and 2403 transitions. cyclomatic complexity: 1151 Second operand has 17 states, 16 states have (on average 2.6875) internal successors, (in total 43), 16 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:03,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:41:03,286 INFO L93 Difference]: Finished difference Result 2431 states and 4265 transitions. [2025-04-26 18:41:03,286 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2431 states and 4265 transitions. [2025-04-26 18:41:03,293 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:03,302 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2431 states to 2428 states and 4262 transitions. [2025-04-26 18:41:03,302 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 283 [2025-04-26 18:41:03,302 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 283 [2025-04-26 18:41:03,302 INFO L74 IsDeterministic]: Start isDeterministic. Operand 2428 states and 4262 transitions. [2025-04-26 18:41:03,302 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:41:03,302 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2428 states and 4262 transitions. [2025-04-26 18:41:03,304 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2428 states and 4262 transitions. [2025-04-26 18:41:03,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2428 to 1782. [2025-04-26 18:41:03,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1782 states, 1782 states have (on average 1.7811447811447811) internal successors, (in total 3174), 1781 states have internal predecessors, (3174), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:03,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1782 states to 1782 states and 3174 transitions. [2025-04-26 18:41:03,324 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1782 states and 3174 transitions. [2025-04-26 18:41:03,324 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-04-26 18:41:03,325 INFO L438 stractBuchiCegarLoop]: Abstraction has 1782 states and 3174 transitions. [2025-04-26 18:41:03,325 INFO L340 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-04-26 18:41:03,325 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1782 states and 3174 transitions. [2025-04-26 18:41:03,328 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:03,328 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:41:03,328 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:41:03,328 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1] [2025-04-26 18:41:03,328 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:41:03,329 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:41:03,329 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:41:03,329 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:03,329 INFO L85 PathProgramCache]: Analyzing trace with hash -1919367187, now seen corresponding path program 3 times [2025-04-26 18:41:03,329 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:03,329 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1070734441] [2025-04-26 18:41:03,329 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-04-26 18:41:03,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:03,331 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 31 statements into 3 equivalence classes. [2025-04-26 18:41:03,335 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) and asserted 31 of 31 statements. [2025-04-26 18:41:03,335 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2025-04-26 18:41:03,335 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:03,573 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 17 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:03,573 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:41:03,573 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1070734441] [2025-04-26 18:41:03,573 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1070734441] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:41:03,573 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [513850177] [2025-04-26 18:41:03,573 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-04-26 18:41:03,573 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:41:03,573 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:03,575 INFO L229 MonitoredProcess]: Starting monitored process 59 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:41:03,575 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Waiting until timeout for monitored process [2025-04-26 18:41:03,594 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 31 statements into 3 equivalence classes. [2025-04-26 18:41:03,603 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) and asserted 31 of 31 statements. [2025-04-26 18:41:03,603 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2025-04-26 18:41:03,603 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:03,604 INFO L256 TraceCheckSpWp]: Trace formula consists of 100 conjuncts, 18 conjuncts are in the unsatisfiable core [2025-04-26 18:41:03,605 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:03,714 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:41:03,751 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:41:03,760 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 17 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:03,760 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:41:03,788 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:03,789 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 13 treesize of output 17 [2025-04-26 18:41:03,845 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:03,845 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 21 [2025-04-26 18:41:03,861 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 17 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:03,861 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [513850177] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:41:03,861 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:41:03,861 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 9, 9] total 17 [2025-04-26 18:41:03,862 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [712116247] [2025-04-26 18:41:03,862 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:41:03,862 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:41:03,862 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:03,862 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 8 times [2025-04-26 18:41:03,862 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:03,862 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [494704124] [2025-04-26 18:41:03,862 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-04-26 18:41:03,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:03,864 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:03,864 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:03,865 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-04-26 18:41:03,865 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:03,865 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:41:03,865 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:03,865 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:03,865 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:03,865 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:03,866 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:03,888 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:41:03,888 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2025-04-26 18:41:03,888 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=300, Unknown=0, NotChecked=0, Total=342 [2025-04-26 18:41:03,888 INFO L87 Difference]: Start difference. First operand 1782 states and 3174 transitions. cyclomatic complexity: 1511 Second operand has 19 states, 18 states have (on average 3.0) internal successors, (in total 54), 18 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:04,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:41:04,328 INFO L93 Difference]: Finished difference Result 2934 states and 5069 transitions. [2025-04-26 18:41:04,328 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2934 states and 5069 transitions. [2025-04-26 18:41:04,336 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:04,345 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2934 states to 2910 states and 5028 transitions. [2025-04-26 18:41:04,345 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 336 [2025-04-26 18:41:04,345 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 351 [2025-04-26 18:41:04,345 INFO L74 IsDeterministic]: Start isDeterministic. Operand 2910 states and 5028 transitions. [2025-04-26 18:41:04,345 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:41:04,345 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2910 states and 5028 transitions. [2025-04-26 18:41:04,347 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2910 states and 5028 transitions. [2025-04-26 18:41:04,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2910 to 1945. [2025-04-26 18:41:04,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1945 states, 1945 states have (on average 1.763496143958869) internal successors, (in total 3430), 1944 states have internal predecessors, (3430), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:04,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1945 states to 1945 states and 3430 transitions. [2025-04-26 18:41:04,371 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1945 states and 3430 transitions. [2025-04-26 18:41:04,372 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2025-04-26 18:41:04,372 INFO L438 stractBuchiCegarLoop]: Abstraction has 1945 states and 3430 transitions. [2025-04-26 18:41:04,372 INFO L340 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-04-26 18:41:04,372 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1945 states and 3430 transitions. [2025-04-26 18:41:04,375 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:04,375 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:41:04,375 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:41:04,375 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1] [2025-04-26 18:41:04,375 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:41:04,376 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:41:04,376 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:41:04,376 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:04,376 INFO L85 PathProgramCache]: Analyzing trace with hash -731550903, now seen corresponding path program 4 times [2025-04-26 18:41:04,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:04,376 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248707527] [2025-04-26 18:41:04,376 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-04-26 18:41:04,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:04,378 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 31 statements into 2 equivalence classes. [2025-04-26 18:41:04,384 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-04-26 18:41:04,384 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-04-26 18:41:04,384 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:04,573 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:04,573 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:41:04,573 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [248707527] [2025-04-26 18:41:04,573 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [248707527] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:41:04,573 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [239756383] [2025-04-26 18:41:04,573 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-04-26 18:41:04,573 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:41:04,573 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:04,575 INFO L229 MonitoredProcess]: Starting monitored process 60 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:41:04,577 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Waiting until timeout for monitored process [2025-04-26 18:41:04,597 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 31 statements into 2 equivalence classes. [2025-04-26 18:41:04,605 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-04-26 18:41:04,605 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-04-26 18:41:04,605 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:04,606 INFO L256 TraceCheckSpWp]: Trace formula consists of 100 conjuncts, 33 conjuncts are in the unsatisfiable core [2025-04-26 18:41:04,607 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:04,733 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:04,733 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 18 treesize of output 10 [2025-04-26 18:41:04,867 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:04,867 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 18 treesize of output 10 [2025-04-26 18:41:04,886 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:04,887 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 13 treesize of output 17 [2025-04-26 18:41:04,893 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:04,893 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:41:04,969 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:04,969 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 28 [2025-04-26 18:41:05,177 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:05,177 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 34 treesize of output 38 [2025-04-26 18:41:05,325 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:05,326 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 41 treesize of output 65 [2025-04-26 18:41:05,481 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 3 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:05,481 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [239756383] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:41:05,481 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:41:05,481 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 14, 14] total 31 [2025-04-26 18:41:05,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2044474756] [2025-04-26 18:41:05,481 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:41:05,481 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:41:05,482 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:05,482 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 9 times [2025-04-26 18:41:05,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:05,482 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1768645764] [2025-04-26 18:41:05,482 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-04-26 18:41:05,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:05,483 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:05,484 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:05,484 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-04-26 18:41:05,484 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:05,484 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:41:05,484 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:05,484 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:05,485 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:05,485 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:05,486 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:05,507 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:41:05,508 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2025-04-26 18:41:05,508 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=146, Invalid=910, Unknown=0, NotChecked=0, Total=1056 [2025-04-26 18:41:05,508 INFO L87 Difference]: Start difference. First operand 1945 states and 3430 transitions. cyclomatic complexity: 1626 Second operand has 33 states, 32 states have (on average 2.53125) internal successors, (in total 81), 32 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:06,838 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:41:06,838 INFO L93 Difference]: Finished difference Result 5362 states and 9314 transitions. [2025-04-26 18:41:06,838 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5362 states and 9314 transitions. [2025-04-26 18:41:06,867 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 40 [2025-04-26 18:41:06,884 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5362 states to 5330 states and 9271 transitions. [2025-04-26 18:41:06,885 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 616 [2025-04-26 18:41:06,885 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 616 [2025-04-26 18:41:06,885 INFO L74 IsDeterministic]: Start isDeterministic. Operand 5330 states and 9271 transitions. [2025-04-26 18:41:06,885 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:41:06,886 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5330 states and 9271 transitions. [2025-04-26 18:41:06,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5330 states and 9271 transitions. [2025-04-26 18:41:06,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5330 to 2221. [2025-04-26 18:41:06,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2221 states, 2221 states have (on average 1.7663214768122468) internal successors, (in total 3923), 2220 states have internal predecessors, (3923), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:06,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2221 states to 2221 states and 3923 transitions. [2025-04-26 18:41:06,917 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2221 states and 3923 transitions. [2025-04-26 18:41:06,917 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2025-04-26 18:41:06,918 INFO L438 stractBuchiCegarLoop]: Abstraction has 2221 states and 3923 transitions. [2025-04-26 18:41:06,918 INFO L340 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2025-04-26 18:41:06,918 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2221 states and 3923 transitions. [2025-04-26 18:41:06,921 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:06,921 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:41:06,921 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:41:06,921 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1] [2025-04-26 18:41:06,921 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:41:06,922 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:41:06,922 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:41:06,922 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:06,922 INFO L85 PathProgramCache]: Analyzing trace with hash 1795289427, now seen corresponding path program 5 times [2025-04-26 18:41:06,922 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:06,923 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [456040173] [2025-04-26 18:41:06,923 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-04-26 18:41:06,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:06,924 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 31 statements into 3 equivalence classes. [2025-04-26 18:41:06,929 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 3 check-sat command(s) and asserted 31 of 31 statements. [2025-04-26 18:41:06,929 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 3 check-sat command(s) [2025-04-26 18:41:06,929 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:07,139 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:07,139 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:41:07,139 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [456040173] [2025-04-26 18:41:07,139 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [456040173] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:41:07,139 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [602679442] [2025-04-26 18:41:07,139 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-04-26 18:41:07,139 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:41:07,139 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:07,141 INFO L229 MonitoredProcess]: Starting monitored process 61 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:41:07,142 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Waiting until timeout for monitored process [2025-04-26 18:41:07,161 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 31 statements into 3 equivalence classes. [2025-04-26 18:41:07,169 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 3 check-sat command(s) and asserted 31 of 31 statements. [2025-04-26 18:41:07,169 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 3 check-sat command(s) [2025-04-26 18:41:07,169 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:07,170 INFO L256 TraceCheckSpWp]: Trace formula consists of 100 conjuncts, 17 conjuncts are in the unsatisfiable core [2025-04-26 18:41:07,171 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:07,239 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:41:07,263 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:41:07,266 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:07,266 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:41:07,290 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:07,290 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 13 treesize of output 17 [2025-04-26 18:41:07,344 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:07,345 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 21 [2025-04-26 18:41:07,432 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:07,433 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [602679442] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:41:07,433 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:41:07,433 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 9, 9] total 22 [2025-04-26 18:41:07,433 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1198482068] [2025-04-26 18:41:07,433 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:41:07,433 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:41:07,433 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:07,433 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 10 times [2025-04-26 18:41:07,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:07,433 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [84245075] [2025-04-26 18:41:07,433 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-04-26 18:41:07,434 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:07,435 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-04-26 18:41:07,435 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:07,435 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-04-26 18:41:07,435 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:07,435 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:41:07,436 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:07,436 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:07,436 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:07,437 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:07,438 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:07,460 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:41:07,461 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2025-04-26 18:41:07,461 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=470, Unknown=0, NotChecked=0, Total=552 [2025-04-26 18:41:07,461 INFO L87 Difference]: Start difference. First operand 2221 states and 3923 transitions. cyclomatic complexity: 1877 Second operand has 24 states, 23 states have (on average 3.130434782608696) internal successors, (in total 72), 23 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:07,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:41:07,804 INFO L93 Difference]: Finished difference Result 3057 states and 5325 transitions. [2025-04-26 18:41:07,804 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3057 states and 5325 transitions. [2025-04-26 18:41:07,811 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:07,818 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3057 states to 3032 states and 5281 transitions. [2025-04-26 18:41:07,818 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 332 [2025-04-26 18:41:07,818 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 334 [2025-04-26 18:41:07,818 INFO L74 IsDeterministic]: Start isDeterministic. Operand 3032 states and 5281 transitions. [2025-04-26 18:41:07,818 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:41:07,818 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3032 states and 5281 transitions. [2025-04-26 18:41:07,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3032 states and 5281 transitions. [2025-04-26 18:41:07,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3032 to 2182. [2025-04-26 18:41:07,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2182 states, 2182 states have (on average 1.7612282309807517) internal successors, (in total 3843), 2181 states have internal predecessors, (3843), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:07,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2182 states to 2182 states and 3843 transitions. [2025-04-26 18:41:07,841 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2182 states and 3843 transitions. [2025-04-26 18:41:07,841 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2025-04-26 18:41:07,841 INFO L438 stractBuchiCegarLoop]: Abstraction has 2182 states and 3843 transitions. [2025-04-26 18:41:07,841 INFO L340 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2025-04-26 18:41:07,841 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2182 states and 3843 transitions. [2025-04-26 18:41:07,845 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:07,845 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:41:07,845 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:41:07,845 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1] [2025-04-26 18:41:07,845 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:41:07,846 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:41:07,846 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:41:07,846 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:07,846 INFO L85 PathProgramCache]: Analyzing trace with hash 957784266, now seen corresponding path program 6 times [2025-04-26 18:41:07,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:07,846 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1403328446] [2025-04-26 18:41:07,846 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-04-26 18:41:07,846 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:07,848 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 33 statements into 5 equivalence classes. [2025-04-26 18:41:07,852 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) and asserted 33 of 33 statements. [2025-04-26 18:41:07,852 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2025-04-26 18:41:07,853 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:08,114 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 19 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2025-04-26 18:41:08,114 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:41:08,114 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1403328446] [2025-04-26 18:41:08,114 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1403328446] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:41:08,114 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1851978407] [2025-04-26 18:41:08,114 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-04-26 18:41:08,114 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:41:08,114 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:08,116 INFO L229 MonitoredProcess]: Starting monitored process 62 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:41:08,118 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Waiting until timeout for monitored process [2025-04-26 18:41:08,138 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 33 statements into 5 equivalence classes. [2025-04-26 18:41:08,149 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) and asserted 33 of 33 statements. [2025-04-26 18:41:08,149 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2025-04-26 18:41:08,149 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:08,150 INFO L256 TraceCheckSpWp]: Trace formula consists of 107 conjuncts, 17 conjuncts are in the unsatisfiable core [2025-04-26 18:41:08,151 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:08,251 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:41:08,308 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:41:08,322 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 2 proven. 17 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2025-04-26 18:41:08,323 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:41:08,372 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:08,373 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 13 treesize of output 17 [2025-04-26 18:41:08,440 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:08,440 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 15 treesize of output 19 [2025-04-26 18:41:08,594 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 4 proven. 15 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2025-04-26 18:41:08,594 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1851978407] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:41:08,594 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:41:08,594 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 8, 8] total 25 [2025-04-26 18:41:08,594 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1298944284] [2025-04-26 18:41:08,594 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:41:08,595 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:41:08,595 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:08,595 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 11 times [2025-04-26 18:41:08,595 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:08,595 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [878867932] [2025-04-26 18:41:08,595 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-04-26 18:41:08,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:08,596 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:08,597 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:08,597 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-04-26 18:41:08,597 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:08,597 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:41:08,597 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:08,598 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:08,598 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:08,598 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:08,598 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:08,624 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:41:08,625 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2025-04-26 18:41:08,625 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=106, Invalid=596, Unknown=0, NotChecked=0, Total=702 [2025-04-26 18:41:08,625 INFO L87 Difference]: Start difference. First operand 2182 states and 3843 transitions. cyclomatic complexity: 1833 Second operand has 27 states, 26 states have (on average 3.3846153846153846) internal successors, (in total 88), 26 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:09,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:41:09,325 INFO L93 Difference]: Finished difference Result 2976 states and 5162 transitions. [2025-04-26 18:41:09,325 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2976 states and 5162 transitions. [2025-04-26 18:41:09,331 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:09,337 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2976 states to 2963 states and 5141 transitions. [2025-04-26 18:41:09,337 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 326 [2025-04-26 18:41:09,338 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 326 [2025-04-26 18:41:09,338 INFO L74 IsDeterministic]: Start isDeterministic. Operand 2963 states and 5141 transitions. [2025-04-26 18:41:09,338 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:41:09,338 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2963 states and 5141 transitions. [2025-04-26 18:41:09,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2963 states and 5141 transitions. [2025-04-26 18:41:09,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2963 to 2034. [2025-04-26 18:41:09,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2034 states, 2034 states have (on average 1.7743362831858407) internal successors, (in total 3609), 2033 states have internal predecessors, (3609), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:09,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2034 states to 2034 states and 3609 transitions. [2025-04-26 18:41:09,360 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2034 states and 3609 transitions. [2025-04-26 18:41:09,364 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2025-04-26 18:41:09,364 INFO L438 stractBuchiCegarLoop]: Abstraction has 2034 states and 3609 transitions. [2025-04-26 18:41:09,364 INFO L340 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2025-04-26 18:41:09,364 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2034 states and 3609 transitions. [2025-04-26 18:41:09,368 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:09,368 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:41:09,368 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:41:09,368 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1] [2025-04-26 18:41:09,368 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:41:09,368 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:41:09,368 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:41:09,369 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:09,369 INFO L85 PathProgramCache]: Analyzing trace with hash 2099272842, now seen corresponding path program 7 times [2025-04-26 18:41:09,369 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:09,369 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [219370910] [2025-04-26 18:41:09,369 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-04-26 18:41:09,369 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:09,371 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 36 statements into 1 equivalence classes. [2025-04-26 18:41:09,374 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 36 of 36 statements. [2025-04-26 18:41:09,374 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:09,374 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:09,413 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 18 proven. 9 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2025-04-26 18:41:09,413 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:41:09,413 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [219370910] [2025-04-26 18:41:09,413 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [219370910] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:41:09,413 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1908840307] [2025-04-26 18:41:09,413 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-04-26 18:41:09,413 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:41:09,413 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:09,415 INFO L229 MonitoredProcess]: Starting monitored process 63 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:41:09,417 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Waiting until timeout for monitored process [2025-04-26 18:41:09,437 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 36 statements into 1 equivalence classes. [2025-04-26 18:41:09,446 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 36 of 36 statements. [2025-04-26 18:41:09,447 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:09,447 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:09,447 INFO L256 TraceCheckSpWp]: Trace formula consists of 113 conjuncts, 6 conjuncts are in the unsatisfiable core [2025-04-26 18:41:09,448 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:09,483 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 18 proven. 9 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2025-04-26 18:41:09,484 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:41:09,525 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 18 proven. 9 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2025-04-26 18:41:09,525 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1908840307] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:41:09,525 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:41:09,525 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 4, 4] total 5 [2025-04-26 18:41:09,525 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1982478842] [2025-04-26 18:41:09,525 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:41:09,525 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:41:09,525 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:09,525 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 12 times [2025-04-26 18:41:09,525 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:09,526 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [856839491] [2025-04-26 18:41:09,526 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-04-26 18:41:09,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:09,527 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:09,527 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:09,527 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-04-26 18:41:09,527 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:09,527 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:41:09,528 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:09,528 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:09,528 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:09,528 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:09,530 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:09,549 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:41:09,550 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-04-26 18:41:09,550 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2025-04-26 18:41:09,550 INFO L87 Difference]: Start difference. First operand 2034 states and 3609 transitions. cyclomatic complexity: 1738 Second operand has 6 states, 6 states have (on average 6.833333333333333) internal successors, (in total 41), 5 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:09,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:41:09,585 INFO L93 Difference]: Finished difference Result 4166 states and 7701 transitions. [2025-04-26 18:41:09,585 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4166 states and 7701 transitions. [2025-04-26 18:41:09,595 INFO L131 ngComponentsAnalysis]: Automaton has 34 accepting balls. 68 [2025-04-26 18:41:09,606 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4166 states to 4026 states and 7462 transitions. [2025-04-26 18:41:09,606 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 493 [2025-04-26 18:41:09,607 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 495 [2025-04-26 18:41:09,607 INFO L74 IsDeterministic]: Start isDeterministic. Operand 4026 states and 7462 transitions. [2025-04-26 18:41:09,607 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:41:09,607 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4026 states and 7462 transitions. [2025-04-26 18:41:09,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4026 states and 7462 transitions. [2025-04-26 18:41:09,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4026 to 2840. [2025-04-26 18:41:09,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2840 states, 2840 states have (on average 1.75) internal successors, (in total 4970), 2839 states have internal predecessors, (4970), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:09,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2840 states to 2840 states and 4970 transitions. [2025-04-26 18:41:09,679 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2840 states and 4970 transitions. [2025-04-26 18:41:09,680 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-04-26 18:41:09,680 INFO L438 stractBuchiCegarLoop]: Abstraction has 2840 states and 4970 transitions. [2025-04-26 18:41:09,680 INFO L340 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2025-04-26 18:41:09,680 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2840 states and 4970 transitions. [2025-04-26 18:41:09,686 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:09,687 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:41:09,687 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:41:09,687 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1] [2025-04-26 18:41:09,687 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:41:09,688 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:41:09,688 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:41:09,688 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:09,688 INFO L85 PathProgramCache]: Analyzing trace with hash -1733774045, now seen corresponding path program 8 times [2025-04-26 18:41:09,688 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:09,689 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [243637607] [2025-04-26 18:41:09,689 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-04-26 18:41:09,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:09,691 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 43 statements into 2 equivalence classes. [2025-04-26 18:41:09,704 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 43 of 43 statements. [2025-04-26 18:41:09,704 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-04-26 18:41:09,705 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:09,982 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 0 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:09,982 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:41:09,982 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [243637607] [2025-04-26 18:41:09,982 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [243637607] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:41:09,982 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1305369636] [2025-04-26 18:41:09,982 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-04-26 18:41:09,982 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:41:09,982 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:09,984 INFO L229 MonitoredProcess]: Starting monitored process 64 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:41:09,986 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Waiting until timeout for monitored process [2025-04-26 18:41:10,011 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 43 statements into 2 equivalence classes. [2025-04-26 18:41:10,022 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 43 of 43 statements. [2025-04-26 18:41:10,023 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-04-26 18:41:10,023 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:10,023 INFO L256 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 26 conjuncts are in the unsatisfiable core [2025-04-26 18:41:10,024 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:10,152 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:41:10,188 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:41:10,194 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 0 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:10,194 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:41:10,253 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:10,253 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 15 treesize of output 19 [2025-04-26 18:41:10,303 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:10,303 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 21 [2025-04-26 18:41:10,323 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 0 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:10,323 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1305369636] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:41:10,323 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:41:10,323 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 14, 14] total 21 [2025-04-26 18:41:10,323 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2086570091] [2025-04-26 18:41:10,323 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:41:10,323 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:41:10,323 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:10,323 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 13 times [2025-04-26 18:41:10,323 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:10,324 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1129235640] [2025-04-26 18:41:10,324 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-04-26 18:41:10,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:10,325 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:10,325 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:10,325 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:10,325 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:10,325 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:41:10,326 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:10,326 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:10,326 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:10,326 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:10,327 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:10,349 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:41:10,350 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2025-04-26 18:41:10,350 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=456, Unknown=0, NotChecked=0, Total=506 [2025-04-26 18:41:10,350 INFO L87 Difference]: Start difference. First operand 2840 states and 4970 transitions. cyclomatic complexity: 2353 Second operand has 23 states, 22 states have (on average 2.772727272727273) internal successors, (in total 61), 22 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:10,941 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:41:10,941 INFO L93 Difference]: Finished difference Result 3552 states and 6133 transitions. [2025-04-26 18:41:10,941 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3552 states and 6133 transitions. [2025-04-26 18:41:10,951 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:10,959 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3552 states to 3549 states and 6130 transitions. [2025-04-26 18:41:10,959 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 377 [2025-04-26 18:41:10,960 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 377 [2025-04-26 18:41:10,960 INFO L74 IsDeterministic]: Start isDeterministic. Operand 3549 states and 6130 transitions. [2025-04-26 18:41:10,960 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:41:10,960 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3549 states and 6130 transitions. [2025-04-26 18:41:10,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3549 states and 6130 transitions. [2025-04-26 18:41:10,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3549 to 3040. [2025-04-26 18:41:10,988 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3040 states, 3040 states have (on average 1.7424342105263158) internal successors, (in total 5297), 3039 states have internal predecessors, (5297), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:10,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3040 states to 3040 states and 5297 transitions. [2025-04-26 18:41:10,994 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3040 states and 5297 transitions. [2025-04-26 18:41:10,994 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2025-04-26 18:41:10,994 INFO L438 stractBuchiCegarLoop]: Abstraction has 3040 states and 5297 transitions. [2025-04-26 18:41:10,994 INFO L340 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2025-04-26 18:41:10,994 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3040 states and 5297 transitions. [2025-04-26 18:41:11,001 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:11,001 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:41:11,001 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:41:11,001 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1] [2025-04-26 18:41:11,001 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:41:11,002 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:41:11,002 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:41:11,002 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:11,002 INFO L85 PathProgramCache]: Analyzing trace with hash 2113955161, now seen corresponding path program 9 times [2025-04-26 18:41:11,002 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:11,002 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2003215262] [2025-04-26 18:41:11,002 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-04-26 18:41:11,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:11,005 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 43 statements into 5 equivalence classes. [2025-04-26 18:41:11,017 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) and asserted 43 of 43 statements. [2025-04-26 18:41:11,018 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2025-04-26 18:41:11,018 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:11,426 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:11,426 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:41:11,426 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2003215262] [2025-04-26 18:41:11,426 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2003215262] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:41:11,426 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1415783029] [2025-04-26 18:41:11,426 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-04-26 18:41:11,427 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:41:11,427 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:11,429 INFO L229 MonitoredProcess]: Starting monitored process 65 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:41:11,450 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Waiting until timeout for monitored process [2025-04-26 18:41:11,473 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 43 statements into 5 equivalence classes. [2025-04-26 18:41:11,486 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) and asserted 43 of 43 statements. [2025-04-26 18:41:11,486 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2025-04-26 18:41:11,486 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:11,487 INFO L256 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 26 conjuncts are in the unsatisfiable core [2025-04-26 18:41:11,487 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:11,659 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:41:11,718 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 11 [2025-04-26 18:41:11,722 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:11,723 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:41:11,784 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:11,784 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 24 treesize of output 24 [2025-04-26 18:41:11,859 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:11,860 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 21 [2025-04-26 18:41:11,879 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:11,879 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1415783029] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:41:11,879 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:41:11,879 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 13, 13] total 25 [2025-04-26 18:41:11,879 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1997065093] [2025-04-26 18:41:11,879 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:41:11,879 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:41:11,879 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:11,880 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 14 times [2025-04-26 18:41:11,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:11,880 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [976564123] [2025-04-26 18:41:11,880 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-04-26 18:41:11,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:11,881 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:11,882 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:11,882 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-04-26 18:41:11,882 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:11,882 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:41:11,882 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:11,882 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:11,882 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:11,882 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:11,883 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:11,908 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:41:11,909 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2025-04-26 18:41:11,909 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=638, Unknown=0, NotChecked=0, Total=702 [2025-04-26 18:41:11,909 INFO L87 Difference]: Start difference. First operand 3040 states and 5297 transitions. cyclomatic complexity: 2500 Second operand has 27 states, 26 states have (on average 2.9615384615384617) internal successors, (in total 77), 26 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:12,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:41:12,496 INFO L93 Difference]: Finished difference Result 4018 states and 6886 transitions. [2025-04-26 18:41:12,497 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4018 states and 6886 transitions. [2025-04-26 18:41:12,508 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:12,519 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4018 states to 3996 states and 6854 transitions. [2025-04-26 18:41:12,520 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 424 [2025-04-26 18:41:12,520 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 424 [2025-04-26 18:41:12,520 INFO L74 IsDeterministic]: Start isDeterministic. Operand 3996 states and 6854 transitions. [2025-04-26 18:41:12,520 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:41:12,520 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3996 states and 6854 transitions. [2025-04-26 18:41:12,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3996 states and 6854 transitions. [2025-04-26 18:41:12,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3996 to 3093. [2025-04-26 18:41:12,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3093 states, 3093 states have (on average 1.7429679922405432) internal successors, (in total 5391), 3092 states have internal predecessors, (5391), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:12,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3093 states to 3093 states and 5391 transitions. [2025-04-26 18:41:12,550 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3093 states and 5391 transitions. [2025-04-26 18:41:12,551 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2025-04-26 18:41:12,551 INFO L438 stractBuchiCegarLoop]: Abstraction has 3093 states and 5391 transitions. [2025-04-26 18:41:12,552 INFO L340 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2025-04-26 18:41:12,552 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3093 states and 5391 transitions. [2025-04-26 18:41:12,557 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:12,558 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:41:12,558 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:41:12,558 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1] [2025-04-26 18:41:12,558 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:41:12,558 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:41:12,558 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:41:12,558 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:12,559 INFO L85 PathProgramCache]: Analyzing trace with hash -595885881, now seen corresponding path program 10 times [2025-04-26 18:41:12,559 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:12,559 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [485277518] [2025-04-26 18:41:12,559 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-04-26 18:41:12,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:12,561 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 43 statements into 2 equivalence classes. [2025-04-26 18:41:12,569 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-04-26 18:41:12,569 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-04-26 18:41:12,569 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:12,818 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:12,818 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:41:12,818 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [485277518] [2025-04-26 18:41:12,818 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [485277518] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:41:12,818 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1018092710] [2025-04-26 18:41:12,819 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-04-26 18:41:12,819 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:41:12,819 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:12,821 INFO L229 MonitoredProcess]: Starting monitored process 66 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:41:12,822 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Waiting until timeout for monitored process [2025-04-26 18:41:12,844 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 43 statements into 2 equivalence classes. [2025-04-26 18:41:12,855 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-04-26 18:41:12,856 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-04-26 18:41:12,856 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:12,856 INFO L256 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 47 conjuncts are in the unsatisfiable core [2025-04-26 18:41:12,857 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:13,417 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:13,417 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 25 treesize of output 13 [2025-04-26 18:41:13,422 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:13,422 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:41:13,570 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:13,571 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 23 [2025-04-26 18:41:13,695 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:13,696 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 41 treesize of output 55 [2025-04-26 18:41:14,030 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:14,031 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 73 treesize of output 137 [2025-04-26 18:41:14,213 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 11 proven. 31 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:14,213 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1018092710] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:41:14,213 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:41:14,213 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 16, 16] total 40 [2025-04-26 18:41:14,213 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1357998007] [2025-04-26 18:41:14,213 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:41:14,214 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:41:14,214 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:14,214 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 15 times [2025-04-26 18:41:14,214 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:14,214 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [443603683] [2025-04-26 18:41:14,214 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-04-26 18:41:14,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:14,215 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:14,216 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:14,216 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-04-26 18:41:14,216 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:14,216 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:41:14,216 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:14,216 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:14,216 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:14,216 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:14,217 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:14,233 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:41:14,233 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2025-04-26 18:41:14,234 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=219, Invalid=1503, Unknown=0, NotChecked=0, Total=1722 [2025-04-26 18:41:14,234 INFO L87 Difference]: Start difference. First operand 3093 states and 5391 transitions. cyclomatic complexity: 2547 Second operand has 42 states, 41 states have (on average 2.8292682926829267) internal successors, (in total 116), 41 states have internal predecessors, (116), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:16,040 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:41:16,041 INFO L93 Difference]: Finished difference Result 7836 states and 13303 transitions. [2025-04-26 18:41:16,041 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7836 states and 13303 transitions. [2025-04-26 18:41:16,082 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:16,107 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7836 states to 7785 states and 13219 transitions. [2025-04-26 18:41:16,107 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 769 [2025-04-26 18:41:16,108 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 769 [2025-04-26 18:41:16,108 INFO L74 IsDeterministic]: Start isDeterministic. Operand 7785 states and 13219 transitions. [2025-04-26 18:41:16,108 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:41:16,108 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7785 states and 13219 transitions. [2025-04-26 18:41:16,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7785 states and 13219 transitions. [2025-04-26 18:41:16,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7785 to 3720. [2025-04-26 18:41:16,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3720 states, 3720 states have (on average 1.739784946236559) internal successors, (in total 6472), 3719 states have internal predecessors, (6472), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:16,170 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3720 states to 3720 states and 6472 transitions. [2025-04-26 18:41:16,170 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3720 states and 6472 transitions. [2025-04-26 18:41:16,175 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2025-04-26 18:41:16,175 INFO L438 stractBuchiCegarLoop]: Abstraction has 3720 states and 6472 transitions. [2025-04-26 18:41:16,175 INFO L340 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2025-04-26 18:41:16,175 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3720 states and 6472 transitions. [2025-04-26 18:41:16,186 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:16,186 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:41:16,186 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:41:16,186 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1] [2025-04-26 18:41:16,186 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:41:16,187 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:41:16,187 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:41:16,187 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:16,188 INFO L85 PathProgramCache]: Analyzing trace with hash 136079075, now seen corresponding path program 11 times [2025-04-26 18:41:16,188 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:16,188 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1597806546] [2025-04-26 18:41:16,188 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-04-26 18:41:16,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:16,191 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 43 statements into 6 equivalence classes. [2025-04-26 18:41:16,200 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) and asserted 43 of 43 statements. [2025-04-26 18:41:16,200 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2025-04-26 18:41:16,200 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:16,574 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 4 proven. 39 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:16,574 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:41:16,574 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1597806546] [2025-04-26 18:41:16,574 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1597806546] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:41:16,574 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1769244225] [2025-04-26 18:41:16,574 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-04-26 18:41:16,574 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:41:16,574 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:16,578 INFO L229 MonitoredProcess]: Starting monitored process 67 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:41:16,579 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Waiting until timeout for monitored process [2025-04-26 18:41:16,602 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 43 statements into 6 equivalence classes. [2025-04-26 18:41:16,616 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) and asserted 43 of 43 statements. [2025-04-26 18:41:16,616 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2025-04-26 18:41:16,616 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:16,617 INFO L256 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 26 conjuncts are in the unsatisfiable core [2025-04-26 18:41:16,618 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:16,777 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:41:16,804 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:41:16,809 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 43 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:16,809 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:41:16,846 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:16,847 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 15 treesize of output 19 [2025-04-26 18:41:16,912 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:16,913 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 21 [2025-04-26 18:41:16,932 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 43 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:16,933 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1769244225] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:41:16,933 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:41:16,933 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 13, 13] total 24 [2025-04-26 18:41:16,933 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1513556291] [2025-04-26 18:41:16,933 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:41:16,934 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:41:16,934 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:16,934 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 16 times [2025-04-26 18:41:16,934 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:16,934 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [398252746] [2025-04-26 18:41:16,934 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-04-26 18:41:16,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:16,935 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-04-26 18:41:16,936 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:16,936 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-04-26 18:41:16,936 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:16,936 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:41:16,936 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:16,936 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:16,936 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:16,936 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:16,937 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:16,957 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:41:16,957 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2025-04-26 18:41:16,957 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=92, Invalid=558, Unknown=0, NotChecked=0, Total=650 [2025-04-26 18:41:16,957 INFO L87 Difference]: Start difference. First operand 3720 states and 6472 transitions. cyclomatic complexity: 3047 Second operand has 26 states, 25 states have (on average 2.92) internal successors, (in total 73), 25 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:21,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:41:21,127 INFO L93 Difference]: Finished difference Result 16908 states and 28275 transitions. [2025-04-26 18:41:21,127 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16908 states and 28275 transitions. [2025-04-26 18:41:21,176 INFO L131 ngComponentsAnalysis]: Automaton has 200 accepting balls. 400 [2025-04-26 18:41:21,221 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16908 states to 16671 states and 27954 transitions. [2025-04-26 18:41:21,222 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1954 [2025-04-26 18:41:21,224 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1954 [2025-04-26 18:41:21,224 INFO L74 IsDeterministic]: Start isDeterministic. Operand 16671 states and 27954 transitions. [2025-04-26 18:41:21,224 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:41:21,224 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16671 states and 27954 transitions. [2025-04-26 18:41:21,235 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16671 states and 27954 transitions. [2025-04-26 18:41:21,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16671 to 5593. [2025-04-26 18:41:21,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5593 states, 5593 states have (on average 1.68138744859646) internal successors, (in total 9404), 5592 states have internal predecessors, (9404), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:21,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5593 states to 5593 states and 9404 transitions. [2025-04-26 18:41:21,326 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5593 states and 9404 transitions. [2025-04-26 18:41:21,327 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 152 states. [2025-04-26 18:41:21,327 INFO L438 stractBuchiCegarLoop]: Abstraction has 5593 states and 9404 transitions. [2025-04-26 18:41:21,327 INFO L340 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2025-04-26 18:41:21,327 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5593 states and 9404 transitions. [2025-04-26 18:41:21,337 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:21,337 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:41:21,337 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:41:21,337 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1] [2025-04-26 18:41:21,337 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:41:21,338 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:41:21,338 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:41:21,338 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:21,338 INFO L85 PathProgramCache]: Analyzing trace with hash -1999104733, now seen corresponding path program 12 times [2025-04-26 18:41:21,338 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:21,338 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1826636036] [2025-04-26 18:41:21,338 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-04-26 18:41:21,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:21,341 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 43 statements into 4 equivalence classes. [2025-04-26 18:41:21,348 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 4 check-sat command(s) and asserted 43 of 43 statements. [2025-04-26 18:41:21,348 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 4 check-sat command(s) [2025-04-26 18:41:21,348 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:21,636 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 2 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:21,636 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:41:21,636 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1826636036] [2025-04-26 18:41:21,636 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1826636036] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:41:21,636 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1318558619] [2025-04-26 18:41:21,636 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-04-26 18:41:21,637 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:41:21,637 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:21,665 INFO L229 MonitoredProcess]: Starting monitored process 68 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:41:21,666 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Waiting until timeout for monitored process [2025-04-26 18:41:21,687 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 43 statements into 4 equivalence classes. [2025-04-26 18:41:21,698 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 4 check-sat command(s) and asserted 43 of 43 statements. [2025-04-26 18:41:21,698 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 4 check-sat command(s) [2025-04-26 18:41:21,698 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:21,699 INFO L256 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 20 conjuncts are in the unsatisfiable core [2025-04-26 18:41:21,700 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:21,808 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:41:21,952 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:41:21,956 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 9 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:21,956 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:41:22,081 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:22,081 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 13 treesize of output 17 [2025-04-26 18:41:22,155 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:22,155 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 27 [2025-04-26 18:41:22,384 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 2 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:22,384 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1318558619] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:41:22,384 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:41:22,384 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 13, 13] total 36 [2025-04-26 18:41:22,384 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [704197583] [2025-04-26 18:41:22,384 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:41:22,384 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:41:22,385 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:22,385 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 17 times [2025-04-26 18:41:22,385 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:22,385 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1539321384] [2025-04-26 18:41:22,385 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-04-26 18:41:22,385 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:22,386 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:22,386 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:22,387 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-04-26 18:41:22,387 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:22,387 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:41:22,387 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:22,387 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:22,387 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:22,387 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:22,388 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:22,414 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:41:22,414 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2025-04-26 18:41:22,415 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=263, Invalid=1143, Unknown=0, NotChecked=0, Total=1406 [2025-04-26 18:41:22,415 INFO L87 Difference]: Start difference. First operand 5593 states and 9404 transitions. cyclomatic complexity: 4217 Second operand has 38 states, 37 states have (on average 3.2972972972972974) internal successors, (in total 122), 37 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:33,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:41:33,591 INFO L93 Difference]: Finished difference Result 45783 states and 83850 transitions. [2025-04-26 18:41:33,591 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45783 states and 83850 transitions. [2025-04-26 18:41:33,784 INFO L131 ngComponentsAnalysis]: Automaton has 624 accepting balls. 1248 [2025-04-26 18:41:33,927 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45783 states to 41556 states and 77357 transitions. [2025-04-26 18:41:33,928 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4972 [2025-04-26 18:41:33,936 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5081 [2025-04-26 18:41:33,936 INFO L74 IsDeterministic]: Start isDeterministic. Operand 41556 states and 77357 transitions. [2025-04-26 18:41:33,936 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:41:33,937 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41556 states and 77357 transitions. [2025-04-26 18:41:33,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41556 states and 77357 transitions. [2025-04-26 18:41:34,352 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41556 to 12013. [2025-04-26 18:41:34,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12013 states, 12013 states have (on average 1.7342046116706902) internal successors, (in total 20833), 12012 states have internal predecessors, (20833), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:34,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12013 states to 12013 states and 20833 transitions. [2025-04-26 18:41:34,379 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12013 states and 20833 transitions. [2025-04-26 18:41:34,379 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 370 states. [2025-04-26 18:41:34,379 INFO L438 stractBuchiCegarLoop]: Abstraction has 12013 states and 20833 transitions. [2025-04-26 18:41:34,379 INFO L340 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2025-04-26 18:41:34,380 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12013 states and 20833 transitions. [2025-04-26 18:41:34,402 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:34,402 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:41:34,402 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:41:34,403 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1] [2025-04-26 18:41:34,403 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:41:34,403 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:41:34,403 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:41:34,404 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:34,404 INFO L85 PathProgramCache]: Analyzing trace with hash 2056378121, now seen corresponding path program 13 times [2025-04-26 18:41:34,404 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:34,404 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1337909887] [2025-04-26 18:41:34,404 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-04-26 18:41:34,404 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:34,406 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-04-26 18:41:34,412 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-04-26 18:41:34,412 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:34,412 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:34,622 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:34,623 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:41:34,623 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1337909887] [2025-04-26 18:41:34,623 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1337909887] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:41:34,623 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1790320690] [2025-04-26 18:41:34,623 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-04-26 18:41:34,623 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:41:34,623 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:34,625 INFO L229 MonitoredProcess]: Starting monitored process 69 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:41:34,627 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Waiting until timeout for monitored process [2025-04-26 18:41:34,649 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-04-26 18:41:34,661 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-04-26 18:41:34,661 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:34,661 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:34,662 INFO L256 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 32 conjuncts are in the unsatisfiable core [2025-04-26 18:41:34,663 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:34,863 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:34,863 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 18 treesize of output 10 [2025-04-26 18:41:34,971 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:34,972 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 18 treesize of output 10 [2025-04-26 18:41:34,975 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:34,975 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:41:35,160 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:35,160 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 29 treesize of output 37 [2025-04-26 18:41:35,328 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:35,328 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 41 treesize of output 65 [2025-04-26 18:41:35,419 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 10 proven. 39 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:35,420 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1790320690] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:41:35,420 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:41:35,420 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 34 [2025-04-26 18:41:35,420 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [9158445] [2025-04-26 18:41:35,420 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:41:35,420 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:41:35,420 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:35,420 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 18 times [2025-04-26 18:41:35,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:35,420 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1541912766] [2025-04-26 18:41:35,420 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-04-26 18:41:35,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:35,421 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:35,422 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:35,422 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-04-26 18:41:35,422 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:35,422 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:41:35,422 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:35,423 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:35,423 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:35,423 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:35,423 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:35,443 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:41:35,443 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2025-04-26 18:41:35,444 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=128, Invalid=1132, Unknown=0, NotChecked=0, Total=1260 [2025-04-26 18:41:35,444 INFO L87 Difference]: Start difference. First operand 12013 states and 20833 transitions. cyclomatic complexity: 9593 Second operand has 36 states, 35 states have (on average 2.9714285714285715) internal successors, (in total 104), 35 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:37,552 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:41:37,553 INFO L93 Difference]: Finished difference Result 20763 states and 37206 transitions. [2025-04-26 18:41:37,553 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20763 states and 37206 transitions. [2025-04-26 18:41:37,620 INFO L131 ngComponentsAnalysis]: Automaton has 160 accepting balls. 320 [2025-04-26 18:41:37,677 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20763 states to 20760 states and 37203 transitions. [2025-04-26 18:41:37,677 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1919 [2025-04-26 18:41:37,680 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1919 [2025-04-26 18:41:37,680 INFO L74 IsDeterministic]: Start isDeterministic. Operand 20760 states and 37203 transitions. [2025-04-26 18:41:37,680 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:41:37,680 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20760 states and 37203 transitions. [2025-04-26 18:41:37,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20760 states and 37203 transitions. [2025-04-26 18:41:37,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20760 to 13086. [2025-04-26 18:41:37,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13086 states, 13086 states have (on average 1.7326914259513984) internal successors, (in total 22674), 13085 states have internal predecessors, (22674), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:38,021 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13086 states to 13086 states and 22674 transitions. [2025-04-26 18:41:38,022 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13086 states and 22674 transitions. [2025-04-26 18:41:38,022 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 78 states. [2025-04-26 18:41:38,022 INFO L438 stractBuchiCegarLoop]: Abstraction has 13086 states and 22674 transitions. [2025-04-26 18:41:38,022 INFO L340 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2025-04-26 18:41:38,023 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13086 states and 22674 transitions. [2025-04-26 18:41:38,051 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:38,051 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:41:38,051 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:41:38,051 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1] [2025-04-26 18:41:38,051 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:41:38,052 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:41:38,052 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:41:38,052 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:38,052 INFO L85 PathProgramCache]: Analyzing trace with hash 1609140031, now seen corresponding path program 14 times [2025-04-26 18:41:38,052 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:38,052 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2071929300] [2025-04-26 18:41:38,052 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-04-26 18:41:38,052 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:38,054 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 43 statements into 2 equivalence classes. [2025-04-26 18:41:38,062 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 43 of 43 statements. [2025-04-26 18:41:38,062 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-04-26 18:41:38,063 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:38,285 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 39 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:38,285 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:41:38,285 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2071929300] [2025-04-26 18:41:38,285 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2071929300] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:41:38,285 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1388238491] [2025-04-26 18:41:38,285 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-04-26 18:41:38,285 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:41:38,285 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:38,288 INFO L229 MonitoredProcess]: Starting monitored process 70 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:41:38,289 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Waiting until timeout for monitored process [2025-04-26 18:41:38,311 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 43 statements into 2 equivalence classes. [2025-04-26 18:41:38,322 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 43 of 43 statements. [2025-04-26 18:41:38,323 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-04-26 18:41:38,323 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:38,323 INFO L256 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 26 conjuncts are in the unsatisfiable core [2025-04-26 18:41:38,324 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:38,420 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:41:38,447 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:41:38,450 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 39 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:38,451 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:41:38,494 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:38,495 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 15 treesize of output 19 [2025-04-26 18:41:38,533 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:38,534 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 23 [2025-04-26 18:41:38,563 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 39 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:38,563 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1388238491] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:41:38,564 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:41:38,564 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 12, 12] total 17 [2025-04-26 18:41:38,564 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1174802906] [2025-04-26 18:41:38,564 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:41:38,564 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:41:38,564 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:38,564 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 19 times [2025-04-26 18:41:38,564 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:38,564 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1646796175] [2025-04-26 18:41:38,564 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-04-26 18:41:38,564 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:38,565 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:38,566 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:38,566 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:38,566 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:38,566 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:41:38,566 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:38,566 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:38,566 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:38,566 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:38,567 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:38,589 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:41:38,589 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2025-04-26 18:41:38,589 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=300, Unknown=0, NotChecked=0, Total=342 [2025-04-26 18:41:38,590 INFO L87 Difference]: Start difference. First operand 13086 states and 22674 transitions. cyclomatic complexity: 10468 Second operand has 19 states, 18 states have (on average 3.0555555555555554) internal successors, (in total 55), 18 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:39,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:41:39,418 INFO L93 Difference]: Finished difference Result 19650 states and 34943 transitions. [2025-04-26 18:41:39,418 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19650 states and 34943 transitions. [2025-04-26 18:41:39,477 INFO L131 ngComponentsAnalysis]: Automaton has 106 accepting balls. 212 [2025-04-26 18:41:39,525 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19650 states to 19618 states and 34884 transitions. [2025-04-26 18:41:39,526 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1648 [2025-04-26 18:41:39,528 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1659 [2025-04-26 18:41:39,528 INFO L74 IsDeterministic]: Start isDeterministic. Operand 19618 states and 34884 transitions. [2025-04-26 18:41:39,528 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:41:39,528 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19618 states and 34884 transitions. [2025-04-26 18:41:39,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19618 states and 34884 transitions. [2025-04-26 18:41:39,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19618 to 13426. [2025-04-26 18:41:39,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13426 states, 13426 states have (on average 1.7323104424251452) internal successors, (in total 23258), 13425 states have internal predecessors, (23258), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:39,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13426 states to 13426 states and 23258 transitions. [2025-04-26 18:41:39,794 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13426 states and 23258 transitions. [2025-04-26 18:41:39,794 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2025-04-26 18:41:39,794 INFO L438 stractBuchiCegarLoop]: Abstraction has 13426 states and 23258 transitions. [2025-04-26 18:41:39,794 INFO L340 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2025-04-26 18:41:39,794 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13426 states and 23258 transitions. [2025-04-26 18:41:39,817 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:39,817 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:41:39,817 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:41:39,817 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1] [2025-04-26 18:41:39,817 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:41:39,818 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:41:39,818 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:41:39,818 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:39,818 INFO L85 PathProgramCache]: Analyzing trace with hash 1216390199, now seen corresponding path program 15 times [2025-04-26 18:41:39,818 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:39,818 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2006715843] [2025-04-26 18:41:39,818 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-04-26 18:41:39,818 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:39,820 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 43 statements into 5 equivalence classes. [2025-04-26 18:41:39,826 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) and asserted 43 of 43 statements. [2025-04-26 18:41:39,827 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2025-04-26 18:41:39,827 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:40,236 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 39 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:40,236 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:41:40,236 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2006715843] [2025-04-26 18:41:40,236 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2006715843] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:41:40,236 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [704416750] [2025-04-26 18:41:40,236 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-04-26 18:41:40,236 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:41:40,236 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:40,238 INFO L229 MonitoredProcess]: Starting monitored process 71 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:41:40,239 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (71)] Waiting until timeout for monitored process [2025-04-26 18:41:40,258 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 43 statements into 5 equivalence classes. [2025-04-26 18:41:40,269 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) and asserted 43 of 43 statements. [2025-04-26 18:41:40,269 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2025-04-26 18:41:40,269 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:40,270 INFO L256 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 23 conjuncts are in the unsatisfiable core [2025-04-26 18:41:40,270 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:40,428 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:41:40,484 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:41:40,498 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 3 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:40,499 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:41:40,542 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:40,542 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 22 [2025-04-26 18:41:40,774 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:40,774 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 29 [2025-04-26 18:41:40,918 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 5 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:40,918 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [704416750] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:41:40,918 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:41:40,918 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 12, 12] total 37 [2025-04-26 18:41:40,918 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1239828678] [2025-04-26 18:41:40,918 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:41:40,918 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:41:40,919 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:40,919 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 20 times [2025-04-26 18:41:40,919 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:40,919 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [76028399] [2025-04-26 18:41:40,919 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-04-26 18:41:40,919 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:40,920 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:40,920 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:40,920 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-04-26 18:41:40,920 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:40,920 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:41:40,921 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:40,921 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:40,921 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:40,921 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:40,922 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:40,940 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:41:40,941 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2025-04-26 18:41:40,941 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=260, Invalid=1222, Unknown=0, NotChecked=0, Total=1482 [2025-04-26 18:41:40,941 INFO L87 Difference]: Start difference. First operand 13426 states and 23258 transitions. cyclomatic complexity: 10752 Second operand has 39 states, 38 states have (on average 3.1578947368421053) internal successors, (in total 120), 38 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:43,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:41:43,178 INFO L93 Difference]: Finished difference Result 19061 states and 32725 transitions. [2025-04-26 18:41:43,178 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19061 states and 32725 transitions. [2025-04-26 18:41:43,257 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:43,310 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19061 states to 18968 states and 32580 transitions. [2025-04-26 18:41:43,310 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1135 [2025-04-26 18:41:43,312 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1160 [2025-04-26 18:41:43,312 INFO L74 IsDeterministic]: Start isDeterministic. Operand 18968 states and 32580 transitions. [2025-04-26 18:41:43,312 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:41:43,312 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18968 states and 32580 transitions. [2025-04-26 18:41:43,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18968 states and 32580 transitions. [2025-04-26 18:41:43,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18968 to 13929. [2025-04-26 18:41:43,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13929 states, 13929 states have (on average 1.727187881398521) internal successors, (in total 24058), 13928 states have internal predecessors, (24058), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:43,506 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13929 states to 13929 states and 24058 transitions. [2025-04-26 18:41:43,507 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13929 states and 24058 transitions. [2025-04-26 18:41:43,507 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2025-04-26 18:41:43,507 INFO L438 stractBuchiCegarLoop]: Abstraction has 13929 states and 24058 transitions. [2025-04-26 18:41:43,507 INFO L340 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2025-04-26 18:41:43,507 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13929 states and 24058 transitions. [2025-04-26 18:41:43,545 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:43,546 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:41:43,546 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:41:43,546 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1] [2025-04-26 18:41:43,546 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:41:43,547 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:41:43,547 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:41:43,547 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:43,547 INFO L85 PathProgramCache]: Analyzing trace with hash -368736055, now seen corresponding path program 16 times [2025-04-26 18:41:43,547 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:43,547 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1112293970] [2025-04-26 18:41:43,547 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-04-26 18:41:43,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:43,550 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 43 statements into 2 equivalence classes. [2025-04-26 18:41:43,561 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-04-26 18:41:43,561 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-04-26 18:41:43,561 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:43,800 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 39 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:43,800 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:41:43,800 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1112293970] [2025-04-26 18:41:43,800 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1112293970] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:41:43,800 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1324333130] [2025-04-26 18:41:43,800 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-04-26 18:41:43,800 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:41:43,800 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:43,802 INFO L229 MonitoredProcess]: Starting monitored process 72 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:41:43,804 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (72)] Waiting until timeout for monitored process [2025-04-26 18:41:43,827 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 43 statements into 2 equivalence classes. [2025-04-26 18:41:43,840 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-04-26 18:41:43,840 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-04-26 18:41:43,840 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:43,841 INFO L256 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 33 conjuncts are in the unsatisfiable core [2025-04-26 18:41:43,842 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:44,186 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:44,187 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 18 treesize of output 10 [2025-04-26 18:41:44,190 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 39 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:44,190 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:41:44,378 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:44,378 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 29 treesize of output 37 [2025-04-26 18:41:44,530 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:44,530 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 42 treesize of output 66 [2025-04-26 18:41:44,603 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 6 proven. 33 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:44,604 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1324333130] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:41:44,604 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:41:44,604 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 35 [2025-04-26 18:41:44,604 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [353179353] [2025-04-26 18:41:44,604 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:41:44,604 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:41:44,604 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:44,604 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 21 times [2025-04-26 18:41:44,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:44,604 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [638833114] [2025-04-26 18:41:44,604 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-04-26 18:41:44,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:44,606 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:44,606 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:44,606 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-04-26 18:41:44,606 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:44,606 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:41:44,607 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:44,607 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:44,607 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:44,607 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:44,608 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:44,628 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:41:44,628 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2025-04-26 18:41:44,629 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=128, Invalid=1204, Unknown=0, NotChecked=0, Total=1332 [2025-04-26 18:41:44,629 INFO L87 Difference]: Start difference. First operand 13929 states and 24058 transitions. cyclomatic complexity: 11112 Second operand has 37 states, 36 states have (on average 3.0833333333333335) internal successors, (in total 111), 36 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:46,793 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:41:46,793 INFO L93 Difference]: Finished difference Result 26735 states and 45593 transitions. [2025-04-26 18:41:46,793 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26735 states and 45593 transitions. [2025-04-26 18:41:46,888 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 60 [2025-04-26 18:41:46,963 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26735 states to 26521 states and 45169 transitions. [2025-04-26 18:41:46,963 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1921 [2025-04-26 18:41:46,966 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1923 [2025-04-26 18:41:46,966 INFO L74 IsDeterministic]: Start isDeterministic. Operand 26521 states and 45169 transitions. [2025-04-26 18:41:46,966 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:41:46,966 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26521 states and 45169 transitions. [2025-04-26 18:41:46,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26521 states and 45169 transitions. [2025-04-26 18:41:47,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26521 to 13448. [2025-04-26 18:41:47,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13448 states, 13448 states have (on average 1.7269482450922071) internal successors, (in total 23224), 13447 states have internal predecessors, (23224), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:47,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13448 states to 13448 states and 23224 transitions. [2025-04-26 18:41:47,152 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13448 states and 23224 transitions. [2025-04-26 18:41:47,153 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2025-04-26 18:41:47,153 INFO L438 stractBuchiCegarLoop]: Abstraction has 13448 states and 23224 transitions. [2025-04-26 18:41:47,153 INFO L340 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2025-04-26 18:41:47,153 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13448 states and 23224 transitions. [2025-04-26 18:41:47,180 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:47,181 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:41:47,181 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:41:47,181 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1] [2025-04-26 18:41:47,181 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:41:47,182 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:41:47,182 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:41:47,182 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:47,182 INFO L85 PathProgramCache]: Analyzing trace with hash -2034624657, now seen corresponding path program 17 times [2025-04-26 18:41:47,182 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:47,182 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [930184729] [2025-04-26 18:41:47,182 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-04-26 18:41:47,182 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:47,184 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 43 statements into 6 equivalence classes. [2025-04-26 18:41:47,189 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) and asserted 43 of 43 statements. [2025-04-26 18:41:47,189 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2025-04-26 18:41:47,189 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:47,402 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 2 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:47,403 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:41:47,403 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [930184729] [2025-04-26 18:41:47,403 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [930184729] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:41:47,403 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1298807871] [2025-04-26 18:41:47,403 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-04-26 18:41:47,403 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:41:47,403 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:47,406 INFO L229 MonitoredProcess]: Starting monitored process 73 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:41:47,406 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (73)] Waiting until timeout for monitored process [2025-04-26 18:41:47,429 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 43 statements into 6 equivalence classes. [2025-04-26 18:41:47,441 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) and asserted 43 of 43 statements. [2025-04-26 18:41:47,442 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2025-04-26 18:41:47,442 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:47,442 INFO L256 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 23 conjuncts are in the unsatisfiable core [2025-04-26 18:41:47,443 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:47,530 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:41:47,655 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:41:47,659 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 9 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:47,660 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:41:47,764 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:47,764 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 13 treesize of output 17 [2025-04-26 18:41:47,874 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:47,874 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 29 [2025-04-26 18:41:47,988 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 2 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:47,988 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1298807871] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:41:47,988 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:41:47,988 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 13, 13] total 33 [2025-04-26 18:41:47,988 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1891218489] [2025-04-26 18:41:47,988 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:41:47,988 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:41:47,988 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:47,988 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 22 times [2025-04-26 18:41:47,989 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:47,989 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1815012821] [2025-04-26 18:41:47,989 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-04-26 18:41:47,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:47,990 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-04-26 18:41:47,990 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:47,990 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-04-26 18:41:47,990 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:47,990 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:41:47,990 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:47,991 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:47,991 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:47,991 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:47,991 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:48,010 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:41:48,011 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2025-04-26 18:41:48,011 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=914, Unknown=0, NotChecked=0, Total=1190 [2025-04-26 18:41:48,011 INFO L87 Difference]: Start difference. First operand 13448 states and 23224 transitions. cyclomatic complexity: 10707 Second operand has 35 states, 34 states have (on average 3.235294117647059) internal successors, (in total 110), 34 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:49,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:41:49,860 INFO L93 Difference]: Finished difference Result 28994 states and 50183 transitions. [2025-04-26 18:41:49,861 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28994 states and 50183 transitions. [2025-04-26 18:41:49,960 INFO L131 ngComponentsAnalysis]: Automaton has 34 accepting balls. 68 [2025-04-26 18:41:50,049 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28994 states to 28395 states and 49184 transitions. [2025-04-26 18:41:50,049 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1952 [2025-04-26 18:41:50,053 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1956 [2025-04-26 18:41:50,053 INFO L74 IsDeterministic]: Start isDeterministic. Operand 28395 states and 49184 transitions. [2025-04-26 18:41:50,053 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:41:50,053 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28395 states and 49184 transitions. [2025-04-26 18:41:50,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28395 states and 49184 transitions. [2025-04-26 18:41:50,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28395 to 15767. [2025-04-26 18:41:50,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15767 states, 15767 states have (on average 1.7245512779856662) internal successors, (in total 27191), 15766 states have internal predecessors, (27191), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:50,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15767 states to 15767 states and 27191 transitions. [2025-04-26 18:41:50,277 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15767 states and 27191 transitions. [2025-04-26 18:41:50,278 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2025-04-26 18:41:50,278 INFO L438 stractBuchiCegarLoop]: Abstraction has 15767 states and 27191 transitions. [2025-04-26 18:41:50,278 INFO L340 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2025-04-26 18:41:50,278 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15767 states and 27191 transitions. [2025-04-26 18:41:50,311 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:50,311 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:41:50,311 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:41:50,312 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1] [2025-04-26 18:41:50,312 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:41:50,312 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:41:50,312 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:41:50,313 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:50,313 INFO L85 PathProgramCache]: Analyzing trace with hash -1317408438, now seen corresponding path program 18 times [2025-04-26 18:41:50,313 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:50,313 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1286187171] [2025-04-26 18:41:50,313 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-04-26 18:41:50,313 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:50,315 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 48 statements into 5 equivalence classes. [2025-04-26 18:41:50,319 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) and asserted 48 of 48 statements. [2025-04-26 18:41:50,319 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2025-04-26 18:41:50,319 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:50,375 INFO L134 CoverageAnalysis]: Checked inductivity of 67 backedges. 34 proven. 21 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-04-26 18:41:50,376 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:41:50,376 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1286187171] [2025-04-26 18:41:50,376 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1286187171] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:41:50,376 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1101410124] [2025-04-26 18:41:50,376 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-04-26 18:41:50,376 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:41:50,376 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:50,380 INFO L229 MonitoredProcess]: Starting monitored process 74 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:41:50,381 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (74)] Waiting until timeout for monitored process [2025-04-26 18:41:50,404 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 48 statements into 5 equivalence classes. [2025-04-26 18:41:50,417 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) and asserted 48 of 48 statements. [2025-04-26 18:41:50,417 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2025-04-26 18:41:50,417 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:50,418 INFO L256 TraceCheckSpWp]: Trace formula consists of 146 conjuncts, 8 conjuncts are in the unsatisfiable core [2025-04-26 18:41:50,418 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:50,460 INFO L134 CoverageAnalysis]: Checked inductivity of 67 backedges. 34 proven. 21 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-04-26 18:41:50,460 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:41:50,516 INFO L134 CoverageAnalysis]: Checked inductivity of 67 backedges. 34 proven. 21 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-04-26 18:41:50,517 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1101410124] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:41:50,517 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:41:50,517 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5, 5] total 6 [2025-04-26 18:41:50,517 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2052569580] [2025-04-26 18:41:50,517 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:41:50,517 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:41:50,517 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:50,517 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 23 times [2025-04-26 18:41:50,517 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:50,517 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [184231333] [2025-04-26 18:41:50,517 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-04-26 18:41:50,517 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:50,518 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:50,519 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:50,519 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-04-26 18:41:50,519 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:50,519 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:41:50,519 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:50,519 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:50,519 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:50,519 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:50,521 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:50,540 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:41:50,541 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-04-26 18:41:50,541 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2025-04-26 18:41:50,541 INFO L87 Difference]: Start difference. First operand 15767 states and 27191 transitions. cyclomatic complexity: 12526 Second operand has 7 states, 7 states have (on average 7.285714285714286) internal successors, (in total 51), 6 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:50,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:41:50,623 INFO L93 Difference]: Finished difference Result 20378 states and 35210 transitions. [2025-04-26 18:41:50,623 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20378 states and 35210 transitions. [2025-04-26 18:41:50,692 INFO L131 ngComponentsAnalysis]: Automaton has 44 accepting balls. 88 [2025-04-26 18:41:50,744 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20378 states to 19561 states and 33851 transitions. [2025-04-26 18:41:50,744 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1438 [2025-04-26 18:41:50,747 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1440 [2025-04-26 18:41:50,747 INFO L74 IsDeterministic]: Start isDeterministic. Operand 19561 states and 33851 transitions. [2025-04-26 18:41:50,747 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:41:50,747 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19561 states and 33851 transitions. [2025-04-26 18:41:50,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19561 states and 33851 transitions. [2025-04-26 18:41:50,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19561 to 12721. [2025-04-26 18:41:50,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12721 states, 12721 states have (on average 1.6831223960380473) internal successors, (in total 21411), 12720 states have internal predecessors, (21411), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:51,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12721 states to 12721 states and 21411 transitions. [2025-04-26 18:41:51,016 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12721 states and 21411 transitions. [2025-04-26 18:41:51,016 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-04-26 18:41:51,017 INFO L438 stractBuchiCegarLoop]: Abstraction has 12721 states and 21411 transitions. [2025-04-26 18:41:51,017 INFO L340 stractBuchiCegarLoop]: ======== Iteration 35 ============ [2025-04-26 18:41:51,017 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12721 states and 21411 transitions. [2025-04-26 18:41:51,043 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:51,043 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:41:51,044 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:41:51,044 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1] [2025-04-26 18:41:51,044 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:41:51,044 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:41:51,045 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:41:51,045 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:51,045 INFO L85 PathProgramCache]: Analyzing trace with hash -1201346374, now seen corresponding path program 19 times [2025-04-26 18:41:51,045 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:51,045 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [37277031] [2025-04-26 18:41:51,045 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-04-26 18:41:51,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:51,047 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-04-26 18:41:51,053 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-04-26 18:41:51,054 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:51,054 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:51,230 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 52 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-04-26 18:41:51,230 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:41:51,230 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [37277031] [2025-04-26 18:41:51,230 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [37277031] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:41:51,230 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1297172776] [2025-04-26 18:41:51,230 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-04-26 18:41:51,230 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:41:51,231 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:51,233 INFO L229 MonitoredProcess]: Starting monitored process 75 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:41:51,234 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (75)] Waiting until timeout for monitored process [2025-04-26 18:41:51,254 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-04-26 18:41:51,266 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-04-26 18:41:51,266 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:51,266 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:51,267 INFO L256 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 38 conjuncts are in the unsatisfiable core [2025-04-26 18:41:51,268 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:51,575 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:51,575 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 22 treesize of output 10 [2025-04-26 18:41:51,627 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:51,627 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 18 treesize of output 10 [2025-04-26 18:41:51,630 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2025-04-26 18:41:51,630 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:41:51,773 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 6 [2025-04-26 18:41:51,851 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:51,851 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 29 treesize of output 37 [2025-04-26 18:41:52,014 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:52,014 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 41 treesize of output 65 [2025-04-26 18:41:52,102 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 5 proven. 45 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2025-04-26 18:41:52,102 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1297172776] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:41:52,102 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:41:52,102 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 15, 14] total 36 [2025-04-26 18:41:52,102 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1075769914] [2025-04-26 18:41:52,102 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:41:52,102 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:41:52,102 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:52,102 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 24 times [2025-04-26 18:41:52,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:52,102 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [130153240] [2025-04-26 18:41:52,102 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-04-26 18:41:52,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:52,103 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:52,104 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:52,104 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-04-26 18:41:52,104 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:52,104 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:41:52,104 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:52,104 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:52,104 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:52,104 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:52,105 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:52,124 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:41:52,124 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2025-04-26 18:41:52,124 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=135, Invalid=1271, Unknown=0, NotChecked=0, Total=1406 [2025-04-26 18:41:52,124 INFO L87 Difference]: Start difference. First operand 12721 states and 21411 transitions. cyclomatic complexity: 9712 Second operand has 38 states, 37 states have (on average 3.324324324324324) internal successors, (in total 123), 37 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:54,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:41:54,265 INFO L93 Difference]: Finished difference Result 23068 states and 38614 transitions. [2025-04-26 18:41:54,265 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23068 states and 38614 transitions. [2025-04-26 18:41:54,344 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:54,407 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23068 states to 23008 states and 38477 transitions. [2025-04-26 18:41:54,407 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1561 [2025-04-26 18:41:54,409 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1561 [2025-04-26 18:41:54,409 INFO L74 IsDeterministic]: Start isDeterministic. Operand 23008 states and 38477 transitions. [2025-04-26 18:41:54,409 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:41:54,409 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23008 states and 38477 transitions. [2025-04-26 18:41:54,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23008 states and 38477 transitions. [2025-04-26 18:41:54,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23008 to 11885. [2025-04-26 18:41:54,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11885 states, 11885 states have (on average 1.6910391249474126) internal successors, (in total 20098), 11884 states have internal predecessors, (20098), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:54,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11885 states to 11885 states and 20098 transitions. [2025-04-26 18:41:54,564 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11885 states and 20098 transitions. [2025-04-26 18:41:54,564 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2025-04-26 18:41:54,564 INFO L438 stractBuchiCegarLoop]: Abstraction has 11885 states and 20098 transitions. [2025-04-26 18:41:54,564 INFO L340 stractBuchiCegarLoop]: ======== Iteration 36 ============ [2025-04-26 18:41:54,564 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11885 states and 20098 transitions. [2025-04-26 18:41:54,587 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:54,587 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:41:54,587 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:41:54,588 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1] [2025-04-26 18:41:54,588 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:41:54,588 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:41:54,588 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:41:54,588 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:54,588 INFO L85 PathProgramCache]: Analyzing trace with hash 281997392, now seen corresponding path program 20 times [2025-04-26 18:41:54,588 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:54,588 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [250938660] [2025-04-26 18:41:54,589 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-04-26 18:41:54,589 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:54,591 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 50 statements into 2 equivalence classes. [2025-04-26 18:41:54,596 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 50 of 50 statements. [2025-04-26 18:41:54,596 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-04-26 18:41:54,596 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:54,837 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 0 proven. 68 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2025-04-26 18:41:54,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:41:54,837 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [250938660] [2025-04-26 18:41:54,837 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [250938660] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:41:54,837 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [960345312] [2025-04-26 18:41:54,837 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-04-26 18:41:54,837 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:41:54,837 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:54,839 INFO L229 MonitoredProcess]: Starting monitored process 76 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:41:54,840 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (76)] Waiting until timeout for monitored process [2025-04-26 18:41:54,865 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 50 statements into 2 equivalence classes. [2025-04-26 18:41:54,876 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 50 of 50 statements. [2025-04-26 18:41:54,876 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-04-26 18:41:54,876 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:54,877 INFO L256 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 28 conjuncts are in the unsatisfiable core [2025-04-26 18:41:54,877 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:54,954 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2025-04-26 18:41:54,986 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:41:54,989 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 0 proven. 68 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2025-04-26 18:41:54,989 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:41:55,045 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:55,045 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 15 treesize of output 19 [2025-04-26 18:41:55,066 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:55,067 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 21 [2025-04-26 18:41:55,110 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 0 proven. 68 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2025-04-26 18:41:55,110 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [960345312] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:41:55,111 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:41:55,111 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 13, 13] total 18 [2025-04-26 18:41:55,111 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1505300900] [2025-04-26 18:41:55,111 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:41:55,111 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:41:55,111 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:55,111 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 25 times [2025-04-26 18:41:55,111 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:55,111 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [234304711] [2025-04-26 18:41:55,111 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-04-26 18:41:55,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:55,112 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:55,112 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:55,113 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:55,113 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:55,113 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:41:55,113 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:55,113 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:55,113 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:55,113 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:55,114 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:55,130 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:41:55,131 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2025-04-26 18:41:55,131 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=338, Unknown=0, NotChecked=0, Total=380 [2025-04-26 18:41:55,131 INFO L87 Difference]: Start difference. First operand 11885 states and 20098 transitions. cyclomatic complexity: 9152 Second operand has 20 states, 19 states have (on average 3.0526315789473686) internal successors, (in total 58), 19 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:56,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:41:56,086 INFO L93 Difference]: Finished difference Result 27759 states and 48856 transitions. [2025-04-26 18:41:56,086 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27759 states and 48856 transitions. [2025-04-26 18:41:56,175 INFO L131 ngComponentsAnalysis]: Automaton has 140 accepting balls. 280 [2025-04-26 18:41:56,320 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27759 states to 27756 states and 48852 transitions. [2025-04-26 18:41:56,321 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2597 [2025-04-26 18:41:56,323 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2597 [2025-04-26 18:41:56,323 INFO L74 IsDeterministic]: Start isDeterministic. Operand 27756 states and 48852 transitions. [2025-04-26 18:41:56,323 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:41:56,324 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27756 states and 48852 transitions. [2025-04-26 18:41:56,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27756 states and 48852 transitions. [2025-04-26 18:41:56,472 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27756 to 13874. [2025-04-26 18:41:56,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13874 states, 13874 states have (on average 1.6997261063860458) internal successors, (in total 23582), 13873 states have internal predecessors, (23582), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:41:56,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13874 states to 13874 states and 23582 transitions. [2025-04-26 18:41:56,502 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13874 states and 23582 transitions. [2025-04-26 18:41:56,502 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2025-04-26 18:41:56,503 INFO L438 stractBuchiCegarLoop]: Abstraction has 13874 states and 23582 transitions. [2025-04-26 18:41:56,503 INFO L340 stractBuchiCegarLoop]: ======== Iteration 37 ============ [2025-04-26 18:41:56,503 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13874 states and 23582 transitions. [2025-04-26 18:41:56,530 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:41:56,531 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:41:56,531 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:41:56,531 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1] [2025-04-26 18:41:56,531 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:41:56,532 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:41:56,532 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:41:56,532 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:56,532 INFO L85 PathProgramCache]: Analyzing trace with hash 598775504, now seen corresponding path program 21 times [2025-04-26 18:41:56,532 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:56,532 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [210310182] [2025-04-26 18:41:56,532 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-04-26 18:41:56,532 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:56,535 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 50 statements into 4 equivalence classes. [2025-04-26 18:41:56,540 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) and asserted 50 of 50 statements. [2025-04-26 18:41:56,540 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2025-04-26 18:41:56,540 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:57,097 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 2 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:41:57,097 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:41:57,098 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [210310182] [2025-04-26 18:41:57,098 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [210310182] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:41:57,098 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [504784635] [2025-04-26 18:41:57,098 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-04-26 18:41:57,098 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:41:57,098 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:41:57,100 INFO L229 MonitoredProcess]: Starting monitored process 77 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:41:57,100 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (77)] Waiting until timeout for monitored process [2025-04-26 18:41:57,120 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 50 statements into 4 equivalence classes. [2025-04-26 18:41:57,133 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) and asserted 50 of 50 statements. [2025-04-26 18:41:57,133 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2025-04-26 18:41:57,133 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:41:57,138 INFO L256 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 26 conjuncts are in the unsatisfiable core [2025-04-26 18:41:57,139 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:41:57,314 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:41:57,354 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 11 [2025-04-26 18:41:57,374 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 0 proven. 46 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2025-04-26 18:41:57,374 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:41:57,420 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:57,420 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 22 [2025-04-26 18:41:57,460 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:41:57,461 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 21 [2025-04-26 18:41:57,501 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 0 proven. 46 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2025-04-26 18:41:57,501 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [504784635] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:41:57,501 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:41:57,501 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 13, 13] total 30 [2025-04-26 18:41:57,501 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1994157784] [2025-04-26 18:41:57,501 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:41:57,502 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:41:57,502 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:41:57,502 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 26 times [2025-04-26 18:41:57,502 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:41:57,502 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1540423494] [2025-04-26 18:41:57,502 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-04-26 18:41:57,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:41:57,503 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:57,503 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:57,503 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-04-26 18:41:57,504 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:57,504 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:41:57,504 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:41:57,504 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:41:57,504 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:41:57,504 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:41:57,505 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:41:57,521 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:41:57,522 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2025-04-26 18:41:57,523 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=826, Unknown=0, NotChecked=0, Total=992 [2025-04-26 18:41:57,523 INFO L87 Difference]: Start difference. First operand 13874 states and 23582 transitions. cyclomatic complexity: 10849 Second operand has 32 states, 31 states have (on average 2.7096774193548385) internal successors, (in total 84), 31 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:42:01,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:42:01,207 INFO L93 Difference]: Finished difference Result 34152 states and 59458 transitions. [2025-04-26 18:42:01,207 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34152 states and 59458 transitions. [2025-04-26 18:42:01,412 INFO L131 ngComponentsAnalysis]: Automaton has 346 accepting balls. 692 [2025-04-26 18:42:01,515 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34152 states to 33989 states and 59205 transitions. [2025-04-26 18:42:01,516 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3497 [2025-04-26 18:42:01,521 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3527 [2025-04-26 18:42:01,521 INFO L74 IsDeterministic]: Start isDeterministic. Operand 33989 states and 59205 transitions. [2025-04-26 18:42:01,521 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:42:01,521 INFO L218 hiAutomatonCegarLoop]: Abstraction has 33989 states and 59205 transitions. [2025-04-26 18:42:01,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33989 states and 59205 transitions. [2025-04-26 18:42:01,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33989 to 14452. [2025-04-26 18:42:01,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14452 states, 14452 states have (on average 1.7088292277885413) internal successors, (in total 24696), 14451 states have internal predecessors, (24696), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:42:01,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14452 states to 14452 states and 24696 transitions. [2025-04-26 18:42:01,745 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14452 states and 24696 transitions. [2025-04-26 18:42:01,745 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 150 states. [2025-04-26 18:42:01,746 INFO L438 stractBuchiCegarLoop]: Abstraction has 14452 states and 24696 transitions. [2025-04-26 18:42:01,746 INFO L340 stractBuchiCegarLoop]: ======== Iteration 38 ============ [2025-04-26 18:42:01,746 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14452 states and 24696 transitions. [2025-04-26 18:42:01,776 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:42:01,777 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:42:01,777 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:42:01,777 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1] [2025-04-26 18:42:01,777 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:42:01,778 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:42:01,778 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:42:01,778 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:42:01,778 INFO L85 PathProgramCache]: Analyzing trace with hash -557990530, now seen corresponding path program 22 times [2025-04-26 18:42:01,778 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:42:01,778 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [17044492] [2025-04-26 18:42:01,778 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-04-26 18:42:01,778 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:42:01,781 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 50 statements into 2 equivalence classes. [2025-04-26 18:42:01,787 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-04-26 18:42:01,788 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-04-26 18:42:01,788 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:42:01,976 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2025-04-26 18:42:01,976 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:42:01,976 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [17044492] [2025-04-26 18:42:01,976 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [17044492] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:42:01,976 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2047748626] [2025-04-26 18:42:01,976 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-04-26 18:42:01,976 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:42:01,976 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:42:01,979 INFO L229 MonitoredProcess]: Starting monitored process 78 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:42:01,980 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (78)] Waiting until timeout for monitored process [2025-04-26 18:42:02,002 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 50 statements into 2 equivalence classes. [2025-04-26 18:42:02,015 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-04-26 18:42:02,015 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-04-26 18:42:02,015 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:42:02,016 INFO L256 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 38 conjuncts are in the unsatisfiable core [2025-04-26 18:42:02,017 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:42:02,284 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:42:02,284 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 22 treesize of output 10 [2025-04-26 18:42:02,359 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:42:02,360 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 18 treesize of output 10 [2025-04-26 18:42:02,363 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2025-04-26 18:42:02,363 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:42:02,448 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 6 [2025-04-26 18:42:02,579 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:42:02,579 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 29 treesize of output 37 [2025-04-26 18:42:02,728 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:42:02,728 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 41 treesize of output 65 [2025-04-26 18:42:02,810 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 3 proven. 46 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2025-04-26 18:42:02,810 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2047748626] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:42:02,810 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:42:02,811 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 15, 14] total 36 [2025-04-26 18:42:02,811 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1968244659] [2025-04-26 18:42:02,811 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:42:02,811 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:42:02,811 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:42:02,811 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 27 times [2025-04-26 18:42:02,811 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:42:02,811 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2122640817] [2025-04-26 18:42:02,811 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-04-26 18:42:02,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:42:02,812 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:42:02,812 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:42:02,812 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-04-26 18:42:02,812 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:42:02,813 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:42:02,813 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:42:02,813 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:42:02,813 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:42:02,813 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:42:02,814 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:42:02,829 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:42:02,830 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2025-04-26 18:42:02,830 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=132, Invalid=1274, Unknown=0, NotChecked=0, Total=1406 [2025-04-26 18:42:02,830 INFO L87 Difference]: Start difference. First operand 14452 states and 24696 transitions. cyclomatic complexity: 11418 Second operand has 38 states, 37 states have (on average 3.3513513513513513) internal successors, (in total 124), 37 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:42:08,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:42:08,842 INFO L93 Difference]: Finished difference Result 56961 states and 101771 transitions. [2025-04-26 18:42:08,842 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 56961 states and 101771 transitions. [2025-04-26 18:42:09,087 INFO L131 ngComponentsAnalysis]: Automaton has 406 accepting balls. 812 [2025-04-26 18:42:09,299 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 56961 states to 56901 states and 101660 transitions. [2025-04-26 18:42:09,299 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5876 [2025-04-26 18:42:09,309 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5876 [2025-04-26 18:42:09,309 INFO L74 IsDeterministic]: Start isDeterministic. Operand 56901 states and 101660 transitions. [2025-04-26 18:42:09,309 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:42:09,309 INFO L218 hiAutomatonCegarLoop]: Abstraction has 56901 states and 101660 transitions. [2025-04-26 18:42:09,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56901 states and 101660 transitions. [2025-04-26 18:42:09,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56901 to 15244. [2025-04-26 18:42:09,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15244 states, 15244 states have (on average 1.7118210443453161) internal successors, (in total 26095), 15243 states have internal predecessors, (26095), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:42:09,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15244 states to 15244 states and 26095 transitions. [2025-04-26 18:42:09,756 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15244 states and 26095 transitions. [2025-04-26 18:42:09,756 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 202 states. [2025-04-26 18:42:09,756 INFO L438 stractBuchiCegarLoop]: Abstraction has 15244 states and 26095 transitions. [2025-04-26 18:42:09,756 INFO L340 stractBuchiCegarLoop]: ======== Iteration 39 ============ [2025-04-26 18:42:09,757 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15244 states and 26095 transitions. [2025-04-26 18:42:09,788 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:42:09,788 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:42:09,788 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:42:09,789 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1] [2025-04-26 18:42:09,789 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:42:09,789 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:42:09,789 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:42:09,789 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:42:09,789 INFO L85 PathProgramCache]: Analyzing trace with hash -1013875106, now seen corresponding path program 23 times [2025-04-26 18:42:09,790 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:42:09,790 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1825765267] [2025-04-26 18:42:09,790 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-04-26 18:42:09,790 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:42:09,792 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 50 statements into 8 equivalence classes. [2025-04-26 18:42:09,797 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) and asserted 50 of 50 statements. [2025-04-26 18:42:09,797 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2025-04-26 18:42:09,797 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:42:10,005 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 0 proven. 75 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-04-26 18:42:10,005 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:42:10,005 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1825765267] [2025-04-26 18:42:10,006 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1825765267] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:42:10,006 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1481715555] [2025-04-26 18:42:10,006 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-04-26 18:42:10,006 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:42:10,006 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:42:10,013 INFO L229 MonitoredProcess]: Starting monitored process 79 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:42:10,014 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (79)] Waiting until timeout for monitored process [2025-04-26 18:42:10,035 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 50 statements into 8 equivalence classes. [2025-04-26 18:42:10,049 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) and asserted 50 of 50 statements. [2025-04-26 18:42:10,049 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2025-04-26 18:42:10,049 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:42:10,050 INFO L256 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 28 conjuncts are in the unsatisfiable core [2025-04-26 18:42:10,051 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:42:10,169 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:42:10,210 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:42:10,215 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 0 proven. 73 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2025-04-26 18:42:10,215 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:42:10,283 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:42:10,284 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 15 treesize of output 19 [2025-04-26 18:42:10,315 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:42:10,315 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 23 [2025-04-26 18:42:10,348 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 0 proven. 73 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2025-04-26 18:42:10,348 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1481715555] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:42:10,348 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:42:10,348 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 13, 13] total 20 [2025-04-26 18:42:10,348 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2087931364] [2025-04-26 18:42:10,348 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:42:10,348 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:42:10,348 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:42:10,348 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 28 times [2025-04-26 18:42:10,348 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:42:10,348 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [755519294] [2025-04-26 18:42:10,348 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-04-26 18:42:10,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:42:10,349 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-04-26 18:42:10,350 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:42:10,350 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-04-26 18:42:10,350 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:42:10,350 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:42:10,350 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:42:10,350 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:42:10,350 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:42:10,350 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:42:10,351 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:42:10,367 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:42:10,368 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2025-04-26 18:42:10,368 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=413, Unknown=0, NotChecked=0, Total=462 [2025-04-26 18:42:10,368 INFO L87 Difference]: Start difference. First operand 15244 states and 26095 transitions. cyclomatic complexity: 12120 Second operand has 22 states, 21 states have (on average 3.142857142857143) internal successors, (in total 66), 21 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:42:10,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:42:10,964 INFO L93 Difference]: Finished difference Result 18978 states and 32360 transitions. [2025-04-26 18:42:10,964 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18978 states and 32360 transitions. [2025-04-26 18:42:11,032 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:42:11,090 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18978 states to 18975 states and 32356 transitions. [2025-04-26 18:42:11,091 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1283 [2025-04-26 18:42:11,093 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1283 [2025-04-26 18:42:11,093 INFO L74 IsDeterministic]: Start isDeterministic. Operand 18975 states and 32356 transitions. [2025-04-26 18:42:11,093 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:42:11,093 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18975 states and 32356 transitions. [2025-04-26 18:42:11,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18975 states and 32356 transitions. [2025-04-26 18:42:11,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18975 to 14698. [2025-04-26 18:42:11,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14698 states, 14698 states have (on average 1.7113893046673017) internal successors, (in total 25154), 14697 states have internal predecessors, (25154), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:42:11,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14698 states to 14698 states and 25154 transitions. [2025-04-26 18:42:11,263 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14698 states and 25154 transitions. [2025-04-26 18:42:11,263 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2025-04-26 18:42:11,263 INFO L438 stractBuchiCegarLoop]: Abstraction has 14698 states and 25154 transitions. [2025-04-26 18:42:11,263 INFO L340 stractBuchiCegarLoop]: ======== Iteration 40 ============ [2025-04-26 18:42:11,264 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14698 states and 25154 transitions. [2025-04-26 18:42:11,294 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:42:11,294 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:42:11,294 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:42:11,295 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1] [2025-04-26 18:42:11,295 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:42:11,295 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:42:11,295 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:42:11,295 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:42:11,295 INFO L85 PathProgramCache]: Analyzing trace with hash -697096994, now seen corresponding path program 24 times [2025-04-26 18:42:11,296 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:42:11,296 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [150720909] [2025-04-26 18:42:11,296 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-04-26 18:42:11,296 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:42:11,298 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 50 statements into 5 equivalence classes. [2025-04-26 18:42:11,303 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) and asserted 50 of 50 statements. [2025-04-26 18:42:11,303 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2025-04-26 18:42:11,303 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:42:11,504 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2025-04-26 18:42:11,504 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:42:11,504 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [150720909] [2025-04-26 18:42:11,504 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [150720909] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:42:11,504 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1305970736] [2025-04-26 18:42:11,505 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-04-26 18:42:11,505 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:42:11,505 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:42:11,507 INFO L229 MonitoredProcess]: Starting monitored process 80 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:42:11,508 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (80)] Waiting until timeout for monitored process [2025-04-26 18:42:11,530 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 50 statements into 5 equivalence classes. [2025-04-26 18:42:11,544 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) and asserted 50 of 50 statements. [2025-04-26 18:42:11,544 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2025-04-26 18:42:11,544 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:42:11,545 INFO L256 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 26 conjuncts are in the unsatisfiable core [2025-04-26 18:42:11,546 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:42:11,666 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:42:11,688 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:42:11,692 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2025-04-26 18:42:11,692 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:42:11,721 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:42:11,721 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 13 treesize of output 17 [2025-04-26 18:42:11,773 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:42:11,773 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 23 [2025-04-26 18:42:11,804 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2025-04-26 18:42:11,804 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1305970736] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:42:11,804 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:42:11,804 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 12, 12] total 18 [2025-04-26 18:42:11,804 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1934966261] [2025-04-26 18:42:11,804 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:42:11,804 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:42:11,804 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:42:11,804 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 29 times [2025-04-26 18:42:11,804 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:42:11,804 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [36875687] [2025-04-26 18:42:11,804 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-04-26 18:42:11,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:42:11,805 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:42:11,806 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:42:11,806 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-04-26 18:42:11,806 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:42:11,806 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:42:11,806 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:42:11,806 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:42:11,806 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:42:11,806 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:42:11,807 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:42:11,823 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:42:11,824 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2025-04-26 18:42:11,824 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=340, Unknown=0, NotChecked=0, Total=380 [2025-04-26 18:42:11,824 INFO L87 Difference]: Start difference. First operand 14698 states and 25154 transitions. cyclomatic complexity: 11699 Second operand has 20 states, 19 states have (on average 3.5789473684210527) internal successors, (in total 68), 19 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:42:12,558 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:42:12,558 INFO L93 Difference]: Finished difference Result 22678 states and 38912 transitions. [2025-04-26 18:42:12,558 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22678 states and 38912 transitions. [2025-04-26 18:42:12,640 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:42:12,697 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22678 states to 22678 states and 38912 transitions. [2025-04-26 18:42:12,697 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1593 [2025-04-26 18:42:12,699 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1593 [2025-04-26 18:42:12,699 INFO L74 IsDeterministic]: Start isDeterministic. Operand 22678 states and 38912 transitions. [2025-04-26 18:42:12,699 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:42:12,700 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22678 states and 38912 transitions. [2025-04-26 18:42:12,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22678 states and 38912 transitions. [2025-04-26 18:42:12,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22678 to 14570. [2025-04-26 18:42:12,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14570 states, 14570 states have (on average 1.7098833218943033) internal successors, (in total 24913), 14569 states have internal predecessors, (24913), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:42:12,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14570 states to 14570 states and 24913 transitions. [2025-04-26 18:42:12,985 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14570 states and 24913 transitions. [2025-04-26 18:42:12,985 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2025-04-26 18:42:12,985 INFO L438 stractBuchiCegarLoop]: Abstraction has 14570 states and 24913 transitions. [2025-04-26 18:42:12,985 INFO L340 stractBuchiCegarLoop]: ======== Iteration 41 ============ [2025-04-26 18:42:12,985 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14570 states and 24913 transitions. [2025-04-26 18:42:13,016 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:42:13,016 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:42:13,016 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:42:13,017 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1] [2025-04-26 18:42:13,017 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:42:13,017 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:42:13,017 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:42:13,018 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:42:13,018 INFO L85 PathProgramCache]: Analyzing trace with hash -1853863028, now seen corresponding path program 25 times [2025-04-26 18:42:13,018 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:42:13,018 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1553503995] [2025-04-26 18:42:13,018 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-04-26 18:42:13,018 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:42:13,020 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-04-26 18:42:13,027 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-04-26 18:42:13,027 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:42:13,027 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:42:13,203 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 52 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2025-04-26 18:42:13,203 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:42:13,203 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1553503995] [2025-04-26 18:42:13,203 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1553503995] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:42:13,203 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [105349215] [2025-04-26 18:42:13,203 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-04-26 18:42:13,203 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:42:13,204 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:42:13,206 INFO L229 MonitoredProcess]: Starting monitored process 81 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:42:13,207 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (81)] Waiting until timeout for monitored process [2025-04-26 18:42:13,228 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-04-26 18:42:13,240 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-04-26 18:42:13,240 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:42:13,240 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:42:13,241 INFO L256 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 28 conjuncts are in the unsatisfiable core [2025-04-26 18:42:13,242 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:42:13,350 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2025-04-26 18:42:13,383 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:42:13,387 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 52 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2025-04-26 18:42:13,387 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:42:13,434 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:42:13,434 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 15 treesize of output 19 [2025-04-26 18:42:13,484 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:42:13,485 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 23 [2025-04-26 18:42:13,523 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 52 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2025-04-26 18:42:13,524 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [105349215] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:42:13,524 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:42:13,524 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 12, 12] total 17 [2025-04-26 18:42:13,524 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [985790824] [2025-04-26 18:42:13,524 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:42:13,524 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:42:13,524 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:42:13,524 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 30 times [2025-04-26 18:42:13,524 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:42:13,524 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [4117271] [2025-04-26 18:42:13,524 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-04-26 18:42:13,524 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:42:13,525 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:42:13,526 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:42:13,526 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-04-26 18:42:13,526 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:42:13,526 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:42:13,526 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:42:13,526 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:42:13,526 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:42:13,526 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:42:13,527 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:42:13,548 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:42:13,548 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2025-04-26 18:42:13,548 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=302, Unknown=0, NotChecked=0, Total=342 [2025-04-26 18:42:13,549 INFO L87 Difference]: Start difference. First operand 14570 states and 24913 transitions. cyclomatic complexity: 11576 Second operand has 19 states, 18 states have (on average 3.7777777777777777) internal successors, (in total 68), 18 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:42:14,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:42:14,151 INFO L93 Difference]: Finished difference Result 24200 states and 41509 transitions. [2025-04-26 18:42:14,151 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24200 states and 41509 transitions. [2025-04-26 18:42:14,229 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:42:14,295 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24200 states to 24197 states and 41505 transitions. [2025-04-26 18:42:14,295 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1699 [2025-04-26 18:42:14,298 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1699 [2025-04-26 18:42:14,298 INFO L74 IsDeterministic]: Start isDeterministic. Operand 24197 states and 41505 transitions. [2025-04-26 18:42:14,298 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:42:14,298 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24197 states and 41505 transitions. [2025-04-26 18:42:14,315 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24197 states and 41505 transitions. [2025-04-26 18:42:14,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24197 to 14465. [2025-04-26 18:42:14,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14465 states, 14465 states have (on average 1.7110957483581057) internal successors, (in total 24751), 14464 states have internal predecessors, (24751), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:42:14,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14465 states to 14465 states and 24751 transitions. [2025-04-26 18:42:14,475 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14465 states and 24751 transitions. [2025-04-26 18:42:14,475 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2025-04-26 18:42:14,475 INFO L438 stractBuchiCegarLoop]: Abstraction has 14465 states and 24751 transitions. [2025-04-26 18:42:14,475 INFO L340 stractBuchiCegarLoop]: ======== Iteration 42 ============ [2025-04-26 18:42:14,475 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14465 states and 24751 transitions. [2025-04-26 18:42:14,505 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:42:14,505 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:42:14,505 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:42:14,506 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1] [2025-04-26 18:42:14,506 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:42:14,506 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:42:14,506 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:42:14,506 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:42:14,507 INFO L85 PathProgramCache]: Analyzing trace with hash -567506540, now seen corresponding path program 26 times [2025-04-26 18:42:14,507 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:42:14,507 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [738048178] [2025-04-26 18:42:14,507 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-04-26 18:42:14,507 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:42:14,509 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 50 statements into 2 equivalence classes. [2025-04-26 18:42:14,516 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 50 of 50 statements. [2025-04-26 18:42:14,517 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-04-26 18:42:14,517 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:42:14,787 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 0 proven. 52 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2025-04-26 18:42:14,787 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:42:14,787 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [738048178] [2025-04-26 18:42:14,787 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [738048178] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:42:14,787 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2040181743] [2025-04-26 18:42:14,787 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-04-26 18:42:14,787 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:42:14,788 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:42:14,790 INFO L229 MonitoredProcess]: Starting monitored process 82 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:42:14,791 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (82)] Waiting until timeout for monitored process [2025-04-26 18:42:14,812 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 50 statements into 2 equivalence classes. [2025-04-26 18:42:14,826 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 50 of 50 statements. [2025-04-26 18:42:14,826 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-04-26 18:42:14,826 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:42:14,827 INFO L256 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 38 conjuncts are in the unsatisfiable core [2025-04-26 18:42:14,828 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:42:15,156 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:42:15,157 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 22 treesize of output 10 [2025-04-26 18:42:15,213 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:42:15,213 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 18 treesize of output 10 [2025-04-26 18:42:15,217 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 0 proven. 52 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2025-04-26 18:42:15,217 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:42:15,369 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 6 [2025-04-26 18:42:15,491 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:42:15,492 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 29 treesize of output 37 [2025-04-26 18:42:15,627 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:42:15,627 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 41 treesize of output 65 [2025-04-26 18:42:15,744 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 9 proven. 43 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2025-04-26 18:42:15,744 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2040181743] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:42:15,744 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:42:15,744 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 15, 14] total 36 [2025-04-26 18:42:15,744 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [244747318] [2025-04-26 18:42:15,744 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:42:15,744 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:42:15,744 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:42:15,744 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 31 times [2025-04-26 18:42:15,744 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:42:15,744 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [582960064] [2025-04-26 18:42:15,745 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-04-26 18:42:15,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:42:15,746 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:42:15,746 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:42:15,746 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:42:15,746 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:42:15,746 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:42:15,746 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:42:15,747 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:42:15,747 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:42:15,747 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:42:15,747 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:42:15,765 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:42:15,765 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2025-04-26 18:42:15,766 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=144, Invalid=1262, Unknown=0, NotChecked=0, Total=1406 [2025-04-26 18:42:15,766 INFO L87 Difference]: Start difference. First operand 14465 states and 24751 transitions. cyclomatic complexity: 11514 Second operand has 38 states, 37 states have (on average 3.1621621621621623) internal successors, (in total 117), 37 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:42:18,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:42:18,398 INFO L93 Difference]: Finished difference Result 27475 states and 46967 transitions. [2025-04-26 18:42:18,398 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27475 states and 46967 transitions. [2025-04-26 18:42:18,495 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:42:18,577 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27475 states to 27461 states and 46948 transitions. [2025-04-26 18:42:18,577 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1890 [2025-04-26 18:42:18,579 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1890 [2025-04-26 18:42:18,579 INFO L74 IsDeterministic]: Start isDeterministic. Operand 27461 states and 46948 transitions. [2025-04-26 18:42:18,579 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:42:18,579 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27461 states and 46948 transitions. [2025-04-26 18:42:18,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27461 states and 46948 transitions. [2025-04-26 18:42:18,736 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27461 to 14702. [2025-04-26 18:42:18,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14702 states, 14702 states have (on average 1.7092232349340226) internal successors, (in total 25129), 14701 states have internal predecessors, (25129), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:42:18,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14702 states to 14702 states and 25129 transitions. [2025-04-26 18:42:18,769 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14702 states and 25129 transitions. [2025-04-26 18:42:18,769 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2025-04-26 18:42:18,770 INFO L438 stractBuchiCegarLoop]: Abstraction has 14702 states and 25129 transitions. [2025-04-26 18:42:18,770 INFO L340 stractBuchiCegarLoop]: ======== Iteration 43 ============ [2025-04-26 18:42:18,770 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14702 states and 25129 transitions. [2025-04-26 18:42:18,829 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:42:18,829 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:42:18,829 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:42:18,829 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1] [2025-04-26 18:42:18,829 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:42:18,830 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:42:18,830 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:42:18,831 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:42:18,831 INFO L85 PathProgramCache]: Analyzing trace with hash -1724272574, now seen corresponding path program 27 times [2025-04-26 18:42:18,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:42:18,831 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [676574900] [2025-04-26 18:42:18,831 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-04-26 18:42:18,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:42:18,834 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 50 statements into 6 equivalence classes. [2025-04-26 18:42:18,840 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) and asserted 50 of 50 statements. [2025-04-26 18:42:18,840 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2025-04-26 18:42:18,840 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:42:19,095 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2025-04-26 18:42:19,095 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:42:19,095 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [676574900] [2025-04-26 18:42:19,095 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [676574900] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:42:19,095 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [180722627] [2025-04-26 18:42:19,095 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-04-26 18:42:19,095 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:42:19,095 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:42:19,098 INFO L229 MonitoredProcess]: Starting monitored process 83 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:42:19,099 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (83)] Waiting until timeout for monitored process [2025-04-26 18:42:19,125 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 50 statements into 6 equivalence classes. [2025-04-26 18:42:19,138 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) and asserted 50 of 50 statements. [2025-04-26 18:42:19,138 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2025-04-26 18:42:19,138 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:42:19,139 INFO L256 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 26 conjuncts are in the unsatisfiable core [2025-04-26 18:42:19,140 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:42:19,225 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:42:19,252 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:42:19,256 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2025-04-26 18:42:19,256 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:42:19,299 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:42:19,299 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 15 treesize of output 19 [2025-04-26 18:42:19,341 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:42:19,342 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 23 [2025-04-26 18:42:19,371 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2025-04-26 18:42:19,371 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [180722627] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:42:19,371 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:42:19,371 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 13, 13] total 20 [2025-04-26 18:42:19,371 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [830166707] [2025-04-26 18:42:19,372 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:42:19,372 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:42:19,372 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:42:19,372 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 32 times [2025-04-26 18:42:19,372 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:42:19,372 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [398907612] [2025-04-26 18:42:19,372 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-04-26 18:42:19,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:42:19,373 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:42:19,373 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:42:19,373 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-04-26 18:42:19,373 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:42:19,373 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:42:19,374 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:42:19,374 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:42:19,374 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:42:19,374 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:42:19,374 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:42:19,392 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:42:19,392 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2025-04-26 18:42:19,392 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=411, Unknown=0, NotChecked=0, Total=462 [2025-04-26 18:42:19,392 INFO L87 Difference]: Start difference. First operand 14702 states and 25129 transitions. cyclomatic complexity: 11683 Second operand has 22 states, 21 states have (on average 3.5238095238095237) internal successors, (in total 74), 21 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:42:20,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:42:20,606 INFO L93 Difference]: Finished difference Result 30317 states and 51722 transitions. [2025-04-26 18:42:20,606 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30317 states and 51722 transitions. [2025-04-26 18:42:20,713 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:42:20,798 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30317 states to 30243 states and 51541 transitions. [2025-04-26 18:42:20,798 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2081 [2025-04-26 18:42:20,802 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2081 [2025-04-26 18:42:20,802 INFO L74 IsDeterministic]: Start isDeterministic. Operand 30243 states and 51541 transitions. [2025-04-26 18:42:20,802 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:42:20,802 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30243 states and 51541 transitions. [2025-04-26 18:42:20,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30243 states and 51541 transitions. [2025-04-26 18:42:20,973 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30243 to 14360. [2025-04-26 18:42:20,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14360 states, 14360 states have (on average 1.7069637883008357) internal successors, (in total 24512), 14359 states have internal predecessors, (24512), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:42:21,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14360 states to 14360 states and 24512 transitions. [2025-04-26 18:42:21,009 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14360 states and 24512 transitions. [2025-04-26 18:42:21,010 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2025-04-26 18:42:21,010 INFO L438 stractBuchiCegarLoop]: Abstraction has 14360 states and 24512 transitions. [2025-04-26 18:42:21,010 INFO L340 stractBuchiCegarLoop]: ======== Iteration 44 ============ [2025-04-26 18:42:21,010 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14360 states and 24512 transitions. [2025-04-26 18:42:21,040 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:42:21,040 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:42:21,040 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:42:21,040 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1] [2025-04-26 18:42:21,040 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:42:21,041 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:42:21,041 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:42:21,041 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:42:21,041 INFO L85 PathProgramCache]: Analyzing trace with hash 1118521440, now seen corresponding path program 28 times [2025-04-26 18:42:21,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:42:21,041 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1577204126] [2025-04-26 18:42:21,041 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-04-26 18:42:21,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:42:21,043 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 50 statements into 2 equivalence classes. [2025-04-26 18:42:21,048 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-04-26 18:42:21,048 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-04-26 18:42:21,048 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:42:21,218 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 0 proven. 58 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-04-26 18:42:21,218 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:42:21,218 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1577204126] [2025-04-26 18:42:21,218 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1577204126] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:42:21,218 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [912429115] [2025-04-26 18:42:21,218 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-04-26 18:42:21,218 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:42:21,218 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:42:21,221 INFO L229 MonitoredProcess]: Starting monitored process 84 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:42:21,222 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (84)] Waiting until timeout for monitored process [2025-04-26 18:42:21,243 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 50 statements into 2 equivalence classes. [2025-04-26 18:42:21,256 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-04-26 18:42:21,256 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-04-26 18:42:21,256 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:42:21,257 INFO L256 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 28 conjuncts are in the unsatisfiable core [2025-04-26 18:42:21,258 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:42:21,380 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2025-04-26 18:42:21,400 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:42:21,404 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2025-04-26 18:42:21,405 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:42:21,431 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:42:21,431 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 13 treesize of output 17 [2025-04-26 18:42:21,466 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:42:21,467 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 21 [2025-04-26 18:42:21,510 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2025-04-26 18:42:21,511 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [912429115] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:42:21,511 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:42:21,511 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11, 11] total 16 [2025-04-26 18:42:21,511 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1026355279] [2025-04-26 18:42:21,511 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:42:21,511 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:42:21,511 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:42:21,511 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 33 times [2025-04-26 18:42:21,511 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:42:21,511 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [535649433] [2025-04-26 18:42:21,511 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-04-26 18:42:21,511 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:42:21,512 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:42:21,512 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:42:21,512 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-04-26 18:42:21,513 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:42:21,513 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:42:21,513 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:42:21,513 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:42:21,513 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:42:21,513 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:42:21,514 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:42:21,530 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:42:21,530 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2025-04-26 18:42:21,530 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=268, Unknown=0, NotChecked=0, Total=306 [2025-04-26 18:42:21,530 INFO L87 Difference]: Start difference. First operand 14360 states and 24512 transitions. cyclomatic complexity: 11371 Second operand has 18 states, 17 states have (on average 3.7058823529411766) internal successors, (in total 63), 17 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:42:22,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:42:22,171 INFO L93 Difference]: Finished difference Result 25368 states and 43184 transitions. [2025-04-26 18:42:22,171 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25368 states and 43184 transitions. [2025-04-26 18:42:22,257 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:42:22,329 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25368 states to 25340 states and 43121 transitions. [2025-04-26 18:42:22,329 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1741 [2025-04-26 18:42:22,332 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1741 [2025-04-26 18:42:22,332 INFO L74 IsDeterministic]: Start isDeterministic. Operand 25340 states and 43121 transitions. [2025-04-26 18:42:22,332 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:42:22,332 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25340 states and 43121 transitions. [2025-04-26 18:42:22,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25340 states and 43121 transitions. [2025-04-26 18:42:22,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25340 to 14175. [2025-04-26 18:42:22,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14175 states, 14175 states have (on average 1.7051851851851851) internal successors, (in total 24171), 14174 states have internal predecessors, (24171), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:42:22,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14175 states to 14175 states and 24171 transitions. [2025-04-26 18:42:22,516 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14175 states and 24171 transitions. [2025-04-26 18:42:22,516 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2025-04-26 18:42:22,517 INFO L438 stractBuchiCegarLoop]: Abstraction has 14175 states and 24171 transitions. [2025-04-26 18:42:22,517 INFO L340 stractBuchiCegarLoop]: ======== Iteration 45 ============ [2025-04-26 18:42:22,517 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14175 states and 24171 transitions. [2025-04-26 18:42:22,546 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:42:22,546 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:42:22,546 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:42:22,546 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 1, 1, 1, 1, 1] [2025-04-26 18:42:22,546 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:42:22,547 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:42:22,547 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:42:22,547 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:42:22,547 INFO L85 PathProgramCache]: Analyzing trace with hash -641050336, now seen corresponding path program 29 times [2025-04-26 18:42:22,547 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:42:22,547 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [944611690] [2025-04-26 18:42:22,547 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-04-26 18:42:22,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:42:22,549 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 53 statements into 5 equivalence classes. [2025-04-26 18:42:22,554 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) and asserted 53 of 53 statements. [2025-04-26 18:42:22,554 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2025-04-26 18:42:22,554 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:42:22,581 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 38 proven. 12 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2025-04-26 18:42:22,581 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:42:22,581 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [944611690] [2025-04-26 18:42:22,581 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [944611690] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:42:22,581 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1439837368] [2025-04-26 18:42:22,581 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-04-26 18:42:22,582 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:42:22,582 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:42:22,584 INFO L229 MonitoredProcess]: Starting monitored process 85 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:42:22,585 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (85)] Waiting until timeout for monitored process [2025-04-26 18:42:22,607 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 53 statements into 5 equivalence classes. [2025-04-26 18:42:22,620 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) and asserted 53 of 53 statements. [2025-04-26 18:42:22,620 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2025-04-26 18:42:22,620 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:42:22,621 INFO L256 TraceCheckSpWp]: Trace formula consists of 159 conjuncts, 8 conjuncts are in the unsatisfiable core [2025-04-26 18:42:22,621 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:42:22,642 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 38 proven. 12 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2025-04-26 18:42:22,642 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:42:22,678 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 38 proven. 12 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2025-04-26 18:42:22,679 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1439837368] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:42:22,679 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:42:22,679 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5 [2025-04-26 18:42:22,679 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [338635124] [2025-04-26 18:42:22,679 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:42:22,679 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:42:22,679 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:42:22,679 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 34 times [2025-04-26 18:42:22,679 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:42:22,679 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1356619941] [2025-04-26 18:42:22,679 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-04-26 18:42:22,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:42:22,680 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-04-26 18:42:22,681 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:42:22,681 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-04-26 18:42:22,681 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:42:22,681 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:42:22,681 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:42:22,681 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:42:22,681 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:42:22,681 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:42:22,682 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:42:22,704 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:42:22,704 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-04-26 18:42:22,704 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2025-04-26 18:42:22,704 INFO L87 Difference]: Start difference. First operand 14175 states and 24171 transitions. cyclomatic complexity: 11185 Second operand has 6 states, 6 states have (on average 6.333333333333333) internal successors, (in total 38), 5 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:42:22,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-04-26 18:42:22,794 INFO L93 Difference]: Finished difference Result 24586 states and 41280 transitions. [2025-04-26 18:42:22,794 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24586 states and 41280 transitions. [2025-04-26 18:42:22,883 INFO L131 ngComponentsAnalysis]: Automaton has 50 accepting balls. 100 [2025-04-26 18:42:22,950 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24586 states to 23037 states and 39241 transitions. [2025-04-26 18:42:22,950 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1917 [2025-04-26 18:42:22,953 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2002 [2025-04-26 18:42:22,953 INFO L74 IsDeterministic]: Start isDeterministic. Operand 23037 states and 39241 transitions. [2025-04-26 18:42:22,953 INFO L81 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-04-26 18:42:22,953 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23037 states and 39241 transitions. [2025-04-26 18:42:22,969 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23037 states and 39241 transitions. [2025-04-26 18:42:23,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23037 to 15933. [2025-04-26 18:42:23,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15933 states, 15933 states have (on average 1.7347015627942006) internal successors, (in total 27639), 15932 states have internal predecessors, (27639), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) [2025-04-26 18:42:23,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15933 states to 15933 states and 27639 transitions. [2025-04-26 18:42:23,142 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15933 states and 27639 transitions. [2025-04-26 18:42:23,142 INFO L140 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-04-26 18:42:23,142 INFO L438 stractBuchiCegarLoop]: Abstraction has 15933 states and 27639 transitions. [2025-04-26 18:42:23,142 INFO L340 stractBuchiCegarLoop]: ======== Iteration 46 ============ [2025-04-26 18:42:23,142 INFO L73 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15933 states and 27639 transitions. [2025-04-26 18:42:23,177 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20 [2025-04-26 18:42:23,177 INFO L88 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-04-26 18:42:23,177 INFO L120 BuchiIsEmpty]: Starting construction of run [2025-04-26 18:42:23,177 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1] [2025-04-26 18:42:23,177 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-04-26 18:42:23,178 INFO L752 eck$LassoCheckResult]: Stem: "[96] $Ultimate##0-->L95: Formula: (and (= v_q3_front_5 v_q3_back_2) (= v_i_5 0) (<= 0 v_N_3) (= v_i_5 v_t_1) (or (and v_f_4 v_g_1) (and (not v_g_1) (not v_f_4))) (= v_q2_front_1 v_q2_back_4) (= v_i_5 v_r_3) v_g_1 (= v_i_5 v_s_3) (= v_q1_back_8 v_q1_front_5)) InVars {q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} OutVars{q3_back=v_q3_back_2, t=v_t_1, s=v_s_3, r=v_r_3, q1_front=v_q1_front_5, N=v_N_3, q2_back=v_q2_back_4, i=v_i_5, g=v_g_1, f=v_f_4, q3_front=v_q3_front_5, q1_back=v_q1_back_8, q2_front=v_q2_front_1} AuxVars[] AssignedVars[]" "[121] L95-->L41: Formula: (= v_thread1Thread1of1ForFork0_thidvar0_2 1) InVars {} OutVars{thread1Thread1of1ForFork0_thidvar0=v_thread1Thread1of1ForFork0_thidvar0_2} AuxVars[] AssignedVars[thread1Thread1of1ForFork0_thidvar0]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[103] L33-->L41: Formula: (and (= v_i_10 (+ v_i_11 1)) (= (+ 1 v_q1_back_18) v_q1_back_17) (= (select v_q1_6 v_q1_back_18) 2)) InVars {q1=v_q1_6, i=v_i_11, q1_back=v_q1_back_18} OutVars{q1=v_q1_6, i=v_i_10, q1_back=v_q1_back_17} AuxVars[] AssignedVars[i, q1_back]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" "[124] L95-1-->L58: Formula: (and (= 2 v_thread2Thread1of1ForFork1_thidvar1_2) (= 2 v_thread2Thread1of1ForFork1_thidvar0_2)) InVars {} OutVars{thread2Thread1of1ForFork1_thidvar0=v_thread2Thread1of1ForFork1_thidvar0_2, thread2Thread1of1ForFork1_thidvar1=v_thread2Thread1of1ForFork1_thidvar1_2} AuxVars[] AssignedVars[thread2Thread1of1ForFork1_thidvar0, thread2Thread1of1ForFork1_thidvar1]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[108] L59-->L59-1: Formula: (and (= (+ v_q1_front_11 1) v_q1_front_10) (< v_q1_front_11 v_q1_back_21) (= (select v_q1_10 v_q1_front_11) v_j_7)) InVars {q1_front=v_q1_front_11, q1=v_q1_10, q1_back=v_q1_back_21} OutVars{q1_front=v_q1_front_10, q1=v_q1_10, q1_back=v_q1_back_21, j=v_j_7} AuxVars[] AssignedVars[q1_front, j]" "[109] L59-1-->L64: Formula: (and (= (+ (select v_q2_3 v_q2_back_7) 1) v_j_9) (= (+ v_q2_back_7 1) v_q2_back_6)) InVars {q2=v_q2_3, q2_back=v_q2_back_7, j=v_j_9} OutVars{q2=v_q2_3, q2_back=v_q2_back_6, j=v_j_9} AuxVars[] AssignedVars[q2_back]" "[110] L64-->L69: Formula: (= v_s_1 (+ v_j_3 v_s_2)) InVars {s=v_s_2, j=v_j_3} OutVars{s=v_s_1, j=v_j_3} AuxVars[] AssignedVars[s]" "[111] L69-->L58: Formula: (or (and (not v_f_2) (<= v_j_4 0)) (and (< 0 v_j_4) v_f_2)) InVars {j=v_j_4} OutVars{j=v_j_4, f=v_f_2} AuxVars[] AssignedVars[f]" "[106] L58-->L59: Formula: v_f_1 InVars {f=v_f_1} OutVars{f=v_f_1} AuxVars[] AssignedVars[]" "[127] L96-->L76: Formula: (and (= 3 v_thread3Thread1of1ForFork2_thidvar0_2) (= 3 v_thread3Thread1of1ForFork2_thidvar1_2) (= 3 v_thread3Thread1of1ForFork2_thidvar2_2)) InVars {} OutVars{thread3Thread1of1ForFork2_thidvar2=v_thread3Thread1of1ForFork2_thidvar2_2, thread3Thread1of1ForFork2_thidvar1=v_thread3Thread1of1ForFork2_thidvar1_2, thread3Thread1of1ForFork2_thidvar0=v_thread3Thread1of1ForFork2_thidvar0_2} AuxVars[] AssignedVars[thread3Thread1of1ForFork2_thidvar2, thread3Thread1of1ForFork2_thidvar1, thread3Thread1of1ForFork2_thidvar0]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[113] L76-->L77: Formula: v_g_4 InVars {g=v_g_4} OutVars{g=v_g_4} AuxVars[] AssignedVars[]" "[115] L77-->L77-1: Formula: (and (< v_q2_front_11 v_q2_back_10) (= (+ v_q2_front_11 1) v_q2_front_10) (= (select v_q2_7 v_q2_front_11) v_k_9)) InVars {q2=v_q2_7, q2_front=v_q2_front_11, q2_back=v_q2_back_10} OutVars{q2=v_q2_7, k=v_k_9, q2_front=v_q2_front_10, q2_back=v_q2_back_10} AuxVars[] AssignedVars[k, q2_front]" "[116] L77-1-->L82: Formula: (and (= (+ (select v_q3_7 v_q3_back_9) 1) v_k_5) (= v_q3_back_8 (+ v_q3_back_9 1))) InVars {q3_back=v_q3_back_9, k=v_k_5, q3=v_q3_7} OutVars{q3_back=v_q3_back_8, k=v_k_5, q3=v_q3_7} AuxVars[] AssignedVars[q3_back]" "[117] L82-->L87: Formula: (= (+ v_k_2 v_t_3) v_t_2) InVars {t=v_t_3, k=v_k_2} OutVars{t=v_t_2, k=v_k_2} AuxVars[] AssignedVars[t]" "[118] L87-->L76: Formula: (or (and (<= v_k_3 0) (not v_g_2)) (and v_g_2 (< 0 v_k_3))) InVars {k=v_k_3} OutVars{k=v_k_3, g=v_g_2} AuxVars[] AssignedVars[g]" "[112] L76-->thread3FINAL: Formula: (not v_g_3) InVars {g=v_g_3} OutVars{g=v_g_3} AuxVars[] AssignedVars[]" [2025-04-26 18:42:23,178 INFO L754 eck$LassoCheckResult]: Loop: "[102] L33-->L41: Formula: (and (= (+ v_q3_front_15 1) v_q3_front_14) (= (+ v_r_14 v_l_7) v_r_13) (< v_q3_front_15 v_q3_back_6) (= v_l_7 (select v_q3_5 v_q3_front_15))) InVars {q3_front=v_q3_front_15, q3_back=v_q3_back_6, q3=v_q3_5, r=v_r_14} OutVars{q3_front=v_q3_front_14, q3_back=v_q3_back_6, l=v_l_7, q3=v_q3_5, r=v_r_13} AuxVars[] AssignedVars[l, q3_front, r]" "[100] L41-->L33: Formula: (< v_i_1 v_N_1) InVars {i=v_i_1, N=v_N_1} OutVars{i=v_i_1, N=v_N_1} AuxVars[] AssignedVars[]" [2025-04-26 18:42:23,178 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:42:23,178 INFO L85 PathProgramCache]: Analyzing trace with hash -1825314243, now seen corresponding path program 30 times [2025-04-26 18:42:23,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:42:23,178 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1449197631] [2025-04-26 18:42:23,178 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-04-26 18:42:23,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:42:23,180 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 55 statements into 5 equivalence classes. [2025-04-26 18:42:23,185 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) and asserted 55 of 55 statements. [2025-04-26 18:42:23,185 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2025-04-26 18:42:23,185 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:42:23,557 INFO L134 CoverageAnalysis]: Checked inductivity of 92 backedges. 18 proven. 74 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:42:23,558 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-04-26 18:42:23,558 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1449197631] [2025-04-26 18:42:23,558 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1449197631] provided 0 perfect and 1 imperfect interpolant sequences [2025-04-26 18:42:23,558 INFO L324 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1506188493] [2025-04-26 18:42:23,558 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-04-26 18:42:23,558 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-04-26 18:42:23,558 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2025-04-26 18:42:23,561 INFO L229 MonitoredProcess]: Starting monitored process 86 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-04-26 18:42:23,561 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (86)] Waiting until timeout for monitored process [2025-04-26 18:42:23,581 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 55 statements into 5 equivalence classes. [2025-04-26 18:42:23,596 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) and asserted 55 of 55 statements. [2025-04-26 18:42:23,597 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2025-04-26 18:42:23,597 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-04-26 18:42:23,597 INFO L256 TraceCheckSpWp]: Trace formula consists of 166 conjuncts, 26 conjuncts are in the unsatisfiable core [2025-04-26 18:42:23,598 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-04-26 18:42:23,893 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:42:24,127 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-04-26 18:42:24,135 INFO L134 CoverageAnalysis]: Checked inductivity of 92 backedges. 21 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:42:24,135 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-04-26 18:42:24,339 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:42:24,339 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 13 treesize of output 17 [2025-04-26 18:42:24,724 INFO L325 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2025-04-26 18:42:24,724 INFO L354 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 43 [2025-04-26 18:42:24,887 INFO L134 CoverageAnalysis]: Checked inductivity of 92 backedges. 9 proven. 83 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-04-26 18:42:24,888 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1506188493] provided 0 perfect and 2 imperfect interpolant sequences [2025-04-26 18:42:24,888 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-04-26 18:42:24,888 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 18, 18] total 52 [2025-04-26 18:42:24,888 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2029171253] [2025-04-26 18:42:24,888 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-04-26 18:42:24,888 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-04-26 18:42:24,888 INFO L155 PredicateUnifier]: Initialized classic predicate unifier [2025-04-26 18:42:24,888 INFO L85 PathProgramCache]: Analyzing trace with hash 4223, now seen corresponding path program 35 times [2025-04-26 18:42:24,888 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-04-26 18:42:24,888 INFO L324 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [81045852] [2025-04-26 18:42:24,888 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-04-26 18:42:24,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-04-26 18:42:24,889 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:42:24,890 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:42:24,890 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-04-26 18:42:24,890 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:42:24,890 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-04-26 18:42:24,890 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-04-26 18:42:24,890 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-04-26 18:42:24,890 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-04-26 18:42:24,890 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-04-26 18:42:24,891 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-04-26 18:42:24,919 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-04-26 18:42:24,919 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2025-04-26 18:42:24,920 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=545, Invalid=2317, Unknown=0, NotChecked=0, Total=2862 [2025-04-26 18:42:24,920 INFO L87 Difference]: Start difference. First operand 15933 states and 27639 transitions. cyclomatic complexity: 13137 Second operand has 54 states, 53 states have (on average 2.981132075471698) internal successors, (in total 158), 53 states have internal predecessors, (158), 0 states have call successors, (0), 0 states have call predecessors, (in total 0), 0 states have return successors, (0), 0 states have call predecessors, ( in total0), 0 states have call successors, (0) Received shutdown request... [2025-04-26 18:45:07,345 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (2)] Ended with exit code 0 [2025-04-26 18:45:07,346 INFO L201 PluginConnector]: Adding new model ring-nondet.wvr.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 26.04 06:45:07 BoogieIcfgContainer [2025-04-26 18:45:07,346 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-04-26 18:45:07,346 INFO L158 Benchmark]: Toolchain (without parser) took 256528.42ms. Allocated memory was 159.4MB in the beginning and 3.3GB in the end (delta: 3.1GB). Free memory was 83.9MB in the beginning and 2.4GB in the end (delta: -2.3GB). Peak memory consumption was 860.0MB. Max. memory is 8.0GB. [2025-04-26 18:45:07,346 INFO L158 Benchmark]: Boogie PL CUP Parser took 0.19ms. Allocated memory is still 159.4MB. Free memory is still 85.1MB. There was no memory consumed. Max. memory is 8.0GB. [2025-04-26 18:45:07,346 INFO L158 Benchmark]: Boogie Procedure Inliner took 34.35ms. Allocated memory is still 159.4MB. Free memory was 83.9MB in the beginning and 82.1MB in the end (delta: 1.8MB). There was no memory consumed. Max. memory is 8.0GB. [2025-04-26 18:45:07,347 INFO L158 Benchmark]: Boogie Preprocessor took 22.50ms. Allocated memory is still 159.4MB. Free memory was 82.0MB in the beginning and 81.0MB in the end (delta: 969.1kB). Peak memory consumption was 4.2MB. Max. memory is 8.0GB. [2025-04-26 18:45:07,347 INFO L158 Benchmark]: RCFGBuilder took 249.16ms. Allocated memory is still 159.4MB. Free memory was 80.9MB in the beginning and 69.2MB in the end (delta: 11.8MB). Peak memory consumption was 8.4MB. Max. memory is 8.0GB. [2025-04-26 18:45:07,347 INFO L158 Benchmark]: BuchiAutomizer took 256219.24ms. Allocated memory was 159.4MB in the beginning and 3.3GB in the end (delta: 3.1GB). Free memory was 69.0MB in the beginning and 2.4GB in the end (delta: -2.3GB). Peak memory consumption was 847.5MB. Max. memory is 8.0GB. [2025-04-26 18:45:07,347 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * Boogie PL CUP Parser took 0.19ms. Allocated memory is still 159.4MB. Free memory is still 85.1MB. There was no memory consumed. Max. memory is 8.0GB. * Boogie Procedure Inliner took 34.35ms. Allocated memory is still 159.4MB. Free memory was 83.9MB in the beginning and 82.1MB in the end (delta: 1.8MB). There was no memory consumed. Max. memory is 8.0GB. * Boogie Preprocessor took 22.50ms. Allocated memory is still 159.4MB. Free memory was 82.0MB in the beginning and 81.0MB in the end (delta: 969.1kB). Peak memory consumption was 4.2MB. Max. memory is 8.0GB. * RCFGBuilder took 249.16ms. Allocated memory is still 159.4MB. Free memory was 80.9MB in the beginning and 69.2MB in the end (delta: 11.8MB). Peak memory consumption was 8.4MB. Max. memory is 8.0GB. * BuchiAutomizer took 256219.24ms. Allocated memory was 159.4MB in the beginning and 3.3GB in the end (delta: 3.1GB). Free memory was 69.0MB in the beginning and 2.4GB in the end (delta: -2.3GB). Peak memory consumption was 847.5MB. Max. memory is 8.0GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 256.1s and 46 iterations. TraceHistogramMax:5. Analysis of lassos took 31.4s. Construction of modules took 16.2s. Büchi inclusion checks took 207.2s. Highest rank in rank-based complementation 3. Minimization of det autom 1. Minimization of nondet autom 44. Automata minimization 5.0s AutomataMinimizationTime, 45 MinimizatonAttempts, 264100 StatesRemovedByMinimization, 45 NontrivialMinimizations. Non-live state removal took 3.8s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [5, 0, 3, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 13170 SdHoareTripleChecker+Valid, 19.1s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 13156 mSDsluCounter, 20507 SdHoareTripleChecker+Invalid, 16.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 18913 mSDsCounter, 2140 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 46307 IncrementalHoareTripleChecker+Invalid, 48447 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 2140 mSolverCounterUnsat, 1594 mSDtfsCounter, 46307 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont0 unkn0 SFLI0 SFLT0 conc3 concLT0 SILN0 SILU35 SILI0 SILT0 lasso8 LassoPreprocessingBenchmarks: Lassos: inital115 mio100 ax100 hnf100 lsp70 ukn97 mio100 lsp62 div100 bol103 ite100 ukn100 eq197 hnf89 smp100 dnf132 smp90 tf100 neg100 sie100 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 42ms VariablesStem: 4 VariablesLoop: 7 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 4 MotzkinApplications: 16 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.2s InitialAbstraction: Time to compute Ample Reduction [ms]: 265, Number of transitions in reduction automaton: 408, Number of states in reduction automaton: 258, Underlying: - StatisticsResult: Constructed decomposition of program Decomposition not yet finished - TimeoutResult: Timeout (de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction) Buchi Automizer is unable to decide termination: Timeout while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 2033 known predicates. RESULT: Ultimate could not prove your program: Timeout Completed graceful shutdown