java -ea -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector-Const.epf -i ../../../trunk/examples/svcomp/array-tiling/pr2_true-unreach-call.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-370d6ab [2018-11-14 17:56:04,269 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-14 17:56:04,271 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-14 17:56:04,288 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-14 17:56:04,288 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-14 17:56:04,290 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-14 17:56:04,291 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-14 17:56:04,293 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-14 17:56:04,295 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-14 17:56:04,296 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-14 17:56:04,297 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-14 17:56:04,297 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-14 17:56:04,298 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-14 17:56:04,299 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-14 17:56:04,300 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-14 17:56:04,301 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-14 17:56:04,302 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-14 17:56:04,303 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-14 17:56:04,305 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-14 17:56:04,307 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-14 17:56:04,309 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-14 17:56:04,310 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-14 17:56:04,312 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-14 17:56:04,313 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-14 17:56:04,313 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-14 17:56:04,314 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-14 17:56:04,315 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-14 17:56:04,316 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-14 17:56:04,316 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-14 17:56:04,318 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-14 17:56:04,318 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-14 17:56:04,318 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-14 17:56:04,319 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-14 17:56:04,319 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-14 17:56:04,320 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-14 17:56:04,321 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-14 17:56:04,321 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector-Const.epf [2018-11-14 17:56:04,350 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-14 17:56:04,353 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-14 17:56:04,355 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-14 17:56:04,355 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-11-14 17:56:04,355 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-14 17:56:04,356 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-14 17:56:04,356 INFO L133 SettingsManager]: * Use SBE=true [2018-11-14 17:56:04,356 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-14 17:56:04,356 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-14 17:56:04,356 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-14 17:56:04,357 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-14 17:56:04,358 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-14 17:56:04,358 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-14 17:56:04,358 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-14 17:56:04,358 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-14 17:56:04,359 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-14 17:56:04,359 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-14 17:56:04,359 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-14 17:56:04,359 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-14 17:56:04,359 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-14 17:56:04,359 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-14 17:56:04,361 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-14 17:56:04,361 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-14 17:56:04,361 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-14 17:56:04,361 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-14 17:56:04,362 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-14 17:56:04,362 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-14 17:56:04,362 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-14 17:56:04,362 INFO L133 SettingsManager]: * Trace refinement strategy=WOLF [2018-11-14 17:56:04,362 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-14 17:56:04,363 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-11-14 17:56:04,363 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-11-14 17:56:04,363 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-14 17:56:04,410 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-14 17:56:04,427 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-14 17:56:04,431 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-14 17:56:04,434 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-14 17:56:04,434 INFO L276 PluginConnector]: CDTParser initialized [2018-11-14 17:56:04,435 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-tiling/pr2_true-unreach-call.i [2018-11-14 17:56:04,493 INFO L218 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/64abf7af9/80a6dbb66b164d75bc499e7213f80b42/FLAG0909633a2 [2018-11-14 17:56:04,899 INFO L298 CDTParser]: Found 1 translation units. [2018-11-14 17:56:04,900 INFO L158 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-tiling/pr2_true-unreach-call.i [2018-11-14 17:56:04,907 INFO L346 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/64abf7af9/80a6dbb66b164d75bc499e7213f80b42/FLAG0909633a2 [2018-11-14 17:56:04,922 INFO L354 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/64abf7af9/80a6dbb66b164d75bc499e7213f80b42 [2018-11-14 17:56:04,932 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-14 17:56:04,934 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-11-14 17:56:04,935 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-14 17:56:04,935 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-14 17:56:04,939 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-14 17:56:04,941 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.11 05:56:04" (1/1) ... [2018-11-14 17:56:04,944 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7b52ee5f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:04, skipping insertion in model container [2018-11-14 17:56:04,944 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.11 05:56:04" (1/1) ... [2018-11-14 17:56:04,955 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-14 17:56:04,980 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-14 17:56:05,234 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-14 17:56:05,243 INFO L191 MainTranslator]: Completed pre-run [2018-11-14 17:56:05,289 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-14 17:56:05,323 INFO L195 MainTranslator]: Completed translation [2018-11-14 17:56:05,323 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:05 WrapperNode [2018-11-14 17:56:05,323 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-14 17:56:05,324 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-14 17:56:05,324 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-14 17:56:05,324 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-14 17:56:05,337 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:05" (1/1) ... [2018-11-14 17:56:05,337 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:05" (1/1) ... [2018-11-14 17:56:05,346 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:05" (1/1) ... [2018-11-14 17:56:05,347 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:05" (1/1) ... [2018-11-14 17:56:05,361 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:05" (1/1) ... [2018-11-14 17:56:05,372 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:05" (1/1) ... [2018-11-14 17:56:05,374 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:05" (1/1) ... [2018-11-14 17:56:05,379 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-14 17:56:05,383 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-14 17:56:05,383 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-14 17:56:05,383 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-14 17:56:05,384 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:05" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-14 17:56:05,524 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-14 17:56:05,525 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-14 17:56:05,525 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-11-14 17:56:05,525 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-14 17:56:05,525 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-11-14 17:56:05,526 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assume [2018-11-14 17:56:05,526 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-11-14 17:56:05,526 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-11-14 17:56:05,526 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-14 17:56:05,526 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-14 17:56:05,526 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-14 17:56:05,527 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE4 [2018-11-14 17:56:05,527 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE4 [2018-11-14 17:56:05,527 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-14 17:56:05,527 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-14 17:56:05,527 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~intINTTYPE4 [2018-11-14 17:56:06,162 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-14 17:56:06,163 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.11 05:56:06 BoogieIcfgContainer [2018-11-14 17:56:06,163 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-14 17:56:06,164 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-14 17:56:06,164 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-14 17:56:06,167 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-14 17:56:06,168 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 14.11 05:56:04" (1/3) ... [2018-11-14 17:56:06,168 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@772b8deb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.11 05:56:06, skipping insertion in model container [2018-11-14 17:56:06,169 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:05" (2/3) ... [2018-11-14 17:56:06,169 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@772b8deb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.11 05:56:06, skipping insertion in model container [2018-11-14 17:56:06,169 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.11 05:56:06" (3/3) ... [2018-11-14 17:56:06,171 INFO L112 eAbstractionObserver]: Analyzing ICFG pr2_true-unreach-call.i [2018-11-14 17:56:06,180 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-14 17:56:06,188 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-14 17:56:06,203 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-14 17:56:06,238 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-14 17:56:06,239 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-14 17:56:06,239 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-14 17:56:06,240 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-14 17:56:06,240 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-14 17:56:06,240 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-14 17:56:06,240 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-14 17:56:06,240 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-14 17:56:06,240 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-14 17:56:06,261 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states. [2018-11-14 17:56:06,269 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-14 17:56:06,269 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:56:06,270 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:56:06,272 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:56:06,278 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:56:06,279 INFO L82 PathProgramCache]: Analyzing trace with hash 1972237412, now seen corresponding path program 1 times [2018-11-14 17:56:06,283 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:56:06,284 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:56:06,301 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 17:56:06,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:06,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:06,412 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:56:06,556 INFO L256 TraceCheckUtils]: 0: Hoare triple {35#true} call ULTIMATE.init(); {35#true} is VALID [2018-11-14 17:56:06,560 INFO L273 TraceCheckUtils]: 1: Hoare triple {35#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {35#true} is VALID [2018-11-14 17:56:06,560 INFO L273 TraceCheckUtils]: 2: Hoare triple {35#true} assume true; {35#true} is VALID [2018-11-14 17:56:06,561 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {35#true} {35#true} #79#return; {35#true} is VALID [2018-11-14 17:56:06,561 INFO L256 TraceCheckUtils]: 4: Hoare triple {35#true} call #t~ret7 := main(); {35#true} is VALID [2018-11-14 17:56:06,561 INFO L273 TraceCheckUtils]: 5: Hoare triple {35#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {35#true} is VALID [2018-11-14 17:56:06,561 INFO L273 TraceCheckUtils]: 6: Hoare triple {35#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {35#true} is VALID [2018-11-14 17:56:06,562 INFO L273 TraceCheckUtils]: 7: Hoare triple {35#true} assume !(~bvsrem32(~CELLCOUNT~0, 2bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 2bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {35#true} is VALID [2018-11-14 17:56:06,563 INFO L273 TraceCheckUtils]: 8: Hoare triple {35#true} assume !true; {36#false} is VALID [2018-11-14 17:56:06,563 INFO L273 TraceCheckUtils]: 9: Hoare triple {36#false} ~i~0 := 0bv32; {36#false} is VALID [2018-11-14 17:56:06,563 INFO L273 TraceCheckUtils]: 10: Hoare triple {36#false} assume true; {36#false} is VALID [2018-11-14 17:56:06,564 INFO L273 TraceCheckUtils]: 11: Hoare triple {36#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {36#false} is VALID [2018-11-14 17:56:06,564 INFO L273 TraceCheckUtils]: 12: Hoare triple {36#false} assume #t~short6; {36#false} is VALID [2018-11-14 17:56:06,564 INFO L256 TraceCheckUtils]: 13: Hoare triple {36#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {36#false} is VALID [2018-11-14 17:56:06,565 INFO L273 TraceCheckUtils]: 14: Hoare triple {36#false} ~cond := #in~cond; {36#false} is VALID [2018-11-14 17:56:06,565 INFO L273 TraceCheckUtils]: 15: Hoare triple {36#false} assume ~cond == 0bv32; {36#false} is VALID [2018-11-14 17:56:06,565 INFO L273 TraceCheckUtils]: 16: Hoare triple {36#false} assume !false; {36#false} is VALID [2018-11-14 17:56:06,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:06,569 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-14 17:56:06,573 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-14 17:56:06,575 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-14 17:56:06,581 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 17 [2018-11-14 17:56:06,588 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:56:06,592 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 2 states. [2018-11-14 17:56:06,742 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 17 edges. 17 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:06,743 INFO L459 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-11-14 17:56:06,754 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-11-14 17:56:06,755 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-14 17:56:06,760 INFO L87 Difference]: Start difference. First operand 32 states. Second operand 2 states. [2018-11-14 17:56:06,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:06,949 INFO L93 Difference]: Finished difference Result 51 states and 64 transitions. [2018-11-14 17:56:06,950 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-11-14 17:56:06,950 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 17 [2018-11-14 17:56:06,950 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:56:06,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2018-11-14 17:56:06,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 64 transitions. [2018-11-14 17:56:06,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2018-11-14 17:56:06,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 64 transitions. [2018-11-14 17:56:06,969 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 2 states and 64 transitions. [2018-11-14 17:56:07,270 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 64 edges. 64 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:07,283 INFO L225 Difference]: With dead ends: 51 [2018-11-14 17:56:07,283 INFO L226 Difference]: Without dead ends: 26 [2018-11-14 17:56:07,287 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 16 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-14 17:56:07,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2018-11-14 17:56:07,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 26. [2018-11-14 17:56:07,335 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:56:07,335 INFO L82 GeneralOperation]: Start isEquivalent. First operand 26 states. Second operand 26 states. [2018-11-14 17:56:07,336 INFO L74 IsIncluded]: Start isIncluded. First operand 26 states. Second operand 26 states. [2018-11-14 17:56:07,336 INFO L87 Difference]: Start difference. First operand 26 states. Second operand 26 states. [2018-11-14 17:56:07,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:07,342 INFO L93 Difference]: Finished difference Result 26 states and 30 transitions. [2018-11-14 17:56:07,342 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 30 transitions. [2018-11-14 17:56:07,343 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:07,343 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:07,343 INFO L74 IsIncluded]: Start isIncluded. First operand 26 states. Second operand 26 states. [2018-11-14 17:56:07,344 INFO L87 Difference]: Start difference. First operand 26 states. Second operand 26 states. [2018-11-14 17:56:07,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:07,348 INFO L93 Difference]: Finished difference Result 26 states and 30 transitions. [2018-11-14 17:56:07,348 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 30 transitions. [2018-11-14 17:56:07,349 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:07,349 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:07,349 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:56:07,350 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:56:07,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2018-11-14 17:56:07,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 30 transitions. [2018-11-14 17:56:07,355 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 30 transitions. Word has length 17 [2018-11-14 17:56:07,355 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:56:07,355 INFO L480 AbstractCegarLoop]: Abstraction has 26 states and 30 transitions. [2018-11-14 17:56:07,356 INFO L481 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-11-14 17:56:07,356 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 30 transitions. [2018-11-14 17:56:07,357 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-11-14 17:56:07,357 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:56:07,357 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:56:07,357 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:56:07,358 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:56:07,358 INFO L82 PathProgramCache]: Analyzing trace with hash 1988162871, now seen corresponding path program 1 times [2018-11-14 17:56:07,359 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:56:07,359 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:56:07,384 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 17:56:07,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:07,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:07,423 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:56:07,578 INFO L256 TraceCheckUtils]: 0: Hoare triple {235#true} call ULTIMATE.init(); {235#true} is VALID [2018-11-14 17:56:07,579 INFO L273 TraceCheckUtils]: 1: Hoare triple {235#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {235#true} is VALID [2018-11-14 17:56:07,579 INFO L273 TraceCheckUtils]: 2: Hoare triple {235#true} assume true; {235#true} is VALID [2018-11-14 17:56:07,580 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {235#true} {235#true} #79#return; {235#true} is VALID [2018-11-14 17:56:07,580 INFO L256 TraceCheckUtils]: 4: Hoare triple {235#true} call #t~ret7 := main(); {235#true} is VALID [2018-11-14 17:56:07,583 INFO L273 TraceCheckUtils]: 5: Hoare triple {235#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {235#true} is VALID [2018-11-14 17:56:07,583 INFO L273 TraceCheckUtils]: 6: Hoare triple {235#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {235#true} is VALID [2018-11-14 17:56:07,583 INFO L273 TraceCheckUtils]: 7: Hoare triple {235#true} assume !(~bvsrem32(~CELLCOUNT~0, 2bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 2bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {235#true} is VALID [2018-11-14 17:56:07,584 INFO L273 TraceCheckUtils]: 8: Hoare triple {235#true} assume true; {235#true} is VALID [2018-11-14 17:56:07,584 INFO L273 TraceCheckUtils]: 9: Hoare triple {235#true} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {235#true} is VALID [2018-11-14 17:56:07,585 INFO L273 TraceCheckUtils]: 10: Hoare triple {235#true} ~i~0 := 0bv32; {235#true} is VALID [2018-11-14 17:56:07,585 INFO L273 TraceCheckUtils]: 11: Hoare triple {235#true} assume true; {235#true} is VALID [2018-11-14 17:56:07,586 INFO L273 TraceCheckUtils]: 12: Hoare triple {235#true} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {235#true} is VALID [2018-11-14 17:56:07,596 INFO L273 TraceCheckUtils]: 13: Hoare triple {235#true} assume #t~short6; {279#|main_#t~short6|} is VALID [2018-11-14 17:56:07,612 INFO L256 TraceCheckUtils]: 14: Hoare triple {279#|main_#t~short6|} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {283#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-14 17:56:07,613 INFO L273 TraceCheckUtils]: 15: Hoare triple {283#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {287#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-14 17:56:07,621 INFO L273 TraceCheckUtils]: 16: Hoare triple {287#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume ~cond == 0bv32; {236#false} is VALID [2018-11-14 17:56:07,622 INFO L273 TraceCheckUtils]: 17: Hoare triple {236#false} assume !false; {236#false} is VALID [2018-11-14 17:56:07,625 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:07,625 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-14 17:56:07,633 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-14 17:56:07,634 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-14 17:56:07,635 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 18 [2018-11-14 17:56:07,637 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:56:07,637 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states. [2018-11-14 17:56:07,868 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 18 edges. 18 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:07,868 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-14 17:56:07,868 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-14 17:56:07,869 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-14 17:56:07,869 INFO L87 Difference]: Start difference. First operand 26 states and 30 transitions. Second operand 5 states. [2018-11-14 17:56:08,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:08,727 INFO L93 Difference]: Finished difference Result 34 states and 38 transitions. [2018-11-14 17:56:08,727 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-14 17:56:08,727 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 18 [2018-11-14 17:56:08,728 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:56:08,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-14 17:56:08,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 38 transitions. [2018-11-14 17:56:08,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-14 17:56:08,738 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 38 transitions. [2018-11-14 17:56:08,739 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states and 38 transitions. [2018-11-14 17:56:08,833 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 38 edges. 38 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:08,836 INFO L225 Difference]: With dead ends: 34 [2018-11-14 17:56:08,836 INFO L226 Difference]: Without dead ends: 32 [2018-11-14 17:56:08,837 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 14 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-14 17:56:08,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states. [2018-11-14 17:56:08,849 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 31. [2018-11-14 17:56:08,850 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:56:08,850 INFO L82 GeneralOperation]: Start isEquivalent. First operand 32 states. Second operand 31 states. [2018-11-14 17:56:08,850 INFO L74 IsIncluded]: Start isIncluded. First operand 32 states. Second operand 31 states. [2018-11-14 17:56:08,851 INFO L87 Difference]: Start difference. First operand 32 states. Second operand 31 states. [2018-11-14 17:56:08,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:08,854 INFO L93 Difference]: Finished difference Result 32 states and 36 transitions. [2018-11-14 17:56:08,854 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 36 transitions. [2018-11-14 17:56:08,855 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:08,855 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:08,856 INFO L74 IsIncluded]: Start isIncluded. First operand 31 states. Second operand 32 states. [2018-11-14 17:56:08,856 INFO L87 Difference]: Start difference. First operand 31 states. Second operand 32 states. [2018-11-14 17:56:08,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:08,859 INFO L93 Difference]: Finished difference Result 32 states and 36 transitions. [2018-11-14 17:56:08,859 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 36 transitions. [2018-11-14 17:56:08,860 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:08,860 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:08,860 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:56:08,860 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:56:08,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2018-11-14 17:56:08,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 35 transitions. [2018-11-14 17:56:08,863 INFO L78 Accepts]: Start accepts. Automaton has 31 states and 35 transitions. Word has length 18 [2018-11-14 17:56:08,864 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:56:08,864 INFO L480 AbstractCegarLoop]: Abstraction has 31 states and 35 transitions. [2018-11-14 17:56:08,864 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-14 17:56:08,864 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 35 transitions. [2018-11-14 17:56:08,865 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-11-14 17:56:08,865 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:56:08,865 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:56:08,866 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:56:08,866 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:56:08,866 INFO L82 PathProgramCache]: Analyzing trace with hash 1990009913, now seen corresponding path program 1 times [2018-11-14 17:56:08,867 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:56:08,867 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:56:08,891 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 17:56:08,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:08,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:08,959 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:56:09,112 INFO L256 TraceCheckUtils]: 0: Hoare triple {444#true} call ULTIMATE.init(); {444#true} is VALID [2018-11-14 17:56:09,113 INFO L273 TraceCheckUtils]: 1: Hoare triple {444#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {444#true} is VALID [2018-11-14 17:56:09,113 INFO L273 TraceCheckUtils]: 2: Hoare triple {444#true} assume true; {444#true} is VALID [2018-11-14 17:56:09,114 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {444#true} {444#true} #79#return; {444#true} is VALID [2018-11-14 17:56:09,114 INFO L256 TraceCheckUtils]: 4: Hoare triple {444#true} call #t~ret7 := main(); {444#true} is VALID [2018-11-14 17:56:09,115 INFO L273 TraceCheckUtils]: 5: Hoare triple {444#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {444#true} is VALID [2018-11-14 17:56:09,116 INFO L273 TraceCheckUtils]: 6: Hoare triple {444#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {467#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} is VALID [2018-11-14 17:56:09,117 INFO L273 TraceCheckUtils]: 7: Hoare triple {467#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} assume !(~bvsrem32(~CELLCOUNT~0, 2bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 2bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {471#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:09,128 INFO L273 TraceCheckUtils]: 8: Hoare triple {471#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {471#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:09,144 INFO L273 TraceCheckUtils]: 9: Hoare triple {471#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {445#false} is VALID [2018-11-14 17:56:09,144 INFO L273 TraceCheckUtils]: 10: Hoare triple {445#false} ~i~0 := 0bv32; {445#false} is VALID [2018-11-14 17:56:09,145 INFO L273 TraceCheckUtils]: 11: Hoare triple {445#false} assume true; {445#false} is VALID [2018-11-14 17:56:09,145 INFO L273 TraceCheckUtils]: 12: Hoare triple {445#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {445#false} is VALID [2018-11-14 17:56:09,145 INFO L273 TraceCheckUtils]: 13: Hoare triple {445#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {445#false} is VALID [2018-11-14 17:56:09,146 INFO L256 TraceCheckUtils]: 14: Hoare triple {445#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {445#false} is VALID [2018-11-14 17:56:09,146 INFO L273 TraceCheckUtils]: 15: Hoare triple {445#false} ~cond := #in~cond; {445#false} is VALID [2018-11-14 17:56:09,146 INFO L273 TraceCheckUtils]: 16: Hoare triple {445#false} assume ~cond == 0bv32; {445#false} is VALID [2018-11-14 17:56:09,147 INFO L273 TraceCheckUtils]: 17: Hoare triple {445#false} assume !false; {445#false} is VALID [2018-11-14 17:56:09,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:09,148 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (4)] Exception during sending of exit command (exit): Stream closed [2018-11-14 17:56:09,152 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-14 17:56:09,153 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-14 17:56:09,153 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 18 [2018-11-14 17:56:09,153 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:56:09,154 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states. [2018-11-14 17:56:09,192 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 18 edges. 18 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:09,192 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-14 17:56:09,193 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-14 17:56:09,193 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-14 17:56:09,193 INFO L87 Difference]: Start difference. First operand 31 states and 35 transitions. Second operand 4 states. [2018-11-14 17:56:09,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:09,633 INFO L93 Difference]: Finished difference Result 54 states and 62 transitions. [2018-11-14 17:56:09,633 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-14 17:56:09,633 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 18 [2018-11-14 17:56:09,634 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:56:09,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-14 17:56:09,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 52 transitions. [2018-11-14 17:56:09,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-14 17:56:09,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 52 transitions. [2018-11-14 17:56:09,642 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states and 52 transitions. [2018-11-14 17:56:09,789 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 52 edges. 52 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:09,792 INFO L225 Difference]: With dead ends: 54 [2018-11-14 17:56:09,792 INFO L226 Difference]: Without dead ends: 36 [2018-11-14 17:56:09,793 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 15 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-14 17:56:09,793 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2018-11-14 17:56:09,850 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 33. [2018-11-14 17:56:09,851 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:56:09,851 INFO L82 GeneralOperation]: Start isEquivalent. First operand 36 states. Second operand 33 states. [2018-11-14 17:56:09,851 INFO L74 IsIncluded]: Start isIncluded. First operand 36 states. Second operand 33 states. [2018-11-14 17:56:09,851 INFO L87 Difference]: Start difference. First operand 36 states. Second operand 33 states. [2018-11-14 17:56:09,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:09,855 INFO L93 Difference]: Finished difference Result 36 states and 42 transitions. [2018-11-14 17:56:09,855 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 42 transitions. [2018-11-14 17:56:09,855 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:09,856 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:09,856 INFO L74 IsIncluded]: Start isIncluded. First operand 33 states. Second operand 36 states. [2018-11-14 17:56:09,857 INFO L87 Difference]: Start difference. First operand 33 states. Second operand 36 states. [2018-11-14 17:56:09,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:09,860 INFO L93 Difference]: Finished difference Result 36 states and 42 transitions. [2018-11-14 17:56:09,861 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 42 transitions. [2018-11-14 17:56:09,861 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:09,861 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:09,862 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:56:09,862 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:56:09,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33 states. [2018-11-14 17:56:09,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 37 transitions. [2018-11-14 17:56:09,864 INFO L78 Accepts]: Start accepts. Automaton has 33 states and 37 transitions. Word has length 18 [2018-11-14 17:56:09,865 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:56:09,865 INFO L480 AbstractCegarLoop]: Abstraction has 33 states and 37 transitions. [2018-11-14 17:56:09,865 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-14 17:56:09,865 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 37 transitions. [2018-11-14 17:56:09,866 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-11-14 17:56:09,866 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:56:09,866 INFO L375 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:56:09,867 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:56:09,867 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:56:09,867 INFO L82 PathProgramCache]: Analyzing trace with hash 1119839610, now seen corresponding path program 1 times [2018-11-14 17:56:09,867 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:56:09,868 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:56:09,886 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 17:56:09,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:09,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:09,969 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:56:10,140 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-14 17:56:10,150 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-14 17:56:10,154 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:56:10,160 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:10,180 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:10,181 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:31, output treesize:27 [2018-11-14 17:56:10,244 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-11-14 17:56:10,256 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:56:10,258 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:56:10,260 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 31 [2018-11-14 17:56:10,281 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:56:10,328 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:10,346 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:10,347 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:31, output treesize:27 [2018-11-14 17:56:10,579 INFO L256 TraceCheckUtils]: 0: Hoare triple {687#true} call ULTIMATE.init(); {687#true} is VALID [2018-11-14 17:56:10,579 INFO L273 TraceCheckUtils]: 1: Hoare triple {687#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {687#true} is VALID [2018-11-14 17:56:10,580 INFO L273 TraceCheckUtils]: 2: Hoare triple {687#true} assume true; {687#true} is VALID [2018-11-14 17:56:10,580 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {687#true} {687#true} #79#return; {687#true} is VALID [2018-11-14 17:56:10,580 INFO L256 TraceCheckUtils]: 4: Hoare triple {687#true} call #t~ret7 := main(); {687#true} is VALID [2018-11-14 17:56:10,581 INFO L273 TraceCheckUtils]: 5: Hoare triple {687#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {687#true} is VALID [2018-11-14 17:56:10,582 INFO L273 TraceCheckUtils]: 6: Hoare triple {687#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {710#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:10,583 INFO L273 TraceCheckUtils]: 7: Hoare triple {710#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !(~bvsrem32(~CELLCOUNT~0, 2bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 2bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {714#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:10,583 INFO L273 TraceCheckUtils]: 8: Hoare triple {714#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {714#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:10,586 INFO L273 TraceCheckUtils]: 9: Hoare triple {714#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {714#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:10,589 INFO L273 TraceCheckUtils]: 10: Hoare triple {714#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {724#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:10,591 INFO L273 TraceCheckUtils]: 11: Hoare triple {724#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {728#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:10,592 INFO L273 TraceCheckUtils]: 12: Hoare triple {728#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {728#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:10,593 INFO L273 TraceCheckUtils]: 13: Hoare triple {728#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume true; {728#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:10,593 INFO L273 TraceCheckUtils]: 14: Hoare triple {728#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {728#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:10,594 INFO L273 TraceCheckUtils]: 15: Hoare triple {728#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} ~i~0 := 0bv32; {741#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:10,595 INFO L273 TraceCheckUtils]: 16: Hoare triple {741#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume true; {741#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:10,596 INFO L273 TraceCheckUtils]: 17: Hoare triple {741#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {748#|main_#t~short6|} is VALID [2018-11-14 17:56:10,597 INFO L273 TraceCheckUtils]: 18: Hoare triple {748#|main_#t~short6|} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {688#false} is VALID [2018-11-14 17:56:10,597 INFO L256 TraceCheckUtils]: 19: Hoare triple {688#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {688#false} is VALID [2018-11-14 17:56:10,598 INFO L273 TraceCheckUtils]: 20: Hoare triple {688#false} ~cond := #in~cond; {688#false} is VALID [2018-11-14 17:56:10,598 INFO L273 TraceCheckUtils]: 21: Hoare triple {688#false} assume ~cond == 0bv32; {688#false} is VALID [2018-11-14 17:56:10,598 INFO L273 TraceCheckUtils]: 22: Hoare triple {688#false} assume !false; {688#false} is VALID [2018-11-14 17:56:10,603 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:10,603 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-14 17:56:10,981 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 21 [2018-11-14 17:56:10,991 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 25 [2018-11-14 17:56:13,224 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (= |main_~#volArray~0.offset| (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32))) [2018-11-14 17:56:13,233 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 17:56:13,234 INFO L303 Elim1Store]: Index analysis took 2175 ms [2018-11-14 17:56:13,235 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 15 [2018-11-14 17:56:13,241 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 17:56:13,276 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 17:56:13,290 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 17:56:13,315 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-14 17:56:13,315 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:31, output treesize:19 [2018-11-14 17:56:13,324 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:56:13,471 INFO L273 TraceCheckUtils]: 22: Hoare triple {688#false} assume !false; {688#false} is VALID [2018-11-14 17:56:13,471 INFO L273 TraceCheckUtils]: 21: Hoare triple {688#false} assume ~cond == 0bv32; {688#false} is VALID [2018-11-14 17:56:13,472 INFO L273 TraceCheckUtils]: 20: Hoare triple {688#false} ~cond := #in~cond; {688#false} is VALID [2018-11-14 17:56:13,472 INFO L256 TraceCheckUtils]: 19: Hoare triple {688#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {688#false} is VALID [2018-11-14 17:56:13,472 INFO L273 TraceCheckUtils]: 18: Hoare triple {748#|main_#t~short6|} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {688#false} is VALID [2018-11-14 17:56:13,473 INFO L273 TraceCheckUtils]: 17: Hoare triple {779#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {748#|main_#t~short6|} is VALID [2018-11-14 17:56:13,474 INFO L273 TraceCheckUtils]: 16: Hoare triple {779#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume true; {779#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is VALID [2018-11-14 17:56:13,476 INFO L273 TraceCheckUtils]: 15: Hoare triple {786#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} ~i~0 := 0bv32; {779#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is VALID [2018-11-14 17:56:13,476 INFO L273 TraceCheckUtils]: 14: Hoare triple {786#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {786#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-14 17:56:13,477 INFO L273 TraceCheckUtils]: 13: Hoare triple {786#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume true; {786#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-14 17:56:13,477 INFO L273 TraceCheckUtils]: 12: Hoare triple {786#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {786#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-14 17:56:13,485 INFO L273 TraceCheckUtils]: 11: Hoare triple {799#(or (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {786#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-14 17:56:13,522 INFO L273 TraceCheckUtils]: 10: Hoare triple {803#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_4 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (bvsge v_arrayElimCell_4 main_~MINVAL~0))) (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {799#(or (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0))} is VALID [2018-11-14 17:56:13,523 INFO L273 TraceCheckUtils]: 9: Hoare triple {803#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_4 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (bvsge v_arrayElimCell_4 main_~MINVAL~0))) (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {803#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_4 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (bvsge v_arrayElimCell_4 main_~MINVAL~0))) (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)))} is VALID [2018-11-14 17:56:13,523 INFO L273 TraceCheckUtils]: 8: Hoare triple {803#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_4 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (bvsge v_arrayElimCell_4 main_~MINVAL~0))) (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)))} assume true; {803#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_4 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (bvsge v_arrayElimCell_4 main_~MINVAL~0))) (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)))} is VALID [2018-11-14 17:56:13,527 INFO L273 TraceCheckUtils]: 7: Hoare triple {687#true} assume !(~bvsrem32(~CELLCOUNT~0, 2bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 2bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {803#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_4 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (bvsge v_arrayElimCell_4 main_~MINVAL~0))) (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)))} is VALID [2018-11-14 17:56:13,527 INFO L273 TraceCheckUtils]: 6: Hoare triple {687#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {687#true} is VALID [2018-11-14 17:56:13,528 INFO L273 TraceCheckUtils]: 5: Hoare triple {687#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {687#true} is VALID [2018-11-14 17:56:13,528 INFO L256 TraceCheckUtils]: 4: Hoare triple {687#true} call #t~ret7 := main(); {687#true} is VALID [2018-11-14 17:56:13,528 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {687#true} {687#true} #79#return; {687#true} is VALID [2018-11-14 17:56:13,528 INFO L273 TraceCheckUtils]: 2: Hoare triple {687#true} assume true; {687#true} is VALID [2018-11-14 17:56:13,529 INFO L273 TraceCheckUtils]: 1: Hoare triple {687#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {687#true} is VALID [2018-11-14 17:56:13,529 INFO L256 TraceCheckUtils]: 0: Hoare triple {687#true} call ULTIMATE.init(); {687#true} is VALID [2018-11-14 17:56:13,531 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:13,535 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-14 17:56:13,536 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7] total 12 [2018-11-14 17:56:13,536 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 23 [2018-11-14 17:56:13,536 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:56:13,537 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 12 states. [2018-11-14 17:56:13,732 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 35 edges. 35 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:13,733 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-14 17:56:13,733 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-14 17:56:13,733 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=99, Unknown=0, NotChecked=0, Total=132 [2018-11-14 17:56:13,734 INFO L87 Difference]: Start difference. First operand 33 states and 37 transitions. Second operand 12 states. [2018-11-14 17:56:18,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:18,169 INFO L93 Difference]: Finished difference Result 125 states and 161 transitions. [2018-11-14 17:56:18,169 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-11-14 17:56:18,170 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 23 [2018-11-14 17:56:18,170 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:56:18,170 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2018-11-14 17:56:18,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 151 transitions. [2018-11-14 17:56:18,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2018-11-14 17:56:18,188 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 151 transitions. [2018-11-14 17:56:18,188 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 20 states and 151 transitions. [2018-11-14 17:56:18,829 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 151 edges. 151 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:18,835 INFO L225 Difference]: With dead ends: 125 [2018-11-14 17:56:18,835 INFO L226 Difference]: Without dead ends: 102 [2018-11-14 17:56:18,836 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 35 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 130 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=201, Invalid=555, Unknown=0, NotChecked=0, Total=756 [2018-11-14 17:56:18,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states. [2018-11-14 17:56:18,990 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 54. [2018-11-14 17:56:18,990 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:56:18,990 INFO L82 GeneralOperation]: Start isEquivalent. First operand 102 states. Second operand 54 states. [2018-11-14 17:56:18,990 INFO L74 IsIncluded]: Start isIncluded. First operand 102 states. Second operand 54 states. [2018-11-14 17:56:18,990 INFO L87 Difference]: Start difference. First operand 102 states. Second operand 54 states. [2018-11-14 17:56:18,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:18,999 INFO L93 Difference]: Finished difference Result 102 states and 130 transitions. [2018-11-14 17:56:18,999 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 130 transitions. [2018-11-14 17:56:19,001 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:19,001 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:19,001 INFO L74 IsIncluded]: Start isIncluded. First operand 54 states. Second operand 102 states. [2018-11-14 17:56:19,001 INFO L87 Difference]: Start difference. First operand 54 states. Second operand 102 states. [2018-11-14 17:56:19,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:19,009 INFO L93 Difference]: Finished difference Result 102 states and 130 transitions. [2018-11-14 17:56:19,009 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 130 transitions. [2018-11-14 17:56:19,011 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:19,011 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:19,011 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:56:19,011 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:56:19,012 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-11-14 17:56:19,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 67 transitions. [2018-11-14 17:56:19,015 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 67 transitions. Word has length 23 [2018-11-14 17:56:19,015 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:56:19,015 INFO L480 AbstractCegarLoop]: Abstraction has 54 states and 67 transitions. [2018-11-14 17:56:19,015 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-14 17:56:19,015 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 67 transitions. [2018-11-14 17:56:19,016 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-11-14 17:56:19,017 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:56:19,017 INFO L375 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:56:19,017 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:56:19,017 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:56:19,018 INFO L82 PathProgramCache]: Analyzing trace with hash 533033596, now seen corresponding path program 1 times [2018-11-14 17:56:19,018 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:56:19,018 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:56:19,048 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 17:56:19,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:19,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:19,120 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:56:19,194 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-14 17:56:19,201 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-14 17:56:19,203 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:56:19,205 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:19,218 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:19,218 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:25, output treesize:21 [2018-11-14 17:56:19,263 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-11-14 17:56:19,268 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:56:19,270 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 23 [2018-11-14 17:56:19,278 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:56:19,289 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:19,301 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:19,302 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:24, output treesize:20 [2018-11-14 17:56:19,535 INFO L256 TraceCheckUtils]: 0: Hoare triple {1302#true} call ULTIMATE.init(); {1302#true} is VALID [2018-11-14 17:56:19,535 INFO L273 TraceCheckUtils]: 1: Hoare triple {1302#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1302#true} is VALID [2018-11-14 17:56:19,535 INFO L273 TraceCheckUtils]: 2: Hoare triple {1302#true} assume true; {1302#true} is VALID [2018-11-14 17:56:19,535 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1302#true} {1302#true} #79#return; {1302#true} is VALID [2018-11-14 17:56:19,536 INFO L256 TraceCheckUtils]: 4: Hoare triple {1302#true} call #t~ret7 := main(); {1302#true} is VALID [2018-11-14 17:56:19,536 INFO L273 TraceCheckUtils]: 5: Hoare triple {1302#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1302#true} is VALID [2018-11-14 17:56:19,536 INFO L273 TraceCheckUtils]: 6: Hoare triple {1302#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {1325#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-14 17:56:19,541 INFO L273 TraceCheckUtils]: 7: Hoare triple {1325#(= |main_~#volArray~0.offset| (_ bv0 32))} assume !(~bvsrem32(~CELLCOUNT~0, 2bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 2bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {1329#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:19,548 INFO L273 TraceCheckUtils]: 8: Hoare triple {1329#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {1329#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:19,549 INFO L273 TraceCheckUtils]: 9: Hoare triple {1329#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {1329#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:19,551 INFO L273 TraceCheckUtils]: 10: Hoare triple {1329#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {1339#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:19,553 INFO L273 TraceCheckUtils]: 11: Hoare triple {1339#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {1343#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:19,553 INFO L273 TraceCheckUtils]: 12: Hoare triple {1343#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1343#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:19,554 INFO L273 TraceCheckUtils]: 13: Hoare triple {1343#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume true; {1343#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:19,554 INFO L273 TraceCheckUtils]: 14: Hoare triple {1343#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {1343#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:19,555 INFO L273 TraceCheckUtils]: 15: Hoare triple {1343#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} ~i~0 := 0bv32; {1356#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:19,556 INFO L273 TraceCheckUtils]: 16: Hoare triple {1356#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume true; {1356#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:19,557 INFO L273 TraceCheckUtils]: 17: Hoare triple {1356#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {1356#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:19,559 INFO L273 TraceCheckUtils]: 18: Hoare triple {1356#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {1366#|main_#t~short6|} is VALID [2018-11-14 17:56:19,560 INFO L256 TraceCheckUtils]: 19: Hoare triple {1366#|main_#t~short6|} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {1370#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-14 17:56:19,563 INFO L273 TraceCheckUtils]: 20: Hoare triple {1370#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {1374#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-14 17:56:19,570 INFO L273 TraceCheckUtils]: 21: Hoare triple {1374#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume ~cond == 0bv32; {1303#false} is VALID [2018-11-14 17:56:19,571 INFO L273 TraceCheckUtils]: 22: Hoare triple {1303#false} assume !false; {1303#false} is VALID [2018-11-14 17:56:19,573 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:19,573 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-14 17:56:19,737 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 13 [2018-11-14 17:56:19,771 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 3 [2018-11-14 17:56:19,773 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:56:19,776 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:19,779 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:19,780 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:15, output treesize:5 [2018-11-14 17:56:19,784 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:56:19,820 INFO L273 TraceCheckUtils]: 22: Hoare triple {1303#false} assume !false; {1303#false} is VALID [2018-11-14 17:56:19,821 INFO L273 TraceCheckUtils]: 21: Hoare triple {1384#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} assume ~cond == 0bv32; {1303#false} is VALID [2018-11-14 17:56:19,823 INFO L273 TraceCheckUtils]: 20: Hoare triple {1388#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} ~cond := #in~cond; {1384#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} is VALID [2018-11-14 17:56:19,824 INFO L256 TraceCheckUtils]: 19: Hoare triple {1366#|main_#t~short6|} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {1388#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-14 17:56:19,825 INFO L273 TraceCheckUtils]: 18: Hoare triple {1395#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {1366#|main_#t~short6|} is VALID [2018-11-14 17:56:19,825 INFO L273 TraceCheckUtils]: 17: Hoare triple {1395#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {1395#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-14 17:56:19,832 INFO L273 TraceCheckUtils]: 16: Hoare triple {1395#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume true; {1395#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-14 17:56:19,832 INFO L273 TraceCheckUtils]: 15: Hoare triple {1405#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|))} ~i~0 := 0bv32; {1395#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-14 17:56:19,833 INFO L273 TraceCheckUtils]: 14: Hoare triple {1405#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {1405#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|))} is VALID [2018-11-14 17:56:19,833 INFO L273 TraceCheckUtils]: 13: Hoare triple {1405#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|))} assume true; {1405#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|))} is VALID [2018-11-14 17:56:19,834 INFO L273 TraceCheckUtils]: 12: Hoare triple {1405#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1405#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|))} is VALID [2018-11-14 17:56:19,836 INFO L273 TraceCheckUtils]: 11: Hoare triple {1405#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {1405#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|))} is VALID [2018-11-14 17:56:19,837 INFO L273 TraceCheckUtils]: 10: Hoare triple {1421#(= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0))} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {1405#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|))} is VALID [2018-11-14 17:56:19,837 INFO L273 TraceCheckUtils]: 9: Hoare triple {1421#(= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {1421#(= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0))} is VALID [2018-11-14 17:56:19,838 INFO L273 TraceCheckUtils]: 8: Hoare triple {1421#(= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0))} assume true; {1421#(= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0))} is VALID [2018-11-14 17:56:19,838 INFO L273 TraceCheckUtils]: 7: Hoare triple {1302#true} assume !(~bvsrem32(~CELLCOUNT~0, 2bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 2bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {1421#(= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0))} is VALID [2018-11-14 17:56:19,838 INFO L273 TraceCheckUtils]: 6: Hoare triple {1302#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {1302#true} is VALID [2018-11-14 17:56:19,839 INFO L273 TraceCheckUtils]: 5: Hoare triple {1302#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1302#true} is VALID [2018-11-14 17:56:19,839 INFO L256 TraceCheckUtils]: 4: Hoare triple {1302#true} call #t~ret7 := main(); {1302#true} is VALID [2018-11-14 17:56:19,839 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1302#true} {1302#true} #79#return; {1302#true} is VALID [2018-11-14 17:56:19,840 INFO L273 TraceCheckUtils]: 2: Hoare triple {1302#true} assume true; {1302#true} is VALID [2018-11-14 17:56:19,840 INFO L273 TraceCheckUtils]: 1: Hoare triple {1302#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1302#true} is VALID [2018-11-14 17:56:19,840 INFO L256 TraceCheckUtils]: 0: Hoare triple {1302#true} call ULTIMATE.init(); {1302#true} is VALID [2018-11-14 17:56:19,842 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:19,843 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-14 17:56:19,843 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 8] total 15 [2018-11-14 17:56:19,844 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 23 [2018-11-14 17:56:19,844 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:56:19,845 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 15 states. [2018-11-14 17:56:20,045 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 39 edges. 39 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:20,045 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-11-14 17:56:20,045 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-11-14 17:56:20,046 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=169, Unknown=0, NotChecked=0, Total=210 [2018-11-14 17:56:20,046 INFO L87 Difference]: Start difference. First operand 54 states and 67 transitions. Second operand 15 states. [2018-11-14 17:56:23,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:23,544 INFO L93 Difference]: Finished difference Result 119 states and 155 transitions. [2018-11-14 17:56:23,544 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-11-14 17:56:23,544 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 23 [2018-11-14 17:56:23,545 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:56:23,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2018-11-14 17:56:23,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 114 transitions. [2018-11-14 17:56:23,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2018-11-14 17:56:23,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 114 transitions. [2018-11-14 17:56:23,554 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 20 states and 114 transitions. [2018-11-14 17:56:23,898 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 114 edges. 114 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:23,902 INFO L225 Difference]: With dead ends: 119 [2018-11-14 17:56:23,903 INFO L226 Difference]: Without dead ends: 117 [2018-11-14 17:56:23,903 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 31 SyntacticMatches, 1 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 108 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=141, Invalid=509, Unknown=0, NotChecked=0, Total=650 [2018-11-14 17:56:23,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states. [2018-11-14 17:56:24,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 79. [2018-11-14 17:56:24,035 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:56:24,036 INFO L82 GeneralOperation]: Start isEquivalent. First operand 117 states. Second operand 79 states. [2018-11-14 17:56:24,036 INFO L74 IsIncluded]: Start isIncluded. First operand 117 states. Second operand 79 states. [2018-11-14 17:56:24,036 INFO L87 Difference]: Start difference. First operand 117 states. Second operand 79 states. [2018-11-14 17:56:24,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:24,043 INFO L93 Difference]: Finished difference Result 117 states and 153 transitions. [2018-11-14 17:56:24,043 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 153 transitions. [2018-11-14 17:56:24,044 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:24,045 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:24,045 INFO L74 IsIncluded]: Start isIncluded. First operand 79 states. Second operand 117 states. [2018-11-14 17:56:24,045 INFO L87 Difference]: Start difference. First operand 79 states. Second operand 117 states. [2018-11-14 17:56:24,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:24,051 INFO L93 Difference]: Finished difference Result 117 states and 153 transitions. [2018-11-14 17:56:24,051 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 153 transitions. [2018-11-14 17:56:24,052 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:24,053 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:24,053 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:56:24,053 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:56:24,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79 states. [2018-11-14 17:56:24,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 103 transitions. [2018-11-14 17:56:24,056 INFO L78 Accepts]: Start accepts. Automaton has 79 states and 103 transitions. Word has length 23 [2018-11-14 17:56:24,057 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:56:24,057 INFO L480 AbstractCegarLoop]: Abstraction has 79 states and 103 transitions. [2018-11-14 17:56:24,057 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-11-14 17:56:24,057 INFO L276 IsEmpty]: Start isEmpty. Operand 79 states and 103 transitions. [2018-11-14 17:56:24,058 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-11-14 17:56:24,058 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:56:24,058 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:56:24,058 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:56:24,059 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:56:24,059 INFO L82 PathProgramCache]: Analyzing trace with hash 1367021017, now seen corresponding path program 1 times [2018-11-14 17:56:24,059 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:56:24,059 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:56:24,087 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 17:56:24,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:24,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:24,124 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:56:24,166 INFO L256 TraceCheckUtils]: 0: Hoare triple {1963#true} call ULTIMATE.init(); {1963#true} is VALID [2018-11-14 17:56:24,167 INFO L273 TraceCheckUtils]: 1: Hoare triple {1963#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1963#true} is VALID [2018-11-14 17:56:24,167 INFO L273 TraceCheckUtils]: 2: Hoare triple {1963#true} assume true; {1963#true} is VALID [2018-11-14 17:56:24,167 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1963#true} {1963#true} #79#return; {1963#true} is VALID [2018-11-14 17:56:24,168 INFO L256 TraceCheckUtils]: 4: Hoare triple {1963#true} call #t~ret7 := main(); {1963#true} is VALID [2018-11-14 17:56:24,168 INFO L273 TraceCheckUtils]: 5: Hoare triple {1963#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1963#true} is VALID [2018-11-14 17:56:24,168 INFO L273 TraceCheckUtils]: 6: Hoare triple {1963#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {1963#true} is VALID [2018-11-14 17:56:24,168 INFO L273 TraceCheckUtils]: 7: Hoare triple {1963#true} assume !(~bvsrem32(~CELLCOUNT~0, 2bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 2bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {1963#true} is VALID [2018-11-14 17:56:24,168 INFO L273 TraceCheckUtils]: 8: Hoare triple {1963#true} assume true; {1963#true} is VALID [2018-11-14 17:56:24,168 INFO L273 TraceCheckUtils]: 9: Hoare triple {1963#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {1963#true} is VALID [2018-11-14 17:56:24,169 INFO L273 TraceCheckUtils]: 10: Hoare triple {1963#true} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {1998#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} is VALID [2018-11-14 17:56:24,169 INFO L273 TraceCheckUtils]: 11: Hoare triple {1998#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} assume ~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL1~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {1998#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} is VALID [2018-11-14 17:56:24,174 INFO L273 TraceCheckUtils]: 12: Hoare triple {1998#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1998#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} is VALID [2018-11-14 17:56:24,192 INFO L273 TraceCheckUtils]: 13: Hoare triple {1998#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} assume true; {1998#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} is VALID [2018-11-14 17:56:24,201 INFO L273 TraceCheckUtils]: 14: Hoare triple {1998#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {1998#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} is VALID [2018-11-14 17:56:24,213 INFO L273 TraceCheckUtils]: 15: Hoare triple {1998#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {1964#false} is VALID [2018-11-14 17:56:24,214 INFO L273 TraceCheckUtils]: 16: Hoare triple {1964#false} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {1964#false} is VALID [2018-11-14 17:56:24,214 INFO L273 TraceCheckUtils]: 17: Hoare triple {1964#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1964#false} is VALID [2018-11-14 17:56:24,214 INFO L273 TraceCheckUtils]: 18: Hoare triple {1964#false} assume true; {1964#false} is VALID [2018-11-14 17:56:24,215 INFO L273 TraceCheckUtils]: 19: Hoare triple {1964#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {1964#false} is VALID [2018-11-14 17:56:24,215 INFO L273 TraceCheckUtils]: 20: Hoare triple {1964#false} ~i~0 := 0bv32; {1964#false} is VALID [2018-11-14 17:56:24,215 INFO L273 TraceCheckUtils]: 21: Hoare triple {1964#false} assume true; {1964#false} is VALID [2018-11-14 17:56:24,215 INFO L273 TraceCheckUtils]: 22: Hoare triple {1964#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {1964#false} is VALID [2018-11-14 17:56:24,215 INFO L273 TraceCheckUtils]: 23: Hoare triple {1964#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {1964#false} is VALID [2018-11-14 17:56:24,216 INFO L256 TraceCheckUtils]: 24: Hoare triple {1964#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {1964#false} is VALID [2018-11-14 17:56:24,216 INFO L273 TraceCheckUtils]: 25: Hoare triple {1964#false} ~cond := #in~cond; {1964#false} is VALID [2018-11-14 17:56:24,216 INFO L273 TraceCheckUtils]: 26: Hoare triple {1964#false} assume ~cond == 0bv32; {1964#false} is VALID [2018-11-14 17:56:24,216 INFO L273 TraceCheckUtils]: 27: Hoare triple {1964#false} assume !false; {1964#false} is VALID [2018-11-14 17:56:24,217 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:24,217 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-14 17:56:24,219 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-14 17:56:24,219 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-14 17:56:24,220 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2018-11-14 17:56:24,220 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:56:24,220 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2018-11-14 17:56:24,304 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 28 edges. 28 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:24,305 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-14 17:56:24,305 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-14 17:56:24,305 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-14 17:56:24,305 INFO L87 Difference]: Start difference. First operand 79 states and 103 transitions. Second operand 3 states. [2018-11-14 17:56:24,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:24,764 INFO L93 Difference]: Finished difference Result 123 states and 160 transitions. [2018-11-14 17:56:24,764 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-14 17:56:24,764 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2018-11-14 17:56:24,765 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:56:24,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-14 17:56:24,766 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 69 transitions. [2018-11-14 17:56:24,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-14 17:56:24,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 69 transitions. [2018-11-14 17:56:24,768 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states and 69 transitions. [2018-11-14 17:56:24,947 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 69 edges. 69 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:24,950 INFO L225 Difference]: With dead ends: 123 [2018-11-14 17:56:24,950 INFO L226 Difference]: Without dead ends: 86 [2018-11-14 17:56:24,951 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 26 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-14 17:56:24,951 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86 states. [2018-11-14 17:56:25,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86 to 79. [2018-11-14 17:56:25,053 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:56:25,053 INFO L82 GeneralOperation]: Start isEquivalent. First operand 86 states. Second operand 79 states. [2018-11-14 17:56:25,053 INFO L74 IsIncluded]: Start isIncluded. First operand 86 states. Second operand 79 states. [2018-11-14 17:56:25,053 INFO L87 Difference]: Start difference. First operand 86 states. Second operand 79 states. [2018-11-14 17:56:25,057 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:25,057 INFO L93 Difference]: Finished difference Result 86 states and 110 transitions. [2018-11-14 17:56:25,057 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 110 transitions. [2018-11-14 17:56:25,058 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:25,058 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:25,058 INFO L74 IsIncluded]: Start isIncluded. First operand 79 states. Second operand 86 states. [2018-11-14 17:56:25,058 INFO L87 Difference]: Start difference. First operand 79 states. Second operand 86 states. [2018-11-14 17:56:25,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:25,062 INFO L93 Difference]: Finished difference Result 86 states and 110 transitions. [2018-11-14 17:56:25,062 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 110 transitions. [2018-11-14 17:56:25,063 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:25,063 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:25,063 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:56:25,063 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:56:25,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79 states. [2018-11-14 17:56:25,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 100 transitions. [2018-11-14 17:56:25,066 INFO L78 Accepts]: Start accepts. Automaton has 79 states and 100 transitions. Word has length 28 [2018-11-14 17:56:25,067 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:56:25,067 INFO L480 AbstractCegarLoop]: Abstraction has 79 states and 100 transitions. [2018-11-14 17:56:25,067 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-14 17:56:25,067 INFO L276 IsEmpty]: Start isEmpty. Operand 79 states and 100 transitions. [2018-11-14 17:56:25,068 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-11-14 17:56:25,068 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:56:25,068 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:56:25,068 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:56:25,068 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:56:25,069 INFO L82 PathProgramCache]: Analyzing trace with hash -1628665577, now seen corresponding path program 1 times [2018-11-14 17:56:25,069 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:56:25,069 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:56:25,095 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 17:56:25,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:25,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:25,129 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:56:25,175 INFO L256 TraceCheckUtils]: 0: Hoare triple {2477#true} call ULTIMATE.init(); {2477#true} is VALID [2018-11-14 17:56:25,176 INFO L273 TraceCheckUtils]: 1: Hoare triple {2477#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {2477#true} is VALID [2018-11-14 17:56:25,176 INFO L273 TraceCheckUtils]: 2: Hoare triple {2477#true} assume true; {2477#true} is VALID [2018-11-14 17:56:25,176 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2477#true} {2477#true} #79#return; {2477#true} is VALID [2018-11-14 17:56:25,177 INFO L256 TraceCheckUtils]: 4: Hoare triple {2477#true} call #t~ret7 := main(); {2477#true} is VALID [2018-11-14 17:56:25,177 INFO L273 TraceCheckUtils]: 5: Hoare triple {2477#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {2477#true} is VALID [2018-11-14 17:56:25,177 INFO L273 TraceCheckUtils]: 6: Hoare triple {2477#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {2477#true} is VALID [2018-11-14 17:56:25,177 INFO L273 TraceCheckUtils]: 7: Hoare triple {2477#true} assume !(~bvsrem32(~CELLCOUNT~0, 2bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 2bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {2477#true} is VALID [2018-11-14 17:56:25,178 INFO L273 TraceCheckUtils]: 8: Hoare triple {2477#true} assume true; {2477#true} is VALID [2018-11-14 17:56:25,178 INFO L273 TraceCheckUtils]: 9: Hoare triple {2477#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {2477#true} is VALID [2018-11-14 17:56:25,178 INFO L273 TraceCheckUtils]: 10: Hoare triple {2477#true} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {2512#(not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} is VALID [2018-11-14 17:56:25,179 INFO L273 TraceCheckUtils]: 11: Hoare triple {2512#(not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {2512#(not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} is VALID [2018-11-14 17:56:25,179 INFO L273 TraceCheckUtils]: 12: Hoare triple {2512#(not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {2512#(not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} is VALID [2018-11-14 17:56:25,179 INFO L273 TraceCheckUtils]: 13: Hoare triple {2512#(not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} assume true; {2512#(not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} is VALID [2018-11-14 17:56:25,180 INFO L273 TraceCheckUtils]: 14: Hoare triple {2512#(not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {2512#(not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} is VALID [2018-11-14 17:56:25,180 INFO L273 TraceCheckUtils]: 15: Hoare triple {2512#(not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {2478#false} is VALID [2018-11-14 17:56:25,180 INFO L273 TraceCheckUtils]: 16: Hoare triple {2478#false} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {2478#false} is VALID [2018-11-14 17:56:25,180 INFO L273 TraceCheckUtils]: 17: Hoare triple {2478#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {2478#false} is VALID [2018-11-14 17:56:25,180 INFO L273 TraceCheckUtils]: 18: Hoare triple {2478#false} assume true; {2478#false} is VALID [2018-11-14 17:56:25,181 INFO L273 TraceCheckUtils]: 19: Hoare triple {2478#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {2478#false} is VALID [2018-11-14 17:56:25,181 INFO L273 TraceCheckUtils]: 20: Hoare triple {2478#false} ~i~0 := 0bv32; {2478#false} is VALID [2018-11-14 17:56:25,181 INFO L273 TraceCheckUtils]: 21: Hoare triple {2478#false} assume true; {2478#false} is VALID [2018-11-14 17:56:25,181 INFO L273 TraceCheckUtils]: 22: Hoare triple {2478#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {2478#false} is VALID [2018-11-14 17:56:25,182 INFO L273 TraceCheckUtils]: 23: Hoare triple {2478#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {2478#false} is VALID [2018-11-14 17:56:25,182 INFO L256 TraceCheckUtils]: 24: Hoare triple {2478#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {2478#false} is VALID [2018-11-14 17:56:25,182 INFO L273 TraceCheckUtils]: 25: Hoare triple {2478#false} ~cond := #in~cond; {2478#false} is VALID [2018-11-14 17:56:25,182 INFO L273 TraceCheckUtils]: 26: Hoare triple {2478#false} assume ~cond == 0bv32; {2478#false} is VALID [2018-11-14 17:56:25,182 INFO L273 TraceCheckUtils]: 27: Hoare triple {2478#false} assume !false; {2478#false} is VALID [2018-11-14 17:56:25,183 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:25,183 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-14 17:56:25,189 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-14 17:56:25,189 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-14 17:56:25,189 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2018-11-14 17:56:25,189 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:56:25,189 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2018-11-14 17:56:25,260 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 28 edges. 28 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:25,260 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-14 17:56:25,260 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-14 17:56:25,260 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-14 17:56:25,261 INFO L87 Difference]: Start difference. First operand 79 states and 100 transitions. Second operand 3 states. [2018-11-14 17:56:25,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:25,831 INFO L93 Difference]: Finished difference Result 112 states and 139 transitions. [2018-11-14 17:56:25,831 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-14 17:56:25,832 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2018-11-14 17:56:25,832 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:56:25,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-14 17:56:25,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 68 transitions. [2018-11-14 17:56:25,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-14 17:56:25,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 68 transitions. [2018-11-14 17:56:25,835 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states and 68 transitions. [2018-11-14 17:56:25,995 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 68 edges. 68 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:25,997 INFO L225 Difference]: With dead ends: 112 [2018-11-14 17:56:25,997 INFO L226 Difference]: Without dead ends: 75 [2018-11-14 17:56:25,997 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 26 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-14 17:56:25,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states. [2018-11-14 17:56:26,225 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 64. [2018-11-14 17:56:26,225 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:56:26,225 INFO L82 GeneralOperation]: Start isEquivalent. First operand 75 states. Second operand 64 states. [2018-11-14 17:56:26,225 INFO L74 IsIncluded]: Start isIncluded. First operand 75 states. Second operand 64 states. [2018-11-14 17:56:26,226 INFO L87 Difference]: Start difference. First operand 75 states. Second operand 64 states. [2018-11-14 17:56:26,228 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:26,228 INFO L93 Difference]: Finished difference Result 75 states and 92 transitions. [2018-11-14 17:56:26,228 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 92 transitions. [2018-11-14 17:56:26,230 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:26,230 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:26,230 INFO L74 IsIncluded]: Start isIncluded. First operand 64 states. Second operand 75 states. [2018-11-14 17:56:26,230 INFO L87 Difference]: Start difference. First operand 64 states. Second operand 75 states. [2018-11-14 17:56:26,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:26,233 INFO L93 Difference]: Finished difference Result 75 states and 92 transitions. [2018-11-14 17:56:26,234 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 92 transitions. [2018-11-14 17:56:26,234 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:26,234 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:26,234 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:56:26,234 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:56:26,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64 states. [2018-11-14 17:56:26,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 77 transitions. [2018-11-14 17:56:26,237 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 77 transitions. Word has length 28 [2018-11-14 17:56:26,237 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:56:26,237 INFO L480 AbstractCegarLoop]: Abstraction has 64 states and 77 transitions. [2018-11-14 17:56:26,237 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-14 17:56:26,237 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 77 transitions. [2018-11-14 17:56:26,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-11-14 17:56:26,245 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:56:26,245 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:56:26,245 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:56:26,245 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:56:26,245 INFO L82 PathProgramCache]: Analyzing trace with hash -614577211, now seen corresponding path program 1 times [2018-11-14 17:56:26,246 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:56:26,246 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:56:26,265 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 17:56:26,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:26,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:26,325 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:56:26,382 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-11-14 17:56:26,393 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-14 17:56:26,395 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:56:26,397 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:26,407 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:26,408 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:17, output treesize:13 [2018-11-14 17:56:26,664 INFO L256 TraceCheckUtils]: 0: Hoare triple {2938#true} call ULTIMATE.init(); {2938#true} is VALID [2018-11-14 17:56:26,664 INFO L273 TraceCheckUtils]: 1: Hoare triple {2938#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {2938#true} is VALID [2018-11-14 17:56:26,665 INFO L273 TraceCheckUtils]: 2: Hoare triple {2938#true} assume true; {2938#true} is VALID [2018-11-14 17:56:26,665 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2938#true} {2938#true} #79#return; {2938#true} is VALID [2018-11-14 17:56:26,665 INFO L256 TraceCheckUtils]: 4: Hoare triple {2938#true} call #t~ret7 := main(); {2938#true} is VALID [2018-11-14 17:56:26,665 INFO L273 TraceCheckUtils]: 5: Hoare triple {2938#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {2938#true} is VALID [2018-11-14 17:56:26,672 INFO L273 TraceCheckUtils]: 6: Hoare triple {2938#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {2961#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-14 17:56:26,673 INFO L273 TraceCheckUtils]: 7: Hoare triple {2961#(= |main_~#volArray~0.offset| (_ bv0 32))} assume !(~bvsrem32(~CELLCOUNT~0, 2bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 2bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {2965#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:26,673 INFO L273 TraceCheckUtils]: 8: Hoare triple {2965#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {2965#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:26,674 INFO L273 TraceCheckUtils]: 9: Hoare triple {2965#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {2965#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:26,674 INFO L273 TraceCheckUtils]: 10: Hoare triple {2965#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {2965#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:26,675 INFO L273 TraceCheckUtils]: 11: Hoare triple {2965#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {2978#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:26,676 INFO L273 TraceCheckUtils]: 12: Hoare triple {2978#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {2978#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:26,677 INFO L273 TraceCheckUtils]: 13: Hoare triple {2978#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume true; {2978#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:26,677 INFO L273 TraceCheckUtils]: 14: Hoare triple {2978#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {2978#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:26,678 INFO L273 TraceCheckUtils]: 15: Hoare triple {2978#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} ~i~0 := 0bv32; {2991#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:26,679 INFO L273 TraceCheckUtils]: 16: Hoare triple {2991#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume true; {2991#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:26,680 INFO L273 TraceCheckUtils]: 17: Hoare triple {2991#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {2991#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:26,681 INFO L273 TraceCheckUtils]: 18: Hoare triple {2991#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume #t~short6; {2991#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:26,683 INFO L256 TraceCheckUtils]: 19: Hoare triple {2991#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3004#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))))} is VALID [2018-11-14 17:56:26,684 INFO L273 TraceCheckUtils]: 20: Hoare triple {3004#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))))} ~cond := #in~cond; {3004#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))))} is VALID [2018-11-14 17:56:26,685 INFO L273 TraceCheckUtils]: 21: Hoare triple {3004#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))))} assume !(~cond == 0bv32); {3004#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))))} is VALID [2018-11-14 17:56:26,693 INFO L273 TraceCheckUtils]: 22: Hoare triple {3004#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))))} assume true; {3004#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))))} is VALID [2018-11-14 17:56:26,694 INFO L268 TraceCheckUtils]: 23: Hoare quadruple {3004#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))))} {2991#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #83#return; {2991#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:26,695 INFO L273 TraceCheckUtils]: 24: Hoare triple {2991#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {2991#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:26,695 INFO L273 TraceCheckUtils]: 25: Hoare triple {2991#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {3023#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:26,696 INFO L273 TraceCheckUtils]: 26: Hoare triple {3023#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {3023#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:26,697 INFO L273 TraceCheckUtils]: 27: Hoare triple {3023#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3023#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:26,697 INFO L273 TraceCheckUtils]: 28: Hoare triple {3023#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {3033#|main_#t~short6|} is VALID [2018-11-14 17:56:26,698 INFO L256 TraceCheckUtils]: 29: Hoare triple {3033#|main_#t~short6|} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3037#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-14 17:56:26,699 INFO L273 TraceCheckUtils]: 30: Hoare triple {3037#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {3041#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-14 17:56:26,700 INFO L273 TraceCheckUtils]: 31: Hoare triple {3041#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume ~cond == 0bv32; {2939#false} is VALID [2018-11-14 17:56:26,700 INFO L273 TraceCheckUtils]: 32: Hoare triple {2939#false} assume !false; {2939#false} is VALID [2018-11-14 17:56:26,703 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:26,703 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-14 17:56:27,063 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 15 [2018-11-14 17:56:27,104 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 3 [2018-11-14 17:56:27,105 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:56:27,108 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:27,110 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:27,111 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:17, output treesize:5 [2018-11-14 17:56:27,117 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:56:27,160 INFO L273 TraceCheckUtils]: 32: Hoare triple {2939#false} assume !false; {2939#false} is VALID [2018-11-14 17:56:27,161 INFO L273 TraceCheckUtils]: 31: Hoare triple {3051#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} assume ~cond == 0bv32; {2939#false} is VALID [2018-11-14 17:56:27,161 INFO L273 TraceCheckUtils]: 30: Hoare triple {3055#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} ~cond := #in~cond; {3051#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} is VALID [2018-11-14 17:56:27,162 INFO L256 TraceCheckUtils]: 29: Hoare triple {3033#|main_#t~short6|} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3055#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-14 17:56:27,163 INFO L273 TraceCheckUtils]: 28: Hoare triple {3062#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {3033#|main_#t~short6|} is VALID [2018-11-14 17:56:27,164 INFO L273 TraceCheckUtils]: 27: Hoare triple {3062#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3062#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-14 17:56:27,164 INFO L273 TraceCheckUtils]: 26: Hoare triple {3062#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume true; {3062#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-14 17:56:27,374 INFO L273 TraceCheckUtils]: 25: Hoare triple {3072#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {3062#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-14 17:56:27,374 INFO L273 TraceCheckUtils]: 24: Hoare triple {3072#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {3072#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-14 17:56:27,375 INFO L268 TraceCheckUtils]: 23: Hoare quadruple {2938#true} {3072#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} #83#return; {3072#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-14 17:56:27,376 INFO L273 TraceCheckUtils]: 22: Hoare triple {2938#true} assume true; {2938#true} is VALID [2018-11-14 17:56:27,376 INFO L273 TraceCheckUtils]: 21: Hoare triple {2938#true} assume !(~cond == 0bv32); {2938#true} is VALID [2018-11-14 17:56:27,376 INFO L273 TraceCheckUtils]: 20: Hoare triple {2938#true} ~cond := #in~cond; {2938#true} is VALID [2018-11-14 17:56:27,376 INFO L256 TraceCheckUtils]: 19: Hoare triple {3072#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {2938#true} is VALID [2018-11-14 17:56:27,377 INFO L273 TraceCheckUtils]: 18: Hoare triple {3072#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} assume #t~short6; {3072#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-14 17:56:27,378 INFO L273 TraceCheckUtils]: 17: Hoare triple {3072#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3072#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-14 17:56:27,381 INFO L273 TraceCheckUtils]: 16: Hoare triple {3072#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} assume true; {3072#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-14 17:56:27,382 INFO L273 TraceCheckUtils]: 15: Hoare triple {3103#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} ~i~0 := 0bv32; {3072#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-14 17:56:27,383 INFO L273 TraceCheckUtils]: 14: Hoare triple {3103#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {3103#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-14 17:56:27,384 INFO L273 TraceCheckUtils]: 13: Hoare triple {3103#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} assume true; {3103#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-14 17:56:27,387 INFO L273 TraceCheckUtils]: 12: Hoare triple {3103#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3103#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-14 17:56:27,391 INFO L273 TraceCheckUtils]: 11: Hoare triple {3116#(= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {3103#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-14 17:56:27,392 INFO L273 TraceCheckUtils]: 10: Hoare triple {3116#(= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {3116#(= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0))} is VALID [2018-11-14 17:56:27,392 INFO L273 TraceCheckUtils]: 9: Hoare triple {3116#(= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {3116#(= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0))} is VALID [2018-11-14 17:56:27,393 INFO L273 TraceCheckUtils]: 8: Hoare triple {3116#(= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0))} assume true; {3116#(= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0))} is VALID [2018-11-14 17:56:27,393 INFO L273 TraceCheckUtils]: 7: Hoare triple {2938#true} assume !(~bvsrem32(~CELLCOUNT~0, 2bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 2bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {3116#(= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0))} is VALID [2018-11-14 17:56:27,394 INFO L273 TraceCheckUtils]: 6: Hoare triple {2938#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {2938#true} is VALID [2018-11-14 17:56:27,394 INFO L273 TraceCheckUtils]: 5: Hoare triple {2938#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {2938#true} is VALID [2018-11-14 17:56:27,394 INFO L256 TraceCheckUtils]: 4: Hoare triple {2938#true} call #t~ret7 := main(); {2938#true} is VALID [2018-11-14 17:56:27,394 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2938#true} {2938#true} #79#return; {2938#true} is VALID [2018-11-14 17:56:27,395 INFO L273 TraceCheckUtils]: 2: Hoare triple {2938#true} assume true; {2938#true} is VALID [2018-11-14 17:56:27,395 INFO L273 TraceCheckUtils]: 1: Hoare triple {2938#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {2938#true} is VALID [2018-11-14 17:56:27,395 INFO L256 TraceCheckUtils]: 0: Hoare triple {2938#true} call ULTIMATE.init(); {2938#true} is VALID [2018-11-14 17:56:27,398 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:27,401 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-14 17:56:27,401 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 9] total 17 [2018-11-14 17:56:27,403 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 33 [2018-11-14 17:56:27,403 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:56:27,403 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 17 states. [2018-11-14 17:56:27,859 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 59 edges. 59 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:27,859 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-11-14 17:56:27,860 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-11-14 17:56:27,860 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=222, Unknown=0, NotChecked=0, Total=272 [2018-11-14 17:56:27,860 INFO L87 Difference]: Start difference. First operand 64 states and 77 transitions. Second operand 17 states. [2018-11-14 17:56:33,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:33,217 INFO L93 Difference]: Finished difference Result 122 states and 141 transitions. [2018-11-14 17:56:33,218 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-11-14 17:56:33,218 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 33 [2018-11-14 17:56:33,218 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:56:33,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17 states. [2018-11-14 17:56:33,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 93 transitions. [2018-11-14 17:56:33,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17 states. [2018-11-14 17:56:33,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 93 transitions. [2018-11-14 17:56:33,222 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 18 states and 93 transitions. [2018-11-14 17:56:33,429 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 93 edges. 93 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:33,432 INFO L225 Difference]: With dead ends: 122 [2018-11-14 17:56:33,432 INFO L226 Difference]: Without dead ends: 120 [2018-11-14 17:56:33,433 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 74 GetRequests, 50 SyntacticMatches, 1 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 112 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=111, Invalid=489, Unknown=0, NotChecked=0, Total=600 [2018-11-14 17:56:33,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states. [2018-11-14 17:56:33,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 102. [2018-11-14 17:56:33,716 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:56:33,716 INFO L82 GeneralOperation]: Start isEquivalent. First operand 120 states. Second operand 102 states. [2018-11-14 17:56:33,716 INFO L74 IsIncluded]: Start isIncluded. First operand 120 states. Second operand 102 states. [2018-11-14 17:56:33,716 INFO L87 Difference]: Start difference. First operand 120 states. Second operand 102 states. [2018-11-14 17:56:33,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:33,721 INFO L93 Difference]: Finished difference Result 120 states and 139 transitions. [2018-11-14 17:56:33,721 INFO L276 IsEmpty]: Start isEmpty. Operand 120 states and 139 transitions. [2018-11-14 17:56:33,721 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:33,721 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:33,722 INFO L74 IsIncluded]: Start isIncluded. First operand 102 states. Second operand 120 states. [2018-11-14 17:56:33,722 INFO L87 Difference]: Start difference. First operand 102 states. Second operand 120 states. [2018-11-14 17:56:33,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:33,726 INFO L93 Difference]: Finished difference Result 120 states and 139 transitions. [2018-11-14 17:56:33,726 INFO L276 IsEmpty]: Start isEmpty. Operand 120 states and 139 transitions. [2018-11-14 17:56:33,727 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:33,727 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:33,727 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:56:33,727 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:56:33,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-11-14 17:56:33,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 120 transitions. [2018-11-14 17:56:33,731 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 120 transitions. Word has length 33 [2018-11-14 17:56:33,731 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:56:33,731 INFO L480 AbstractCegarLoop]: Abstraction has 102 states and 120 transitions. [2018-11-14 17:56:33,732 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-11-14 17:56:33,732 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 120 transitions. [2018-11-14 17:56:33,732 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-11-14 17:56:33,733 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:56:33,733 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:56:33,733 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:56:33,733 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:56:33,733 INFO L82 PathProgramCache]: Analyzing trace with hash -833431929, now seen corresponding path program 1 times [2018-11-14 17:56:33,734 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:56:33,734 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:56:33,754 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 17:56:33,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:33,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:33,821 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:56:33,958 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-11-14 17:56:33,964 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-14 17:56:33,966 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:56:33,969 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:33,982 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:33,982 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:23, output treesize:16 [2018-11-14 17:56:34,174 INFO L256 TraceCheckUtils]: 0: Hoare triple {3698#true} call ULTIMATE.init(); {3698#true} is VALID [2018-11-14 17:56:34,175 INFO L273 TraceCheckUtils]: 1: Hoare triple {3698#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {3698#true} is VALID [2018-11-14 17:56:34,175 INFO L273 TraceCheckUtils]: 2: Hoare triple {3698#true} assume true; {3698#true} is VALID [2018-11-14 17:56:34,175 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {3698#true} {3698#true} #79#return; {3698#true} is VALID [2018-11-14 17:56:34,175 INFO L256 TraceCheckUtils]: 4: Hoare triple {3698#true} call #t~ret7 := main(); {3698#true} is VALID [2018-11-14 17:56:34,175 INFO L273 TraceCheckUtils]: 5: Hoare triple {3698#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {3698#true} is VALID [2018-11-14 17:56:34,176 INFO L273 TraceCheckUtils]: 6: Hoare triple {3698#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {3721#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:34,176 INFO L273 TraceCheckUtils]: 7: Hoare triple {3721#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !(~bvsrem32(~CELLCOUNT~0, 2bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 2bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {3725#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:34,177 INFO L273 TraceCheckUtils]: 8: Hoare triple {3725#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {3725#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:34,177 INFO L273 TraceCheckUtils]: 9: Hoare triple {3725#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {3725#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:34,178 INFO L273 TraceCheckUtils]: 10: Hoare triple {3725#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {3735#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:34,179 INFO L273 TraceCheckUtils]: 11: Hoare triple {3735#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL1~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {3739#(and (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:34,180 INFO L273 TraceCheckUtils]: 12: Hoare triple {3739#(and (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3739#(and (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:34,180 INFO L273 TraceCheckUtils]: 13: Hoare triple {3739#(and (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)))} assume true; {3739#(and (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:34,181 INFO L273 TraceCheckUtils]: 14: Hoare triple {3739#(and (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {3739#(and (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:34,192 INFO L273 TraceCheckUtils]: 15: Hoare triple {3739#(and (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)))} ~i~0 := 0bv32; {3752#(and (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:34,192 INFO L273 TraceCheckUtils]: 16: Hoare triple {3752#(and (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)))} assume true; {3752#(and (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:34,193 INFO L273 TraceCheckUtils]: 17: Hoare triple {3752#(and (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3752#(and (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:34,194 INFO L273 TraceCheckUtils]: 18: Hoare triple {3752#(and (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)))} assume #t~short6; {3752#(and (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:34,195 INFO L256 TraceCheckUtils]: 19: Hoare triple {3752#(and (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3765#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))))} is VALID [2018-11-14 17:56:34,196 INFO L273 TraceCheckUtils]: 20: Hoare triple {3765#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))))} ~cond := #in~cond; {3765#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))))} is VALID [2018-11-14 17:56:34,196 INFO L273 TraceCheckUtils]: 21: Hoare triple {3765#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))))} assume !(~cond == 0bv32); {3765#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))))} is VALID [2018-11-14 17:56:34,196 INFO L273 TraceCheckUtils]: 22: Hoare triple {3765#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))))} assume true; {3765#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))))} is VALID [2018-11-14 17:56:34,197 INFO L268 TraceCheckUtils]: 23: Hoare quadruple {3765#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))))} {3752#(and (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)))} #83#return; {3752#(and (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:34,198 INFO L273 TraceCheckUtils]: 24: Hoare triple {3752#(and (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)))} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {3752#(and (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:34,198 INFO L273 TraceCheckUtils]: 25: Hoare triple {3752#(and (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {3784#(and (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:34,199 INFO L273 TraceCheckUtils]: 26: Hoare triple {3784#(and (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {3784#(and (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:34,200 INFO L273 TraceCheckUtils]: 27: Hoare triple {3784#(and (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967295 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3791#|main_#t~short6|} is VALID [2018-11-14 17:56:34,201 INFO L273 TraceCheckUtils]: 28: Hoare triple {3791#|main_#t~short6|} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {3699#false} is VALID [2018-11-14 17:56:34,201 INFO L256 TraceCheckUtils]: 29: Hoare triple {3699#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3699#false} is VALID [2018-11-14 17:56:34,202 INFO L273 TraceCheckUtils]: 30: Hoare triple {3699#false} ~cond := #in~cond; {3699#false} is VALID [2018-11-14 17:56:34,202 INFO L273 TraceCheckUtils]: 31: Hoare triple {3699#false} assume ~cond == 0bv32; {3699#false} is VALID [2018-11-14 17:56:34,202 INFO L273 TraceCheckUtils]: 32: Hoare triple {3699#false} assume !false; {3699#false} is VALID [2018-11-14 17:56:34,206 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:34,206 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-14 17:56:34,479 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 15 [2018-11-14 17:56:34,540 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 3 [2018-11-14 17:56:34,543 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 17:56:34,560 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 17:56:34,574 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 17:56:34,575 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:22, output treesize:13 [2018-11-14 17:56:34,582 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:56:34,748 INFO L273 TraceCheckUtils]: 32: Hoare triple {3699#false} assume !false; {3699#false} is VALID [2018-11-14 17:56:34,748 INFO L273 TraceCheckUtils]: 31: Hoare triple {3699#false} assume ~cond == 0bv32; {3699#false} is VALID [2018-11-14 17:56:34,748 INFO L273 TraceCheckUtils]: 30: Hoare triple {3699#false} ~cond := #in~cond; {3699#false} is VALID [2018-11-14 17:56:34,749 INFO L256 TraceCheckUtils]: 29: Hoare triple {3699#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3699#false} is VALID [2018-11-14 17:56:34,749 INFO L273 TraceCheckUtils]: 28: Hoare triple {3791#|main_#t~short6|} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {3699#false} is VALID [2018-11-14 17:56:34,750 INFO L273 TraceCheckUtils]: 27: Hoare triple {3822#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3791#|main_#t~short6|} is VALID [2018-11-14 17:56:34,750 INFO L273 TraceCheckUtils]: 26: Hoare triple {3822#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume true; {3822#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is VALID [2018-11-14 17:56:36,773 INFO L273 TraceCheckUtils]: 25: Hoare triple {3829#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {3822#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is UNKNOWN [2018-11-14 17:56:36,774 INFO L273 TraceCheckUtils]: 24: Hoare triple {3829#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {3829#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:56:36,775 INFO L268 TraceCheckUtils]: 23: Hoare quadruple {3698#true} {3829#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} #83#return; {3829#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:56:36,775 INFO L273 TraceCheckUtils]: 22: Hoare triple {3698#true} assume true; {3698#true} is VALID [2018-11-14 17:56:36,776 INFO L273 TraceCheckUtils]: 21: Hoare triple {3698#true} assume !(~cond == 0bv32); {3698#true} is VALID [2018-11-14 17:56:36,776 INFO L273 TraceCheckUtils]: 20: Hoare triple {3698#true} ~cond := #in~cond; {3698#true} is VALID [2018-11-14 17:56:36,776 INFO L256 TraceCheckUtils]: 19: Hoare triple {3829#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3698#true} is VALID [2018-11-14 17:56:36,795 INFO L273 TraceCheckUtils]: 18: Hoare triple {3829#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} assume #t~short6; {3829#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:56:36,808 INFO L273 TraceCheckUtils]: 17: Hoare triple {3829#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3829#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:56:36,821 INFO L273 TraceCheckUtils]: 16: Hoare triple {3829#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} assume true; {3829#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:56:36,828 INFO L273 TraceCheckUtils]: 15: Hoare triple {3860#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} ~i~0 := 0bv32; {3829#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:56:36,828 INFO L273 TraceCheckUtils]: 14: Hoare triple {3860#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {3860#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:56:36,829 INFO L273 TraceCheckUtils]: 13: Hoare triple {3860#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume true; {3860#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:56:36,829 INFO L273 TraceCheckUtils]: 12: Hoare triple {3860#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3860#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:56:36,854 INFO L273 TraceCheckUtils]: 11: Hoare triple {3873#(or (forall ((v_arrayElimCell_14 (_ BitVec 32))) (bvsge v_arrayElimCell_14 main_~MINVAL~0)) (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)))} assume ~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL1~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {3860#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:56:36,878 INFO L273 TraceCheckUtils]: 10: Hoare triple {3877#(or (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)) (forall ((v_arrayElimCell_14 (_ BitVec 32)) (main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_14 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)))))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {3873#(or (forall ((v_arrayElimCell_14 (_ BitVec 32))) (bvsge v_arrayElimCell_14 main_~MINVAL~0)) (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)))} is VALID [2018-11-14 17:56:36,878 INFO L273 TraceCheckUtils]: 9: Hoare triple {3877#(or (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)) (forall ((v_arrayElimCell_14 (_ BitVec 32)) (main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_14 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)))))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {3877#(or (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)) (forall ((v_arrayElimCell_14 (_ BitVec 32)) (main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_14 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)))))} is VALID [2018-11-14 17:56:36,879 INFO L273 TraceCheckUtils]: 8: Hoare triple {3877#(or (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)) (forall ((v_arrayElimCell_14 (_ BitVec 32)) (main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_14 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)))))} assume true; {3877#(or (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)) (forall ((v_arrayElimCell_14 (_ BitVec 32)) (main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_14 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)))))} is VALID [2018-11-14 17:56:36,879 INFO L273 TraceCheckUtils]: 7: Hoare triple {3698#true} assume !(~bvsrem32(~CELLCOUNT~0, 2bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 2bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {3877#(or (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)) (forall ((v_arrayElimCell_14 (_ BitVec 32)) (main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_14 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)))))} is VALID [2018-11-14 17:56:36,880 INFO L273 TraceCheckUtils]: 6: Hoare triple {3698#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {3698#true} is VALID [2018-11-14 17:56:36,880 INFO L273 TraceCheckUtils]: 5: Hoare triple {3698#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {3698#true} is VALID [2018-11-14 17:56:36,880 INFO L256 TraceCheckUtils]: 4: Hoare triple {3698#true} call #t~ret7 := main(); {3698#true} is VALID [2018-11-14 17:56:36,880 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {3698#true} {3698#true} #79#return; {3698#true} is VALID [2018-11-14 17:56:36,880 INFO L273 TraceCheckUtils]: 2: Hoare triple {3698#true} assume true; {3698#true} is VALID [2018-11-14 17:56:36,880 INFO L273 TraceCheckUtils]: 1: Hoare triple {3698#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {3698#true} is VALID [2018-11-14 17:56:36,881 INFO L256 TraceCheckUtils]: 0: Hoare triple {3698#true} call ULTIMATE.init(); {3698#true} is VALID [2018-11-14 17:56:36,883 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:36,885 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-14 17:56:36,885 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 8] total 15 [2018-11-14 17:56:36,886 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 33 [2018-11-14 17:56:36,886 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:56:36,886 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 15 states. [2018-11-14 17:56:39,120 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 55 edges. 54 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:39,120 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-11-14 17:56:39,120 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-11-14 17:56:39,120 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=166, Unknown=0, NotChecked=0, Total=210 [2018-11-14 17:56:39,120 INFO L87 Difference]: Start difference. First operand 102 states and 120 transitions. Second operand 15 states. [2018-11-14 17:56:44,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:44,926 INFO L93 Difference]: Finished difference Result 211 states and 255 transitions. [2018-11-14 17:56:44,926 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-11-14 17:56:44,927 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 33 [2018-11-14 17:56:44,927 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:56:44,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2018-11-14 17:56:44,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 149 transitions. [2018-11-14 17:56:44,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2018-11-14 17:56:44,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 149 transitions. [2018-11-14 17:56:44,934 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 21 states and 149 transitions. [2018-11-14 17:56:47,470 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 149 edges. 148 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:47,474 INFO L225 Difference]: With dead ends: 211 [2018-11-14 17:56:47,475 INFO L226 Difference]: Without dead ends: 175 [2018-11-14 17:56:47,476 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 81 GetRequests, 51 SyntacticMatches, 1 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 165 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=199, Invalid=731, Unknown=0, NotChecked=0, Total=930 [2018-11-14 17:56:47,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175 states. [2018-11-14 17:56:47,800 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175 to 119. [2018-11-14 17:56:47,800 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:56:47,800 INFO L82 GeneralOperation]: Start isEquivalent. First operand 175 states. Second operand 119 states. [2018-11-14 17:56:47,800 INFO L74 IsIncluded]: Start isIncluded. First operand 175 states. Second operand 119 states. [2018-11-14 17:56:47,801 INFO L87 Difference]: Start difference. First operand 175 states. Second operand 119 states. [2018-11-14 17:56:47,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:47,807 INFO L93 Difference]: Finished difference Result 175 states and 209 transitions. [2018-11-14 17:56:47,807 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 209 transitions. [2018-11-14 17:56:47,808 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:47,808 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:47,808 INFO L74 IsIncluded]: Start isIncluded. First operand 119 states. Second operand 175 states. [2018-11-14 17:56:47,808 INFO L87 Difference]: Start difference. First operand 119 states. Second operand 175 states. [2018-11-14 17:56:47,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:47,814 INFO L93 Difference]: Finished difference Result 175 states and 209 transitions. [2018-11-14 17:56:47,814 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 209 transitions. [2018-11-14 17:56:47,815 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:47,815 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:47,815 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:56:47,815 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:56:47,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 119 states. [2018-11-14 17:56:47,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 140 transitions. [2018-11-14 17:56:47,819 INFO L78 Accepts]: Start accepts. Automaton has 119 states and 140 transitions. Word has length 33 [2018-11-14 17:56:47,819 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:56:47,819 INFO L480 AbstractCegarLoop]: Abstraction has 119 states and 140 transitions. [2018-11-14 17:56:47,819 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-11-14 17:56:47,820 INFO L276 IsEmpty]: Start isEmpty. Operand 119 states and 140 transitions. [2018-11-14 17:56:47,821 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-11-14 17:56:47,821 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:56:47,821 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:56:47,821 INFO L423 AbstractCegarLoop]: === Iteration 10 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:56:47,821 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:56:47,822 INFO L82 PathProgramCache]: Analyzing trace with hash -568979376, now seen corresponding path program 2 times [2018-11-14 17:56:47,822 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:56:47,822 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:56:47,853 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-14 17:56:47,931 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-14 17:56:47,932 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-14 17:56:47,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:47,974 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:56:48,816 WARN L179 SmtUtils]: Spent 108.00 ms on a formula simplification that was a NOOP. DAG size: 15 [2018-11-14 17:56:49,116 WARN L179 SmtUtils]: Spent 112.00 ms on a formula simplification that was a NOOP. DAG size: 13 [2018-11-14 17:56:49,154 INFO L256 TraceCheckUtils]: 0: Hoare triple {4720#true} call ULTIMATE.init(); {4720#true} is VALID [2018-11-14 17:56:49,154 INFO L273 TraceCheckUtils]: 1: Hoare triple {4720#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {4720#true} is VALID [2018-11-14 17:56:49,154 INFO L273 TraceCheckUtils]: 2: Hoare triple {4720#true} assume true; {4720#true} is VALID [2018-11-14 17:56:49,154 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {4720#true} {4720#true} #79#return; {4720#true} is VALID [2018-11-14 17:56:49,155 INFO L256 TraceCheckUtils]: 4: Hoare triple {4720#true} call #t~ret7 := main(); {4720#true} is VALID [2018-11-14 17:56:49,155 INFO L273 TraceCheckUtils]: 5: Hoare triple {4720#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {4720#true} is VALID [2018-11-14 17:56:49,160 INFO L273 TraceCheckUtils]: 6: Hoare triple {4720#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {4743#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} is VALID [2018-11-14 17:56:49,161 INFO L273 TraceCheckUtils]: 7: Hoare triple {4743#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} assume !(~bvsrem32(~CELLCOUNT~0, 2bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 2bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {4747#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:49,162 INFO L273 TraceCheckUtils]: 8: Hoare triple {4747#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {4747#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:49,162 INFO L273 TraceCheckUtils]: 9: Hoare triple {4747#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {4747#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:49,164 INFO L273 TraceCheckUtils]: 10: Hoare triple {4747#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {4747#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:49,165 INFO L273 TraceCheckUtils]: 11: Hoare triple {4747#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {4747#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:49,166 INFO L273 TraceCheckUtils]: 12: Hoare triple {4747#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {4763#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:56:49,166 INFO L273 TraceCheckUtils]: 13: Hoare triple {4763#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume true; {4763#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:56:49,168 INFO L273 TraceCheckUtils]: 14: Hoare triple {4763#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {4770#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-14 17:56:49,169 INFO L273 TraceCheckUtils]: 15: Hoare triple {4770#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} ~i~0 := 0bv32; {4774#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-14 17:56:49,170 INFO L273 TraceCheckUtils]: 16: Hoare triple {4774#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} assume true; {4774#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-14 17:56:49,172 INFO L273 TraceCheckUtils]: 17: Hoare triple {4774#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {4774#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-14 17:56:49,173 INFO L273 TraceCheckUtils]: 18: Hoare triple {4774#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} assume #t~short6; {4774#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-14 17:56:49,178 INFO L256 TraceCheckUtils]: 19: Hoare triple {4774#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {4770#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-14 17:56:49,180 INFO L273 TraceCheckUtils]: 20: Hoare triple {4770#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} ~cond := #in~cond; {4770#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-14 17:56:49,180 INFO L273 TraceCheckUtils]: 21: Hoare triple {4770#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} assume !(~cond == 0bv32); {4770#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-14 17:56:49,182 INFO L273 TraceCheckUtils]: 22: Hoare triple {4770#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} assume true; {4770#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-14 17:56:49,183 INFO L268 TraceCheckUtils]: 23: Hoare quadruple {4770#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} {4774#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} #83#return; {4774#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-14 17:56:49,184 INFO L273 TraceCheckUtils]: 24: Hoare triple {4774#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {4774#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-14 17:56:49,186 INFO L273 TraceCheckUtils]: 25: Hoare triple {4774#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {4805#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:49,187 INFO L273 TraceCheckUtils]: 26: Hoare triple {4805#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {4805#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:49,188 INFO L273 TraceCheckUtils]: 27: Hoare triple {4805#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {4805#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:49,188 INFO L273 TraceCheckUtils]: 28: Hoare triple {4805#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume #t~short6; {4805#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:49,190 INFO L256 TraceCheckUtils]: 29: Hoare triple {4805#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {4770#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-14 17:56:49,190 INFO L273 TraceCheckUtils]: 30: Hoare triple {4770#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} ~cond := #in~cond; {4770#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-14 17:56:49,192 INFO L273 TraceCheckUtils]: 31: Hoare triple {4770#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} assume !(~cond == 0bv32); {4770#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-14 17:56:49,192 INFO L273 TraceCheckUtils]: 32: Hoare triple {4770#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} assume true; {4770#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-14 17:56:49,194 INFO L268 TraceCheckUtils]: 33: Hoare quadruple {4770#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} {4805#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #83#return; {4805#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:49,194 INFO L273 TraceCheckUtils]: 34: Hoare triple {4805#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {4805#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:49,196 INFO L273 TraceCheckUtils]: 35: Hoare triple {4805#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {4836#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:56:49,197 INFO L273 TraceCheckUtils]: 36: Hoare triple {4836#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (_ bv2 32) main_~i~0))} assume true; {4836#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:56:49,214 INFO L273 TraceCheckUtils]: 37: Hoare triple {4836#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (_ bv2 32) main_~i~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {4721#false} is VALID [2018-11-14 17:56:49,215 INFO L273 TraceCheckUtils]: 38: Hoare triple {4721#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {4721#false} is VALID [2018-11-14 17:56:49,215 INFO L256 TraceCheckUtils]: 39: Hoare triple {4721#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {4721#false} is VALID [2018-11-14 17:56:49,215 INFO L273 TraceCheckUtils]: 40: Hoare triple {4721#false} ~cond := #in~cond; {4721#false} is VALID [2018-11-14 17:56:49,215 INFO L273 TraceCheckUtils]: 41: Hoare triple {4721#false} assume ~cond == 0bv32; {4721#false} is VALID [2018-11-14 17:56:49,215 INFO L273 TraceCheckUtils]: 42: Hoare triple {4721#false} assume !false; {4721#false} is VALID [2018-11-14 17:56:49,223 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 8 proven. 12 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-14 17:56:49,223 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-14 17:56:50,767 WARN L179 SmtUtils]: Spent 131.00 ms on a formula simplification that was a NOOP. DAG size: 12 [2018-11-14 17:56:50,841 INFO L273 TraceCheckUtils]: 42: Hoare triple {4721#false} assume !false; {4721#false} is VALID [2018-11-14 17:56:50,841 INFO L273 TraceCheckUtils]: 41: Hoare triple {4721#false} assume ~cond == 0bv32; {4721#false} is VALID [2018-11-14 17:56:50,842 INFO L273 TraceCheckUtils]: 40: Hoare triple {4721#false} ~cond := #in~cond; {4721#false} is VALID [2018-11-14 17:56:50,842 INFO L256 TraceCheckUtils]: 39: Hoare triple {4721#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {4721#false} is VALID [2018-11-14 17:56:50,842 INFO L273 TraceCheckUtils]: 38: Hoare triple {4721#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {4721#false} is VALID [2018-11-14 17:56:50,844 INFO L273 TraceCheckUtils]: 37: Hoare triple {4873#(not (bvslt main_~i~0 ~CELLCOUNT~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {4721#false} is VALID [2018-11-14 17:56:50,844 INFO L273 TraceCheckUtils]: 36: Hoare triple {4873#(not (bvslt main_~i~0 ~CELLCOUNT~0))} assume true; {4873#(not (bvslt main_~i~0 ~CELLCOUNT~0))} is VALID [2018-11-14 17:56:50,846 INFO L273 TraceCheckUtils]: 35: Hoare triple {4880#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {4873#(not (bvslt main_~i~0 ~CELLCOUNT~0))} is VALID [2018-11-14 17:56:50,850 INFO L273 TraceCheckUtils]: 34: Hoare triple {4880#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {4880#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} is VALID [2018-11-14 17:56:50,851 INFO L268 TraceCheckUtils]: 33: Hoare quadruple {4720#true} {4880#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} #83#return; {4880#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} is VALID [2018-11-14 17:56:50,851 INFO L273 TraceCheckUtils]: 32: Hoare triple {4720#true} assume true; {4720#true} is VALID [2018-11-14 17:56:50,851 INFO L273 TraceCheckUtils]: 31: Hoare triple {4720#true} assume !(~cond == 0bv32); {4720#true} is VALID [2018-11-14 17:56:50,851 INFO L273 TraceCheckUtils]: 30: Hoare triple {4720#true} ~cond := #in~cond; {4720#true} is VALID [2018-11-14 17:56:50,852 INFO L256 TraceCheckUtils]: 29: Hoare triple {4880#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {4720#true} is VALID [2018-11-14 17:56:50,852 INFO L273 TraceCheckUtils]: 28: Hoare triple {4880#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} assume #t~short6; {4880#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} is VALID [2018-11-14 17:56:50,852 INFO L273 TraceCheckUtils]: 27: Hoare triple {4880#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {4880#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} is VALID [2018-11-14 17:56:50,853 INFO L273 TraceCheckUtils]: 26: Hoare triple {4880#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} assume true; {4880#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} is VALID [2018-11-14 17:56:50,872 INFO L273 TraceCheckUtils]: 25: Hoare triple {4911#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {4880#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} is VALID [2018-11-14 17:56:50,873 INFO L273 TraceCheckUtils]: 24: Hoare triple {4911#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {4911#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} is VALID [2018-11-14 17:56:50,875 INFO L268 TraceCheckUtils]: 23: Hoare quadruple {4720#true} {4911#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} #83#return; {4911#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} is VALID [2018-11-14 17:56:50,875 INFO L273 TraceCheckUtils]: 22: Hoare triple {4720#true} assume true; {4720#true} is VALID [2018-11-14 17:56:50,875 INFO L273 TraceCheckUtils]: 21: Hoare triple {4720#true} assume !(~cond == 0bv32); {4720#true} is VALID [2018-11-14 17:56:50,876 INFO L273 TraceCheckUtils]: 20: Hoare triple {4720#true} ~cond := #in~cond; {4720#true} is VALID [2018-11-14 17:56:50,876 INFO L256 TraceCheckUtils]: 19: Hoare triple {4911#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {4720#true} is VALID [2018-11-14 17:56:50,876 INFO L273 TraceCheckUtils]: 18: Hoare triple {4911#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} assume #t~short6; {4911#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} is VALID [2018-11-14 17:56:50,877 INFO L273 TraceCheckUtils]: 17: Hoare triple {4911#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {4911#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} is VALID [2018-11-14 17:56:50,877 INFO L273 TraceCheckUtils]: 16: Hoare triple {4911#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} assume true; {4911#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} is VALID [2018-11-14 17:56:50,877 INFO L273 TraceCheckUtils]: 15: Hoare triple {4942#(not (bvslt (_ bv2 32) ~CELLCOUNT~0))} ~i~0 := 0bv32; {4911#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} is VALID [2018-11-14 17:56:50,878 INFO L273 TraceCheckUtils]: 14: Hoare triple {4946#(or (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {4942#(not (bvslt (_ bv2 32) ~CELLCOUNT~0))} is VALID [2018-11-14 17:56:50,878 INFO L273 TraceCheckUtils]: 13: Hoare triple {4946#(or (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} assume true; {4946#(or (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} is VALID [2018-11-14 17:56:50,895 INFO L273 TraceCheckUtils]: 12: Hoare triple {4953#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {4946#(or (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} is VALID [2018-11-14 17:56:50,895 INFO L273 TraceCheckUtils]: 11: Hoare triple {4953#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {4953#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} is VALID [2018-11-14 17:56:50,896 INFO L273 TraceCheckUtils]: 10: Hoare triple {4953#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {4953#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} is VALID [2018-11-14 17:56:50,896 INFO L273 TraceCheckUtils]: 9: Hoare triple {4963#(or (not (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {4953#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} is VALID [2018-11-14 17:56:50,897 INFO L273 TraceCheckUtils]: 8: Hoare triple {4963#(or (not (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} assume true; {4963#(or (not (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} is VALID [2018-11-14 17:56:50,915 INFO L273 TraceCheckUtils]: 7: Hoare triple {4720#true} assume !(~bvsrem32(~CELLCOUNT~0, 2bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 2bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {4963#(or (not (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} is VALID [2018-11-14 17:56:50,915 INFO L273 TraceCheckUtils]: 6: Hoare triple {4720#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {4720#true} is VALID [2018-11-14 17:56:50,915 INFO L273 TraceCheckUtils]: 5: Hoare triple {4720#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {4720#true} is VALID [2018-11-14 17:56:50,915 INFO L256 TraceCheckUtils]: 4: Hoare triple {4720#true} call #t~ret7 := main(); {4720#true} is VALID [2018-11-14 17:56:50,916 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {4720#true} {4720#true} #79#return; {4720#true} is VALID [2018-11-14 17:56:50,916 INFO L273 TraceCheckUtils]: 2: Hoare triple {4720#true} assume true; {4720#true} is VALID [2018-11-14 17:56:50,916 INFO L273 TraceCheckUtils]: 1: Hoare triple {4720#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {4720#true} is VALID [2018-11-14 17:56:50,916 INFO L256 TraceCheckUtils]: 0: Hoare triple {4720#true} call ULTIMATE.init(); {4720#true} is VALID [2018-11-14 17:56:50,919 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 8 proven. 12 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-14 17:56:50,921 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-14 17:56:50,922 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 16 [2018-11-14 17:56:50,923 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 43 [2018-11-14 17:56:50,923 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:56:50,923 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 16 states. [2018-11-14 17:56:51,509 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 69 edges. 69 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:51,509 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-11-14 17:56:51,510 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-11-14 17:56:51,510 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=168, Unknown=0, NotChecked=0, Total=240 [2018-11-14 17:56:51,510 INFO L87 Difference]: Start difference. First operand 119 states and 140 transitions. Second operand 16 states. [2018-11-14 17:56:56,179 WARN L179 SmtUtils]: Spent 161.00 ms on a formula simplification that was a NOOP. DAG size: 14 [2018-11-14 17:56:56,580 WARN L179 SmtUtils]: Spent 141.00 ms on a formula simplification that was a NOOP. DAG size: 11 [2018-11-14 17:56:57,313 WARN L179 SmtUtils]: Spent 135.00 ms on a formula simplification that was a NOOP. DAG size: 14 [2018-11-14 17:57:02,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:57:02,483 INFO L93 Difference]: Finished difference Result 245 states and 285 transitions. [2018-11-14 17:57:02,484 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-14 17:57:02,484 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 43 [2018-11-14 17:57:02,484 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:57:02,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2018-11-14 17:57:02,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 96 transitions. [2018-11-14 17:57:02,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2018-11-14 17:57:02,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 96 transitions. [2018-11-14 17:57:02,488 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 13 states and 96 transitions. [2018-11-14 17:57:03,595 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 96 edges. 96 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:57:03,600 INFO L225 Difference]: With dead ends: 245 [2018-11-14 17:57:03,600 INFO L226 Difference]: Without dead ends: 148 [2018-11-14 17:57:03,601 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 69 SyntacticMatches, 2 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 76 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=104, Invalid=238, Unknown=0, NotChecked=0, Total=342 [2018-11-14 17:57:03,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2018-11-14 17:57:04,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 125. [2018-11-14 17:57:04,525 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:57:04,525 INFO L82 GeneralOperation]: Start isEquivalent. First operand 148 states. Second operand 125 states. [2018-11-14 17:57:04,526 INFO L74 IsIncluded]: Start isIncluded. First operand 148 states. Second operand 125 states. [2018-11-14 17:57:04,526 INFO L87 Difference]: Start difference. First operand 148 states. Second operand 125 states. [2018-11-14 17:57:04,530 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:57:04,531 INFO L93 Difference]: Finished difference Result 148 states and 174 transitions. [2018-11-14 17:57:04,531 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 174 transitions. [2018-11-14 17:57:04,531 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:57:04,532 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:57:04,532 INFO L74 IsIncluded]: Start isIncluded. First operand 125 states. Second operand 148 states. [2018-11-14 17:57:04,532 INFO L87 Difference]: Start difference. First operand 125 states. Second operand 148 states. [2018-11-14 17:57:04,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:57:04,536 INFO L93 Difference]: Finished difference Result 148 states and 174 transitions. [2018-11-14 17:57:04,536 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 174 transitions. [2018-11-14 17:57:04,537 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:57:04,537 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:57:04,537 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:57:04,537 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:57:04,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2018-11-14 17:57:04,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 145 transitions. [2018-11-14 17:57:04,540 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 145 transitions. Word has length 43 [2018-11-14 17:57:04,541 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:57:04,541 INFO L480 AbstractCegarLoop]: Abstraction has 125 states and 145 transitions. [2018-11-14 17:57:04,541 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-11-14 17:57:04,541 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 145 transitions. [2018-11-14 17:57:04,542 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-11-14 17:57:04,542 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:57:04,542 INFO L375 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:57:04,542 INFO L423 AbstractCegarLoop]: === Iteration 11 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:57:04,542 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:57:04,543 INFO L82 PathProgramCache]: Analyzing trace with hash -977539355, now seen corresponding path program 1 times [2018-11-14 17:57:04,543 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:57:04,543 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:57:04,561 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-14 17:57:04,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:57:04,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:57:04,613 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:57:04,726 INFO L256 TraceCheckUtils]: 0: Hoare triple {5777#true} call ULTIMATE.init(); {5777#true} is VALID [2018-11-14 17:57:04,727 INFO L273 TraceCheckUtils]: 1: Hoare triple {5777#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {5777#true} is VALID [2018-11-14 17:57:04,727 INFO L273 TraceCheckUtils]: 2: Hoare triple {5777#true} assume true; {5777#true} is VALID [2018-11-14 17:57:04,727 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {5777#true} {5777#true} #79#return; {5777#true} is VALID [2018-11-14 17:57:04,727 INFO L256 TraceCheckUtils]: 4: Hoare triple {5777#true} call #t~ret7 := main(); {5777#true} is VALID [2018-11-14 17:57:04,727 INFO L273 TraceCheckUtils]: 5: Hoare triple {5777#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {5777#true} is VALID [2018-11-14 17:57:04,727 INFO L273 TraceCheckUtils]: 6: Hoare triple {5777#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {5777#true} is VALID [2018-11-14 17:57:04,727 INFO L273 TraceCheckUtils]: 7: Hoare triple {5777#true} assume !(~bvsrem32(~CELLCOUNT~0, 2bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 2bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {5777#true} is VALID [2018-11-14 17:57:04,728 INFO L273 TraceCheckUtils]: 8: Hoare triple {5777#true} assume true; {5777#true} is VALID [2018-11-14 17:57:04,728 INFO L273 TraceCheckUtils]: 9: Hoare triple {5777#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {5777#true} is VALID [2018-11-14 17:57:04,728 INFO L273 TraceCheckUtils]: 10: Hoare triple {5777#true} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {5777#true} is VALID [2018-11-14 17:57:04,728 INFO L273 TraceCheckUtils]: 11: Hoare triple {5777#true} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {5815#(not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))} is VALID [2018-11-14 17:57:04,729 INFO L273 TraceCheckUtils]: 12: Hoare triple {5815#(not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {5815#(not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))} is VALID [2018-11-14 17:57:04,729 INFO L273 TraceCheckUtils]: 13: Hoare triple {5815#(not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))} assume true; {5815#(not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))} is VALID [2018-11-14 17:57:04,729 INFO L273 TraceCheckUtils]: 14: Hoare triple {5815#(not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {5815#(not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))} is VALID [2018-11-14 17:57:04,730 INFO L273 TraceCheckUtils]: 15: Hoare triple {5815#(not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {5815#(not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))} is VALID [2018-11-14 17:57:04,730 INFO L273 TraceCheckUtils]: 16: Hoare triple {5815#(not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))} assume ~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL1~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {5778#false} is VALID [2018-11-14 17:57:04,730 INFO L273 TraceCheckUtils]: 17: Hoare triple {5778#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {5778#false} is VALID [2018-11-14 17:57:04,730 INFO L273 TraceCheckUtils]: 18: Hoare triple {5778#false} assume true; {5778#false} is VALID [2018-11-14 17:57:04,730 INFO L273 TraceCheckUtils]: 19: Hoare triple {5778#false} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {5778#false} is VALID [2018-11-14 17:57:04,730 INFO L273 TraceCheckUtils]: 20: Hoare triple {5778#false} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {5778#false} is VALID [2018-11-14 17:57:04,731 INFO L273 TraceCheckUtils]: 21: Hoare triple {5778#false} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {5778#false} is VALID [2018-11-14 17:57:04,731 INFO L273 TraceCheckUtils]: 22: Hoare triple {5778#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {5778#false} is VALID [2018-11-14 17:57:04,731 INFO L273 TraceCheckUtils]: 23: Hoare triple {5778#false} assume true; {5778#false} is VALID [2018-11-14 17:57:04,731 INFO L273 TraceCheckUtils]: 24: Hoare triple {5778#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {5778#false} is VALID [2018-11-14 17:57:04,731 INFO L273 TraceCheckUtils]: 25: Hoare triple {5778#false} ~i~0 := 0bv32; {5778#false} is VALID [2018-11-14 17:57:04,731 INFO L273 TraceCheckUtils]: 26: Hoare triple {5778#false} assume true; {5778#false} is VALID [2018-11-14 17:57:04,731 INFO L273 TraceCheckUtils]: 27: Hoare triple {5778#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {5778#false} is VALID [2018-11-14 17:57:04,732 INFO L273 TraceCheckUtils]: 28: Hoare triple {5778#false} assume #t~short6; {5778#false} is VALID [2018-11-14 17:57:04,732 INFO L256 TraceCheckUtils]: 29: Hoare triple {5778#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {5778#false} is VALID [2018-11-14 17:57:04,732 INFO L273 TraceCheckUtils]: 30: Hoare triple {5778#false} ~cond := #in~cond; {5778#false} is VALID [2018-11-14 17:57:04,732 INFO L273 TraceCheckUtils]: 31: Hoare triple {5778#false} assume !(~cond == 0bv32); {5778#false} is VALID [2018-11-14 17:57:04,732 INFO L273 TraceCheckUtils]: 32: Hoare triple {5778#false} assume true; {5778#false} is VALID [2018-11-14 17:57:04,733 INFO L268 TraceCheckUtils]: 33: Hoare quadruple {5778#false} {5778#false} #83#return; {5778#false} is VALID [2018-11-14 17:57:04,733 INFO L273 TraceCheckUtils]: 34: Hoare triple {5778#false} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {5778#false} is VALID [2018-11-14 17:57:04,733 INFO L273 TraceCheckUtils]: 35: Hoare triple {5778#false} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {5778#false} is VALID [2018-11-14 17:57:04,733 INFO L273 TraceCheckUtils]: 36: Hoare triple {5778#false} assume true; {5778#false} is VALID [2018-11-14 17:57:04,733 INFO L273 TraceCheckUtils]: 37: Hoare triple {5778#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {5778#false} is VALID [2018-11-14 17:57:04,734 INFO L273 TraceCheckUtils]: 38: Hoare triple {5778#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {5778#false} is VALID [2018-11-14 17:57:04,734 INFO L256 TraceCheckUtils]: 39: Hoare triple {5778#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {5778#false} is VALID [2018-11-14 17:57:04,734 INFO L273 TraceCheckUtils]: 40: Hoare triple {5778#false} ~cond := #in~cond; {5778#false} is VALID [2018-11-14 17:57:04,734 INFO L273 TraceCheckUtils]: 41: Hoare triple {5778#false} assume ~cond == 0bv32; {5778#false} is VALID [2018-11-14 17:57:04,734 INFO L273 TraceCheckUtils]: 42: Hoare triple {5778#false} assume !false; {5778#false} is VALID [2018-11-14 17:57:04,735 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-14 17:57:04,735 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-14 17:57:04,737 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-14 17:57:04,737 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-14 17:57:04,737 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 43 [2018-11-14 17:57:04,737 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:57:04,737 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2018-11-14 17:57:04,835 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 37 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:57:04,836 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-14 17:57:04,836 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-14 17:57:04,836 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-14 17:57:04,836 INFO L87 Difference]: Start difference. First operand 125 states and 145 transitions. Second operand 3 states. [2018-11-14 17:57:05,575 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:57:05,576 INFO L93 Difference]: Finished difference Result 148 states and 170 transitions. [2018-11-14 17:57:05,576 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-14 17:57:05,576 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 43 [2018-11-14 17:57:05,576 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:57:05,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-14 17:57:05,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 68 transitions. [2018-11-14 17:57:05,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-14 17:57:05,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 68 transitions. [2018-11-14 17:57:05,578 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states and 68 transitions. [2018-11-14 17:57:05,742 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 68 edges. 68 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:57:05,746 INFO L225 Difference]: With dead ends: 148 [2018-11-14 17:57:05,746 INFO L226 Difference]: Without dead ends: 109 [2018-11-14 17:57:05,747 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 41 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-14 17:57:05,747 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109 states. [2018-11-14 17:57:05,951 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109 to 109. [2018-11-14 17:57:05,951 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:57:05,951 INFO L82 GeneralOperation]: Start isEquivalent. First operand 109 states. Second operand 109 states. [2018-11-14 17:57:05,951 INFO L74 IsIncluded]: Start isIncluded. First operand 109 states. Second operand 109 states. [2018-11-14 17:57:05,951 INFO L87 Difference]: Start difference. First operand 109 states. Second operand 109 states. [2018-11-14 17:57:05,954 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:57:05,955 INFO L93 Difference]: Finished difference Result 109 states and 123 transitions. [2018-11-14 17:57:05,955 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 123 transitions. [2018-11-14 17:57:05,955 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:57:05,955 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:57:05,956 INFO L74 IsIncluded]: Start isIncluded. First operand 109 states. Second operand 109 states. [2018-11-14 17:57:05,956 INFO L87 Difference]: Start difference. First operand 109 states. Second operand 109 states. [2018-11-14 17:57:05,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:57:05,959 INFO L93 Difference]: Finished difference Result 109 states and 123 transitions. [2018-11-14 17:57:05,959 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 123 transitions. [2018-11-14 17:57:05,959 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:57:05,959 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:57:05,960 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:57:05,960 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:57:05,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 109 states. [2018-11-14 17:57:05,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 123 transitions. [2018-11-14 17:57:05,963 INFO L78 Accepts]: Start accepts. Automaton has 109 states and 123 transitions. Word has length 43 [2018-11-14 17:57:05,963 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:57:05,963 INFO L480 AbstractCegarLoop]: Abstraction has 109 states and 123 transitions. [2018-11-14 17:57:05,963 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-14 17:57:05,963 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 123 transitions. [2018-11-14 17:57:05,964 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-14 17:57:05,964 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:57:05,964 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:57:05,964 INFO L423 AbstractCegarLoop]: === Iteration 12 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:57:05,965 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:57:05,965 INFO L82 PathProgramCache]: Analyzing trace with hash 1115490863, now seen corresponding path program 3 times [2018-11-14 17:57:05,965 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:57:05,965 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:57:05,993 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2018-11-14 17:57:06,241 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-11-14 17:57:06,242 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-14 17:57:06,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:57:06,302 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:57:06,687 WARN L179 SmtUtils]: Spent 117.00 ms on a formula simplification that was a NOOP. DAG size: 10 [2018-11-14 17:57:06,862 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-14 17:57:06,873 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-14 17:57:06,874 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:57:06,878 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:06,896 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:06,897 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:31, output treesize:27 [2018-11-14 17:57:07,015 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 24 [2018-11-14 17:57:07,022 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:57:07,024 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:57:07,025 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 52 [2018-11-14 17:57:07,029 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:57:07,042 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:07,068 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:07,068 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:41, output treesize:37 [2018-11-14 17:57:07,140 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 25 [2018-11-14 17:57:07,151 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:57:07,153 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:57:07,154 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:57:07,156 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:57:07,157 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 4 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 68 [2018-11-14 17:57:07,161 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:57:07,177 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:07,201 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:07,202 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:42, output treesize:38 [2018-11-14 17:57:07,571 INFO L256 TraceCheckUtils]: 0: Hoare triple {6462#true} call ULTIMATE.init(); {6462#true} is VALID [2018-11-14 17:57:07,572 INFO L273 TraceCheckUtils]: 1: Hoare triple {6462#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {6462#true} is VALID [2018-11-14 17:57:07,572 INFO L273 TraceCheckUtils]: 2: Hoare triple {6462#true} assume true; {6462#true} is VALID [2018-11-14 17:57:07,572 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {6462#true} {6462#true} #79#return; {6462#true} is VALID [2018-11-14 17:57:07,572 INFO L256 TraceCheckUtils]: 4: Hoare triple {6462#true} call #t~ret7 := main(); {6462#true} is VALID [2018-11-14 17:57:07,573 INFO L273 TraceCheckUtils]: 5: Hoare triple {6462#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {6462#true} is VALID [2018-11-14 17:57:07,573 INFO L273 TraceCheckUtils]: 6: Hoare triple {6462#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {6485#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:57:07,574 INFO L273 TraceCheckUtils]: 7: Hoare triple {6485#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !(~bvsrem32(~CELLCOUNT~0, 2bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 2bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {6489#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:07,575 INFO L273 TraceCheckUtils]: 8: Hoare triple {6489#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {6489#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:07,575 INFO L273 TraceCheckUtils]: 9: Hoare triple {6489#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {6489#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:07,576 INFO L273 TraceCheckUtils]: 10: Hoare triple {6489#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {6489#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:07,579 INFO L273 TraceCheckUtils]: 11: Hoare triple {6489#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {6502#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32))) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:07,580 INFO L273 TraceCheckUtils]: 12: Hoare triple {6502#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32))) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {6506#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:57:07,581 INFO L273 TraceCheckUtils]: 13: Hoare triple {6506#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume true; {6506#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:57:07,596 INFO L273 TraceCheckUtils]: 14: Hoare triple {6506#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {6506#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:57:07,598 INFO L273 TraceCheckUtils]: 15: Hoare triple {6506#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {6516#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:57:07,599 INFO L273 TraceCheckUtils]: 16: Hoare triple {6516#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {6520#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:57:07,600 INFO L273 TraceCheckUtils]: 17: Hoare triple {6520#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {6520#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:57:07,601 INFO L273 TraceCheckUtils]: 18: Hoare triple {6520#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume true; {6520#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:57:07,601 INFO L273 TraceCheckUtils]: 19: Hoare triple {6520#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {6520#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:57:07,603 INFO L273 TraceCheckUtils]: 20: Hoare triple {6520#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} ~i~0 := 0bv32; {6533#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:57:07,605 INFO L273 TraceCheckUtils]: 21: Hoare triple {6533#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume true; {6533#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:57:07,607 INFO L273 TraceCheckUtils]: 22: Hoare triple {6533#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {6533#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:57:07,609 INFO L273 TraceCheckUtils]: 23: Hoare triple {6533#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume #t~short6; {6533#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:57:07,611 INFO L256 TraceCheckUtils]: 24: Hoare triple {6533#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {6546#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv12 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv4 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32)))))} is VALID [2018-11-14 17:57:07,612 INFO L273 TraceCheckUtils]: 25: Hoare triple {6546#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv12 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv4 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32)))))} ~cond := #in~cond; {6546#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv12 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv4 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32)))))} is VALID [2018-11-14 17:57:07,613 INFO L273 TraceCheckUtils]: 26: Hoare triple {6546#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv12 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv4 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32)))))} assume !(~cond == 0bv32); {6546#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv12 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv4 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32)))))} is VALID [2018-11-14 17:57:07,613 INFO L273 TraceCheckUtils]: 27: Hoare triple {6546#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv12 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv4 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32)))))} assume true; {6546#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv12 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv4 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32)))))} is VALID [2018-11-14 17:57:07,614 INFO L268 TraceCheckUtils]: 28: Hoare quadruple {6546#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv12 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv4 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32)))))} {6533#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #83#return; {6533#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:57:07,615 INFO L273 TraceCheckUtils]: 29: Hoare triple {6533#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {6533#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:57:07,616 INFO L273 TraceCheckUtils]: 30: Hoare triple {6533#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {6565#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:07,617 INFO L273 TraceCheckUtils]: 31: Hoare triple {6565#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {6565#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:07,619 INFO L273 TraceCheckUtils]: 32: Hoare triple {6565#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {6572#(not |main_#t~short6|)} is VALID [2018-11-14 17:57:07,619 INFO L273 TraceCheckUtils]: 33: Hoare triple {6572#(not |main_#t~short6|)} assume #t~short6; {6463#false} is VALID [2018-11-14 17:57:07,620 INFO L256 TraceCheckUtils]: 34: Hoare triple {6463#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {6463#false} is VALID [2018-11-14 17:57:07,620 INFO L273 TraceCheckUtils]: 35: Hoare triple {6463#false} ~cond := #in~cond; {6463#false} is VALID [2018-11-14 17:57:07,620 INFO L273 TraceCheckUtils]: 36: Hoare triple {6463#false} assume !(~cond == 0bv32); {6463#false} is VALID [2018-11-14 17:57:07,620 INFO L273 TraceCheckUtils]: 37: Hoare triple {6463#false} assume true; {6463#false} is VALID [2018-11-14 17:57:07,621 INFO L268 TraceCheckUtils]: 38: Hoare quadruple {6463#false} {6463#false} #83#return; {6463#false} is VALID [2018-11-14 17:57:07,621 INFO L273 TraceCheckUtils]: 39: Hoare triple {6463#false} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {6463#false} is VALID [2018-11-14 17:57:07,621 INFO L273 TraceCheckUtils]: 40: Hoare triple {6463#false} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {6463#false} is VALID [2018-11-14 17:57:07,621 INFO L273 TraceCheckUtils]: 41: Hoare triple {6463#false} assume true; {6463#false} is VALID [2018-11-14 17:57:07,621 INFO L273 TraceCheckUtils]: 42: Hoare triple {6463#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {6463#false} is VALID [2018-11-14 17:57:07,622 INFO L273 TraceCheckUtils]: 43: Hoare triple {6463#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {6463#false} is VALID [2018-11-14 17:57:07,622 INFO L256 TraceCheckUtils]: 44: Hoare triple {6463#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {6463#false} is VALID [2018-11-14 17:57:07,622 INFO L273 TraceCheckUtils]: 45: Hoare triple {6463#false} ~cond := #in~cond; {6463#false} is VALID [2018-11-14 17:57:07,622 INFO L273 TraceCheckUtils]: 46: Hoare triple {6463#false} assume ~cond == 0bv32; {6463#false} is VALID [2018-11-14 17:57:07,623 INFO L273 TraceCheckUtils]: 47: Hoare triple {6463#false} assume !false; {6463#false} is VALID [2018-11-14 17:57:07,632 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 16 proven. 12 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-11-14 17:57:07,632 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-14 17:57:08,951 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 31 [2018-11-14 17:57:08,960 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 35 [2018-11-14 17:57:08,974 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 17:57:08,978 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 50 [2018-11-14 17:57:09,081 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 17:57:09,086 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 23 [2018-11-14 17:57:09,089 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-14 17:57:09,096 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 17:57:09,099 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 17:57:09,117 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 2 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 46 [2018-11-14 17:57:09,124 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-14 17:57:09,162 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-14 17:57:09,181 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-14 17:57:09,204 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-14 17:57:09,244 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 3 dim-0 vars, and 2 xjuncts. [2018-11-14 17:57:09,244 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 3 variables, input treesize:41, output treesize:40 [2018-11-14 17:57:09,261 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:57:09,671 INFO L273 TraceCheckUtils]: 47: Hoare triple {6463#false} assume !false; {6463#false} is VALID [2018-11-14 17:57:09,671 INFO L273 TraceCheckUtils]: 46: Hoare triple {6463#false} assume ~cond == 0bv32; {6463#false} is VALID [2018-11-14 17:57:09,671 INFO L273 TraceCheckUtils]: 45: Hoare triple {6463#false} ~cond := #in~cond; {6463#false} is VALID [2018-11-14 17:57:09,671 INFO L256 TraceCheckUtils]: 44: Hoare triple {6463#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {6463#false} is VALID [2018-11-14 17:57:09,672 INFO L273 TraceCheckUtils]: 43: Hoare triple {6463#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {6463#false} is VALID [2018-11-14 17:57:09,672 INFO L273 TraceCheckUtils]: 42: Hoare triple {6463#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {6463#false} is VALID [2018-11-14 17:57:09,672 INFO L273 TraceCheckUtils]: 41: Hoare triple {6463#false} assume true; {6463#false} is VALID [2018-11-14 17:57:09,672 INFO L273 TraceCheckUtils]: 40: Hoare triple {6463#false} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {6463#false} is VALID [2018-11-14 17:57:09,672 INFO L273 TraceCheckUtils]: 39: Hoare triple {6463#false} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {6463#false} is VALID [2018-11-14 17:57:09,673 INFO L268 TraceCheckUtils]: 38: Hoare quadruple {6462#true} {6463#false} #83#return; {6463#false} is VALID [2018-11-14 17:57:09,673 INFO L273 TraceCheckUtils]: 37: Hoare triple {6462#true} assume true; {6462#true} is VALID [2018-11-14 17:57:09,673 INFO L273 TraceCheckUtils]: 36: Hoare triple {6462#true} assume !(~cond == 0bv32); {6462#true} is VALID [2018-11-14 17:57:09,673 INFO L273 TraceCheckUtils]: 35: Hoare triple {6462#true} ~cond := #in~cond; {6462#true} is VALID [2018-11-14 17:57:09,673 INFO L256 TraceCheckUtils]: 34: Hoare triple {6463#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {6462#true} is VALID [2018-11-14 17:57:09,689 INFO L273 TraceCheckUtils]: 33: Hoare triple {6572#(not |main_#t~short6|)} assume #t~short6; {6463#false} is VALID [2018-11-14 17:57:09,692 INFO L273 TraceCheckUtils]: 32: Hoare triple {6663#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {6572#(not |main_#t~short6|)} is VALID [2018-11-14 17:57:09,692 INFO L273 TraceCheckUtils]: 31: Hoare triple {6663#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0))} assume true; {6663#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0))} is VALID [2018-11-14 17:57:11,708 INFO L273 TraceCheckUtils]: 30: Hoare triple {6670#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {6663#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0))} is UNKNOWN [2018-11-14 17:57:11,709 INFO L273 TraceCheckUtils]: 29: Hoare triple {6670#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {6670#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-14 17:57:11,709 INFO L268 TraceCheckUtils]: 28: Hoare quadruple {6462#true} {6670#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} #83#return; {6670#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-14 17:57:11,710 INFO L273 TraceCheckUtils]: 27: Hoare triple {6462#true} assume true; {6462#true} is VALID [2018-11-14 17:57:11,710 INFO L273 TraceCheckUtils]: 26: Hoare triple {6462#true} assume !(~cond == 0bv32); {6462#true} is VALID [2018-11-14 17:57:11,710 INFO L273 TraceCheckUtils]: 25: Hoare triple {6462#true} ~cond := #in~cond; {6462#true} is VALID [2018-11-14 17:57:11,710 INFO L256 TraceCheckUtils]: 24: Hoare triple {6670#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {6462#true} is VALID [2018-11-14 17:57:11,710 INFO L273 TraceCheckUtils]: 23: Hoare triple {6670#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} assume #t~short6; {6670#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-14 17:57:11,711 INFO L273 TraceCheckUtils]: 22: Hoare triple {6670#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {6670#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-14 17:57:11,711 INFO L273 TraceCheckUtils]: 21: Hoare triple {6670#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} assume true; {6670#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-14 17:57:11,711 INFO L273 TraceCheckUtils]: 20: Hoare triple {6701#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} ~i~0 := 0bv32; {6670#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-14 17:57:11,712 INFO L273 TraceCheckUtils]: 19: Hoare triple {6701#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {6701#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-14 17:57:11,712 INFO L273 TraceCheckUtils]: 18: Hoare triple {6701#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} assume true; {6701#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-14 17:57:11,713 INFO L273 TraceCheckUtils]: 17: Hoare triple {6701#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {6701#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-14 17:57:11,747 INFO L273 TraceCheckUtils]: 16: Hoare triple {6714#(or (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (not (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {6701#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-14 17:57:11,827 INFO L273 TraceCheckUtils]: 15: Hoare triple {6718#(forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (not (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {6714#(or (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (not (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)))} is VALID [2018-11-14 17:57:11,828 INFO L273 TraceCheckUtils]: 14: Hoare triple {6718#(forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (not (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {6718#(forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (not (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))))} is VALID [2018-11-14 17:57:11,828 INFO L273 TraceCheckUtils]: 13: Hoare triple {6718#(forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (not (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))))} assume true; {6718#(forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (not (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))))} is VALID [2018-11-14 17:57:11,899 INFO L273 TraceCheckUtils]: 12: Hoare triple {6728#(forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (not (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {6718#(forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (not (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))))} is VALID [2018-11-14 17:57:11,987 INFO L273 TraceCheckUtils]: 11: Hoare triple {6732#(and (forall ((v_prenex_1 (_ BitVec 32))) (or (bvsge main_~CCCELVOL1~0 v_prenex_1) (not (bvsge main_~CCCELVOL2~0 v_prenex_1)) (not (bvsge (_ bv0 32) v_prenex_1)))) (or (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)) (= (bvmul (_ bv8 32) main_~i~0) (_ bv0 32)) (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_19 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (not (bvsge v_arrayElimCell_19 main_~MINVAL~0))))))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {6728#(forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (not (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))))} is VALID [2018-11-14 17:57:11,988 INFO L273 TraceCheckUtils]: 10: Hoare triple {6732#(and (forall ((v_prenex_1 (_ BitVec 32))) (or (bvsge main_~CCCELVOL1~0 v_prenex_1) (not (bvsge main_~CCCELVOL2~0 v_prenex_1)) (not (bvsge (_ bv0 32) v_prenex_1)))) (or (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)) (= (bvmul (_ bv8 32) main_~i~0) (_ bv0 32)) (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_19 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (not (bvsge v_arrayElimCell_19 main_~MINVAL~0))))))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {6732#(and (forall ((v_prenex_1 (_ BitVec 32))) (or (bvsge main_~CCCELVOL1~0 v_prenex_1) (not (bvsge main_~CCCELVOL2~0 v_prenex_1)) (not (bvsge (_ bv0 32) v_prenex_1)))) (or (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)) (= (bvmul (_ bv8 32) main_~i~0) (_ bv0 32)) (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_19 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (not (bvsge v_arrayElimCell_19 main_~MINVAL~0))))))} is VALID [2018-11-14 17:57:11,988 INFO L273 TraceCheckUtils]: 9: Hoare triple {6732#(and (forall ((v_prenex_1 (_ BitVec 32))) (or (bvsge main_~CCCELVOL1~0 v_prenex_1) (not (bvsge main_~CCCELVOL2~0 v_prenex_1)) (not (bvsge (_ bv0 32) v_prenex_1)))) (or (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)) (= (bvmul (_ bv8 32) main_~i~0) (_ bv0 32)) (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_19 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (not (bvsge v_arrayElimCell_19 main_~MINVAL~0))))))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {6732#(and (forall ((v_prenex_1 (_ BitVec 32))) (or (bvsge main_~CCCELVOL1~0 v_prenex_1) (not (bvsge main_~CCCELVOL2~0 v_prenex_1)) (not (bvsge (_ bv0 32) v_prenex_1)))) (or (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)) (= (bvmul (_ bv8 32) main_~i~0) (_ bv0 32)) (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_19 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (not (bvsge v_arrayElimCell_19 main_~MINVAL~0))))))} is VALID [2018-11-14 17:57:11,989 INFO L273 TraceCheckUtils]: 8: Hoare triple {6732#(and (forall ((v_prenex_1 (_ BitVec 32))) (or (bvsge main_~CCCELVOL1~0 v_prenex_1) (not (bvsge main_~CCCELVOL2~0 v_prenex_1)) (not (bvsge (_ bv0 32) v_prenex_1)))) (or (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)) (= (bvmul (_ bv8 32) main_~i~0) (_ bv0 32)) (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_19 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (not (bvsge v_arrayElimCell_19 main_~MINVAL~0))))))} assume true; {6732#(and (forall ((v_prenex_1 (_ BitVec 32))) (or (bvsge main_~CCCELVOL1~0 v_prenex_1) (not (bvsge main_~CCCELVOL2~0 v_prenex_1)) (not (bvsge (_ bv0 32) v_prenex_1)))) (or (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)) (= (bvmul (_ bv8 32) main_~i~0) (_ bv0 32)) (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_19 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (not (bvsge v_arrayElimCell_19 main_~MINVAL~0))))))} is VALID [2018-11-14 17:57:12,008 INFO L273 TraceCheckUtils]: 7: Hoare triple {6745#(forall ((v_prenex_1 (_ BitVec 32))) (or (bvsge main_~CCCELVOL1~0 v_prenex_1) (not (bvsge main_~CCCELVOL2~0 v_prenex_1)) (not (bvsge (_ bv0 32) v_prenex_1))))} assume !(~bvsrem32(~CELLCOUNT~0, 2bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 2bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {6732#(and (forall ((v_prenex_1 (_ BitVec 32))) (or (bvsge main_~CCCELVOL1~0 v_prenex_1) (not (bvsge main_~CCCELVOL2~0 v_prenex_1)) (not (bvsge (_ bv0 32) v_prenex_1)))) (or (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)) (= (bvmul (_ bv8 32) main_~i~0) (_ bv0 32)) (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_19 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (not (bvsge v_arrayElimCell_19 main_~MINVAL~0))))))} is VALID [2018-11-14 17:57:12,024 INFO L273 TraceCheckUtils]: 6: Hoare triple {6462#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {6745#(forall ((v_prenex_1 (_ BitVec 32))) (or (bvsge main_~CCCELVOL1~0 v_prenex_1) (not (bvsge main_~CCCELVOL2~0 v_prenex_1)) (not (bvsge (_ bv0 32) v_prenex_1))))} is VALID [2018-11-14 17:57:12,024 INFO L273 TraceCheckUtils]: 5: Hoare triple {6462#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {6462#true} is VALID [2018-11-14 17:57:12,024 INFO L256 TraceCheckUtils]: 4: Hoare triple {6462#true} call #t~ret7 := main(); {6462#true} is VALID [2018-11-14 17:57:12,025 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {6462#true} {6462#true} #79#return; {6462#true} is VALID [2018-11-14 17:57:12,025 INFO L273 TraceCheckUtils]: 2: Hoare triple {6462#true} assume true; {6462#true} is VALID [2018-11-14 17:57:12,025 INFO L273 TraceCheckUtils]: 1: Hoare triple {6462#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {6462#true} is VALID [2018-11-14 17:57:12,025 INFO L256 TraceCheckUtils]: 0: Hoare triple {6462#true} call ULTIMATE.init(); {6462#true} is VALID [2018-11-14 17:57:12,033 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 14 proven. 12 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-14 17:57:12,034 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-14 17:57:12,035 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11] total 20 [2018-11-14 17:57:12,035 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 48 [2018-11-14 17:57:12,035 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:57:12,035 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 20 states. [2018-11-14 17:57:14,823 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 75 edges. 74 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2018-11-14 17:57:14,824 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-14 17:57:14,824 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-14 17:57:14,824 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=73, Invalid=307, Unknown=0, NotChecked=0, Total=380 [2018-11-14 17:57:14,825 INFO L87 Difference]: Start difference. First operand 109 states and 123 transitions. Second operand 20 states. [2018-11-14 17:57:16,396 WARN L179 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 42 [2018-11-14 17:57:18,658 WARN L179 SmtUtils]: Spent 115.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 35 [2018-11-14 17:57:19,039 WARN L179 SmtUtils]: Spent 152.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 50 [2018-11-14 17:57:21,085 WARN L179 SmtUtils]: Spent 195.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 45 [2018-11-14 17:57:21,572 WARN L179 SmtUtils]: Spent 268.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 53 [2018-11-14 17:57:22,935 WARN L179 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 45 [2018-11-14 17:57:25,804 WARN L179 SmtUtils]: Spent 172.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 52 [2018-11-14 17:57:27,613 WARN L179 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 37 [2018-11-14 17:57:29,158 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:57:29,158 INFO L93 Difference]: Finished difference Result 180 states and 204 transitions. [2018-11-14 17:57:29,158 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-14 17:57:29,158 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 48 [2018-11-14 17:57:29,159 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:57:29,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2018-11-14 17:57:29,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 163 transitions. [2018-11-14 17:57:29,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2018-11-14 17:57:29,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 163 transitions. [2018-11-14 17:57:29,167 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 25 states and 163 transitions. [2018-11-14 17:57:31,033 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 163 edges. 163 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:57:31,035 INFO L225 Difference]: With dead ends: 180 [2018-11-14 17:57:31,035 INFO L226 Difference]: Without dead ends: 163 [2018-11-14 17:57:31,037 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 76 SyntacticMatches, 1 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 308 ImplicationChecksByTransitivity, 4.9s TimeCoverageRelationStatistics Valid=372, Invalid=1188, Unknown=0, NotChecked=0, Total=1560 [2018-11-14 17:57:31,037 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states. [2018-11-14 17:57:31,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 136. [2018-11-14 17:57:31,416 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:57:31,416 INFO L82 GeneralOperation]: Start isEquivalent. First operand 163 states. Second operand 136 states. [2018-11-14 17:57:31,416 INFO L74 IsIncluded]: Start isIncluded. First operand 163 states. Second operand 136 states. [2018-11-14 17:57:31,416 INFO L87 Difference]: Start difference. First operand 163 states. Second operand 136 states. [2018-11-14 17:57:31,421 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:57:31,421 INFO L93 Difference]: Finished difference Result 163 states and 183 transitions. [2018-11-14 17:57:31,421 INFO L276 IsEmpty]: Start isEmpty. Operand 163 states and 183 transitions. [2018-11-14 17:57:31,422 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:57:31,422 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:57:31,422 INFO L74 IsIncluded]: Start isIncluded. First operand 136 states. Second operand 163 states. [2018-11-14 17:57:31,422 INFO L87 Difference]: Start difference. First operand 136 states. Second operand 163 states. [2018-11-14 17:57:31,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:57:31,427 INFO L93 Difference]: Finished difference Result 163 states and 183 transitions. [2018-11-14 17:57:31,427 INFO L276 IsEmpty]: Start isEmpty. Operand 163 states and 183 transitions. [2018-11-14 17:57:31,428 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:57:31,428 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:57:31,428 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:57:31,428 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:57:31,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136 states. [2018-11-14 17:57:31,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 153 transitions. [2018-11-14 17:57:31,432 INFO L78 Accepts]: Start accepts. Automaton has 136 states and 153 transitions. Word has length 48 [2018-11-14 17:57:31,432 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:57:31,432 INFO L480 AbstractCegarLoop]: Abstraction has 136 states and 153 transitions. [2018-11-14 17:57:31,432 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-14 17:57:31,432 INFO L276 IsEmpty]: Start isEmpty. Operand 136 states and 153 transitions. [2018-11-14 17:57:31,433 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-14 17:57:31,433 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:57:31,433 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:57:31,434 INFO L423 AbstractCegarLoop]: === Iteration 13 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:57:31,434 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:57:31,434 INFO L82 PathProgramCache]: Analyzing trace with hash -164372815, now seen corresponding path program 4 times [2018-11-14 17:57:31,434 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:57:31,434 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 14 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:57:31,461 INFO L101 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-14 17:57:31,608 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-14 17:57:31,609 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-14 17:57:31,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:57:31,667 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:57:32,186 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-14 17:57:32,193 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-14 17:57:32,194 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:57:32,200 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:32,218 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:32,219 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:27, output treesize:23 [2018-11-14 17:57:32,277 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 18 [2018-11-14 17:57:32,293 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:57:32,295 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:57:32,296 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 37 [2018-11-14 17:57:32,299 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:57:32,316 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:32,337 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:32,337 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:30, output treesize:26 [2018-11-14 17:57:32,883 INFO L256 TraceCheckUtils]: 0: Hoare triple {7546#true} call ULTIMATE.init(); {7546#true} is VALID [2018-11-14 17:57:32,883 INFO L273 TraceCheckUtils]: 1: Hoare triple {7546#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {7546#true} is VALID [2018-11-14 17:57:32,883 INFO L273 TraceCheckUtils]: 2: Hoare triple {7546#true} assume true; {7546#true} is VALID [2018-11-14 17:57:32,884 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {7546#true} {7546#true} #79#return; {7546#true} is VALID [2018-11-14 17:57:32,884 INFO L256 TraceCheckUtils]: 4: Hoare triple {7546#true} call #t~ret7 := main(); {7546#true} is VALID [2018-11-14 17:57:32,884 INFO L273 TraceCheckUtils]: 5: Hoare triple {7546#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {7546#true} is VALID [2018-11-14 17:57:32,884 INFO L273 TraceCheckUtils]: 6: Hoare triple {7546#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {7569#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0))} is VALID [2018-11-14 17:57:32,885 INFO L273 TraceCheckUtils]: 7: Hoare triple {7569#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0))} assume !(~bvsrem32(~CELLCOUNT~0, 2bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 2bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {7573#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:32,885 INFO L273 TraceCheckUtils]: 8: Hoare triple {7573#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {7573#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:32,886 INFO L273 TraceCheckUtils]: 9: Hoare triple {7573#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {7573#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:32,886 INFO L273 TraceCheckUtils]: 10: Hoare triple {7573#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {7583#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:32,887 INFO L273 TraceCheckUtils]: 11: Hoare triple {7583#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {7587#(and (= (_ bv3 32) main_~CCCELVOL2~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:32,887 INFO L273 TraceCheckUtils]: 12: Hoare triple {7587#(and (= (_ bv3 32) main_~CCCELVOL2~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {7591#(and (= (_ bv3 32) main_~CCCELVOL2~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:57:32,888 INFO L273 TraceCheckUtils]: 13: Hoare triple {7591#(and (= (_ bv3 32) main_~CCCELVOL2~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (= (_ bv2 32) main_~i~0))} assume true; {7591#(and (= (_ bv3 32) main_~CCCELVOL2~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:57:32,889 INFO L273 TraceCheckUtils]: 14: Hoare triple {7591#(and (= (_ bv3 32) main_~CCCELVOL2~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (= (_ bv2 32) main_~i~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {7591#(and (= (_ bv3 32) main_~CCCELVOL2~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:57:32,902 INFO L273 TraceCheckUtils]: 15: Hoare triple {7591#(and (= (_ bv3 32) main_~CCCELVOL2~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (= (_ bv2 32) main_~i~0))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {7601#(and (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)))) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:57:32,904 INFO L273 TraceCheckUtils]: 16: Hoare triple {7601#(and (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)))) (= (_ bv2 32) main_~i~0))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {7605#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:57:32,905 INFO L273 TraceCheckUtils]: 17: Hoare triple {7605#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {7605#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:57:32,906 INFO L273 TraceCheckUtils]: 18: Hoare triple {7605#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume true; {7605#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:57:32,907 INFO L273 TraceCheckUtils]: 19: Hoare triple {7605#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {7605#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:57:32,908 INFO L273 TraceCheckUtils]: 20: Hoare triple {7605#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} ~i~0 := 0bv32; {7618#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:57:32,909 INFO L273 TraceCheckUtils]: 21: Hoare triple {7618#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume true; {7618#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:57:32,910 INFO L273 TraceCheckUtils]: 22: Hoare triple {7618#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {7618#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:57:32,910 INFO L273 TraceCheckUtils]: 23: Hoare triple {7618#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume #t~short6; {7618#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:57:32,914 INFO L256 TraceCheckUtils]: 24: Hoare triple {7618#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {7631#(exists ((|v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv12 32))))))} is VALID [2018-11-14 17:57:32,915 INFO L273 TraceCheckUtils]: 25: Hoare triple {7631#(exists ((|v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv12 32))))))} ~cond := #in~cond; {7631#(exists ((|v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv12 32))))))} is VALID [2018-11-14 17:57:32,915 INFO L273 TraceCheckUtils]: 26: Hoare triple {7631#(exists ((|v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv12 32))))))} assume !(~cond == 0bv32); {7631#(exists ((|v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv12 32))))))} is VALID [2018-11-14 17:57:32,916 INFO L273 TraceCheckUtils]: 27: Hoare triple {7631#(exists ((|v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv12 32))))))} assume true; {7631#(exists ((|v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv12 32))))))} is VALID [2018-11-14 17:57:32,916 INFO L268 TraceCheckUtils]: 28: Hoare quadruple {7631#(exists ((|v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv12 32))))))} {7618#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} #83#return; {7618#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:57:32,917 INFO L273 TraceCheckUtils]: 29: Hoare triple {7618#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {7618#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:57:32,918 INFO L273 TraceCheckUtils]: 30: Hoare triple {7618#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {7650#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:32,918 INFO L273 TraceCheckUtils]: 31: Hoare triple {7650#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {7650#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:32,919 INFO L273 TraceCheckUtils]: 32: Hoare triple {7650#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {7650#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:32,921 INFO L273 TraceCheckUtils]: 33: Hoare triple {7650#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {7650#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:32,924 INFO L256 TraceCheckUtils]: 34: Hoare triple {7650#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {7631#(exists ((|v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv12 32))))))} is VALID [2018-11-14 17:57:32,925 INFO L273 TraceCheckUtils]: 35: Hoare triple {7631#(exists ((|v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv12 32))))))} ~cond := #in~cond; {7631#(exists ((|v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv12 32))))))} is VALID [2018-11-14 17:57:32,926 INFO L273 TraceCheckUtils]: 36: Hoare triple {7631#(exists ((|v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv12 32))))))} assume !(~cond == 0bv32); {7631#(exists ((|v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv12 32))))))} is VALID [2018-11-14 17:57:32,926 INFO L273 TraceCheckUtils]: 37: Hoare triple {7631#(exists ((|v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv12 32))))))} assume true; {7631#(exists ((|v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv12 32))))))} is VALID [2018-11-14 17:57:32,927 INFO L268 TraceCheckUtils]: 38: Hoare quadruple {7631#(exists ((|v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (bvadd |v_main_~#volArray~0.offset_BEFORE_CALL_7| (_ bv12 32))))))} {7650#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #83#return; {7650#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:32,928 INFO L273 TraceCheckUtils]: 39: Hoare triple {7650#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {7650#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:32,929 INFO L273 TraceCheckUtils]: 40: Hoare triple {7650#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {7681#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:57:32,930 INFO L273 TraceCheckUtils]: 41: Hoare triple {7681#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~i~0))} assume true; {7681#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:57:32,933 INFO L273 TraceCheckUtils]: 42: Hoare triple {7681#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~i~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {7688#|main_#t~short6|} is VALID [2018-11-14 17:57:32,933 INFO L273 TraceCheckUtils]: 43: Hoare triple {7688#|main_#t~short6|} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {7547#false} is VALID [2018-11-14 17:57:32,934 INFO L256 TraceCheckUtils]: 44: Hoare triple {7547#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {7547#false} is VALID [2018-11-14 17:57:32,934 INFO L273 TraceCheckUtils]: 45: Hoare triple {7547#false} ~cond := #in~cond; {7547#false} is VALID [2018-11-14 17:57:32,934 INFO L273 TraceCheckUtils]: 46: Hoare triple {7547#false} assume ~cond == 0bv32; {7547#false} is VALID [2018-11-14 17:57:32,934 INFO L273 TraceCheckUtils]: 47: Hoare triple {7547#false} assume !false; {7547#false} is VALID [2018-11-14 17:57:32,942 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 6 proven. 21 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-14 17:57:32,942 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-14 17:57:35,378 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 15 [2018-11-14 17:57:35,439 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 3 [2018-11-14 17:57:35,441 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 17:57:35,462 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 3 xjuncts. [2018-11-14 17:57:35,498 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 3 xjuncts. [2018-11-14 17:57:35,498 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:17, output treesize:27 [2018-11-14 17:57:35,510 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:57:36,033 INFO L273 TraceCheckUtils]: 47: Hoare triple {7547#false} assume !false; {7547#false} is VALID [2018-11-14 17:57:36,034 INFO L273 TraceCheckUtils]: 46: Hoare triple {7547#false} assume ~cond == 0bv32; {7547#false} is VALID [2018-11-14 17:57:36,034 INFO L273 TraceCheckUtils]: 45: Hoare triple {7547#false} ~cond := #in~cond; {7547#false} is VALID [2018-11-14 17:57:36,034 INFO L256 TraceCheckUtils]: 44: Hoare triple {7547#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {7547#false} is VALID [2018-11-14 17:57:36,035 INFO L273 TraceCheckUtils]: 43: Hoare triple {7688#|main_#t~short6|} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {7547#false} is VALID [2018-11-14 17:57:36,036 INFO L273 TraceCheckUtils]: 42: Hoare triple {7719#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {7688#|main_#t~short6|} is VALID [2018-11-14 17:57:36,036 INFO L273 TraceCheckUtils]: 41: Hoare triple {7719#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume true; {7719#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:38,069 INFO L273 TraceCheckUtils]: 40: Hoare triple {7726#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {7719#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is UNKNOWN [2018-11-14 17:57:38,069 INFO L273 TraceCheckUtils]: 39: Hoare triple {7726#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {7726#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:38,070 INFO L268 TraceCheckUtils]: 38: Hoare quadruple {7546#true} {7726#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} #83#return; {7726#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:38,070 INFO L273 TraceCheckUtils]: 37: Hoare triple {7546#true} assume true; {7546#true} is VALID [2018-11-14 17:57:38,070 INFO L273 TraceCheckUtils]: 36: Hoare triple {7546#true} assume !(~cond == 0bv32); {7546#true} is VALID [2018-11-14 17:57:38,071 INFO L273 TraceCheckUtils]: 35: Hoare triple {7546#true} ~cond := #in~cond; {7546#true} is VALID [2018-11-14 17:57:38,071 INFO L256 TraceCheckUtils]: 34: Hoare triple {7726#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {7546#true} is VALID [2018-11-14 17:57:38,071 INFO L273 TraceCheckUtils]: 33: Hoare triple {7726#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {7726#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:38,071 INFO L273 TraceCheckUtils]: 32: Hoare triple {7726#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {7726#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:38,072 INFO L273 TraceCheckUtils]: 31: Hoare triple {7726#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} assume true; {7726#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:40,094 INFO L273 TraceCheckUtils]: 30: Hoare triple {7757#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {7726#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is UNKNOWN [2018-11-14 17:57:40,094 INFO L273 TraceCheckUtils]: 29: Hoare triple {7757#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {7757#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:40,095 INFO L268 TraceCheckUtils]: 28: Hoare quadruple {7546#true} {7757#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} #83#return; {7757#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:40,096 INFO L273 TraceCheckUtils]: 27: Hoare triple {7546#true} assume true; {7546#true} is VALID [2018-11-14 17:57:40,096 INFO L273 TraceCheckUtils]: 26: Hoare triple {7546#true} assume !(~cond == 0bv32); {7546#true} is VALID [2018-11-14 17:57:40,096 INFO L273 TraceCheckUtils]: 25: Hoare triple {7546#true} ~cond := #in~cond; {7546#true} is VALID [2018-11-14 17:57:40,096 INFO L256 TraceCheckUtils]: 24: Hoare triple {7757#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {7546#true} is VALID [2018-11-14 17:57:40,104 INFO L273 TraceCheckUtils]: 23: Hoare triple {7757#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} assume #t~short6; {7757#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:40,105 INFO L273 TraceCheckUtils]: 22: Hoare triple {7757#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {7757#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:40,109 INFO L273 TraceCheckUtils]: 21: Hoare triple {7757#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} assume true; {7757#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:40,109 INFO L273 TraceCheckUtils]: 20: Hoare triple {7788#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} ~i~0 := 0bv32; {7757#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:40,111 INFO L273 TraceCheckUtils]: 19: Hoare triple {7788#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {7788#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:40,111 INFO L273 TraceCheckUtils]: 18: Hoare triple {7788#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} assume true; {7788#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:40,113 INFO L273 TraceCheckUtils]: 17: Hoare triple {7788#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {7788#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:40,127 INFO L273 TraceCheckUtils]: 16: Hoare triple {7788#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {7788#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:40,152 INFO L273 TraceCheckUtils]: 15: Hoare triple {7804#(and (or (forall ((v_arrayElimCell_23 (_ BitVec 32))) (bvsge v_arrayElimCell_23 main_~MINVAL~0)) (= (_ bv16 32) (bvmul (_ bv8 32) main_~i~0))) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {7788#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:40,153 INFO L273 TraceCheckUtils]: 14: Hoare triple {7804#(and (or (forall ((v_arrayElimCell_23 (_ BitVec 32))) (bvsge v_arrayElimCell_23 main_~MINVAL~0)) (= (_ bv16 32) (bvmul (_ bv8 32) main_~i~0))) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {7804#(and (or (forall ((v_arrayElimCell_23 (_ BitVec 32))) (bvsge v_arrayElimCell_23 main_~MINVAL~0)) (= (_ bv16 32) (bvmul (_ bv8 32) main_~i~0))) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} is VALID [2018-11-14 17:57:40,156 INFO L273 TraceCheckUtils]: 13: Hoare triple {7804#(and (or (forall ((v_arrayElimCell_23 (_ BitVec 32))) (bvsge v_arrayElimCell_23 main_~MINVAL~0)) (= (_ bv16 32) (bvmul (_ bv8 32) main_~i~0))) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} assume true; {7804#(and (or (forall ((v_arrayElimCell_23 (_ BitVec 32))) (bvsge v_arrayElimCell_23 main_~MINVAL~0)) (= (_ bv16 32) (bvmul (_ bv8 32) main_~i~0))) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} is VALID [2018-11-14 17:57:40,162 INFO L273 TraceCheckUtils]: 12: Hoare triple {7814#(and (or (= (bvadd (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (forall ((v_arrayElimCell_23 (_ BitVec 32))) (bvsge v_arrayElimCell_23 main_~MINVAL~0))) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {7804#(and (or (forall ((v_arrayElimCell_23 (_ BitVec 32))) (bvsge v_arrayElimCell_23 main_~MINVAL~0)) (= (_ bv16 32) (bvmul (_ bv8 32) main_~i~0))) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} is VALID [2018-11-14 17:57:40,166 INFO L273 TraceCheckUtils]: 11: Hoare triple {7818#(and (or (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (or (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32))))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 1bv32))), 4bv32); {7814#(and (or (= (bvadd (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (forall ((v_arrayElimCell_23 (_ BitVec 32))) (bvsge v_arrayElimCell_23 main_~MINVAL~0))) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} is VALID [2018-11-14 17:57:40,193 INFO L273 TraceCheckUtils]: 10: Hoare triple {7822#(or (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))) (= (bvadd (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), 2bv32))), 4bv32); {7818#(and (or (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (or (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32))))} is VALID [2018-11-14 17:57:40,195 INFO L273 TraceCheckUtils]: 9: Hoare triple {7822#(or (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))) (= (bvadd (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {7822#(or (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))) (= (bvadd (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:40,195 INFO L273 TraceCheckUtils]: 8: Hoare triple {7822#(or (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))) (= (bvadd (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)))} assume true; {7822#(or (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))) (= (bvadd (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:40,197 INFO L273 TraceCheckUtils]: 7: Hoare triple {7546#true} assume !(~bvsrem32(~CELLCOUNT~0, 2bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 2bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {7822#(or (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))) (= (bvadd (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:40,197 INFO L273 TraceCheckUtils]: 6: Hoare triple {7546#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {7546#true} is VALID [2018-11-14 17:57:40,197 INFO L273 TraceCheckUtils]: 5: Hoare triple {7546#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {7546#true} is VALID [2018-11-14 17:57:40,197 INFO L256 TraceCheckUtils]: 4: Hoare triple {7546#true} call #t~ret7 := main(); {7546#true} is VALID [2018-11-14 17:57:40,197 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {7546#true} {7546#true} #79#return; {7546#true} is VALID [2018-11-14 17:57:40,197 INFO L273 TraceCheckUtils]: 2: Hoare triple {7546#true} assume true; {7546#true} is VALID [2018-11-14 17:57:40,197 INFO L273 TraceCheckUtils]: 1: Hoare triple {7546#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {7546#true} is VALID [2018-11-14 17:57:40,198 INFO L256 TraceCheckUtils]: 0: Hoare triple {7546#true} call ULTIMATE.init(); {7546#true} is VALID [2018-11-14 17:57:40,202 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 6 proven. 21 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-14 17:57:40,203 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-14 17:57:40,203 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 11] total 22 [2018-11-14 17:57:40,204 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 48 [2018-11-14 17:57:40,204 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:57:40,204 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 22 states.