java -ea -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector-Const.epf -i ../../../trunk/examples/svcomp/array-tiling/pr4_true-unreach-call.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-370d6ab [2018-11-14 17:56:13,542 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-14 17:56:13,544 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-14 17:56:13,564 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-14 17:56:13,565 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-14 17:56:13,566 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-14 17:56:13,567 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-14 17:56:13,570 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-14 17:56:13,572 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-14 17:56:13,573 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-14 17:56:13,582 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-14 17:56:13,583 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-14 17:56:13,584 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-14 17:56:13,585 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-14 17:56:13,588 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-14 17:56:13,589 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-14 17:56:13,590 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-14 17:56:13,594 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-14 17:56:13,600 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-14 17:56:13,603 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-14 17:56:13,604 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-14 17:56:13,606 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-14 17:56:13,608 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-14 17:56:13,608 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-14 17:56:13,610 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-14 17:56:13,611 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-14 17:56:13,612 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-14 17:56:13,613 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-14 17:56:13,613 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-14 17:56:13,617 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-14 17:56:13,618 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-14 17:56:13,618 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-14 17:56:13,618 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-14 17:56:13,620 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-14 17:56:13,621 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-14 17:56:13,622 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-14 17:56:13,623 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector-Const.epf [2018-11-14 17:56:13,654 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-14 17:56:13,654 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-14 17:56:13,655 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-14 17:56:13,655 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-11-14 17:56:13,657 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-14 17:56:13,657 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-14 17:56:13,657 INFO L133 SettingsManager]: * Use SBE=true [2018-11-14 17:56:13,658 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-14 17:56:13,659 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-14 17:56:13,659 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-14 17:56:13,659 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-14 17:56:13,659 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-14 17:56:13,659 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-14 17:56:13,660 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-14 17:56:13,660 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-14 17:56:13,660 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-14 17:56:13,660 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-14 17:56:13,660 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-14 17:56:13,660 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-14 17:56:13,662 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-14 17:56:13,662 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-14 17:56:13,662 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-14 17:56:13,662 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-14 17:56:13,662 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-14 17:56:13,663 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-14 17:56:13,663 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-14 17:56:13,663 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-14 17:56:13,663 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-14 17:56:13,664 INFO L133 SettingsManager]: * Trace refinement strategy=WOLF [2018-11-14 17:56:13,664 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-14 17:56:13,664 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-11-14 17:56:13,664 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-11-14 17:56:13,664 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-14 17:56:13,738 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-14 17:56:13,751 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-14 17:56:13,755 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-14 17:56:13,757 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-14 17:56:13,757 INFO L276 PluginConnector]: CDTParser initialized [2018-11-14 17:56:13,758 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-tiling/pr4_true-unreach-call.i [2018-11-14 17:56:13,819 INFO L218 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/379772375/683391bfce3a44f8acffdf8a4d53f9d8/FLAG055a211eb [2018-11-14 17:56:14,329 INFO L298 CDTParser]: Found 1 translation units. [2018-11-14 17:56:14,329 INFO L158 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-tiling/pr4_true-unreach-call.i [2018-11-14 17:56:14,338 INFO L346 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/379772375/683391bfce3a44f8acffdf8a4d53f9d8/FLAG055a211eb [2018-11-14 17:56:14,359 INFO L354 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/379772375/683391bfce3a44f8acffdf8a4d53f9d8 [2018-11-14 17:56:14,370 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-14 17:56:14,372 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-11-14 17:56:14,373 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-14 17:56:14,373 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-14 17:56:14,378 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-14 17:56:14,380 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.11 05:56:14" (1/1) ... [2018-11-14 17:56:14,383 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2518234d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:14, skipping insertion in model container [2018-11-14 17:56:14,383 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.11 05:56:14" (1/1) ... [2018-11-14 17:56:14,392 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-14 17:56:14,416 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-14 17:56:14,690 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-14 17:56:14,697 INFO L191 MainTranslator]: Completed pre-run [2018-11-14 17:56:14,747 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-14 17:56:14,784 INFO L195 MainTranslator]: Completed translation [2018-11-14 17:56:14,785 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:14 WrapperNode [2018-11-14 17:56:14,785 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-14 17:56:14,786 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-14 17:56:14,786 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-14 17:56:14,786 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-14 17:56:14,803 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:14" (1/1) ... [2018-11-14 17:56:14,804 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:14" (1/1) ... [2018-11-14 17:56:14,815 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:14" (1/1) ... [2018-11-14 17:56:14,817 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:14" (1/1) ... [2018-11-14 17:56:14,834 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:14" (1/1) ... [2018-11-14 17:56:14,847 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:14" (1/1) ... [2018-11-14 17:56:14,851 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:14" (1/1) ... [2018-11-14 17:56:14,854 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-14 17:56:14,855 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-14 17:56:14,855 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-14 17:56:14,855 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-14 17:56:14,856 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:14" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-14 17:56:14,979 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-14 17:56:14,979 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-14 17:56:14,979 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-11-14 17:56:14,979 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-14 17:56:14,980 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-11-14 17:56:14,980 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assume [2018-11-14 17:56:14,980 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-11-14 17:56:14,980 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-11-14 17:56:14,980 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-14 17:56:14,980 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-14 17:56:14,980 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-14 17:56:14,981 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE4 [2018-11-14 17:56:14,981 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE4 [2018-11-14 17:56:14,981 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-14 17:56:14,981 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-14 17:56:14,981 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~intINTTYPE4 [2018-11-14 17:56:15,791 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-14 17:56:15,792 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.11 05:56:15 BoogieIcfgContainer [2018-11-14 17:56:15,792 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-14 17:56:15,793 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-14 17:56:15,793 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-14 17:56:15,797 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-14 17:56:15,797 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 14.11 05:56:14" (1/3) ... [2018-11-14 17:56:15,798 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6b07b7dc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.11 05:56:15, skipping insertion in model container [2018-11-14 17:56:15,798 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:14" (2/3) ... [2018-11-14 17:56:15,799 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6b07b7dc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.11 05:56:15, skipping insertion in model container [2018-11-14 17:56:15,799 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.11 05:56:15" (3/3) ... [2018-11-14 17:56:15,801 INFO L112 eAbstractionObserver]: Analyzing ICFG pr4_true-unreach-call.i [2018-11-14 17:56:15,812 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-14 17:56:15,821 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-14 17:56:15,841 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-14 17:56:15,875 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-14 17:56:15,876 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-14 17:56:15,876 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-14 17:56:15,876 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-14 17:56:15,877 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-14 17:56:15,877 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-14 17:56:15,877 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-14 17:56:15,877 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-14 17:56:15,877 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-14 17:56:15,895 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states. [2018-11-14 17:56:15,901 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-14 17:56:15,902 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:56:15,902 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:56:15,905 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:56:15,911 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:56:15,912 INFO L82 PathProgramCache]: Analyzing trace with hash 1675708158, now seen corresponding path program 1 times [2018-11-14 17:56:15,918 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:56:15,918 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:56:15,939 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 17:56:16,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:16,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:16,062 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:56:16,164 INFO L256 TraceCheckUtils]: 0: Hoare triple {37#true} call ULTIMATE.init(); {37#true} is VALID [2018-11-14 17:56:16,168 INFO L273 TraceCheckUtils]: 1: Hoare triple {37#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {37#true} is VALID [2018-11-14 17:56:16,168 INFO L273 TraceCheckUtils]: 2: Hoare triple {37#true} assume true; {37#true} is VALID [2018-11-14 17:56:16,169 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {37#true} {37#true} #91#return; {37#true} is VALID [2018-11-14 17:56:16,169 INFO L256 TraceCheckUtils]: 4: Hoare triple {37#true} call #t~ret7 := main(); {37#true} is VALID [2018-11-14 17:56:16,169 INFO L273 TraceCheckUtils]: 5: Hoare triple {37#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {37#true} is VALID [2018-11-14 17:56:16,170 INFO L273 TraceCheckUtils]: 6: Hoare triple {37#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {37#true} is VALID [2018-11-14 17:56:16,170 INFO L273 TraceCheckUtils]: 7: Hoare triple {37#true} assume !(~bvsrem32(~CELLCOUNT~0, 4bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 4bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {37#true} is VALID [2018-11-14 17:56:16,171 INFO L273 TraceCheckUtils]: 8: Hoare triple {37#true} assume !true; {38#false} is VALID [2018-11-14 17:56:16,172 INFO L273 TraceCheckUtils]: 9: Hoare triple {38#false} ~i~0 := 0bv32; {38#false} is VALID [2018-11-14 17:56:16,172 INFO L273 TraceCheckUtils]: 10: Hoare triple {38#false} assume true; {38#false} is VALID [2018-11-14 17:56:16,172 INFO L273 TraceCheckUtils]: 11: Hoare triple {38#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {38#false} is VALID [2018-11-14 17:56:16,172 INFO L273 TraceCheckUtils]: 12: Hoare triple {38#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {38#false} is VALID [2018-11-14 17:56:16,173 INFO L256 TraceCheckUtils]: 13: Hoare triple {38#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {38#false} is VALID [2018-11-14 17:56:16,173 INFO L273 TraceCheckUtils]: 14: Hoare triple {38#false} ~cond := #in~cond; {38#false} is VALID [2018-11-14 17:56:16,173 INFO L273 TraceCheckUtils]: 15: Hoare triple {38#false} assume ~cond == 0bv32; {38#false} is VALID [2018-11-14 17:56:16,174 INFO L273 TraceCheckUtils]: 16: Hoare triple {38#false} assume !false; {38#false} is VALID [2018-11-14 17:56:16,178 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:16,178 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-14 17:56:16,193 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-14 17:56:16,193 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-14 17:56:16,199 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 17 [2018-11-14 17:56:16,202 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:56:16,206 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 2 states. [2018-11-14 17:56:16,288 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 17 edges. 17 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:16,288 INFO L459 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-11-14 17:56:16,296 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-11-14 17:56:16,297 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-14 17:56:16,299 INFO L87 Difference]: Start difference. First operand 34 states. Second operand 2 states. [2018-11-14 17:56:16,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:16,437 INFO L93 Difference]: Finished difference Result 53 states and 68 transitions. [2018-11-14 17:56:16,437 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-11-14 17:56:16,438 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 17 [2018-11-14 17:56:16,438 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:56:16,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2018-11-14 17:56:16,450 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 68 transitions. [2018-11-14 17:56:16,450 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2018-11-14 17:56:16,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 68 transitions. [2018-11-14 17:56:16,456 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 2 states and 68 transitions. [2018-11-14 17:56:16,771 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 68 edges. 68 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:16,783 INFO L225 Difference]: With dead ends: 53 [2018-11-14 17:56:16,784 INFO L226 Difference]: Without dead ends: 28 [2018-11-14 17:56:16,788 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 16 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-14 17:56:16,806 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2018-11-14 17:56:16,850 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 28. [2018-11-14 17:56:16,850 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:56:16,851 INFO L82 GeneralOperation]: Start isEquivalent. First operand 28 states. Second operand 28 states. [2018-11-14 17:56:16,851 INFO L74 IsIncluded]: Start isIncluded. First operand 28 states. Second operand 28 states. [2018-11-14 17:56:16,852 INFO L87 Difference]: Start difference. First operand 28 states. Second operand 28 states. [2018-11-14 17:56:16,856 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:16,857 INFO L93 Difference]: Finished difference Result 28 states and 34 transitions. [2018-11-14 17:56:16,857 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 34 transitions. [2018-11-14 17:56:16,858 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:16,858 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:16,858 INFO L74 IsIncluded]: Start isIncluded. First operand 28 states. Second operand 28 states. [2018-11-14 17:56:16,858 INFO L87 Difference]: Start difference. First operand 28 states. Second operand 28 states. [2018-11-14 17:56:16,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:16,863 INFO L93 Difference]: Finished difference Result 28 states and 34 transitions. [2018-11-14 17:56:16,864 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 34 transitions. [2018-11-14 17:56:16,864 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:16,865 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:16,865 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:56:16,865 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:56:16,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28 states. [2018-11-14 17:56:16,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 34 transitions. [2018-11-14 17:56:16,872 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 34 transitions. Word has length 17 [2018-11-14 17:56:16,872 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:56:16,873 INFO L480 AbstractCegarLoop]: Abstraction has 28 states and 34 transitions. [2018-11-14 17:56:16,873 INFO L481 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-11-14 17:56:16,873 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 34 transitions. [2018-11-14 17:56:16,874 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-11-14 17:56:16,874 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:56:16,874 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:56:16,875 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:56:16,876 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:56:16,876 INFO L82 PathProgramCache]: Analyzing trace with hash -391908819, now seen corresponding path program 1 times [2018-11-14 17:56:16,876 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:56:16,877 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:56:16,899 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 17:56:16,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:16,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:16,971 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:56:17,186 WARN L179 SmtUtils]: Spent 113.00 ms on a formula simplification that was a NOOP. DAG size: 12 [2018-11-14 17:56:17,406 INFO L256 TraceCheckUtils]: 0: Hoare triple {245#true} call ULTIMATE.init(); {245#true} is VALID [2018-11-14 17:56:17,407 INFO L273 TraceCheckUtils]: 1: Hoare triple {245#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {245#true} is VALID [2018-11-14 17:56:17,407 INFO L273 TraceCheckUtils]: 2: Hoare triple {245#true} assume true; {245#true} is VALID [2018-11-14 17:56:17,408 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {245#true} {245#true} #91#return; {245#true} is VALID [2018-11-14 17:56:17,408 INFO L256 TraceCheckUtils]: 4: Hoare triple {245#true} call #t~ret7 := main(); {245#true} is VALID [2018-11-14 17:56:17,408 INFO L273 TraceCheckUtils]: 5: Hoare triple {245#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {245#true} is VALID [2018-11-14 17:56:17,409 INFO L273 TraceCheckUtils]: 6: Hoare triple {245#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {268#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} is VALID [2018-11-14 17:56:17,411 INFO L273 TraceCheckUtils]: 7: Hoare triple {268#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} assume !(~bvsrem32(~CELLCOUNT~0, 4bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 4bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {272#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:17,412 INFO L273 TraceCheckUtils]: 8: Hoare triple {272#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {272#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:17,428 INFO L273 TraceCheckUtils]: 9: Hoare triple {272#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {246#false} is VALID [2018-11-14 17:56:17,429 INFO L273 TraceCheckUtils]: 10: Hoare triple {246#false} ~i~0 := 0bv32; {246#false} is VALID [2018-11-14 17:56:17,429 INFO L273 TraceCheckUtils]: 11: Hoare triple {246#false} assume true; {246#false} is VALID [2018-11-14 17:56:17,430 INFO L273 TraceCheckUtils]: 12: Hoare triple {246#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {246#false} is VALID [2018-11-14 17:56:17,430 INFO L273 TraceCheckUtils]: 13: Hoare triple {246#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {246#false} is VALID [2018-11-14 17:56:17,430 INFO L256 TraceCheckUtils]: 14: Hoare triple {246#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {246#false} is VALID [2018-11-14 17:56:17,431 INFO L273 TraceCheckUtils]: 15: Hoare triple {246#false} ~cond := #in~cond; {246#false} is VALID [2018-11-14 17:56:17,431 INFO L273 TraceCheckUtils]: 16: Hoare triple {246#false} assume ~cond == 0bv32; {246#false} is VALID [2018-11-14 17:56:17,432 INFO L273 TraceCheckUtils]: 17: Hoare triple {246#false} assume !false; {246#false} is VALID [2018-11-14 17:56:17,434 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:17,435 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-14 17:56:17,440 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-14 17:56:17,440 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-14 17:56:17,444 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 18 [2018-11-14 17:56:17,445 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:56:17,445 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states. [2018-11-14 17:56:17,590 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 18 edges. 18 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:17,590 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-14 17:56:17,591 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-14 17:56:17,591 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-14 17:56:17,591 INFO L87 Difference]: Start difference. First operand 28 states and 34 transitions. Second operand 4 states. [2018-11-14 17:56:18,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:18,473 INFO L93 Difference]: Finished difference Result 48 states and 60 transitions. [2018-11-14 17:56:18,473 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-14 17:56:18,473 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 18 [2018-11-14 17:56:18,474 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:56:18,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-14 17:56:18,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 60 transitions. [2018-11-14 17:56:18,478 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-14 17:56:18,481 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 60 transitions. [2018-11-14 17:56:18,481 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states and 60 transitions. [2018-11-14 17:56:18,670 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 60 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:18,672 INFO L225 Difference]: With dead ends: 48 [2018-11-14 17:56:18,673 INFO L226 Difference]: Without dead ends: 35 [2018-11-14 17:56:18,674 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 15 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-14 17:56:18,675 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states. [2018-11-14 17:56:18,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 30. [2018-11-14 17:56:18,701 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:56:18,701 INFO L82 GeneralOperation]: Start isEquivalent. First operand 35 states. Second operand 30 states. [2018-11-14 17:56:18,702 INFO L74 IsIncluded]: Start isIncluded. First operand 35 states. Second operand 30 states. [2018-11-14 17:56:18,702 INFO L87 Difference]: Start difference. First operand 35 states. Second operand 30 states. [2018-11-14 17:56:18,705 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:18,706 INFO L93 Difference]: Finished difference Result 35 states and 45 transitions. [2018-11-14 17:56:18,706 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 45 transitions. [2018-11-14 17:56:18,707 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:18,707 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:18,707 INFO L74 IsIncluded]: Start isIncluded. First operand 30 states. Second operand 35 states. [2018-11-14 17:56:18,707 INFO L87 Difference]: Start difference. First operand 30 states. Second operand 35 states. [2018-11-14 17:56:18,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:18,711 INFO L93 Difference]: Finished difference Result 35 states and 45 transitions. [2018-11-14 17:56:18,711 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 45 transitions. [2018-11-14 17:56:18,712 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:18,712 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:18,713 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:56:18,713 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:56:18,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-11-14 17:56:18,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 36 transitions. [2018-11-14 17:56:18,716 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 36 transitions. Word has length 18 [2018-11-14 17:56:18,716 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:56:18,716 INFO L480 AbstractCegarLoop]: Abstraction has 30 states and 36 transitions. [2018-11-14 17:56:18,716 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-14 17:56:18,716 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 36 transitions. [2018-11-14 17:56:18,717 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-11-14 17:56:18,717 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:56:18,718 INFO L375 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:56:18,718 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:56:18,718 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:56:18,718 INFO L82 PathProgramCache]: Analyzing trace with hash 721099660, now seen corresponding path program 1 times [2018-11-14 17:56:18,719 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:56:18,719 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:56:18,747 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 17:56:18,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:18,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:18,818 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:56:18,948 INFO L256 TraceCheckUtils]: 0: Hoare triple {471#true} call ULTIMATE.init(); {471#true} is VALID [2018-11-14 17:56:18,949 INFO L273 TraceCheckUtils]: 1: Hoare triple {471#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {471#true} is VALID [2018-11-14 17:56:18,949 INFO L273 TraceCheckUtils]: 2: Hoare triple {471#true} assume true; {471#true} is VALID [2018-11-14 17:56:18,949 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {471#true} {471#true} #91#return; {471#true} is VALID [2018-11-14 17:56:18,950 INFO L256 TraceCheckUtils]: 4: Hoare triple {471#true} call #t~ret7 := main(); {471#true} is VALID [2018-11-14 17:56:18,950 INFO L273 TraceCheckUtils]: 5: Hoare triple {471#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {471#true} is VALID [2018-11-14 17:56:18,951 INFO L273 TraceCheckUtils]: 6: Hoare triple {471#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {494#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv5 32) main_~CCCELVOL4~0))} is VALID [2018-11-14 17:56:18,953 INFO L273 TraceCheckUtils]: 7: Hoare triple {494#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv5 32) main_~CCCELVOL4~0))} assume !(~bvsrem32(~CELLCOUNT~0, 4bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 4bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {494#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv5 32) main_~CCCELVOL4~0))} is VALID [2018-11-14 17:56:18,954 INFO L273 TraceCheckUtils]: 8: Hoare triple {494#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv5 32) main_~CCCELVOL4~0))} assume true; {494#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv5 32) main_~CCCELVOL4~0))} is VALID [2018-11-14 17:56:18,956 INFO L273 TraceCheckUtils]: 9: Hoare triple {494#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv5 32) main_~CCCELVOL4~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {494#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv5 32) main_~CCCELVOL4~0))} is VALID [2018-11-14 17:56:18,957 INFO L273 TraceCheckUtils]: 10: Hoare triple {494#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv5 32) main_~CCCELVOL4~0))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {507#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv7 32) main_~CCCELVOL3~0))} is VALID [2018-11-14 17:56:18,961 INFO L273 TraceCheckUtils]: 11: Hoare triple {507#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv7 32) main_~CCCELVOL3~0))} assume !~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {472#false} is VALID [2018-11-14 17:56:18,961 INFO L273 TraceCheckUtils]: 12: Hoare triple {472#false} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {472#false} is VALID [2018-11-14 17:56:18,962 INFO L273 TraceCheckUtils]: 13: Hoare triple {472#false} assume ~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL1~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {472#false} is VALID [2018-11-14 17:56:18,962 INFO L273 TraceCheckUtils]: 14: Hoare triple {472#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {472#false} is VALID [2018-11-14 17:56:18,962 INFO L273 TraceCheckUtils]: 15: Hoare triple {472#false} assume true; {472#false} is VALID [2018-11-14 17:56:18,963 INFO L273 TraceCheckUtils]: 16: Hoare triple {472#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {472#false} is VALID [2018-11-14 17:56:18,963 INFO L273 TraceCheckUtils]: 17: Hoare triple {472#false} ~i~0 := 0bv32; {472#false} is VALID [2018-11-14 17:56:18,963 INFO L273 TraceCheckUtils]: 18: Hoare triple {472#false} assume true; {472#false} is VALID [2018-11-14 17:56:18,964 INFO L273 TraceCheckUtils]: 19: Hoare triple {472#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {472#false} is VALID [2018-11-14 17:56:18,964 INFO L273 TraceCheckUtils]: 20: Hoare triple {472#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {472#false} is VALID [2018-11-14 17:56:18,964 INFO L256 TraceCheckUtils]: 21: Hoare triple {472#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {472#false} is VALID [2018-11-14 17:56:18,965 INFO L273 TraceCheckUtils]: 22: Hoare triple {472#false} ~cond := #in~cond; {472#false} is VALID [2018-11-14 17:56:18,965 INFO L273 TraceCheckUtils]: 23: Hoare triple {472#false} assume ~cond == 0bv32; {472#false} is VALID [2018-11-14 17:56:18,965 INFO L273 TraceCheckUtils]: 24: Hoare triple {472#false} assume !false; {472#false} is VALID [2018-11-14 17:56:18,968 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:18,968 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-14 17:56:18,970 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-14 17:56:18,970 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-14 17:56:18,971 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 25 [2018-11-14 17:56:18,971 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:56:18,971 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states. [2018-11-14 17:56:19,067 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 25 edges. 25 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:19,068 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-14 17:56:19,068 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-14 17:56:19,069 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-14 17:56:19,069 INFO L87 Difference]: Start difference. First operand 30 states and 36 transitions. Second operand 4 states. [2018-11-14 17:56:19,546 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:19,546 INFO L93 Difference]: Finished difference Result 64 states and 83 transitions. [2018-11-14 17:56:19,546 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-14 17:56:19,546 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 25 [2018-11-14 17:56:19,547 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:56:19,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-14 17:56:19,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 81 transitions. [2018-11-14 17:56:19,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-14 17:56:19,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 81 transitions. [2018-11-14 17:56:19,555 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states and 81 transitions. [2018-11-14 17:56:19,795 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 81 edges. 81 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:19,798 INFO L225 Difference]: With dead ends: 64 [2018-11-14 17:56:19,799 INFO L226 Difference]: Without dead ends: 44 [2018-11-14 17:56:19,800 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 22 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-14 17:56:19,800 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2018-11-14 17:56:19,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 37. [2018-11-14 17:56:19,840 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:56:19,841 INFO L82 GeneralOperation]: Start isEquivalent. First operand 44 states. Second operand 37 states. [2018-11-14 17:56:19,841 INFO L74 IsIncluded]: Start isIncluded. First operand 44 states. Second operand 37 states. [2018-11-14 17:56:19,841 INFO L87 Difference]: Start difference. First operand 44 states. Second operand 37 states. [2018-11-14 17:56:19,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:19,846 INFO L93 Difference]: Finished difference Result 44 states and 55 transitions. [2018-11-14 17:56:19,846 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 55 transitions. [2018-11-14 17:56:19,847 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:19,847 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:19,847 INFO L74 IsIncluded]: Start isIncluded. First operand 37 states. Second operand 44 states. [2018-11-14 17:56:19,848 INFO L87 Difference]: Start difference. First operand 37 states. Second operand 44 states. [2018-11-14 17:56:19,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:19,852 INFO L93 Difference]: Finished difference Result 44 states and 55 transitions. [2018-11-14 17:56:19,855 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 55 transitions. [2018-11-14 17:56:19,856 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:19,856 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:19,856 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:56:19,856 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:56:19,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2018-11-14 17:56:19,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 46 transitions. [2018-11-14 17:56:19,862 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 46 transitions. Word has length 25 [2018-11-14 17:56:19,862 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:56:19,862 INFO L480 AbstractCegarLoop]: Abstraction has 37 states and 46 transitions. [2018-11-14 17:56:19,862 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-14 17:56:19,862 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 46 transitions. [2018-11-14 17:56:19,863 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-11-14 17:56:19,863 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:56:19,866 INFO L375 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:56:19,866 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:56:19,866 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:56:19,867 INFO L82 PathProgramCache]: Analyzing trace with hash 1732216910, now seen corresponding path program 1 times [2018-11-14 17:56:19,867 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:56:19,867 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:56:19,884 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 17:56:19,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:19,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:19,998 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:56:20,207 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-14 17:56:20,220 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-14 17:56:20,227 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:56:20,235 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:20,258 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:20,258 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:34, output treesize:30 [2018-11-14 17:56:20,355 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 26 [2018-11-14 17:56:20,366 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:56:20,373 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 41 [2018-11-14 17:56:20,381 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:56:20,393 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:20,425 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:20,426 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:48, output treesize:32 [2018-11-14 17:56:20,440 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:56:20,475 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 26 [2018-11-14 17:56:20,493 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:56:20,495 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:56:20,497 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 54 [2018-11-14 17:56:20,500 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:56:20,511 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:20,537 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:20,538 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:48, output treesize:41 [2018-11-14 17:56:20,637 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 27 [2018-11-14 17:56:20,648 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:56:20,653 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:56:20,654 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:56:20,655 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:56:20,656 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:56:20,660 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:56:20,662 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 82 [2018-11-14 17:56:20,667 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:56:20,696 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:20,718 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:20,718 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:43, output treesize:36 [2018-11-14 17:56:21,079 INFO L256 TraceCheckUtils]: 0: Hoare triple {766#true} call ULTIMATE.init(); {766#true} is VALID [2018-11-14 17:56:21,079 INFO L273 TraceCheckUtils]: 1: Hoare triple {766#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {766#true} is VALID [2018-11-14 17:56:21,080 INFO L273 TraceCheckUtils]: 2: Hoare triple {766#true} assume true; {766#true} is VALID [2018-11-14 17:56:21,080 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {766#true} {766#true} #91#return; {766#true} is VALID [2018-11-14 17:56:21,081 INFO L256 TraceCheckUtils]: 4: Hoare triple {766#true} call #t~ret7 := main(); {766#true} is VALID [2018-11-14 17:56:21,081 INFO L273 TraceCheckUtils]: 5: Hoare triple {766#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {766#true} is VALID [2018-11-14 17:56:21,083 INFO L273 TraceCheckUtils]: 6: Hoare triple {766#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {789#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:21,084 INFO L273 TraceCheckUtils]: 7: Hoare triple {789#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !(~bvsrem32(~CELLCOUNT~0, 4bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 4bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {793#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:21,084 INFO L273 TraceCheckUtils]: 8: Hoare triple {793#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {793#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:21,085 INFO L273 TraceCheckUtils]: 9: Hoare triple {793#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {793#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:21,088 INFO L273 TraceCheckUtils]: 10: Hoare triple {793#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {803#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:21,092 INFO L273 TraceCheckUtils]: 11: Hoare triple {803#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {803#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:21,095 INFO L273 TraceCheckUtils]: 12: Hoare triple {803#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {810#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:21,098 INFO L273 TraceCheckUtils]: 13: Hoare triple {810#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL1~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {814#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:56:21,101 INFO L273 TraceCheckUtils]: 14: Hoare triple {814#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {814#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:56:21,105 INFO L273 TraceCheckUtils]: 15: Hoare triple {814#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume true; {814#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:56:21,120 INFO L273 TraceCheckUtils]: 16: Hoare triple {814#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {814#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:56:21,121 INFO L273 TraceCheckUtils]: 17: Hoare triple {814#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} ~i~0 := 0bv32; {827#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:56:21,122 INFO L273 TraceCheckUtils]: 18: Hoare triple {827#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume true; {827#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:56:21,124 INFO L273 TraceCheckUtils]: 19: Hoare triple {827#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {834#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) |main_#t~short6| (= main_~i~0 (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:56:21,124 INFO L273 TraceCheckUtils]: 20: Hoare triple {834#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) |main_#t~short6| (= main_~i~0 (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {767#false} is VALID [2018-11-14 17:56:21,125 INFO L256 TraceCheckUtils]: 21: Hoare triple {767#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {767#false} is VALID [2018-11-14 17:56:21,125 INFO L273 TraceCheckUtils]: 22: Hoare triple {767#false} ~cond := #in~cond; {767#false} is VALID [2018-11-14 17:56:21,125 INFO L273 TraceCheckUtils]: 23: Hoare triple {767#false} assume ~cond == 0bv32; {767#false} is VALID [2018-11-14 17:56:21,126 INFO L273 TraceCheckUtils]: 24: Hoare triple {767#false} assume !false; {767#false} is VALID [2018-11-14 17:56:21,133 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:21,133 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-14 17:56:21,945 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 63 treesize of output 59 [2018-11-14 17:56:21,954 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 59 treesize of output 54 [2018-11-14 17:56:22,012 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 17:56:22,020 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 54 treesize of output 62 [2018-11-14 17:56:22,155 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 17:56:24,205 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (= (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) |main_~#volArray~0.offset|) [2018-11-14 17:56:24,208 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 17:56:24,222 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 17:56:24,229 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 17:56:24,230 INFO L303 Elim1Store]: Index analysis took 2079 ms [2018-11-14 17:56:24,231 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 5 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 42 [2018-11-14 17:56:24,235 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 17:56:24,270 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 17:56:24,287 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 17:56:24,305 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 17:56:24,369 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-14 17:56:24,370 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:75, output treesize:27 [2018-11-14 17:56:24,381 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:56:24,518 INFO L273 TraceCheckUtils]: 24: Hoare triple {767#false} assume !false; {767#false} is VALID [2018-11-14 17:56:24,519 INFO L273 TraceCheckUtils]: 23: Hoare triple {853#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} assume ~cond == 0bv32; {767#false} is VALID [2018-11-14 17:56:24,520 INFO L273 TraceCheckUtils]: 22: Hoare triple {857#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} ~cond := #in~cond; {853#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} is VALID [2018-11-14 17:56:24,521 INFO L256 TraceCheckUtils]: 21: Hoare triple {861#|main_#t~short6|} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {857#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-14 17:56:24,522 INFO L273 TraceCheckUtils]: 20: Hoare triple {865#(or |main_#t~short6| (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {861#|main_#t~short6|} is VALID [2018-11-14 17:56:24,525 INFO L273 TraceCheckUtils]: 19: Hoare triple {869#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {865#(or |main_#t~short6| (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} is VALID [2018-11-14 17:56:24,526 INFO L273 TraceCheckUtils]: 18: Hoare triple {869#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} assume true; {869#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} is VALID [2018-11-14 17:56:24,527 INFO L273 TraceCheckUtils]: 17: Hoare triple {876#(or (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0))} ~i~0 := 0bv32; {869#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} is VALID [2018-11-14 17:56:24,527 INFO L273 TraceCheckUtils]: 16: Hoare triple {876#(or (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {876#(or (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0))} is VALID [2018-11-14 17:56:24,528 INFO L273 TraceCheckUtils]: 15: Hoare triple {876#(or (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0))} assume true; {876#(or (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0))} is VALID [2018-11-14 17:56:24,528 INFO L273 TraceCheckUtils]: 14: Hoare triple {876#(or (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {876#(or (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0))} is VALID [2018-11-14 17:56:24,539 INFO L273 TraceCheckUtils]: 13: Hoare triple {889#(or (= (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) (_ bv0 32)) (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)))} assume ~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL1~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {876#(or (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0))} is VALID [2018-11-14 17:56:24,554 INFO L273 TraceCheckUtils]: 12: Hoare triple {893#(or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) (_ bv0 32)) (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) main_~MINVAL~0))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {889#(or (= (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) (_ bv0 32)) (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)))} is VALID [2018-11-14 17:56:24,568 INFO L273 TraceCheckUtils]: 11: Hoare triple {893#(or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) (_ bv0 32)) (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) main_~MINVAL~0))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {893#(or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) (_ bv0 32)) (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) main_~MINVAL~0))} is VALID [2018-11-14 17:56:24,612 INFO L273 TraceCheckUtils]: 10: Hoare triple {900#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_6 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_6 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_6))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {893#(or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) (_ bv0 32)) (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) main_~MINVAL~0))} is VALID [2018-11-14 17:56:24,613 INFO L273 TraceCheckUtils]: 9: Hoare triple {900#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_6 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_6 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_6))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {900#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_6 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_6 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_6))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:24,613 INFO L273 TraceCheckUtils]: 8: Hoare triple {900#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_6 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_6 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_6))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} assume true; {900#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_6 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_6 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_6))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:24,620 INFO L273 TraceCheckUtils]: 7: Hoare triple {766#true} assume !(~bvsrem32(~CELLCOUNT~0, 4bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 4bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {900#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_6 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_6 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_6))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:24,620 INFO L273 TraceCheckUtils]: 6: Hoare triple {766#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {766#true} is VALID [2018-11-14 17:56:24,620 INFO L273 TraceCheckUtils]: 5: Hoare triple {766#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {766#true} is VALID [2018-11-14 17:56:24,621 INFO L256 TraceCheckUtils]: 4: Hoare triple {766#true} call #t~ret7 := main(); {766#true} is VALID [2018-11-14 17:56:24,621 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {766#true} {766#true} #91#return; {766#true} is VALID [2018-11-14 17:56:24,621 INFO L273 TraceCheckUtils]: 2: Hoare triple {766#true} assume true; {766#true} is VALID [2018-11-14 17:56:24,622 INFO L273 TraceCheckUtils]: 1: Hoare triple {766#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {766#true} is VALID [2018-11-14 17:56:24,622 INFO L256 TraceCheckUtils]: 0: Hoare triple {766#true} call ULTIMATE.init(); {766#true} is VALID [2018-11-14 17:56:24,626 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:24,629 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-14 17:56:24,629 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 11] total 18 [2018-11-14 17:56:24,629 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 25 [2018-11-14 17:56:24,630 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:56:24,630 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 18 states. [2018-11-14 17:56:25,014 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 43 edges. 43 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:25,015 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-14 17:56:25,015 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-14 17:56:25,015 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=249, Unknown=0, NotChecked=0, Total=306 [2018-11-14 17:56:25,016 INFO L87 Difference]: Start difference. First operand 37 states and 46 transitions. Second operand 18 states. [2018-11-14 17:56:26,851 WARN L179 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 43 [2018-11-14 17:56:27,707 WARN L179 SmtUtils]: Spent 163.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 47 [2018-11-14 17:56:35,219 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:35,219 INFO L93 Difference]: Finished difference Result 136 states and 180 transitions. [2018-11-14 17:56:35,219 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-11-14 17:56:35,220 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 25 [2018-11-14 17:56:35,220 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:56:35,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2018-11-14 17:56:35,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 170 transitions. [2018-11-14 17:56:35,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2018-11-14 17:56:35,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 170 transitions. [2018-11-14 17:56:35,234 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 28 states and 170 transitions. [2018-11-14 17:56:36,320 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 170 edges. 170 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:36,327 INFO L225 Difference]: With dead ends: 136 [2018-11-14 17:56:36,327 INFO L226 Difference]: Without dead ends: 116 [2018-11-14 17:56:36,328 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 71 GetRequests, 32 SyntacticMatches, 1 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 268 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=343, Invalid=1217, Unknown=0, NotChecked=0, Total=1560 [2018-11-14 17:56:36,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states. [2018-11-14 17:56:36,477 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 70. [2018-11-14 17:56:36,477 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:56:36,477 INFO L82 GeneralOperation]: Start isEquivalent. First operand 116 states. Second operand 70 states. [2018-11-14 17:56:36,478 INFO L74 IsIncluded]: Start isIncluded. First operand 116 states. Second operand 70 states. [2018-11-14 17:56:36,478 INFO L87 Difference]: Start difference. First operand 116 states. Second operand 70 states. [2018-11-14 17:56:36,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:36,485 INFO L93 Difference]: Finished difference Result 116 states and 150 transitions. [2018-11-14 17:56:36,486 INFO L276 IsEmpty]: Start isEmpty. Operand 116 states and 150 transitions. [2018-11-14 17:56:36,487 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:36,487 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:36,487 INFO L74 IsIncluded]: Start isIncluded. First operand 70 states. Second operand 116 states. [2018-11-14 17:56:36,487 INFO L87 Difference]: Start difference. First operand 70 states. Second operand 116 states. [2018-11-14 17:56:36,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:36,494 INFO L93 Difference]: Finished difference Result 116 states and 150 transitions. [2018-11-14 17:56:36,495 INFO L276 IsEmpty]: Start isEmpty. Operand 116 states and 150 transitions. [2018-11-14 17:56:36,496 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:36,496 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:36,496 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:56:36,497 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:56:36,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-11-14 17:56:36,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 88 transitions. [2018-11-14 17:56:36,501 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 88 transitions. Word has length 25 [2018-11-14 17:56:36,501 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:56:36,501 INFO L480 AbstractCegarLoop]: Abstraction has 70 states and 88 transitions. [2018-11-14 17:56:36,501 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-14 17:56:36,501 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 88 transitions. [2018-11-14 17:56:36,503 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-11-14 17:56:36,503 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:56:36,503 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:56:36,503 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:56:36,503 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:56:36,504 INFO L82 PathProgramCache]: Analyzing trace with hash -500679399, now seen corresponding path program 1 times [2018-11-14 17:56:36,504 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:56:36,504 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:56:36,533 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 17:56:36,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:36,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:36,642 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:56:36,915 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-14 17:56:36,920 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-14 17:56:36,923 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:56:36,926 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:36,950 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:36,950 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:34, output treesize:30 [2018-11-14 17:56:37,010 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 24 [2018-11-14 17:56:37,019 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:56:37,021 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:56:37,023 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 52 [2018-11-14 17:56:37,024 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:56:37,036 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:37,065 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:37,065 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:46, output treesize:39 [2018-11-14 17:56:37,145 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 27 [2018-11-14 17:56:37,164 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:56:37,165 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:56:37,166 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:56:37,170 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:56:37,171 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:56:37,172 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:56:37,174 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 90 [2018-11-14 17:56:37,177 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:56:37,198 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:37,219 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:37,220 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:43, output treesize:36 [2018-11-14 17:56:37,845 INFO L256 TraceCheckUtils]: 0: Hoare triple {1465#true} call ULTIMATE.init(); {1465#true} is VALID [2018-11-14 17:56:37,846 INFO L273 TraceCheckUtils]: 1: Hoare triple {1465#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1465#true} is VALID [2018-11-14 17:56:37,846 INFO L273 TraceCheckUtils]: 2: Hoare triple {1465#true} assume true; {1465#true} is VALID [2018-11-14 17:56:37,846 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1465#true} {1465#true} #91#return; {1465#true} is VALID [2018-11-14 17:56:37,847 INFO L256 TraceCheckUtils]: 4: Hoare triple {1465#true} call #t~ret7 := main(); {1465#true} is VALID [2018-11-14 17:56:37,847 INFO L273 TraceCheckUtils]: 5: Hoare triple {1465#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1465#true} is VALID [2018-11-14 17:56:37,848 INFO L273 TraceCheckUtils]: 6: Hoare triple {1465#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {1488#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:37,849 INFO L273 TraceCheckUtils]: 7: Hoare triple {1488#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !(~bvsrem32(~CELLCOUNT~0, 4bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 4bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {1492#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:37,849 INFO L273 TraceCheckUtils]: 8: Hoare triple {1492#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {1492#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:37,850 INFO L273 TraceCheckUtils]: 9: Hoare triple {1492#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1492#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:37,851 INFO L273 TraceCheckUtils]: 10: Hoare triple {1492#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {1502#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:37,867 INFO L273 TraceCheckUtils]: 11: Hoare triple {1502#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {1506#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:37,870 INFO L273 TraceCheckUtils]: 12: Hoare triple {1506#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {1510#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:37,875 INFO L273 TraceCheckUtils]: 13: Hoare triple {1510#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL1~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {1514#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:37,877 INFO L273 TraceCheckUtils]: 14: Hoare triple {1514#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1514#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:37,878 INFO L273 TraceCheckUtils]: 15: Hoare triple {1514#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} assume true; {1514#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:37,892 INFO L273 TraceCheckUtils]: 16: Hoare triple {1514#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1514#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:37,894 INFO L273 TraceCheckUtils]: 17: Hoare triple {1514#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} ~i~0 := 0bv32; {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:37,898 INFO L273 TraceCheckUtils]: 18: Hoare triple {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} assume true; {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:37,900 INFO L273 TraceCheckUtils]: 19: Hoare triple {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:37,901 INFO L273 TraceCheckUtils]: 20: Hoare triple {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} assume #t~short6; {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:37,904 INFO L256 TraceCheckUtils]: 21: Hoare triple {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {1540#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} is VALID [2018-11-14 17:56:37,904 INFO L273 TraceCheckUtils]: 22: Hoare triple {1540#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} ~cond := #in~cond; {1540#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} is VALID [2018-11-14 17:56:37,905 INFO L273 TraceCheckUtils]: 23: Hoare triple {1540#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} assume !(~cond == 0bv32); {1540#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} is VALID [2018-11-14 17:56:37,906 INFO L273 TraceCheckUtils]: 24: Hoare triple {1540#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} assume true; {1540#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} is VALID [2018-11-14 17:56:37,907 INFO L268 TraceCheckUtils]: 25: Hoare quadruple {1540#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} #95#return; {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:37,908 INFO L273 TraceCheckUtils]: 26: Hoare triple {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:37,910 INFO L273 TraceCheckUtils]: 27: Hoare triple {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {1559#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:37,911 INFO L273 TraceCheckUtils]: 28: Hoare triple {1559#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {1559#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:37,913 INFO L273 TraceCheckUtils]: 29: Hoare triple {1559#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {1566#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) |main_#t~short6| (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:37,914 INFO L273 TraceCheckUtils]: 30: Hoare triple {1566#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) |main_#t~short6| (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {1466#false} is VALID [2018-11-14 17:56:37,915 INFO L256 TraceCheckUtils]: 31: Hoare triple {1466#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {1466#false} is VALID [2018-11-14 17:56:37,915 INFO L273 TraceCheckUtils]: 32: Hoare triple {1466#false} ~cond := #in~cond; {1466#false} is VALID [2018-11-14 17:56:37,915 INFO L273 TraceCheckUtils]: 33: Hoare triple {1466#false} assume ~cond == 0bv32; {1466#false} is VALID [2018-11-14 17:56:37,916 INFO L273 TraceCheckUtils]: 34: Hoare triple {1466#false} assume !false; {1466#false} is VALID [2018-11-14 17:56:37,925 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:37,925 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-14 17:56:38,796 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 67 treesize of output 63 [2018-11-14 17:56:38,819 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 63 treesize of output 58 [2018-11-14 17:56:38,834 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 17:56:38,839 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 66 [2018-11-14 17:56:38,984 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 17:56:38,985 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 17:56:38,997 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 17:56:39,012 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 37 treesize of output 48 [2018-11-14 17:56:39,020 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-14 17:56:39,084 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-14 17:56:39,109 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-14 17:56:39,134 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-14 17:56:39,179 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-14 17:56:39,179 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 2 variables, input treesize:75, output treesize:41 [2018-11-14 17:56:39,215 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:56:39,645 INFO L273 TraceCheckUtils]: 34: Hoare triple {1466#false} assume !false; {1466#false} is VALID [2018-11-14 17:56:39,646 INFO L273 TraceCheckUtils]: 33: Hoare triple {1585#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} assume ~cond == 0bv32; {1466#false} is VALID [2018-11-14 17:56:39,647 INFO L273 TraceCheckUtils]: 32: Hoare triple {1589#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} ~cond := #in~cond; {1585#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} is VALID [2018-11-14 17:56:39,648 INFO L256 TraceCheckUtils]: 31: Hoare triple {1593#|main_#t~short6|} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {1589#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-14 17:56:39,667 INFO L273 TraceCheckUtils]: 30: Hoare triple {1597#(or |main_#t~short6| (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {1593#|main_#t~short6|} is VALID [2018-11-14 17:56:39,683 INFO L273 TraceCheckUtils]: 29: Hoare triple {1601#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {1597#(or |main_#t~short6| (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} is VALID [2018-11-14 17:56:39,697 INFO L273 TraceCheckUtils]: 28: Hoare triple {1601#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} assume true; {1601#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} is VALID [2018-11-14 17:56:41,715 INFO L273 TraceCheckUtils]: 27: Hoare triple {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {1601#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} is UNKNOWN [2018-11-14 17:56:41,716 INFO L273 TraceCheckUtils]: 26: Hoare triple {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} is VALID [2018-11-14 17:56:41,717 INFO L268 TraceCheckUtils]: 25: Hoare quadruple {1465#true} {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} #95#return; {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} is VALID [2018-11-14 17:56:41,717 INFO L273 TraceCheckUtils]: 24: Hoare triple {1465#true} assume true; {1465#true} is VALID [2018-11-14 17:56:41,717 INFO L273 TraceCheckUtils]: 23: Hoare triple {1465#true} assume !(~cond == 0bv32); {1465#true} is VALID [2018-11-14 17:56:41,718 INFO L273 TraceCheckUtils]: 22: Hoare triple {1465#true} ~cond := #in~cond; {1465#true} is VALID [2018-11-14 17:56:41,718 INFO L256 TraceCheckUtils]: 21: Hoare triple {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {1465#true} is VALID [2018-11-14 17:56:41,718 INFO L273 TraceCheckUtils]: 20: Hoare triple {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} assume #t~short6; {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} is VALID [2018-11-14 17:56:41,719 INFO L273 TraceCheckUtils]: 19: Hoare triple {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} is VALID [2018-11-14 17:56:41,719 INFO L273 TraceCheckUtils]: 18: Hoare triple {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} assume true; {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} is VALID [2018-11-14 17:56:41,720 INFO L273 TraceCheckUtils]: 17: Hoare triple {1639#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} ~i~0 := 0bv32; {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} is VALID [2018-11-14 17:56:41,720 INFO L273 TraceCheckUtils]: 16: Hoare triple {1639#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1639#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:41,721 INFO L273 TraceCheckUtils]: 15: Hoare triple {1639#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume true; {1639#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:41,721 INFO L273 TraceCheckUtils]: 14: Hoare triple {1639#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1639#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:41,738 INFO L273 TraceCheckUtils]: 13: Hoare triple {1652#(or (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (= (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL1~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {1639#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:41,748 INFO L273 TraceCheckUtils]: 12: Hoare triple {1656#(or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (= (_ bv0 32) (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {1652#(or (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (= (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 17:56:41,776 INFO L273 TraceCheckUtils]: 11: Hoare triple {1660#(and (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= (_ bv0 32) main_~CCCELVOL3~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (forall ((v_arrayElimCell_11 (_ BitVec 32))) (or (bvsge v_arrayElimCell_11 main_~MINVAL~0) (= (_ bv0 32) v_arrayElimCell_11))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {1656#(or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (= (_ bv0 32) (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)))} is VALID [2018-11-14 17:56:42,007 INFO L273 TraceCheckUtils]: 10: Hoare triple {1664#(and (or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_11 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_11 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_11))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (or (forall ((v_prenex_3 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 v_prenex_3)) (not (bvsge main_~CCCELVOL4~0 v_prenex_3)) (bvsge main_~CCCELVOL3~0 v_prenex_3) (not (bvsge main_~CCCELVOL1~0 v_prenex_3)))) (= (_ bv0 32) main_~CCCELVOL3~0)))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {1660#(and (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= (_ bv0 32) main_~CCCELVOL3~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (forall ((v_arrayElimCell_11 (_ BitVec 32))) (or (bvsge v_arrayElimCell_11 main_~MINVAL~0) (= (_ bv0 32) v_arrayElimCell_11))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))))} is VALID [2018-11-14 17:56:42,008 INFO L273 TraceCheckUtils]: 9: Hoare triple {1664#(and (or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_11 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_11 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_11))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (or (forall ((v_prenex_3 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 v_prenex_3)) (not (bvsge main_~CCCELVOL4~0 v_prenex_3)) (bvsge main_~CCCELVOL3~0 v_prenex_3) (not (bvsge main_~CCCELVOL1~0 v_prenex_3)))) (= (_ bv0 32) main_~CCCELVOL3~0)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1664#(and (or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_11 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_11 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_11))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (or (forall ((v_prenex_3 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 v_prenex_3)) (not (bvsge main_~CCCELVOL4~0 v_prenex_3)) (bvsge main_~CCCELVOL3~0 v_prenex_3) (not (bvsge main_~CCCELVOL1~0 v_prenex_3)))) (= (_ bv0 32) main_~CCCELVOL3~0)))} is VALID [2018-11-14 17:56:42,009 INFO L273 TraceCheckUtils]: 8: Hoare triple {1664#(and (or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_11 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_11 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_11))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (or (forall ((v_prenex_3 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 v_prenex_3)) (not (bvsge main_~CCCELVOL4~0 v_prenex_3)) (bvsge main_~CCCELVOL3~0 v_prenex_3) (not (bvsge main_~CCCELVOL1~0 v_prenex_3)))) (= (_ bv0 32) main_~CCCELVOL3~0)))} assume true; {1664#(and (or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_11 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_11 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_11))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (or (forall ((v_prenex_3 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 v_prenex_3)) (not (bvsge main_~CCCELVOL4~0 v_prenex_3)) (bvsge main_~CCCELVOL3~0 v_prenex_3) (not (bvsge main_~CCCELVOL1~0 v_prenex_3)))) (= (_ bv0 32) main_~CCCELVOL3~0)))} is VALID [2018-11-14 17:56:42,010 INFO L273 TraceCheckUtils]: 7: Hoare triple {1674#(or (forall ((v_prenex_3 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 v_prenex_3)) (not (bvsge main_~CCCELVOL4~0 v_prenex_3)) (bvsge main_~CCCELVOL3~0 v_prenex_3) (not (bvsge main_~CCCELVOL1~0 v_prenex_3)))) (= (_ bv0 32) main_~CCCELVOL3~0))} assume !(~bvsrem32(~CELLCOUNT~0, 4bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 4bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {1664#(and (or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_11 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_11 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_11))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (or (forall ((v_prenex_3 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 v_prenex_3)) (not (bvsge main_~CCCELVOL4~0 v_prenex_3)) (bvsge main_~CCCELVOL3~0 v_prenex_3) (not (bvsge main_~CCCELVOL1~0 v_prenex_3)))) (= (_ bv0 32) main_~CCCELVOL3~0)))} is VALID [2018-11-14 17:56:42,013 INFO L273 TraceCheckUtils]: 6: Hoare triple {1465#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {1674#(or (forall ((v_prenex_3 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 v_prenex_3)) (not (bvsge main_~CCCELVOL4~0 v_prenex_3)) (bvsge main_~CCCELVOL3~0 v_prenex_3) (not (bvsge main_~CCCELVOL1~0 v_prenex_3)))) (= (_ bv0 32) main_~CCCELVOL3~0))} is VALID [2018-11-14 17:56:42,014 INFO L273 TraceCheckUtils]: 5: Hoare triple {1465#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1465#true} is VALID [2018-11-14 17:56:42,014 INFO L256 TraceCheckUtils]: 4: Hoare triple {1465#true} call #t~ret7 := main(); {1465#true} is VALID [2018-11-14 17:56:42,014 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1465#true} {1465#true} #91#return; {1465#true} is VALID [2018-11-14 17:56:42,015 INFO L273 TraceCheckUtils]: 2: Hoare triple {1465#true} assume true; {1465#true} is VALID [2018-11-14 17:56:42,015 INFO L273 TraceCheckUtils]: 1: Hoare triple {1465#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1465#true} is VALID [2018-11-14 17:56:42,015 INFO L256 TraceCheckUtils]: 0: Hoare triple {1465#true} call ULTIMATE.init(); {1465#true} is VALID [2018-11-14 17:56:42,022 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (6)] Exception during sending of exit command (exit): Broken pipe [2018-11-14 17:56:42,034 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-14 17:56:42,034 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 14] total 24 [2018-11-14 17:56:42,034 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 35 [2018-11-14 17:56:42,035 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:56:42,035 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 24 states. [2018-11-14 17:56:44,895 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 63 edges. 62 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:44,895 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-14 17:56:44,896 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-14 17:56:44,896 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=87, Invalid=465, Unknown=0, NotChecked=0, Total=552 [2018-11-14 17:56:44,897 INFO L87 Difference]: Start difference. First operand 70 states and 88 transitions. Second operand 24 states. [2018-11-14 17:56:46,313 WARN L179 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 38 DAG size of output: 33 [2018-11-14 17:56:47,286 WARN L179 SmtUtils]: Spent 121.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 39 [2018-11-14 17:56:47,573 WARN L179 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 38 [2018-11-14 17:56:47,834 WARN L179 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 42 DAG size of output: 37 [2018-11-14 17:56:48,049 WARN L179 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 36 [2018-11-14 17:56:52,965 WARN L179 SmtUtils]: Spent 202.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 46 [2018-11-14 17:57:01,355 WARN L179 SmtUtils]: Spent 145.00 ms on a formula simplification. DAG size of input: 45 DAG size of output: 40 [2018-11-14 17:57:06,433 WARN L179 SmtUtils]: Spent 405.00 ms on a formula simplification that was a NOOP. DAG size: 44 [2018-11-14 17:57:07,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:57:07,449 INFO L93 Difference]: Finished difference Result 190 states and 239 transitions. [2018-11-14 17:57:07,450 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-11-14 17:57:07,450 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 35 [2018-11-14 17:57:07,450 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:57:07,450 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-11-14 17:57:07,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 199 transitions. [2018-11-14 17:57:07,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-11-14 17:57:07,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 199 transitions. [2018-11-14 17:57:07,463 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 43 states and 199 transitions. [2018-11-14 17:57:13,530 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 199 edges. 197 inductive. 0 not inductive. 2 times theorem prover too weak to decide inductivity. [2018-11-14 17:57:13,536 INFO L225 Difference]: With dead ends: 190 [2018-11-14 17:57:13,536 INFO L226 Difference]: Without dead ends: 167 [2018-11-14 17:57:13,537 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 106 GetRequests, 47 SyntacticMatches, 1 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 796 ImplicationChecksByTransitivity, 6.7s TimeCoverageRelationStatistics Valid=671, Invalid=2869, Unknown=0, NotChecked=0, Total=3540 [2018-11-14 17:57:13,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 167 states. [2018-11-14 17:57:13,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 167 to 114. [2018-11-14 17:57:13,758 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:57:13,758 INFO L82 GeneralOperation]: Start isEquivalent. First operand 167 states. Second operand 114 states. [2018-11-14 17:57:13,758 INFO L74 IsIncluded]: Start isIncluded. First operand 167 states. Second operand 114 states. [2018-11-14 17:57:13,758 INFO L87 Difference]: Start difference. First operand 167 states. Second operand 114 states. [2018-11-14 17:57:13,766 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:57:13,767 INFO L93 Difference]: Finished difference Result 167 states and 210 transitions. [2018-11-14 17:57:13,767 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 210 transitions. [2018-11-14 17:57:13,768 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:57:13,769 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:57:13,769 INFO L74 IsIncluded]: Start isIncluded. First operand 114 states. Second operand 167 states. [2018-11-14 17:57:13,769 INFO L87 Difference]: Start difference. First operand 114 states. Second operand 167 states. [2018-11-14 17:57:13,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:57:13,776 INFO L93 Difference]: Finished difference Result 167 states and 210 transitions. [2018-11-14 17:57:13,777 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 210 transitions. [2018-11-14 17:57:13,778 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:57:13,778 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:57:13,778 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:57:13,778 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:57:13,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-11-14 17:57:13,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 137 transitions. [2018-11-14 17:57:13,784 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 137 transitions. Word has length 35 [2018-11-14 17:57:13,784 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:57:13,784 INFO L480 AbstractCegarLoop]: Abstraction has 114 states and 137 transitions. [2018-11-14 17:57:13,784 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-14 17:57:13,784 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 137 transitions. [2018-11-14 17:57:13,785 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-11-14 17:57:13,786 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:57:13,786 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:57:13,786 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:57:13,786 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:57:13,786 INFO L82 PathProgramCache]: Analyzing trace with hash -2037277082, now seen corresponding path program 1 times [2018-11-14 17:57:13,787 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:57:13,787 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:57:13,814 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 17:57:13,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:57:13,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:57:13,931 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:57:14,031 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-14 17:57:14,067 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-14 17:57:14,078 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:57:14,081 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:14,094 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:14,094 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:25, output treesize:21 [2018-11-14 17:57:14,148 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 26 [2018-11-14 17:57:14,155 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:57:14,158 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 41 [2018-11-14 17:57:14,161 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:57:14,170 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:14,189 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:14,189 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:39, output treesize:23 [2018-11-14 17:57:14,202 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:57:14,229 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 26 [2018-11-14 17:57:14,239 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:57:14,243 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 41 [2018-11-14 17:57:14,246 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:57:14,256 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:14,274 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:14,274 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:39, output treesize:23 [2018-11-14 17:57:14,286 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:57:14,299 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 18 [2018-11-14 17:57:14,307 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:57:14,308 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:57:14,309 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 33 [2018-11-14 17:57:14,317 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:57:14,327 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:14,337 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:14,337 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:26, output treesize:22 [2018-11-14 17:57:14,501 INFO L256 TraceCheckUtils]: 0: Hoare triple {2489#true} call ULTIMATE.init(); {2489#true} is VALID [2018-11-14 17:57:14,501 INFO L273 TraceCheckUtils]: 1: Hoare triple {2489#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {2489#true} is VALID [2018-11-14 17:57:14,501 INFO L273 TraceCheckUtils]: 2: Hoare triple {2489#true} assume true; {2489#true} is VALID [2018-11-14 17:57:14,502 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2489#true} {2489#true} #91#return; {2489#true} is VALID [2018-11-14 17:57:14,502 INFO L256 TraceCheckUtils]: 4: Hoare triple {2489#true} call #t~ret7 := main(); {2489#true} is VALID [2018-11-14 17:57:14,502 INFO L273 TraceCheckUtils]: 5: Hoare triple {2489#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {2489#true} is VALID [2018-11-14 17:57:14,503 INFO L273 TraceCheckUtils]: 6: Hoare triple {2489#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {2512#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:57:14,503 INFO L273 TraceCheckUtils]: 7: Hoare triple {2512#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !(~bvsrem32(~CELLCOUNT~0, 4bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 4bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {2516#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:14,505 INFO L273 TraceCheckUtils]: 8: Hoare triple {2516#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {2516#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:14,505 INFO L273 TraceCheckUtils]: 9: Hoare triple {2516#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {2516#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:14,514 INFO L273 TraceCheckUtils]: 10: Hoare triple {2516#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {2526#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:14,517 INFO L273 TraceCheckUtils]: 11: Hoare triple {2526#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {2526#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:14,522 INFO L273 TraceCheckUtils]: 12: Hoare triple {2526#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {2526#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:14,526 INFO L273 TraceCheckUtils]: 13: Hoare triple {2526#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {2536#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:57:14,527 INFO L273 TraceCheckUtils]: 14: Hoare triple {2536#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {2536#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:57:14,527 INFO L273 TraceCheckUtils]: 15: Hoare triple {2536#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume true; {2536#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:57:14,530 INFO L273 TraceCheckUtils]: 16: Hoare triple {2536#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {2536#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:57:14,530 INFO L273 TraceCheckUtils]: 17: Hoare triple {2536#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} ~i~0 := 0bv32; {2549#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:57:14,537 INFO L273 TraceCheckUtils]: 18: Hoare triple {2549#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume true; {2549#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:57:14,540 INFO L273 TraceCheckUtils]: 19: Hoare triple {2549#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {2549#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:57:14,542 INFO L273 TraceCheckUtils]: 20: Hoare triple {2549#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {2559#(not |main_#t~short6|)} is VALID [2018-11-14 17:57:14,542 INFO L256 TraceCheckUtils]: 21: Hoare triple {2559#(not |main_#t~short6|)} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {2489#true} is VALID [2018-11-14 17:57:14,542 INFO L273 TraceCheckUtils]: 22: Hoare triple {2489#true} ~cond := #in~cond; {2566#(= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)} is VALID [2018-11-14 17:57:14,548 INFO L273 TraceCheckUtils]: 23: Hoare triple {2566#(= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)} assume !(~cond == 0bv32); {2570#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-14 17:57:14,549 INFO L273 TraceCheckUtils]: 24: Hoare triple {2570#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} assume true; {2570#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-14 17:57:14,550 INFO L268 TraceCheckUtils]: 25: Hoare quadruple {2570#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} {2559#(not |main_#t~short6|)} #95#return; {2490#false} is VALID [2018-11-14 17:57:14,550 INFO L273 TraceCheckUtils]: 26: Hoare triple {2490#false} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {2490#false} is VALID [2018-11-14 17:57:14,550 INFO L273 TraceCheckUtils]: 27: Hoare triple {2490#false} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {2490#false} is VALID [2018-11-14 17:57:14,550 INFO L273 TraceCheckUtils]: 28: Hoare triple {2490#false} assume true; {2490#false} is VALID [2018-11-14 17:57:14,550 INFO L273 TraceCheckUtils]: 29: Hoare triple {2490#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {2490#false} is VALID [2018-11-14 17:57:14,550 INFO L273 TraceCheckUtils]: 30: Hoare triple {2490#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {2490#false} is VALID [2018-11-14 17:57:14,551 INFO L256 TraceCheckUtils]: 31: Hoare triple {2490#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {2490#false} is VALID [2018-11-14 17:57:14,551 INFO L273 TraceCheckUtils]: 32: Hoare triple {2490#false} ~cond := #in~cond; {2490#false} is VALID [2018-11-14 17:57:14,551 INFO L273 TraceCheckUtils]: 33: Hoare triple {2490#false} assume !(~cond == 0bv32); {2490#false} is VALID [2018-11-14 17:57:14,551 INFO L273 TraceCheckUtils]: 34: Hoare triple {2490#false} assume true; {2490#false} is VALID [2018-11-14 17:57:14,551 INFO L268 TraceCheckUtils]: 35: Hoare quadruple {2490#false} {2490#false} #95#return; {2490#false} is VALID [2018-11-14 17:57:14,551 INFO L273 TraceCheckUtils]: 36: Hoare triple {2490#false} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {2490#false} is VALID [2018-11-14 17:57:14,551 INFO L273 TraceCheckUtils]: 37: Hoare triple {2490#false} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {2490#false} is VALID [2018-11-14 17:57:14,552 INFO L273 TraceCheckUtils]: 38: Hoare triple {2490#false} assume true; {2490#false} is VALID [2018-11-14 17:57:14,552 INFO L273 TraceCheckUtils]: 39: Hoare triple {2490#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {2490#false} is VALID [2018-11-14 17:57:14,552 INFO L273 TraceCheckUtils]: 40: Hoare triple {2490#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {2490#false} is VALID [2018-11-14 17:57:14,552 INFO L256 TraceCheckUtils]: 41: Hoare triple {2490#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {2490#false} is VALID [2018-11-14 17:57:14,552 INFO L273 TraceCheckUtils]: 42: Hoare triple {2490#false} ~cond := #in~cond; {2490#false} is VALID [2018-11-14 17:57:14,552 INFO L273 TraceCheckUtils]: 43: Hoare triple {2490#false} assume ~cond == 0bv32; {2490#false} is VALID [2018-11-14 17:57:14,552 INFO L273 TraceCheckUtils]: 44: Hoare triple {2490#false} assume !false; {2490#false} is VALID [2018-11-14 17:57:14,556 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 2 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-11-14 17:57:14,557 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-14 17:57:15,008 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2018-11-14 17:57:15,036 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 7 [2018-11-14 17:57:15,037 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:57:15,048 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-14 17:57:15,056 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 2 xjuncts. [2018-11-14 17:57:15,056 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:12 [2018-11-14 17:57:15,061 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:57:15,130 INFO L273 TraceCheckUtils]: 44: Hoare triple {2490#false} assume !false; {2490#false} is VALID [2018-11-14 17:57:15,131 INFO L273 TraceCheckUtils]: 43: Hoare triple {2490#false} assume ~cond == 0bv32; {2490#false} is VALID [2018-11-14 17:57:15,131 INFO L273 TraceCheckUtils]: 42: Hoare triple {2490#false} ~cond := #in~cond; {2490#false} is VALID [2018-11-14 17:57:15,131 INFO L256 TraceCheckUtils]: 41: Hoare triple {2490#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {2490#false} is VALID [2018-11-14 17:57:15,132 INFO L273 TraceCheckUtils]: 40: Hoare triple {2490#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {2490#false} is VALID [2018-11-14 17:57:15,132 INFO L273 TraceCheckUtils]: 39: Hoare triple {2490#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {2490#false} is VALID [2018-11-14 17:57:15,132 INFO L273 TraceCheckUtils]: 38: Hoare triple {2490#false} assume true; {2490#false} is VALID [2018-11-14 17:57:15,133 INFO L273 TraceCheckUtils]: 37: Hoare triple {2490#false} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {2490#false} is VALID [2018-11-14 17:57:15,133 INFO L273 TraceCheckUtils]: 36: Hoare triple {2490#false} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {2490#false} is VALID [2018-11-14 17:57:15,133 INFO L268 TraceCheckUtils]: 35: Hoare quadruple {2489#true} {2490#false} #95#return; {2490#false} is VALID [2018-11-14 17:57:15,133 INFO L273 TraceCheckUtils]: 34: Hoare triple {2489#true} assume true; {2489#true} is VALID [2018-11-14 17:57:15,133 INFO L273 TraceCheckUtils]: 33: Hoare triple {2489#true} assume !(~cond == 0bv32); {2489#true} is VALID [2018-11-14 17:57:15,133 INFO L273 TraceCheckUtils]: 32: Hoare triple {2489#true} ~cond := #in~cond; {2489#true} is VALID [2018-11-14 17:57:15,134 INFO L256 TraceCheckUtils]: 31: Hoare triple {2490#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {2489#true} is VALID [2018-11-14 17:57:15,134 INFO L273 TraceCheckUtils]: 30: Hoare triple {2490#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {2490#false} is VALID [2018-11-14 17:57:15,134 INFO L273 TraceCheckUtils]: 29: Hoare triple {2490#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {2490#false} is VALID [2018-11-14 17:57:15,134 INFO L273 TraceCheckUtils]: 28: Hoare triple {2490#false} assume true; {2490#false} is VALID [2018-11-14 17:57:15,134 INFO L273 TraceCheckUtils]: 27: Hoare triple {2490#false} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {2490#false} is VALID [2018-11-14 17:57:15,134 INFO L273 TraceCheckUtils]: 26: Hoare triple {2490#false} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {2490#false} is VALID [2018-11-14 17:57:15,135 INFO L268 TraceCheckUtils]: 25: Hoare quadruple {2570#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} {2559#(not |main_#t~short6|)} #95#return; {2490#false} is VALID [2018-11-14 17:57:15,135 INFO L273 TraceCheckUtils]: 24: Hoare triple {2570#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} assume true; {2570#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-14 17:57:15,136 INFO L273 TraceCheckUtils]: 23: Hoare triple {2700#(or (= (_ bv0 32) __VERIFIER_assert_~cond) (not (= |__VERIFIER_assert_#in~cond| (_ bv0 32))))} assume !(~cond == 0bv32); {2570#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-14 17:57:15,136 INFO L273 TraceCheckUtils]: 22: Hoare triple {2489#true} ~cond := #in~cond; {2700#(or (= (_ bv0 32) __VERIFIER_assert_~cond) (not (= |__VERIFIER_assert_#in~cond| (_ bv0 32))))} is VALID [2018-11-14 17:57:15,136 INFO L256 TraceCheckUtils]: 21: Hoare triple {2559#(not |main_#t~short6|)} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {2489#true} is VALID [2018-11-14 17:57:15,138 INFO L273 TraceCheckUtils]: 20: Hoare triple {2707#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {2559#(not |main_#t~short6|)} is VALID [2018-11-14 17:57:15,138 INFO L273 TraceCheckUtils]: 19: Hoare triple {2707#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {2707#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} is VALID [2018-11-14 17:57:15,139 INFO L273 TraceCheckUtils]: 18: Hoare triple {2707#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} assume true; {2707#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} is VALID [2018-11-14 17:57:15,139 INFO L273 TraceCheckUtils]: 17: Hoare triple {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} ~i~0 := 0bv32; {2707#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} is VALID [2018-11-14 17:57:15,141 INFO L273 TraceCheckUtils]: 16: Hoare triple {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} is VALID [2018-11-14 17:57:15,145 INFO L273 TraceCheckUtils]: 15: Hoare triple {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} assume true; {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} is VALID [2018-11-14 17:57:15,148 INFO L273 TraceCheckUtils]: 14: Hoare triple {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} is VALID [2018-11-14 17:57:15,152 INFO L273 TraceCheckUtils]: 13: Hoare triple {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} is VALID [2018-11-14 17:57:15,155 INFO L273 TraceCheckUtils]: 12: Hoare triple {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} is VALID [2018-11-14 17:57:15,158 INFO L273 TraceCheckUtils]: 11: Hoare triple {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} is VALID [2018-11-14 17:57:15,160 INFO L273 TraceCheckUtils]: 10: Hoare triple {2739#(and (not (= (_ bv0 32) main_~CCCELVOL4~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} is VALID [2018-11-14 17:57:15,161 INFO L273 TraceCheckUtils]: 9: Hoare triple {2739#(and (not (= (_ bv0 32) main_~CCCELVOL4~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {2739#(and (not (= (_ bv0 32) main_~CCCELVOL4~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:15,162 INFO L273 TraceCheckUtils]: 8: Hoare triple {2739#(and (not (= (_ bv0 32) main_~CCCELVOL4~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} assume true; {2739#(and (not (= (_ bv0 32) main_~CCCELVOL4~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:15,163 INFO L273 TraceCheckUtils]: 7: Hoare triple {2749#(not (= (_ bv0 32) main_~CCCELVOL4~0))} assume !(~bvsrem32(~CELLCOUNT~0, 4bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 4bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {2739#(and (not (= (_ bv0 32) main_~CCCELVOL4~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:15,164 INFO L273 TraceCheckUtils]: 6: Hoare triple {2489#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {2749#(not (= (_ bv0 32) main_~CCCELVOL4~0))} is VALID [2018-11-14 17:57:15,164 INFO L273 TraceCheckUtils]: 5: Hoare triple {2489#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {2489#true} is VALID [2018-11-14 17:57:15,164 INFO L256 TraceCheckUtils]: 4: Hoare triple {2489#true} call #t~ret7 := main(); {2489#true} is VALID [2018-11-14 17:57:15,164 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2489#true} {2489#true} #91#return; {2489#true} is VALID [2018-11-14 17:57:15,165 INFO L273 TraceCheckUtils]: 2: Hoare triple {2489#true} assume true; {2489#true} is VALID [2018-11-14 17:57:15,165 INFO L273 TraceCheckUtils]: 1: Hoare triple {2489#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {2489#true} is VALID [2018-11-14 17:57:15,165 INFO L256 TraceCheckUtils]: 0: Hoare triple {2489#true} call ULTIMATE.init(); {2489#true} is VALID [2018-11-14 17:57:15,169 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 12 proven. 5 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-11-14 17:57:15,171 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-14 17:57:15,171 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 15 [2018-11-14 17:57:15,171 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 45 [2018-11-14 17:57:15,173 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:57:15,173 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 15 states. [2018-11-14 17:57:15,317 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 60 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:57:15,317 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-11-14 17:57:15,317 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-11-14 17:57:15,318 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=171, Unknown=0, NotChecked=0, Total=210 [2018-11-14 17:57:15,318 INFO L87 Difference]: Start difference. First operand 114 states and 137 transitions. Second operand 15 states. [2018-11-14 17:57:19,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:57:19,726 INFO L93 Difference]: Finished difference Result 204 states and 256 transitions. [2018-11-14 17:57:19,726 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-14 17:57:19,726 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 45 [2018-11-14 17:57:19,727 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:57:19,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2018-11-14 17:57:19,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 131 transitions. [2018-11-14 17:57:19,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2018-11-14 17:57:19,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 131 transitions. [2018-11-14 17:57:19,737 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 14 states and 131 transitions. [2018-11-14 17:57:20,135 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 131 edges. 131 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:57:20,140 INFO L225 Difference]: With dead ends: 204 [2018-11-14 17:57:20,140 INFO L226 Difference]: Without dead ends: 175 [2018-11-14 17:57:20,141 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 73 SyntacticMatches, 3 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 72 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=118, Invalid=434, Unknown=0, NotChecked=0, Total=552 [2018-11-14 17:57:20,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175 states. [2018-11-14 17:57:20,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175 to 125. [2018-11-14 17:57:20,455 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:57:20,455 INFO L82 GeneralOperation]: Start isEquivalent. First operand 175 states. Second operand 125 states. [2018-11-14 17:57:20,455 INFO L74 IsIncluded]: Start isIncluded. First operand 175 states. Second operand 125 states. [2018-11-14 17:57:20,455 INFO L87 Difference]: Start difference. First operand 175 states. Second operand 125 states. [2018-11-14 17:57:20,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:57:20,464 INFO L93 Difference]: Finished difference Result 175 states and 221 transitions. [2018-11-14 17:57:20,464 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 221 transitions. [2018-11-14 17:57:20,465 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:57:20,465 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:57:20,465 INFO L74 IsIncluded]: Start isIncluded. First operand 125 states. Second operand 175 states. [2018-11-14 17:57:20,466 INFO L87 Difference]: Start difference. First operand 125 states. Second operand 175 states. [2018-11-14 17:57:20,473 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:57:20,474 INFO L93 Difference]: Finished difference Result 175 states and 221 transitions. [2018-11-14 17:57:20,474 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 221 transitions. [2018-11-14 17:57:20,475 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:57:20,475 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:57:20,475 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:57:20,475 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:57:20,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2018-11-14 17:57:20,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 151 transitions. [2018-11-14 17:57:20,479 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 151 transitions. Word has length 45 [2018-11-14 17:57:20,479 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:57:20,480 INFO L480 AbstractCegarLoop]: Abstraction has 125 states and 151 transitions. [2018-11-14 17:57:20,480 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-11-14 17:57:20,480 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 151 transitions. [2018-11-14 17:57:20,481 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-11-14 17:57:20,481 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:57:20,481 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:57:20,481 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:57:20,481 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:57:20,482 INFO L82 PathProgramCache]: Analyzing trace with hash 2117141604, now seen corresponding path program 1 times [2018-11-14 17:57:20,482 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:57:20,482 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:57:20,501 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 17:57:20,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:57:20,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:57:20,627 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:57:20,744 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-14 17:57:20,754 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-14 17:57:20,756 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:57:20,761 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:20,781 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:20,782 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:34, output treesize:27 [2018-11-14 17:57:20,846 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 20 [2018-11-14 17:57:20,857 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:57:20,859 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:57:20,860 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 39 [2018-11-14 17:57:20,863 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:57:20,876 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:20,898 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:20,898 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:35, output treesize:31 [2018-11-14 17:57:21,365 INFO L256 TraceCheckUtils]: 0: Hoare triple {3567#true} call ULTIMATE.init(); {3567#true} is VALID [2018-11-14 17:57:21,366 INFO L273 TraceCheckUtils]: 1: Hoare triple {3567#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {3567#true} is VALID [2018-11-14 17:57:21,366 INFO L273 TraceCheckUtils]: 2: Hoare triple {3567#true} assume true; {3567#true} is VALID [2018-11-14 17:57:21,366 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {3567#true} {3567#true} #91#return; {3567#true} is VALID [2018-11-14 17:57:21,366 INFO L256 TraceCheckUtils]: 4: Hoare triple {3567#true} call #t~ret7 := main(); {3567#true} is VALID [2018-11-14 17:57:21,367 INFO L273 TraceCheckUtils]: 5: Hoare triple {3567#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {3567#true} is VALID [2018-11-14 17:57:21,368 INFO L273 TraceCheckUtils]: 6: Hoare triple {3567#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {3590#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:57:21,369 INFO L273 TraceCheckUtils]: 7: Hoare triple {3590#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !(~bvsrem32(~CELLCOUNT~0, 4bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 4bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {3594#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:21,369 INFO L273 TraceCheckUtils]: 8: Hoare triple {3594#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {3594#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:21,370 INFO L273 TraceCheckUtils]: 9: Hoare triple {3594#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3594#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:21,371 INFO L273 TraceCheckUtils]: 10: Hoare triple {3594#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {3604#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:21,372 INFO L273 TraceCheckUtils]: 11: Hoare triple {3604#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {3604#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:21,374 INFO L273 TraceCheckUtils]: 12: Hoare triple {3604#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {3611#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:21,377 INFO L273 TraceCheckUtils]: 13: Hoare triple {3611#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {3615#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:57:21,379 INFO L273 TraceCheckUtils]: 14: Hoare triple {3615#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3615#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:57:21,380 INFO L273 TraceCheckUtils]: 15: Hoare triple {3615#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume true; {3615#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:57:21,395 INFO L273 TraceCheckUtils]: 16: Hoare triple {3615#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3615#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:57:21,396 INFO L273 TraceCheckUtils]: 17: Hoare triple {3615#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} ~i~0 := 0bv32; {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:57:21,397 INFO L273 TraceCheckUtils]: 18: Hoare triple {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume true; {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:57:21,397 INFO L273 TraceCheckUtils]: 19: Hoare triple {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:57:21,398 INFO L273 TraceCheckUtils]: 20: Hoare triple {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume #t~short6; {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:57:21,400 INFO L256 TraceCheckUtils]: 21: Hoare triple {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} is VALID [2018-11-14 17:57:21,401 INFO L273 TraceCheckUtils]: 22: Hoare triple {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} ~cond := #in~cond; {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} is VALID [2018-11-14 17:57:21,401 INFO L273 TraceCheckUtils]: 23: Hoare triple {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} assume !(~cond == 0bv32); {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} is VALID [2018-11-14 17:57:21,402 INFO L273 TraceCheckUtils]: 24: Hoare triple {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} assume true; {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} is VALID [2018-11-14 17:57:21,403 INFO L268 TraceCheckUtils]: 25: Hoare quadruple {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} #95#return; {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:57:21,404 INFO L273 TraceCheckUtils]: 26: Hoare triple {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 17:57:21,405 INFO L273 TraceCheckUtils]: 27: Hoare triple {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:21,407 INFO L273 TraceCheckUtils]: 28: Hoare triple {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:21,409 INFO L273 TraceCheckUtils]: 29: Hoare triple {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:21,411 INFO L273 TraceCheckUtils]: 30: Hoare triple {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:21,414 INFO L256 TraceCheckUtils]: 31: Hoare triple {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} is VALID [2018-11-14 17:57:21,415 INFO L273 TraceCheckUtils]: 32: Hoare triple {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} ~cond := #in~cond; {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} is VALID [2018-11-14 17:57:21,415 INFO L273 TraceCheckUtils]: 33: Hoare triple {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} assume !(~cond == 0bv32); {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} is VALID [2018-11-14 17:57:21,415 INFO L273 TraceCheckUtils]: 34: Hoare triple {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} assume true; {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} is VALID [2018-11-14 17:57:21,416 INFO L268 TraceCheckUtils]: 35: Hoare quadruple {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #95#return; {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:21,417 INFO L273 TraceCheckUtils]: 36: Hoare triple {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:21,419 INFO L273 TraceCheckUtils]: 37: Hoare triple {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {3691#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:57:21,420 INFO L273 TraceCheckUtils]: 38: Hoare triple {3691#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~i~0))} assume true; {3691#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:57:21,421 INFO L273 TraceCheckUtils]: 39: Hoare triple {3691#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~i~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3698#|main_#t~short6|} is VALID [2018-11-14 17:57:21,423 INFO L273 TraceCheckUtils]: 40: Hoare triple {3698#|main_#t~short6|} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {3568#false} is VALID [2018-11-14 17:57:21,423 INFO L256 TraceCheckUtils]: 41: Hoare triple {3568#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3568#false} is VALID [2018-11-14 17:57:21,424 INFO L273 TraceCheckUtils]: 42: Hoare triple {3568#false} ~cond := #in~cond; {3568#false} is VALID [2018-11-14 17:57:21,424 INFO L273 TraceCheckUtils]: 43: Hoare triple {3568#false} assume ~cond == 0bv32; {3568#false} is VALID [2018-11-14 17:57:21,424 INFO L273 TraceCheckUtils]: 44: Hoare triple {3568#false} assume !false; {3568#false} is VALID [2018-11-14 17:57:21,432 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 6 proven. 14 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-14 17:57:21,432 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-14 17:57:21,889 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 23 [2018-11-14 17:57:21,897 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 27 [2018-11-14 17:57:24,090 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (= (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) [2018-11-14 17:57:24,096 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 17:57:24,097 INFO L303 Elim1Store]: Index analysis took 2130 ms [2018-11-14 17:57:24,097 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 17 [2018-11-14 17:57:24,100 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 17:57:24,123 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 17:57:24,136 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 17:57:24,158 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 17:57:24,159 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 2 variables, input treesize:33, output treesize:21 [2018-11-14 17:57:24,173 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:57:24,551 INFO L273 TraceCheckUtils]: 44: Hoare triple {3568#false} assume !false; {3568#false} is VALID [2018-11-14 17:57:24,551 INFO L273 TraceCheckUtils]: 43: Hoare triple {3568#false} assume ~cond == 0bv32; {3568#false} is VALID [2018-11-14 17:57:24,551 INFO L273 TraceCheckUtils]: 42: Hoare triple {3568#false} ~cond := #in~cond; {3568#false} is VALID [2018-11-14 17:57:24,551 INFO L256 TraceCheckUtils]: 41: Hoare triple {3568#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3568#false} is VALID [2018-11-14 17:57:24,552 INFO L273 TraceCheckUtils]: 40: Hoare triple {3698#|main_#t~short6|} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {3568#false} is VALID [2018-11-14 17:57:24,554 INFO L273 TraceCheckUtils]: 39: Hoare triple {3729#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3698#|main_#t~short6|} is VALID [2018-11-14 17:57:24,554 INFO L273 TraceCheckUtils]: 38: Hoare triple {3729#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume true; {3729#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:26,583 INFO L273 TraceCheckUtils]: 37: Hoare triple {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {3729#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is UNKNOWN [2018-11-14 17:57:26,584 INFO L273 TraceCheckUtils]: 36: Hoare triple {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:26,584 INFO L268 TraceCheckUtils]: 35: Hoare quadruple {3567#true} {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} #95#return; {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:26,584 INFO L273 TraceCheckUtils]: 34: Hoare triple {3567#true} assume true; {3567#true} is VALID [2018-11-14 17:57:26,585 INFO L273 TraceCheckUtils]: 33: Hoare triple {3567#true} assume !(~cond == 0bv32); {3567#true} is VALID [2018-11-14 17:57:26,585 INFO L273 TraceCheckUtils]: 32: Hoare triple {3567#true} ~cond := #in~cond; {3567#true} is VALID [2018-11-14 17:57:26,585 INFO L256 TraceCheckUtils]: 31: Hoare triple {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3567#true} is VALID [2018-11-14 17:57:26,585 INFO L273 TraceCheckUtils]: 30: Hoare triple {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:26,586 INFO L273 TraceCheckUtils]: 29: Hoare triple {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:26,586 INFO L273 TraceCheckUtils]: 28: Hoare triple {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} assume true; {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:28,604 INFO L273 TraceCheckUtils]: 27: Hoare triple {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is UNKNOWN [2018-11-14 17:57:28,605 INFO L273 TraceCheckUtils]: 26: Hoare triple {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:28,606 INFO L268 TraceCheckUtils]: 25: Hoare quadruple {3567#true} {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} #95#return; {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:28,606 INFO L273 TraceCheckUtils]: 24: Hoare triple {3567#true} assume true; {3567#true} is VALID [2018-11-14 17:57:28,606 INFO L273 TraceCheckUtils]: 23: Hoare triple {3567#true} assume !(~cond == 0bv32); {3567#true} is VALID [2018-11-14 17:57:28,606 INFO L273 TraceCheckUtils]: 22: Hoare triple {3567#true} ~cond := #in~cond; {3567#true} is VALID [2018-11-14 17:57:28,607 INFO L256 TraceCheckUtils]: 21: Hoare triple {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3567#true} is VALID [2018-11-14 17:57:28,607 INFO L273 TraceCheckUtils]: 20: Hoare triple {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} assume #t~short6; {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:28,607 INFO L273 TraceCheckUtils]: 19: Hoare triple {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:28,608 INFO L273 TraceCheckUtils]: 18: Hoare triple {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} assume true; {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:28,608 INFO L273 TraceCheckUtils]: 17: Hoare triple {3798#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} ~i~0 := 0bv32; {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:28,609 INFO L273 TraceCheckUtils]: 16: Hoare triple {3798#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3798#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:28,609 INFO L273 TraceCheckUtils]: 15: Hoare triple {3798#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} assume true; {3798#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:28,609 INFO L273 TraceCheckUtils]: 14: Hoare triple {3798#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3798#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:28,619 INFO L273 TraceCheckUtils]: 13: Hoare triple {3811#(or (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {3798#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 17:57:28,641 INFO L273 TraceCheckUtils]: 12: Hoare triple {3815#(or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {3811#(or (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0))} is VALID [2018-11-14 17:57:28,642 INFO L273 TraceCheckUtils]: 11: Hoare triple {3815#(or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {3815#(or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:28,696 INFO L273 TraceCheckUtils]: 10: Hoare triple {3822#(or (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {3815#(or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:28,696 INFO L273 TraceCheckUtils]: 9: Hoare triple {3822#(or (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3822#(or (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:28,697 INFO L273 TraceCheckUtils]: 8: Hoare triple {3822#(or (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} assume true; {3822#(or (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:28,697 INFO L273 TraceCheckUtils]: 7: Hoare triple {3567#true} assume !(~bvsrem32(~CELLCOUNT~0, 4bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 4bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {3822#(or (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:28,698 INFO L273 TraceCheckUtils]: 6: Hoare triple {3567#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {3567#true} is VALID [2018-11-14 17:57:28,698 INFO L273 TraceCheckUtils]: 5: Hoare triple {3567#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {3567#true} is VALID [2018-11-14 17:57:28,698 INFO L256 TraceCheckUtils]: 4: Hoare triple {3567#true} call #t~ret7 := main(); {3567#true} is VALID [2018-11-14 17:57:28,698 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {3567#true} {3567#true} #91#return; {3567#true} is VALID [2018-11-14 17:57:28,698 INFO L273 TraceCheckUtils]: 2: Hoare triple {3567#true} assume true; {3567#true} is VALID [2018-11-14 17:57:28,698 INFO L273 TraceCheckUtils]: 1: Hoare triple {3567#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {3567#true} is VALID [2018-11-14 17:57:28,698 INFO L256 TraceCheckUtils]: 0: Hoare triple {3567#true} call ULTIMATE.init(); {3567#true} is VALID [2018-11-14 17:57:28,702 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 6 proven. 14 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-14 17:57:28,704 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-14 17:57:28,704 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 10] total 19 [2018-11-14 17:57:28,705 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 45 [2018-11-14 17:57:28,705 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:57:28,705 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 19 states. [2018-11-14 17:57:33,156 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 73 edges. 71 inductive. 0 not inductive. 2 times theorem prover too weak to decide inductivity. [2018-11-14 17:57:33,157 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-11-14 17:57:33,157 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-11-14 17:57:33,157 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=276, Unknown=0, NotChecked=0, Total=342 [2018-11-14 17:57:33,157 INFO L87 Difference]: Start difference. First operand 125 states and 151 transitions. Second operand 19 states.