java -ea -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector-Const.epf -i ../../../trunk/examples/svcomp/array-tiling/rewrev_true-unreach-call.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-370d6ab [2018-11-14 17:56:34,535 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-14 17:56:34,538 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-14 17:56:34,555 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-14 17:56:34,555 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-14 17:56:34,557 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-14 17:56:34,558 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-14 17:56:34,561 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-14 17:56:34,563 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-14 17:56:34,565 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-14 17:56:34,566 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-14 17:56:34,568 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-14 17:56:34,569 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-14 17:56:34,572 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-14 17:56:34,580 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-14 17:56:34,581 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-14 17:56:34,582 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-14 17:56:34,583 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-14 17:56:34,587 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-14 17:56:34,589 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-14 17:56:34,592 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-14 17:56:34,594 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-14 17:56:34,598 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-14 17:56:34,598 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-14 17:56:34,598 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-14 17:56:34,599 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-14 17:56:34,600 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-14 17:56:34,601 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-14 17:56:34,602 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-14 17:56:34,605 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-14 17:56:34,605 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-14 17:56:34,606 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-14 17:56:34,606 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-14 17:56:34,606 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-14 17:56:34,608 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-14 17:56:34,609 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-14 17:56:34,609 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector-Const.epf [2018-11-14 17:56:34,636 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-14 17:56:34,637 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-14 17:56:34,641 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-14 17:56:34,641 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-11-14 17:56:34,642 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-14 17:56:34,642 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-14 17:56:34,643 INFO L133 SettingsManager]: * Use SBE=true [2018-11-14 17:56:34,643 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-14 17:56:34,643 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-14 17:56:34,643 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-14 17:56:34,643 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-14 17:56:34,644 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-14 17:56:34,644 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-14 17:56:34,644 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-14 17:56:34,644 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-14 17:56:34,644 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-14 17:56:34,645 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-14 17:56:34,645 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-14 17:56:34,645 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-14 17:56:34,645 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-14 17:56:34,645 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-14 17:56:34,646 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-14 17:56:34,646 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-14 17:56:34,646 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-14 17:56:34,646 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-14 17:56:34,646 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-14 17:56:34,646 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-14 17:56:34,647 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-14 17:56:34,647 INFO L133 SettingsManager]: * Trace refinement strategy=WOLF [2018-11-14 17:56:34,647 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-14 17:56:34,647 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-11-14 17:56:34,647 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-11-14 17:56:34,648 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-14 17:56:34,690 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-14 17:56:34,707 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-14 17:56:34,712 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-14 17:56:34,713 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-14 17:56:34,714 INFO L276 PluginConnector]: CDTParser initialized [2018-11-14 17:56:34,714 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-tiling/rewrev_true-unreach-call.i [2018-11-14 17:56:34,792 INFO L218 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4cf855d56/55350cbd5c0147778de4ddc93b000104/FLAG88142032d [2018-11-14 17:56:35,247 INFO L298 CDTParser]: Found 1 translation units. [2018-11-14 17:56:35,248 INFO L158 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-tiling/rewrev_true-unreach-call.i [2018-11-14 17:56:35,255 INFO L346 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4cf855d56/55350cbd5c0147778de4ddc93b000104/FLAG88142032d [2018-11-14 17:56:35,273 INFO L354 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4cf855d56/55350cbd5c0147778de4ddc93b000104 [2018-11-14 17:56:35,284 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-14 17:56:35,285 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-11-14 17:56:35,286 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-14 17:56:35,287 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-14 17:56:35,290 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-14 17:56:35,292 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.11 05:56:35" (1/1) ... [2018-11-14 17:56:35,295 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1747d2e2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:35, skipping insertion in model container [2018-11-14 17:56:35,295 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.11 05:56:35" (1/1) ... [2018-11-14 17:56:35,306 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-14 17:56:35,329 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-14 17:56:35,617 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-14 17:56:35,625 INFO L191 MainTranslator]: Completed pre-run [2018-11-14 17:56:35,660 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-14 17:56:35,685 INFO L195 MainTranslator]: Completed translation [2018-11-14 17:56:35,685 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:35 WrapperNode [2018-11-14 17:56:35,686 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-14 17:56:35,686 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-14 17:56:35,687 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-14 17:56:35,687 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-14 17:56:35,702 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:35" (1/1) ... [2018-11-14 17:56:35,702 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:35" (1/1) ... [2018-11-14 17:56:35,712 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:35" (1/1) ... [2018-11-14 17:56:35,713 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:35" (1/1) ... [2018-11-14 17:56:35,728 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:35" (1/1) ... [2018-11-14 17:56:35,737 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:35" (1/1) ... [2018-11-14 17:56:35,739 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:35" (1/1) ... [2018-11-14 17:56:35,742 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-14 17:56:35,742 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-14 17:56:35,743 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-14 17:56:35,743 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-14 17:56:35,744 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:35" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-14 17:56:35,871 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-14 17:56:35,871 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-14 17:56:35,871 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-11-14 17:56:35,871 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-14 17:56:35,872 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-11-14 17:56:35,872 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assume [2018-11-14 17:56:35,872 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-11-14 17:56:35,872 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-11-14 17:56:35,872 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-14 17:56:35,872 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-14 17:56:35,872 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE4 [2018-11-14 17:56:35,873 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE4 [2018-11-14 17:56:35,873 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-14 17:56:35,873 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-14 17:56:35,873 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-14 17:56:35,873 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~intINTTYPE4 [2018-11-14 17:56:36,445 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-14 17:56:36,446 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.11 05:56:36 BoogieIcfgContainer [2018-11-14 17:56:36,447 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-14 17:56:36,448 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-14 17:56:36,448 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-14 17:56:36,451 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-14 17:56:36,452 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 14.11 05:56:35" (1/3) ... [2018-11-14 17:56:36,452 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3cb3d3a6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.11 05:56:36, skipping insertion in model container [2018-11-14 17:56:36,453 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 05:56:35" (2/3) ... [2018-11-14 17:56:36,453 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3cb3d3a6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.11 05:56:36, skipping insertion in model container [2018-11-14 17:56:36,453 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.11 05:56:36" (3/3) ... [2018-11-14 17:56:36,455 INFO L112 eAbstractionObserver]: Analyzing ICFG rewrev_true-unreach-call.i [2018-11-14 17:56:36,466 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-14 17:56:36,476 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-14 17:56:36,494 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-14 17:56:36,527 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-14 17:56:36,528 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-14 17:56:36,528 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-14 17:56:36,528 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-14 17:56:36,528 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-14 17:56:36,530 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-14 17:56:36,530 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-14 17:56:36,530 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-14 17:56:36,530 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-14 17:56:36,551 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states. [2018-11-14 17:56:36,558 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-11-14 17:56:36,558 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:56:36,559 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:56:36,562 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:56:36,568 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:56:36,569 INFO L82 PathProgramCache]: Analyzing trace with hash -780591074, now seen corresponding path program 1 times [2018-11-14 17:56:36,574 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:56:36,574 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:56:36,596 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 17:56:36,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:36,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:36,674 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:56:36,904 INFO L256 TraceCheckUtils]: 0: Hoare triple {33#true} call ULTIMATE.init(); {33#true} is VALID [2018-11-14 17:56:36,908 INFO L273 TraceCheckUtils]: 1: Hoare triple {33#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {33#true} is VALID [2018-11-14 17:56:36,909 INFO L273 TraceCheckUtils]: 2: Hoare triple {33#true} assume true; {33#true} is VALID [2018-11-14 17:56:36,910 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {33#true} {33#true} #65#return; {33#true} is VALID [2018-11-14 17:56:36,910 INFO L256 TraceCheckUtils]: 4: Hoare triple {33#true} call #t~ret5 := main(); {33#true} is VALID [2018-11-14 17:56:36,911 INFO L273 TraceCheckUtils]: 5: Hoare triple {33#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1; {33#true} is VALID [2018-11-14 17:56:36,911 INFO L273 TraceCheckUtils]: 6: Hoare triple {33#true} assume ~bvsgt32(~SIZE~0, 1bv32);havoc ~i~0;call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~val2~0 := 3bv32;~val1~0 := 7bv32;~low~0 := 2bv32;~i~0 := ~bvsub32(~SIZE~0, 2bv32); {33#true} is VALID [2018-11-14 17:56:36,925 INFO L273 TraceCheckUtils]: 7: Hoare triple {33#true} assume !true; {34#false} is VALID [2018-11-14 17:56:36,925 INFO L273 TraceCheckUtils]: 8: Hoare triple {34#false} ~i~0 := 0bv32; {34#false} is VALID [2018-11-14 17:56:36,926 INFO L273 TraceCheckUtils]: 9: Hoare triple {34#false} assume true; {34#false} is VALID [2018-11-14 17:56:36,926 INFO L273 TraceCheckUtils]: 10: Hoare triple {34#false} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {34#false} is VALID [2018-11-14 17:56:36,926 INFO L256 TraceCheckUtils]: 11: Hoare triple {34#false} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {34#false} is VALID [2018-11-14 17:56:36,927 INFO L273 TraceCheckUtils]: 12: Hoare triple {34#false} ~cond := #in~cond; {34#false} is VALID [2018-11-14 17:56:36,927 INFO L273 TraceCheckUtils]: 13: Hoare triple {34#false} assume ~cond == 0bv32; {34#false} is VALID [2018-11-14 17:56:36,927 INFO L273 TraceCheckUtils]: 14: Hoare triple {34#false} assume !false; {34#false} is VALID [2018-11-14 17:56:36,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:36,933 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-14 17:56:36,939 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-14 17:56:36,939 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-14 17:56:36,945 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 15 [2018-11-14 17:56:36,948 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:56:36,951 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 2 states. [2018-11-14 17:56:37,072 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 15 edges. 15 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:37,072 INFO L459 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-11-14 17:56:37,080 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-11-14 17:56:37,081 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-14 17:56:37,083 INFO L87 Difference]: Start difference. First operand 30 states. Second operand 2 states. [2018-11-14 17:56:37,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:37,224 INFO L93 Difference]: Finished difference Result 48 states and 57 transitions. [2018-11-14 17:56:37,224 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-11-14 17:56:37,224 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 15 [2018-11-14 17:56:37,225 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:56:37,226 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2018-11-14 17:56:37,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 57 transitions. [2018-11-14 17:56:37,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2018-11-14 17:56:37,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 57 transitions. [2018-11-14 17:56:37,242 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 2 states and 57 transitions. [2018-11-14 17:56:37,515 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 57 edges. 57 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:37,527 INFO L225 Difference]: With dead ends: 48 [2018-11-14 17:56:37,528 INFO L226 Difference]: Without dead ends: 24 [2018-11-14 17:56:37,532 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 14 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-14 17:56:37,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states. [2018-11-14 17:56:37,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 24. [2018-11-14 17:56:37,576 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:56:37,576 INFO L82 GeneralOperation]: Start isEquivalent. First operand 24 states. Second operand 24 states. [2018-11-14 17:56:37,577 INFO L74 IsIncluded]: Start isIncluded. First operand 24 states. Second operand 24 states. [2018-11-14 17:56:37,577 INFO L87 Difference]: Start difference. First operand 24 states. Second operand 24 states. [2018-11-14 17:56:37,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:37,582 INFO L93 Difference]: Finished difference Result 24 states and 26 transitions. [2018-11-14 17:56:37,582 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 26 transitions. [2018-11-14 17:56:37,582 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:37,583 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:37,583 INFO L74 IsIncluded]: Start isIncluded. First operand 24 states. Second operand 24 states. [2018-11-14 17:56:37,583 INFO L87 Difference]: Start difference. First operand 24 states. Second operand 24 states. [2018-11-14 17:56:37,587 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:37,587 INFO L93 Difference]: Finished difference Result 24 states and 26 transitions. [2018-11-14 17:56:37,588 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 26 transitions. [2018-11-14 17:56:37,588 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:37,589 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:37,589 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:56:37,589 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:56:37,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-11-14 17:56:37,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 26 transitions. [2018-11-14 17:56:37,594 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 26 transitions. Word has length 15 [2018-11-14 17:56:37,594 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:56:37,595 INFO L480 AbstractCegarLoop]: Abstraction has 24 states and 26 transitions. [2018-11-14 17:56:37,595 INFO L481 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-11-14 17:56:37,595 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 26 transitions. [2018-11-14 17:56:37,596 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-11-14 17:56:37,596 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:56:37,596 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:56:37,596 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:56:37,597 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:56:37,597 INFO L82 PathProgramCache]: Analyzing trace with hash 629098255, now seen corresponding path program 1 times [2018-11-14 17:56:37,597 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:56:37,598 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:56:37,623 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 17:56:37,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:37,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:37,669 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:56:37,768 INFO L256 TraceCheckUtils]: 0: Hoare triple {218#true} call ULTIMATE.init(); {218#true} is VALID [2018-11-14 17:56:37,768 INFO L273 TraceCheckUtils]: 1: Hoare triple {218#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {218#true} is VALID [2018-11-14 17:56:37,769 INFO L273 TraceCheckUtils]: 2: Hoare triple {218#true} assume true; {218#true} is VALID [2018-11-14 17:56:37,769 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {218#true} {218#true} #65#return; {218#true} is VALID [2018-11-14 17:56:37,769 INFO L256 TraceCheckUtils]: 4: Hoare triple {218#true} call #t~ret5 := main(); {218#true} is VALID [2018-11-14 17:56:37,770 INFO L273 TraceCheckUtils]: 5: Hoare triple {218#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1; {218#true} is VALID [2018-11-14 17:56:37,773 INFO L273 TraceCheckUtils]: 6: Hoare triple {218#true} assume ~bvsgt32(~SIZE~0, 1bv32);havoc ~i~0;call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~val2~0 := 3bv32;~val1~0 := 7bv32;~low~0 := 2bv32;~i~0 := ~bvsub32(~SIZE~0, 2bv32); {241#(bvsgt (bvadd main_~i~0 (_ bv2 32)) (_ bv1 32))} is VALID [2018-11-14 17:56:37,775 INFO L273 TraceCheckUtils]: 7: Hoare triple {241#(bvsgt (bvadd main_~i~0 (_ bv2 32)) (_ bv1 32))} assume true; {241#(bvsgt (bvadd main_~i~0 (_ bv2 32)) (_ bv1 32))} is VALID [2018-11-14 17:56:37,777 INFO L273 TraceCheckUtils]: 8: Hoare triple {241#(bvsgt (bvadd main_~i~0 (_ bv2 32)) (_ bv1 32))} assume !~bvsge32(~i~0, 4294967295bv32); {219#false} is VALID [2018-11-14 17:56:37,778 INFO L273 TraceCheckUtils]: 9: Hoare triple {219#false} ~i~0 := 0bv32; {219#false} is VALID [2018-11-14 17:56:37,778 INFO L273 TraceCheckUtils]: 10: Hoare triple {219#false} assume true; {219#false} is VALID [2018-11-14 17:56:37,779 INFO L273 TraceCheckUtils]: 11: Hoare triple {219#false} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {219#false} is VALID [2018-11-14 17:56:37,779 INFO L256 TraceCheckUtils]: 12: Hoare triple {219#false} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {219#false} is VALID [2018-11-14 17:56:37,780 INFO L273 TraceCheckUtils]: 13: Hoare triple {219#false} ~cond := #in~cond; {219#false} is VALID [2018-11-14 17:56:37,780 INFO L273 TraceCheckUtils]: 14: Hoare triple {219#false} assume ~cond == 0bv32; {219#false} is VALID [2018-11-14 17:56:37,781 INFO L273 TraceCheckUtils]: 15: Hoare triple {219#false} assume !false; {219#false} is VALID [2018-11-14 17:56:37,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:37,783 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-14 17:56:37,788 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-14 17:56:37,788 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-14 17:56:37,790 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 16 [2018-11-14 17:56:37,790 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:56:37,790 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2018-11-14 17:56:37,849 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 16 edges. 16 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:37,849 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-14 17:56:37,849 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-14 17:56:37,850 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-14 17:56:37,850 INFO L87 Difference]: Start difference. First operand 24 states and 26 transitions. Second operand 3 states. [2018-11-14 17:56:38,386 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:38,386 INFO L93 Difference]: Finished difference Result 51 states and 58 transitions. [2018-11-14 17:56:38,386 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-14 17:56:38,386 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 16 [2018-11-14 17:56:38,387 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:56:38,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-14 17:56:38,391 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 58 transitions. [2018-11-14 17:56:38,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-14 17:56:38,394 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 58 transitions. [2018-11-14 17:56:38,395 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states and 58 transitions. [2018-11-14 17:56:38,556 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 58 edges. 58 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:38,559 INFO L225 Difference]: With dead ends: 51 [2018-11-14 17:56:38,559 INFO L226 Difference]: Without dead ends: 34 [2018-11-14 17:56:38,561 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 14 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-14 17:56:38,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-11-14 17:56:38,570 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 27. [2018-11-14 17:56:38,570 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:56:38,570 INFO L82 GeneralOperation]: Start isEquivalent. First operand 34 states. Second operand 27 states. [2018-11-14 17:56:38,571 INFO L74 IsIncluded]: Start isIncluded. First operand 34 states. Second operand 27 states. [2018-11-14 17:56:38,571 INFO L87 Difference]: Start difference. First operand 34 states. Second operand 27 states. [2018-11-14 17:56:38,576 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:38,576 INFO L93 Difference]: Finished difference Result 34 states and 37 transitions. [2018-11-14 17:56:38,577 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 37 transitions. [2018-11-14 17:56:38,577 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:38,578 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:38,578 INFO L74 IsIncluded]: Start isIncluded. First operand 27 states. Second operand 34 states. [2018-11-14 17:56:38,578 INFO L87 Difference]: Start difference. First operand 27 states. Second operand 34 states. [2018-11-14 17:56:38,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:38,582 INFO L93 Difference]: Finished difference Result 34 states and 37 transitions. [2018-11-14 17:56:38,582 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 37 transitions. [2018-11-14 17:56:38,583 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:38,583 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:38,583 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:56:38,583 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:56:38,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27 states. [2018-11-14 17:56:38,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 29 transitions. [2018-11-14 17:56:38,586 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 29 transitions. Word has length 16 [2018-11-14 17:56:38,586 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:56:38,586 INFO L480 AbstractCegarLoop]: Abstraction has 27 states and 29 transitions. [2018-11-14 17:56:38,587 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-14 17:56:38,587 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 29 transitions. [2018-11-14 17:56:38,588 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-11-14 17:56:38,588 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:56:38,588 INFO L375 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:56:38,588 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:56:38,589 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:56:38,589 INFO L82 PathProgramCache]: Analyzing trace with hash -1434210682, now seen corresponding path program 1 times [2018-11-14 17:56:38,589 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:56:38,590 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:56:38,612 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 17:56:38,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:38,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:38,667 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:56:38,808 INFO L256 TraceCheckUtils]: 0: Hoare triple {438#true} call ULTIMATE.init(); {438#true} is VALID [2018-11-14 17:56:38,809 INFO L273 TraceCheckUtils]: 1: Hoare triple {438#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {438#true} is VALID [2018-11-14 17:56:38,809 INFO L273 TraceCheckUtils]: 2: Hoare triple {438#true} assume true; {438#true} is VALID [2018-11-14 17:56:38,809 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {438#true} {438#true} #65#return; {438#true} is VALID [2018-11-14 17:56:38,809 INFO L256 TraceCheckUtils]: 4: Hoare triple {438#true} call #t~ret5 := main(); {438#true} is VALID [2018-11-14 17:56:38,810 INFO L273 TraceCheckUtils]: 5: Hoare triple {438#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1; {438#true} is VALID [2018-11-14 17:56:38,810 INFO L273 TraceCheckUtils]: 6: Hoare triple {438#true} assume ~bvsgt32(~SIZE~0, 1bv32);havoc ~i~0;call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~val2~0 := 3bv32;~val1~0 := 7bv32;~low~0 := 2bv32;~i~0 := ~bvsub32(~SIZE~0, 2bv32); {438#true} is VALID [2018-11-14 17:56:38,810 INFO L273 TraceCheckUtils]: 7: Hoare triple {438#true} assume true; {438#true} is VALID [2018-11-14 17:56:38,810 INFO L273 TraceCheckUtils]: 8: Hoare triple {438#true} assume !!~bvsge32(~i~0, 4294967295bv32); {438#true} is VALID [2018-11-14 17:56:38,814 INFO L273 TraceCheckUtils]: 9: Hoare triple {438#true} assume ~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~val1~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {470#(bvsge main_~i~0 (_ bv0 32))} is VALID [2018-11-14 17:56:38,817 INFO L273 TraceCheckUtils]: 10: Hoare triple {470#(bvsge main_~i~0 (_ bv0 32))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {470#(bvsge main_~i~0 (_ bv0 32))} is VALID [2018-11-14 17:56:38,819 INFO L273 TraceCheckUtils]: 11: Hoare triple {470#(bvsge main_~i~0 (_ bv0 32))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {477#(bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32))} is VALID [2018-11-14 17:56:38,819 INFO L273 TraceCheckUtils]: 12: Hoare triple {477#(bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32))} assume true; {477#(bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32))} is VALID [2018-11-14 17:56:38,821 INFO L273 TraceCheckUtils]: 13: Hoare triple {477#(bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32))} assume !~bvsge32(~i~0, 4294967295bv32); {439#false} is VALID [2018-11-14 17:56:38,821 INFO L273 TraceCheckUtils]: 14: Hoare triple {439#false} ~i~0 := 0bv32; {439#false} is VALID [2018-11-14 17:56:38,821 INFO L273 TraceCheckUtils]: 15: Hoare triple {439#false} assume true; {439#false} is VALID [2018-11-14 17:56:38,822 INFO L273 TraceCheckUtils]: 16: Hoare triple {439#false} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {439#false} is VALID [2018-11-14 17:56:38,822 INFO L256 TraceCheckUtils]: 17: Hoare triple {439#false} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {439#false} is VALID [2018-11-14 17:56:38,822 INFO L273 TraceCheckUtils]: 18: Hoare triple {439#false} ~cond := #in~cond; {439#false} is VALID [2018-11-14 17:56:38,823 INFO L273 TraceCheckUtils]: 19: Hoare triple {439#false} assume ~cond == 0bv32; {439#false} is VALID [2018-11-14 17:56:38,823 INFO L273 TraceCheckUtils]: 20: Hoare triple {439#false} assume !false; {439#false} is VALID [2018-11-14 17:56:38,825 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:38,825 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-14 17:56:38,828 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-14 17:56:38,828 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-14 17:56:38,828 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 21 [2018-11-14 17:56:38,829 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:56:38,830 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states. [2018-11-14 17:56:38,902 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 21 edges. 21 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:38,903 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-14 17:56:38,903 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-14 17:56:38,903 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-14 17:56:38,903 INFO L87 Difference]: Start difference. First operand 27 states and 29 transitions. Second operand 4 states. [2018-11-14 17:56:39,255 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:39,255 INFO L93 Difference]: Finished difference Result 50 states and 54 transitions. [2018-11-14 17:56:39,255 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-14 17:56:39,256 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 21 [2018-11-14 17:56:39,256 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:56:39,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-14 17:56:39,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 54 transitions. [2018-11-14 17:56:39,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-14 17:56:39,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 54 transitions. [2018-11-14 17:56:39,263 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states and 54 transitions. [2018-11-14 17:56:39,427 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 54 edges. 54 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:39,430 INFO L225 Difference]: With dead ends: 50 [2018-11-14 17:56:39,430 INFO L226 Difference]: Without dead ends: 38 [2018-11-14 17:56:39,431 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 19 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-14 17:56:39,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states. [2018-11-14 17:56:39,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 31. [2018-11-14 17:56:39,445 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:56:39,445 INFO L82 GeneralOperation]: Start isEquivalent. First operand 38 states. Second operand 31 states. [2018-11-14 17:56:39,446 INFO L74 IsIncluded]: Start isIncluded. First operand 38 states. Second operand 31 states. [2018-11-14 17:56:39,446 INFO L87 Difference]: Start difference. First operand 38 states. Second operand 31 states. [2018-11-14 17:56:39,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:39,449 INFO L93 Difference]: Finished difference Result 38 states and 41 transitions. [2018-11-14 17:56:39,449 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 41 transitions. [2018-11-14 17:56:39,450 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:39,450 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:39,450 INFO L74 IsIncluded]: Start isIncluded. First operand 31 states. Second operand 38 states. [2018-11-14 17:56:39,450 INFO L87 Difference]: Start difference. First operand 31 states. Second operand 38 states. [2018-11-14 17:56:39,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:39,453 INFO L93 Difference]: Finished difference Result 38 states and 41 transitions. [2018-11-14 17:56:39,453 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 41 transitions. [2018-11-14 17:56:39,454 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:39,454 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:39,454 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:56:39,454 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:56:39,455 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2018-11-14 17:56:39,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 33 transitions. [2018-11-14 17:56:39,457 INFO L78 Accepts]: Start accepts. Automaton has 31 states and 33 transitions. Word has length 21 [2018-11-14 17:56:39,457 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:56:39,457 INFO L480 AbstractCegarLoop]: Abstraction has 31 states and 33 transitions. [2018-11-14 17:56:39,457 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-14 17:56:39,457 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 33 transitions. [2018-11-14 17:56:39,458 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-11-14 17:56:39,458 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:56:39,459 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:56:39,459 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:56:39,459 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:56:39,459 INFO L82 PathProgramCache]: Analyzing trace with hash 1167828013, now seen corresponding path program 1 times [2018-11-14 17:56:39,460 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:56:39,460 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:56:39,477 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 17:56:39,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:39,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:39,552 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:56:39,895 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-14 17:56:39,907 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-14 17:56:39,913 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:56:39,917 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:39,939 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 17:56:39,940 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:34, output treesize:30 [2018-11-14 17:56:39,961 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:56:40,524 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 17 [2018-11-14 17:56:40,582 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 17:56:40,583 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 13 [2018-11-14 17:56:40,585 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:56:40,590 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:40,607 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:40,607 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:35, output treesize:11 [2018-11-14 17:56:40,612 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:56:40,689 INFO L256 TraceCheckUtils]: 0: Hoare triple {688#true} call ULTIMATE.init(); {688#true} is VALID [2018-11-14 17:56:40,689 INFO L273 TraceCheckUtils]: 1: Hoare triple {688#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {688#true} is VALID [2018-11-14 17:56:40,690 INFO L273 TraceCheckUtils]: 2: Hoare triple {688#true} assume true; {688#true} is VALID [2018-11-14 17:56:40,690 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {688#true} {688#true} #65#return; {688#true} is VALID [2018-11-14 17:56:40,690 INFO L256 TraceCheckUtils]: 4: Hoare triple {688#true} call #t~ret5 := main(); {688#true} is VALID [2018-11-14 17:56:40,690 INFO L273 TraceCheckUtils]: 5: Hoare triple {688#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1; {688#true} is VALID [2018-11-14 17:56:40,691 INFO L273 TraceCheckUtils]: 6: Hoare triple {688#true} assume ~bvsgt32(~SIZE~0, 1bv32);havoc ~i~0;call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~val2~0 := 3bv32;~val1~0 := 7bv32;~low~0 := 2bv32;~i~0 := ~bvsub32(~SIZE~0, 2bv32); {711#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:40,692 INFO L273 TraceCheckUtils]: 7: Hoare triple {711#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} assume true; {711#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:40,693 INFO L273 TraceCheckUtils]: 8: Hoare triple {711#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} assume !!~bvsge32(~i~0, 4294967295bv32); {711#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:40,693 INFO L273 TraceCheckUtils]: 9: Hoare triple {711#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} assume ~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~val1~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {721#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~i~0 (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:40,696 INFO L273 TraceCheckUtils]: 10: Hoare triple {721#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~i~0 (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {721#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~i~0 (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:40,700 INFO L273 TraceCheckUtils]: 11: Hoare triple {721#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~i~0 (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {728#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:40,701 INFO L273 TraceCheckUtils]: 12: Hoare triple {728#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} assume true; {728#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:40,702 INFO L273 TraceCheckUtils]: 13: Hoare triple {728#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} assume !!~bvsge32(~i~0, 4294967295bv32); {728#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:40,703 INFO L273 TraceCheckUtils]: 14: Hoare triple {728#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} assume !~bvsge32(~i~0, 0bv32); {738#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (not (bvsge main_~i~0 (_ bv0 32))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:40,706 INFO L273 TraceCheckUtils]: 15: Hoare triple {738#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (not (bvsge main_~i~0 (_ bv0 32))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {742#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:40,708 INFO L273 TraceCheckUtils]: 16: Hoare triple {742#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {742#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:40,720 INFO L273 TraceCheckUtils]: 17: Hoare triple {742#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} assume true; {742#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:40,722 INFO L273 TraceCheckUtils]: 18: Hoare triple {742#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} assume !~bvsge32(~i~0, 4294967295bv32); {742#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:40,724 INFO L273 TraceCheckUtils]: 19: Hoare triple {742#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} ~i~0 := 0bv32; {755#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((v_prenex_1 (_ BitVec 32))) (and (not (bvsge v_prenex_1 (_ bv0 32))) (bvsge (bvadd v_prenex_1 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_1) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} is VALID [2018-11-14 17:56:40,726 INFO L273 TraceCheckUtils]: 20: Hoare triple {755#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((v_prenex_1 (_ BitVec 32))) (and (not (bvsge v_prenex_1 (_ bv0 32))) (bvsge (bvadd v_prenex_1 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_1) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} assume true; {755#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((v_prenex_1 (_ BitVec 32))) (and (not (bvsge v_prenex_1 (_ bv0 32))) (bvsge (bvadd v_prenex_1 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_1) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} is VALID [2018-11-14 17:56:40,730 INFO L273 TraceCheckUtils]: 21: Hoare triple {755#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((v_prenex_1 (_ BitVec 32))) (and (not (bvsge v_prenex_1 (_ bv0 32))) (bvsge (bvadd v_prenex_1 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_1) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {762#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv3 32) |main_#t~mem4|))} is VALID [2018-11-14 17:56:40,731 INFO L256 TraceCheckUtils]: 22: Hoare triple {762#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv3 32) |main_#t~mem4|))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {766#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-14 17:56:40,732 INFO L273 TraceCheckUtils]: 23: Hoare triple {766#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {770#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-14 17:56:40,732 INFO L273 TraceCheckUtils]: 24: Hoare triple {770#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume ~cond == 0bv32; {689#false} is VALID [2018-11-14 17:56:40,733 INFO L273 TraceCheckUtils]: 25: Hoare triple {689#false} assume !false; {689#false} is VALID [2018-11-14 17:56:40,739 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:40,740 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-14 17:56:40,933 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 13 [2018-11-14 17:56:41,001 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 3 [2018-11-14 17:56:41,003 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 17:56:41,035 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 3 xjuncts. [2018-11-14 17:56:41,073 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 3 xjuncts. [2018-11-14 17:56:41,074 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:15, output treesize:31 [2018-11-14 17:56:41,082 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:56:41,605 INFO L273 TraceCheckUtils]: 25: Hoare triple {689#false} assume !false; {689#false} is VALID [2018-11-14 17:56:41,605 INFO L273 TraceCheckUtils]: 24: Hoare triple {780#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} assume ~cond == 0bv32; {689#false} is VALID [2018-11-14 17:56:41,606 INFO L273 TraceCheckUtils]: 23: Hoare triple {784#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} ~cond := #in~cond; {780#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} is VALID [2018-11-14 17:56:41,609 INFO L256 TraceCheckUtils]: 22: Hoare triple {788#(bvsge |main_#t~mem4| main_~low~0)} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {784#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-14 17:56:41,610 INFO L273 TraceCheckUtils]: 21: Hoare triple {792#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~low~0)} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {788#(bvsge |main_#t~mem4| main_~low~0)} is VALID [2018-11-14 17:56:41,610 INFO L273 TraceCheckUtils]: 20: Hoare triple {792#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~low~0)} assume true; {792#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~low~0)} is VALID [2018-11-14 17:56:41,611 INFO L273 TraceCheckUtils]: 19: Hoare triple {799#(bvsge (select (select |#memory_int| |main_~#a~0.base|) |main_~#a~0.offset|) main_~low~0)} ~i~0 := 0bv32; {792#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~low~0)} is VALID [2018-11-14 17:56:41,611 INFO L273 TraceCheckUtils]: 18: Hoare triple {799#(bvsge (select (select |#memory_int| |main_~#a~0.base|) |main_~#a~0.offset|) main_~low~0)} assume !~bvsge32(~i~0, 4294967295bv32); {799#(bvsge (select (select |#memory_int| |main_~#a~0.base|) |main_~#a~0.offset|) main_~low~0)} is VALID [2018-11-14 17:56:41,612 INFO L273 TraceCheckUtils]: 17: Hoare triple {799#(bvsge (select (select |#memory_int| |main_~#a~0.base|) |main_~#a~0.offset|) main_~low~0)} assume true; {799#(bvsge (select (select |#memory_int| |main_~#a~0.base|) |main_~#a~0.offset|) main_~low~0)} is VALID [2018-11-14 17:56:41,613 INFO L273 TraceCheckUtils]: 16: Hoare triple {799#(bvsge (select (select |#memory_int| |main_~#a~0.base|) |main_~#a~0.offset|) main_~low~0)} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {799#(bvsge (select (select |#memory_int| |main_~#a~0.base|) |main_~#a~0.offset|) main_~low~0)} is VALID [2018-11-14 17:56:41,634 INFO L273 TraceCheckUtils]: 15: Hoare triple {812#(and (or (forall ((v_prenex_2 (_ BitVec 32))) (bvsge v_prenex_2 main_~low~0)) (= (bvadd (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) (_ bv0 32))) (bvsge main_~val2~0 main_~low~0))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {799#(bvsge (select (select |#memory_int| |main_~#a~0.base|) |main_~#a~0.offset|) main_~low~0)} is VALID [2018-11-14 17:56:41,636 INFO L273 TraceCheckUtils]: 14: Hoare triple {816#(and (or (bvsge main_~i~0 (_ bv0 32)) (bvsge main_~val2~0 main_~low~0)) (or (bvsge main_~i~0 (_ bv0 32)) (forall ((v_prenex_2 (_ BitVec 32))) (bvsge v_prenex_2 main_~low~0)) (= (bvadd (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) (_ bv0 32))))} assume !~bvsge32(~i~0, 0bv32); {812#(and (or (forall ((v_prenex_2 (_ BitVec 32))) (bvsge v_prenex_2 main_~low~0)) (= (bvadd (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) (_ bv0 32))) (bvsge main_~val2~0 main_~low~0))} is VALID [2018-11-14 17:56:41,638 INFO L273 TraceCheckUtils]: 13: Hoare triple {816#(and (or (bvsge main_~i~0 (_ bv0 32)) (bvsge main_~val2~0 main_~low~0)) (or (bvsge main_~i~0 (_ bv0 32)) (forall ((v_prenex_2 (_ BitVec 32))) (bvsge v_prenex_2 main_~low~0)) (= (bvadd (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) (_ bv0 32))))} assume !!~bvsge32(~i~0, 4294967295bv32); {816#(and (or (bvsge main_~i~0 (_ bv0 32)) (bvsge main_~val2~0 main_~low~0)) (or (bvsge main_~i~0 (_ bv0 32)) (forall ((v_prenex_2 (_ BitVec 32))) (bvsge v_prenex_2 main_~low~0)) (= (bvadd (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) (_ bv0 32))))} is VALID [2018-11-14 17:56:41,639 INFO L273 TraceCheckUtils]: 12: Hoare triple {816#(and (or (bvsge main_~i~0 (_ bv0 32)) (bvsge main_~val2~0 main_~low~0)) (or (bvsge main_~i~0 (_ bv0 32)) (forall ((v_prenex_2 (_ BitVec 32))) (bvsge v_prenex_2 main_~low~0)) (= (bvadd (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) (_ bv0 32))))} assume true; {816#(and (or (bvsge main_~i~0 (_ bv0 32)) (bvsge main_~val2~0 main_~low~0)) (or (bvsge main_~i~0 (_ bv0 32)) (forall ((v_prenex_2 (_ BitVec 32))) (bvsge v_prenex_2 main_~low~0)) (= (bvadd (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) (_ bv0 32))))} is VALID [2018-11-14 17:56:41,645 INFO L273 TraceCheckUtils]: 11: Hoare triple {826#(and (or (bvsge main_~val2~0 main_~low~0) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (or (= (bvmul (_ bv4 32) main_~i~0) (_ bv0 32)) (forall ((v_prenex_2 (_ BitVec 32))) (bvsge v_prenex_2 main_~low~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {816#(and (or (bvsge main_~i~0 (_ bv0 32)) (bvsge main_~val2~0 main_~low~0)) (or (bvsge main_~i~0 (_ bv0 32)) (forall ((v_prenex_2 (_ BitVec 32))) (bvsge v_prenex_2 main_~low~0)) (= (bvadd (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) (_ bv0 32))))} is VALID [2018-11-14 17:56:41,648 INFO L273 TraceCheckUtils]: 10: Hoare triple {826#(and (or (bvsge main_~val2~0 main_~low~0) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (or (= (bvmul (_ bv4 32) main_~i~0) (_ bv0 32)) (forall ((v_prenex_2 (_ BitVec 32))) (bvsge v_prenex_2 main_~low~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {826#(and (or (bvsge main_~val2~0 main_~low~0) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (or (= (bvmul (_ bv4 32) main_~i~0) (_ bv0 32)) (forall ((v_prenex_2 (_ BitVec 32))) (bvsge v_prenex_2 main_~low~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))))} is VALID [2018-11-14 17:56:41,652 INFO L273 TraceCheckUtils]: 9: Hoare triple {833#(bvsge main_~val2~0 main_~low~0)} assume ~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~val1~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {826#(and (or (bvsge main_~val2~0 main_~low~0) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (or (= (bvmul (_ bv4 32) main_~i~0) (_ bv0 32)) (forall ((v_prenex_2 (_ BitVec 32))) (bvsge v_prenex_2 main_~low~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))))} is VALID [2018-11-14 17:56:41,652 INFO L273 TraceCheckUtils]: 8: Hoare triple {833#(bvsge main_~val2~0 main_~low~0)} assume !!~bvsge32(~i~0, 4294967295bv32); {833#(bvsge main_~val2~0 main_~low~0)} is VALID [2018-11-14 17:56:41,653 INFO L273 TraceCheckUtils]: 7: Hoare triple {833#(bvsge main_~val2~0 main_~low~0)} assume true; {833#(bvsge main_~val2~0 main_~low~0)} is VALID [2018-11-14 17:56:41,654 INFO L273 TraceCheckUtils]: 6: Hoare triple {688#true} assume ~bvsgt32(~SIZE~0, 1bv32);havoc ~i~0;call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~val2~0 := 3bv32;~val1~0 := 7bv32;~low~0 := 2bv32;~i~0 := ~bvsub32(~SIZE~0, 2bv32); {833#(bvsge main_~val2~0 main_~low~0)} is VALID [2018-11-14 17:56:41,654 INFO L273 TraceCheckUtils]: 5: Hoare triple {688#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1; {688#true} is VALID [2018-11-14 17:56:41,654 INFO L256 TraceCheckUtils]: 4: Hoare triple {688#true} call #t~ret5 := main(); {688#true} is VALID [2018-11-14 17:56:41,655 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {688#true} {688#true} #65#return; {688#true} is VALID [2018-11-14 17:56:41,655 INFO L273 TraceCheckUtils]: 2: Hoare triple {688#true} assume true; {688#true} is VALID [2018-11-14 17:56:41,655 INFO L273 TraceCheckUtils]: 1: Hoare triple {688#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {688#true} is VALID [2018-11-14 17:56:41,655 INFO L256 TraceCheckUtils]: 0: Hoare triple {688#true} call ULTIMATE.init(); {688#true} is VALID [2018-11-14 17:56:41,659 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:41,660 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-14 17:56:41,660 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 20 [2018-11-14 17:56:41,661 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 26 [2018-11-14 17:56:41,661 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:56:41,661 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 20 states. [2018-11-14 17:56:41,786 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 45 edges. 45 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:41,786 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-14 17:56:41,787 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-14 17:56:41,788 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=320, Unknown=0, NotChecked=0, Total=380 [2018-11-14 17:56:41,788 INFO L87 Difference]: Start difference. First operand 31 states and 33 transitions. Second operand 20 states. [2018-11-14 17:56:44,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:44,904 INFO L93 Difference]: Finished difference Result 49 states and 52 transitions. [2018-11-14 17:56:44,904 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-14 17:56:44,905 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 26 [2018-11-14 17:56:44,905 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:56:44,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2018-11-14 17:56:44,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 52 transitions. [2018-11-14 17:56:44,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2018-11-14 17:56:44,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 52 transitions. [2018-11-14 17:56:44,912 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 17 states and 52 transitions. [2018-11-14 17:56:45,095 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 52 edges. 52 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:45,097 INFO L225 Difference]: With dead ends: 49 [2018-11-14 17:56:45,098 INFO L226 Difference]: Without dead ends: 47 [2018-11-14 17:56:45,099 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 33 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 131 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=173, Invalid=697, Unknown=0, NotChecked=0, Total=870 [2018-11-14 17:56:45,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2018-11-14 17:56:45,197 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 38. [2018-11-14 17:56:45,198 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:56:45,198 INFO L82 GeneralOperation]: Start isEquivalent. First operand 47 states. Second operand 38 states. [2018-11-14 17:56:45,198 INFO L74 IsIncluded]: Start isIncluded. First operand 47 states. Second operand 38 states. [2018-11-14 17:56:45,199 INFO L87 Difference]: Start difference. First operand 47 states. Second operand 38 states. [2018-11-14 17:56:45,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:45,202 INFO L93 Difference]: Finished difference Result 47 states and 50 transitions. [2018-11-14 17:56:45,202 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 50 transitions. [2018-11-14 17:56:45,202 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:45,203 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:45,203 INFO L74 IsIncluded]: Start isIncluded. First operand 38 states. Second operand 47 states. [2018-11-14 17:56:45,203 INFO L87 Difference]: Start difference. First operand 38 states. Second operand 47 states. [2018-11-14 17:56:45,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:56:45,206 INFO L93 Difference]: Finished difference Result 47 states and 50 transitions. [2018-11-14 17:56:45,206 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 50 transitions. [2018-11-14 17:56:45,207 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:56:45,207 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:56:45,207 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:56:45,208 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:56:45,208 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2018-11-14 17:56:45,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 40 transitions. [2018-11-14 17:56:45,210 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 40 transitions. Word has length 26 [2018-11-14 17:56:45,210 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:56:45,211 INFO L480 AbstractCegarLoop]: Abstraction has 38 states and 40 transitions. [2018-11-14 17:56:45,211 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-14 17:56:45,211 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 40 transitions. [2018-11-14 17:56:45,212 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-11-14 17:56:45,212 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:56:45,212 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:56:45,213 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:56:45,213 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:56:45,213 INFO L82 PathProgramCache]: Analyzing trace with hash 1015321010, now seen corresponding path program 1 times [2018-11-14 17:56:45,214 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:56:45,214 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:56:45,230 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 17:56:45,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:45,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:56:45,309 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:56:45,437 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-14 17:56:45,445 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-14 17:56:45,447 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:56:45,452 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:45,473 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:45,473 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:33, output treesize:29 [2018-11-14 17:56:45,752 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 24 [2018-11-14 17:56:45,805 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:56:45,806 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 39 [2018-11-14 17:56:45,808 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:56:45,822 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:45,849 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 17:56:45,850 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:46, output treesize:42 [2018-11-14 17:56:45,868 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:56:46,536 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 26 [2018-11-14 17:56:46,548 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:56:46,549 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 17:56:46,551 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 24 [2018-11-14 17:56:46,552 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:56:46,562 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:46,577 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:56:46,577 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:46, output treesize:11 [2018-11-14 17:56:46,585 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:56:46,712 INFO L256 TraceCheckUtils]: 0: Hoare triple {1091#true} call ULTIMATE.init(); {1091#true} is VALID [2018-11-14 17:56:46,712 INFO L273 TraceCheckUtils]: 1: Hoare triple {1091#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {1091#true} is VALID [2018-11-14 17:56:46,713 INFO L273 TraceCheckUtils]: 2: Hoare triple {1091#true} assume true; {1091#true} is VALID [2018-11-14 17:56:46,713 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1091#true} {1091#true} #65#return; {1091#true} is VALID [2018-11-14 17:56:46,713 INFO L256 TraceCheckUtils]: 4: Hoare triple {1091#true} call #t~ret5 := main(); {1091#true} is VALID [2018-11-14 17:56:46,713 INFO L273 TraceCheckUtils]: 5: Hoare triple {1091#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1; {1091#true} is VALID [2018-11-14 17:56:46,719 INFO L273 TraceCheckUtils]: 6: Hoare triple {1091#true} assume ~bvsgt32(~SIZE~0, 1bv32);havoc ~i~0;call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~val2~0 := 3bv32;~val1~0 := 7bv32;~low~0 := 2bv32;~i~0 := ~bvsub32(~SIZE~0, 2bv32); {1114#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:46,720 INFO L273 TraceCheckUtils]: 7: Hoare triple {1114#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} assume true; {1114#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:46,721 INFO L273 TraceCheckUtils]: 8: Hoare triple {1114#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} assume !!~bvsge32(~i~0, 4294967295bv32); {1114#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:46,722 INFO L273 TraceCheckUtils]: 9: Hoare triple {1114#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} assume ~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~val1~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1124#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~i~0 (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:46,723 INFO L273 TraceCheckUtils]: 10: Hoare triple {1124#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~i~0 (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {1128#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~i~0 (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~val2~0))} is VALID [2018-11-14 17:56:48,732 INFO L273 TraceCheckUtils]: 11: Hoare triple {1128#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~i~0 (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~val2~0))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {1132#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is UNKNOWN [2018-11-14 17:56:48,733 INFO L273 TraceCheckUtils]: 12: Hoare triple {1132#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} assume true; {1132#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is VALID [2018-11-14 17:56:48,733 INFO L273 TraceCheckUtils]: 13: Hoare triple {1132#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} assume !!~bvsge32(~i~0, 4294967295bv32); {1132#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is VALID [2018-11-14 17:56:48,734 INFO L273 TraceCheckUtils]: 14: Hoare triple {1132#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} assume !~bvsge32(~i~0, 0bv32); {1142#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (not (bvsge main_~i~0 (_ bv0 32))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is VALID [2018-11-14 17:56:48,737 INFO L273 TraceCheckUtils]: 15: Hoare triple {1142#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (not (bvsge main_~i~0 (_ bv0 32))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {1146#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:48,737 INFO L273 TraceCheckUtils]: 16: Hoare triple {1146#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {1146#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:48,752 INFO L273 TraceCheckUtils]: 17: Hoare triple {1146#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} assume true; {1146#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:48,753 INFO L273 TraceCheckUtils]: 18: Hoare triple {1146#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} assume !~bvsge32(~i~0, 4294967295bv32); {1146#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:56:48,756 INFO L273 TraceCheckUtils]: 19: Hoare triple {1146#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} ~i~0 := 0bv32; {1159#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_3 (_ BitVec 32))) (and (bvsge (bvadd v_prenex_3 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_3 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv8 32)))))))} is VALID [2018-11-14 17:56:48,757 INFO L273 TraceCheckUtils]: 20: Hoare triple {1159#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_3 (_ BitVec 32))) (and (bvsge (bvadd v_prenex_3 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_3 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv8 32)))))))} assume true; {1159#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_3 (_ BitVec 32))) (and (bvsge (bvadd v_prenex_3 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_3 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv8 32)))))))} is VALID [2018-11-14 17:56:48,758 INFO L273 TraceCheckUtils]: 21: Hoare triple {1159#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_3 (_ BitVec 32))) (and (bvsge (bvadd v_prenex_3 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_3 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv8 32)))))))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1159#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_3 (_ BitVec 32))) (and (bvsge (bvadd v_prenex_3 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_3 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv8 32)))))))} is VALID [2018-11-14 17:56:48,761 INFO L256 TraceCheckUtils]: 22: Hoare triple {1159#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_3 (_ BitVec 32))) (and (bvsge (bvadd v_prenex_3 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_3 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv8 32)))))))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {1169#(exists ((|v_main_~#a~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_3 (_ BitVec 32))) (and (bvsge (bvadd v_prenex_3 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_3) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_3) (_ bv4 32)))) (not (bvsge v_prenex_3 (_ bv0 32)))))} is VALID [2018-11-14 17:56:48,762 INFO L273 TraceCheckUtils]: 23: Hoare triple {1169#(exists ((|v_main_~#a~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_3 (_ BitVec 32))) (and (bvsge (bvadd v_prenex_3 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_3) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_3) (_ bv4 32)))) (not (bvsge v_prenex_3 (_ bv0 32)))))} ~cond := #in~cond; {1169#(exists ((|v_main_~#a~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_3 (_ BitVec 32))) (and (bvsge (bvadd v_prenex_3 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_3) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_3) (_ bv4 32)))) (not (bvsge v_prenex_3 (_ bv0 32)))))} is VALID [2018-11-14 17:56:48,765 INFO L273 TraceCheckUtils]: 24: Hoare triple {1169#(exists ((|v_main_~#a~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_3 (_ BitVec 32))) (and (bvsge (bvadd v_prenex_3 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_3) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_3) (_ bv4 32)))) (not (bvsge v_prenex_3 (_ bv0 32)))))} assume !(~cond == 0bv32); {1169#(exists ((|v_main_~#a~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_3 (_ BitVec 32))) (and (bvsge (bvadd v_prenex_3 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_3) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_3) (_ bv4 32)))) (not (bvsge v_prenex_3 (_ bv0 32)))))} is VALID [2018-11-14 17:56:48,766 INFO L273 TraceCheckUtils]: 25: Hoare triple {1169#(exists ((|v_main_~#a~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_3 (_ BitVec 32))) (and (bvsge (bvadd v_prenex_3 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_3) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_3) (_ bv4 32)))) (not (bvsge v_prenex_3 (_ bv0 32)))))} assume true; {1169#(exists ((|v_main_~#a~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_3 (_ BitVec 32))) (and (bvsge (bvadd v_prenex_3 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_3) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_3) (_ bv4 32)))) (not (bvsge v_prenex_3 (_ bv0 32)))))} is VALID [2018-11-14 17:56:48,766 INFO L268 TraceCheckUtils]: 26: Hoare quadruple {1169#(exists ((|v_main_~#a~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_3 (_ BitVec 32))) (and (bvsge (bvadd v_prenex_3 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_3) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv4 32) v_prenex_3) (_ bv4 32)))) (not (bvsge v_prenex_3 (_ bv0 32)))))} {1159#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_3 (_ BitVec 32))) (and (bvsge (bvadd v_prenex_3 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_3 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv8 32)))))))} #69#return; {1159#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_3 (_ BitVec 32))) (and (bvsge (bvadd v_prenex_3 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_3 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv8 32)))))))} is VALID [2018-11-14 17:56:48,767 INFO L273 TraceCheckUtils]: 27: Hoare triple {1159#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_3 (_ BitVec 32))) (and (bvsge (bvadd v_prenex_3 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_3 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv8 32)))))))} havoc #t~mem4; {1159#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_3 (_ BitVec 32))) (and (bvsge (bvadd v_prenex_3 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_3 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv8 32)))))))} is VALID [2018-11-14 17:56:48,768 INFO L273 TraceCheckUtils]: 28: Hoare triple {1159#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_3 (_ BitVec 32))) (and (bvsge (bvadd v_prenex_3 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_3 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv8 32)))))))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {1188#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_3 (_ BitVec 32))) (and (bvsge (bvadd v_prenex_3 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_3 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv8 32)))))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:48,769 INFO L273 TraceCheckUtils]: 29: Hoare triple {1188#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_3 (_ BitVec 32))) (and (bvsge (bvadd v_prenex_3 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_3 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv8 32)))))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {1188#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_3 (_ BitVec 32))) (and (bvsge (bvadd v_prenex_3 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_3 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv8 32)))))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:48,779 INFO L273 TraceCheckUtils]: 30: Hoare triple {1188#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_3 (_ BitVec 32))) (and (bvsge (bvadd v_prenex_3 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_3 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_3) (_ bv8 32)))))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1195#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv3 32) |main_#t~mem4|))} is VALID [2018-11-14 17:56:48,780 INFO L256 TraceCheckUtils]: 31: Hoare triple {1195#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv3 32) |main_#t~mem4|))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {1199#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-14 17:56:48,780 INFO L273 TraceCheckUtils]: 32: Hoare triple {1199#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {1203#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-14 17:56:48,781 INFO L273 TraceCheckUtils]: 33: Hoare triple {1203#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume ~cond == 0bv32; {1092#false} is VALID [2018-11-14 17:56:48,781 INFO L273 TraceCheckUtils]: 34: Hoare triple {1092#false} assume !false; {1092#false} is VALID [2018-11-14 17:56:48,790 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:48,791 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-14 17:56:49,652 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 22 [2018-11-14 17:56:49,658 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 26 [2018-11-14 17:56:49,756 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 6 [2018-11-14 17:56:49,758 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-14 17:56:49,780 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 19 [2018-11-14 17:56:49,784 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-14 17:56:49,831 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-14 17:56:49,850 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-14 17:56:49,881 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-14 17:56:49,881 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 2 variables, input treesize:30, output treesize:34 [2018-11-14 17:56:49,894 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:56:50,086 INFO L273 TraceCheckUtils]: 34: Hoare triple {1092#false} assume !false; {1092#false} is VALID [2018-11-14 17:56:50,087 INFO L273 TraceCheckUtils]: 33: Hoare triple {1213#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} assume ~cond == 0bv32; {1092#false} is VALID [2018-11-14 17:56:50,088 INFO L273 TraceCheckUtils]: 32: Hoare triple {1217#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} ~cond := #in~cond; {1213#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} is VALID [2018-11-14 17:56:50,088 INFO L256 TraceCheckUtils]: 31: Hoare triple {1221#(bvsge |main_#t~mem4| main_~low~0)} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {1217#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-14 17:56:50,089 INFO L273 TraceCheckUtils]: 30: Hoare triple {1225#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~low~0)} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1221#(bvsge |main_#t~mem4| main_~low~0)} is VALID [2018-11-14 17:56:50,090 INFO L273 TraceCheckUtils]: 29: Hoare triple {1225#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~low~0)} assume true; {1225#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~low~0)} is VALID [2018-11-14 17:56:52,097 INFO L273 TraceCheckUtils]: 28: Hoare triple {1232#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~low~0)} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {1225#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~low~0)} is UNKNOWN [2018-11-14 17:56:52,098 INFO L273 TraceCheckUtils]: 27: Hoare triple {1232#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~low~0)} havoc #t~mem4; {1232#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~low~0)} is VALID [2018-11-14 17:56:52,099 INFO L268 TraceCheckUtils]: 26: Hoare quadruple {1091#true} {1232#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~low~0)} #69#return; {1232#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~low~0)} is VALID [2018-11-14 17:56:52,099 INFO L273 TraceCheckUtils]: 25: Hoare triple {1091#true} assume true; {1091#true} is VALID [2018-11-14 17:56:52,099 INFO L273 TraceCheckUtils]: 24: Hoare triple {1091#true} assume !(~cond == 0bv32); {1091#true} is VALID [2018-11-14 17:56:52,099 INFO L273 TraceCheckUtils]: 23: Hoare triple {1091#true} ~cond := #in~cond; {1091#true} is VALID [2018-11-14 17:56:52,100 INFO L256 TraceCheckUtils]: 22: Hoare triple {1232#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~low~0)} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {1091#true} is VALID [2018-11-14 17:56:52,101 INFO L273 TraceCheckUtils]: 21: Hoare triple {1232#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~low~0)} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1232#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~low~0)} is VALID [2018-11-14 17:56:52,101 INFO L273 TraceCheckUtils]: 20: Hoare triple {1232#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~low~0)} assume true; {1232#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~low~0)} is VALID [2018-11-14 17:56:52,102 INFO L273 TraceCheckUtils]: 19: Hoare triple {1260#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv4 32))) main_~low~0)} ~i~0 := 0bv32; {1232#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~low~0)} is VALID [2018-11-14 17:56:52,102 INFO L273 TraceCheckUtils]: 18: Hoare triple {1260#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv4 32))) main_~low~0)} assume !~bvsge32(~i~0, 4294967295bv32); {1260#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv4 32))) main_~low~0)} is VALID [2018-11-14 17:56:52,102 INFO L273 TraceCheckUtils]: 17: Hoare triple {1260#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv4 32))) main_~low~0)} assume true; {1260#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv4 32))) main_~low~0)} is VALID [2018-11-14 17:56:52,106 INFO L273 TraceCheckUtils]: 16: Hoare triple {1260#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv4 32))) main_~low~0)} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {1260#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv4 32))) main_~low~0)} is VALID [2018-11-14 17:56:52,140 INFO L273 TraceCheckUtils]: 15: Hoare triple {1273#(bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv4 32))) main_~low~0)} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {1260#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv4 32))) main_~low~0)} is VALID [2018-11-14 17:56:52,141 INFO L273 TraceCheckUtils]: 14: Hoare triple {1277#(or (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv4 32))) main_~low~0) (bvsge main_~i~0 (_ bv0 32)))} assume !~bvsge32(~i~0, 0bv32); {1273#(bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv4 32))) main_~low~0)} is VALID [2018-11-14 17:56:52,141 INFO L273 TraceCheckUtils]: 13: Hoare triple {1277#(or (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv4 32))) main_~low~0) (bvsge main_~i~0 (_ bv0 32)))} assume !!~bvsge32(~i~0, 4294967295bv32); {1277#(or (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv4 32))) main_~low~0) (bvsge main_~i~0 (_ bv0 32)))} is VALID [2018-11-14 17:56:52,142 INFO L273 TraceCheckUtils]: 12: Hoare triple {1277#(or (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv4 32))) main_~low~0) (bvsge main_~i~0 (_ bv0 32)))} assume true; {1277#(or (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv4 32))) main_~low~0) (bvsge main_~i~0 (_ bv0 32)))} is VALID [2018-11-14 17:56:52,153 INFO L273 TraceCheckUtils]: 11: Hoare triple {1287#(or (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv4 32))) main_~low~0) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {1277#(or (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv4 32))) main_~low~0) (bvsge main_~i~0 (_ bv0 32)))} is VALID [2018-11-14 17:56:52,179 INFO L273 TraceCheckUtils]: 10: Hoare triple {1291#(and (or (= (bvmul (_ bv4 32) main_~i~0) (_ bv0 32)) (forall ((v_arrayElimCell_9 (_ BitVec 32))) (bvsge v_arrayElimCell_9 main_~low~0)) (= (_ bv4 32) (bvmul (_ bv4 32) main_~i~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (or (bvsge main_~val2~0 main_~low~0) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {1287#(or (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv4 32))) main_~low~0) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:56:52,182 INFO L273 TraceCheckUtils]: 9: Hoare triple {1295#(bvsge main_~val2~0 main_~low~0)} assume ~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~val1~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1291#(and (or (= (bvmul (_ bv4 32) main_~i~0) (_ bv0 32)) (forall ((v_arrayElimCell_9 (_ BitVec 32))) (bvsge v_arrayElimCell_9 main_~low~0)) (= (_ bv4 32) (bvmul (_ bv4 32) main_~i~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (or (bvsge main_~val2~0 main_~low~0) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))))} is VALID [2018-11-14 17:56:52,183 INFO L273 TraceCheckUtils]: 8: Hoare triple {1295#(bvsge main_~val2~0 main_~low~0)} assume !!~bvsge32(~i~0, 4294967295bv32); {1295#(bvsge main_~val2~0 main_~low~0)} is VALID [2018-11-14 17:56:52,183 INFO L273 TraceCheckUtils]: 7: Hoare triple {1295#(bvsge main_~val2~0 main_~low~0)} assume true; {1295#(bvsge main_~val2~0 main_~low~0)} is VALID [2018-11-14 17:56:52,184 INFO L273 TraceCheckUtils]: 6: Hoare triple {1091#true} assume ~bvsgt32(~SIZE~0, 1bv32);havoc ~i~0;call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~val2~0 := 3bv32;~val1~0 := 7bv32;~low~0 := 2bv32;~i~0 := ~bvsub32(~SIZE~0, 2bv32); {1295#(bvsge main_~val2~0 main_~low~0)} is VALID [2018-11-14 17:56:52,185 INFO L273 TraceCheckUtils]: 5: Hoare triple {1091#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1; {1091#true} is VALID [2018-11-14 17:56:52,185 INFO L256 TraceCheckUtils]: 4: Hoare triple {1091#true} call #t~ret5 := main(); {1091#true} is VALID [2018-11-14 17:56:52,185 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1091#true} {1091#true} #65#return; {1091#true} is VALID [2018-11-14 17:56:52,186 INFO L273 TraceCheckUtils]: 2: Hoare triple {1091#true} assume true; {1091#true} is VALID [2018-11-14 17:56:52,186 INFO L273 TraceCheckUtils]: 1: Hoare triple {1091#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {1091#true} is VALID [2018-11-14 17:56:52,186 INFO L256 TraceCheckUtils]: 0: Hoare triple {1091#true} call ULTIMATE.init(); {1091#true} is VALID [2018-11-14 17:56:52,189 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 17:56:52,191 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-14 17:56:52,191 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13] total 25 [2018-11-14 17:56:52,192 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 35 [2018-11-14 17:56:52,192 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:56:52,192 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 25 states. [2018-11-14 17:56:56,458 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 63 edges. 61 inductive. 0 not inductive. 2 times theorem prover too weak to decide inductivity. [2018-11-14 17:56:56,459 INFO L459 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-11-14 17:56:56,459 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-11-14 17:56:56,460 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=90, Invalid=510, Unknown=0, NotChecked=0, Total=600 [2018-11-14 17:56:56,460 INFO L87 Difference]: Start difference. First operand 38 states and 40 transitions. Second operand 25 states. [2018-11-14 17:57:03,485 WARN L179 SmtUtils]: Spent 121.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 40 [2018-11-14 17:57:04,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:57:04,374 INFO L93 Difference]: Finished difference Result 67 states and 72 transitions. [2018-11-14 17:57:04,374 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-11-14 17:57:04,374 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 35 [2018-11-14 17:57:04,375 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:57:04,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2018-11-14 17:57:04,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 69 transitions. [2018-11-14 17:57:04,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2018-11-14 17:57:04,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 69 transitions. [2018-11-14 17:57:04,383 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 22 states and 69 transitions. [2018-11-14 17:57:08,700 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 69 edges. 67 inductive. 0 not inductive. 2 times theorem prover too weak to decide inductivity. [2018-11-14 17:57:08,702 INFO L225 Difference]: With dead ends: 67 [2018-11-14 17:57:08,702 INFO L226 Difference]: Without dead ends: 65 [2018-11-14 17:57:08,703 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 46 SyntacticMatches, 1 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 313 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=286, Invalid=1274, Unknown=0, NotChecked=0, Total=1560 [2018-11-14 17:57:08,704 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states. [2018-11-14 17:57:08,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 47. [2018-11-14 17:57:08,789 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:57:08,790 INFO L82 GeneralOperation]: Start isEquivalent. First operand 65 states. Second operand 47 states. [2018-11-14 17:57:08,790 INFO L74 IsIncluded]: Start isIncluded. First operand 65 states. Second operand 47 states. [2018-11-14 17:57:08,790 INFO L87 Difference]: Start difference. First operand 65 states. Second operand 47 states. [2018-11-14 17:57:08,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:57:08,795 INFO L93 Difference]: Finished difference Result 65 states and 70 transitions. [2018-11-14 17:57:08,795 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 70 transitions. [2018-11-14 17:57:08,796 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:57:08,797 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:57:08,797 INFO L74 IsIncluded]: Start isIncluded. First operand 47 states. Second operand 65 states. [2018-11-14 17:57:08,797 INFO L87 Difference]: Start difference. First operand 47 states. Second operand 65 states. [2018-11-14 17:57:08,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:57:08,801 INFO L93 Difference]: Finished difference Result 65 states and 70 transitions. [2018-11-14 17:57:08,801 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 70 transitions. [2018-11-14 17:57:08,802 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:57:08,802 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:57:08,803 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:57:08,803 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:57:08,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47 states. [2018-11-14 17:57:08,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 49 transitions. [2018-11-14 17:57:08,805 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 49 transitions. Word has length 35 [2018-11-14 17:57:08,806 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:57:08,806 INFO L480 AbstractCegarLoop]: Abstraction has 47 states and 49 transitions. [2018-11-14 17:57:08,806 INFO L481 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-11-14 17:57:08,806 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 49 transitions. [2018-11-14 17:57:08,807 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-11-14 17:57:08,807 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:57:08,808 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:57:08,808 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:57:08,808 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:57:08,808 INFO L82 PathProgramCache]: Analyzing trace with hash 1920862669, now seen corresponding path program 2 times [2018-11-14 17:57:08,809 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:57:08,809 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:57:08,841 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-14 17:57:08,919 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-14 17:57:08,919 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-14 17:57:08,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:57:08,938 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:57:09,234 INFO L256 TraceCheckUtils]: 0: Hoare triple {1636#true} call ULTIMATE.init(); {1636#true} is VALID [2018-11-14 17:57:09,234 INFO L273 TraceCheckUtils]: 1: Hoare triple {1636#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {1636#true} is VALID [2018-11-14 17:57:09,235 INFO L273 TraceCheckUtils]: 2: Hoare triple {1636#true} assume true; {1636#true} is VALID [2018-11-14 17:57:09,235 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1636#true} {1636#true} #65#return; {1636#true} is VALID [2018-11-14 17:57:09,235 INFO L256 TraceCheckUtils]: 4: Hoare triple {1636#true} call #t~ret5 := main(); {1636#true} is VALID [2018-11-14 17:57:09,235 INFO L273 TraceCheckUtils]: 5: Hoare triple {1636#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1; {1636#true} is VALID [2018-11-14 17:57:09,249 INFO L273 TraceCheckUtils]: 6: Hoare triple {1636#true} assume ~bvsgt32(~SIZE~0, 1bv32);havoc ~i~0;call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~val2~0 := 3bv32;~val1~0 := 7bv32;~low~0 := 2bv32;~i~0 := ~bvsub32(~SIZE~0, 2bv32); {1659#(= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0)} is VALID [2018-11-14 17:57:09,250 INFO L273 TraceCheckUtils]: 7: Hoare triple {1659#(= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0)} assume true; {1659#(= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0)} is VALID [2018-11-14 17:57:09,251 INFO L273 TraceCheckUtils]: 8: Hoare triple {1659#(= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0)} assume !!~bvsge32(~i~0, 4294967295bv32); {1659#(= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0)} is VALID [2018-11-14 17:57:09,251 INFO L273 TraceCheckUtils]: 9: Hoare triple {1659#(= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0)} assume ~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~val1~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1669#(and (= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0) (bvsge main_~i~0 (_ bv0 32)))} is VALID [2018-11-14 17:57:09,252 INFO L273 TraceCheckUtils]: 10: Hoare triple {1669#(and (= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0) (bvsge main_~i~0 (_ bv0 32)))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {1669#(and (= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0) (bvsge main_~i~0 (_ bv0 32)))} is VALID [2018-11-14 17:57:09,278 INFO L273 TraceCheckUtils]: 11: Hoare triple {1669#(and (= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0) (bvsge main_~i~0 (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {1676#(and (= (bvadd ~SIZE~0 (_ bv4294967293 32)) main_~i~0) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,279 INFO L273 TraceCheckUtils]: 12: Hoare triple {1676#(and (= (bvadd ~SIZE~0 (_ bv4294967293 32)) main_~i~0) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} assume true; {1676#(and (= (bvadd ~SIZE~0 (_ bv4294967293 32)) main_~i~0) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,280 INFO L273 TraceCheckUtils]: 13: Hoare triple {1676#(and (= (bvadd ~SIZE~0 (_ bv4294967293 32)) main_~i~0) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} assume !!~bvsge32(~i~0, 4294967295bv32); {1676#(and (= (bvadd ~SIZE~0 (_ bv4294967293 32)) main_~i~0) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,283 INFO L273 TraceCheckUtils]: 14: Hoare triple {1676#(and (= (bvadd ~SIZE~0 (_ bv4294967293 32)) main_~i~0) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} assume !~bvsge32(~i~0, 0bv32); {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,284 INFO L273 TraceCheckUtils]: 15: Hoare triple {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,285 INFO L273 TraceCheckUtils]: 16: Hoare triple {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,286 INFO L273 TraceCheckUtils]: 17: Hoare triple {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} assume true; {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,287 INFO L273 TraceCheckUtils]: 18: Hoare triple {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} assume !~bvsge32(~i~0, 4294967295bv32); {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,287 INFO L273 TraceCheckUtils]: 19: Hoare triple {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} ~i~0 := 0bv32; {1702#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,288 INFO L273 TraceCheckUtils]: 20: Hoare triple {1702#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} assume true; {1702#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,289 INFO L273 TraceCheckUtils]: 21: Hoare triple {1702#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1702#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,291 INFO L256 TraceCheckUtils]: 22: Hoare triple {1702#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,292 INFO L273 TraceCheckUtils]: 23: Hoare triple {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} ~cond := #in~cond; {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,293 INFO L273 TraceCheckUtils]: 24: Hoare triple {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} assume !(~cond == 0bv32); {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,294 INFO L273 TraceCheckUtils]: 25: Hoare triple {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} assume true; {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,295 INFO L268 TraceCheckUtils]: 26: Hoare quadruple {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} {1702#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} #69#return; {1702#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,296 INFO L273 TraceCheckUtils]: 27: Hoare triple {1702#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} havoc #t~mem4; {1702#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,303 INFO L273 TraceCheckUtils]: 28: Hoare triple {1702#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {1730#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,309 INFO L273 TraceCheckUtils]: 29: Hoare triple {1730#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {1730#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,310 INFO L273 TraceCheckUtils]: 30: Hoare triple {1730#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1730#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,311 INFO L256 TraceCheckUtils]: 31: Hoare triple {1730#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,312 INFO L273 TraceCheckUtils]: 32: Hoare triple {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} ~cond := #in~cond; {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,313 INFO L273 TraceCheckUtils]: 33: Hoare triple {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} assume !(~cond == 0bv32); {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,313 INFO L273 TraceCheckUtils]: 34: Hoare triple {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} assume true; {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,314 INFO L268 TraceCheckUtils]: 35: Hoare quadruple {1686#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)))} {1730#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #69#return; {1730#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,316 INFO L273 TraceCheckUtils]: 36: Hoare triple {1730#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} havoc #t~mem4; {1730#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,317 INFO L273 TraceCheckUtils]: 37: Hoare triple {1730#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {1758#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:57:09,318 INFO L273 TraceCheckUtils]: 38: Hoare triple {1758#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume true; {1758#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:57:09,321 INFO L273 TraceCheckUtils]: 39: Hoare triple {1758#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1637#false} is VALID [2018-11-14 17:57:09,322 INFO L256 TraceCheckUtils]: 40: Hoare triple {1637#false} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {1637#false} is VALID [2018-11-14 17:57:09,322 INFO L273 TraceCheckUtils]: 41: Hoare triple {1637#false} ~cond := #in~cond; {1637#false} is VALID [2018-11-14 17:57:09,322 INFO L273 TraceCheckUtils]: 42: Hoare triple {1637#false} assume ~cond == 0bv32; {1637#false} is VALID [2018-11-14 17:57:09,323 INFO L273 TraceCheckUtils]: 43: Hoare triple {1637#false} assume !false; {1637#false} is VALID [2018-11-14 17:57:09,331 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 6 proven. 18 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-14 17:57:09,331 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-14 17:57:09,803 INFO L273 TraceCheckUtils]: 43: Hoare triple {1637#false} assume !false; {1637#false} is VALID [2018-11-14 17:57:09,803 INFO L273 TraceCheckUtils]: 42: Hoare triple {1637#false} assume ~cond == 0bv32; {1637#false} is VALID [2018-11-14 17:57:09,803 INFO L273 TraceCheckUtils]: 41: Hoare triple {1637#false} ~cond := #in~cond; {1637#false} is VALID [2018-11-14 17:57:09,803 INFO L256 TraceCheckUtils]: 40: Hoare triple {1637#false} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {1637#false} is VALID [2018-11-14 17:57:09,804 INFO L273 TraceCheckUtils]: 39: Hoare triple {1789#(not (bvslt main_~i~0 ~SIZE~0))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1637#false} is VALID [2018-11-14 17:57:09,822 INFO L273 TraceCheckUtils]: 38: Hoare triple {1789#(not (bvslt main_~i~0 ~SIZE~0))} assume true; {1789#(not (bvslt main_~i~0 ~SIZE~0))} is VALID [2018-11-14 17:57:09,830 INFO L273 TraceCheckUtils]: 37: Hoare triple {1796#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {1789#(not (bvslt main_~i~0 ~SIZE~0))} is VALID [2018-11-14 17:57:09,831 INFO L273 TraceCheckUtils]: 36: Hoare triple {1796#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} havoc #t~mem4; {1796#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} is VALID [2018-11-14 17:57:09,832 INFO L268 TraceCheckUtils]: 35: Hoare quadruple {1636#true} {1796#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} #69#return; {1796#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} is VALID [2018-11-14 17:57:09,832 INFO L273 TraceCheckUtils]: 34: Hoare triple {1636#true} assume true; {1636#true} is VALID [2018-11-14 17:57:09,832 INFO L273 TraceCheckUtils]: 33: Hoare triple {1636#true} assume !(~cond == 0bv32); {1636#true} is VALID [2018-11-14 17:57:09,832 INFO L273 TraceCheckUtils]: 32: Hoare triple {1636#true} ~cond := #in~cond; {1636#true} is VALID [2018-11-14 17:57:09,833 INFO L256 TraceCheckUtils]: 31: Hoare triple {1796#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {1636#true} is VALID [2018-11-14 17:57:09,833 INFO L273 TraceCheckUtils]: 30: Hoare triple {1796#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1796#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} is VALID [2018-11-14 17:57:09,834 INFO L273 TraceCheckUtils]: 29: Hoare triple {1796#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} assume true; {1796#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} is VALID [2018-11-14 17:57:09,857 INFO L273 TraceCheckUtils]: 28: Hoare triple {1824#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {1796#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} is VALID [2018-11-14 17:57:09,857 INFO L273 TraceCheckUtils]: 27: Hoare triple {1824#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} havoc #t~mem4; {1824#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} is VALID [2018-11-14 17:57:09,858 INFO L268 TraceCheckUtils]: 26: Hoare quadruple {1636#true} {1824#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} #69#return; {1824#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} is VALID [2018-11-14 17:57:09,858 INFO L273 TraceCheckUtils]: 25: Hoare triple {1636#true} assume true; {1636#true} is VALID [2018-11-14 17:57:09,858 INFO L273 TraceCheckUtils]: 24: Hoare triple {1636#true} assume !(~cond == 0bv32); {1636#true} is VALID [2018-11-14 17:57:09,859 INFO L273 TraceCheckUtils]: 23: Hoare triple {1636#true} ~cond := #in~cond; {1636#true} is VALID [2018-11-14 17:57:09,859 INFO L256 TraceCheckUtils]: 22: Hoare triple {1824#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {1636#true} is VALID [2018-11-14 17:57:09,859 INFO L273 TraceCheckUtils]: 21: Hoare triple {1824#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1824#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} is VALID [2018-11-14 17:57:09,860 INFO L273 TraceCheckUtils]: 20: Hoare triple {1824#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} assume true; {1824#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} is VALID [2018-11-14 17:57:09,860 INFO L273 TraceCheckUtils]: 19: Hoare triple {1852#(not (bvslt (_ bv2 32) ~SIZE~0))} ~i~0 := 0bv32; {1824#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} is VALID [2018-11-14 17:57:09,861 INFO L273 TraceCheckUtils]: 18: Hoare triple {1852#(not (bvslt (_ bv2 32) ~SIZE~0))} assume !~bvsge32(~i~0, 4294967295bv32); {1852#(not (bvslt (_ bv2 32) ~SIZE~0))} is VALID [2018-11-14 17:57:09,861 INFO L273 TraceCheckUtils]: 17: Hoare triple {1852#(not (bvslt (_ bv2 32) ~SIZE~0))} assume true; {1852#(not (bvslt (_ bv2 32) ~SIZE~0))} is VALID [2018-11-14 17:57:09,861 INFO L273 TraceCheckUtils]: 16: Hoare triple {1852#(not (bvslt (_ bv2 32) ~SIZE~0))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {1852#(not (bvslt (_ bv2 32) ~SIZE~0))} is VALID [2018-11-14 17:57:09,862 INFO L273 TraceCheckUtils]: 15: Hoare triple {1852#(not (bvslt (_ bv2 32) ~SIZE~0))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {1852#(not (bvslt (_ bv2 32) ~SIZE~0))} is VALID [2018-11-14 17:57:09,862 INFO L273 TraceCheckUtils]: 14: Hoare triple {1868#(or (not (bvslt (_ bv2 32) ~SIZE~0)) (bvsge main_~i~0 (_ bv0 32)))} assume !~bvsge32(~i~0, 0bv32); {1852#(not (bvslt (_ bv2 32) ~SIZE~0))} is VALID [2018-11-14 17:57:09,863 INFO L273 TraceCheckUtils]: 13: Hoare triple {1868#(or (not (bvslt (_ bv2 32) ~SIZE~0)) (bvsge main_~i~0 (_ bv0 32)))} assume !!~bvsge32(~i~0, 4294967295bv32); {1868#(or (not (bvslt (_ bv2 32) ~SIZE~0)) (bvsge main_~i~0 (_ bv0 32)))} is VALID [2018-11-14 17:57:09,866 INFO L273 TraceCheckUtils]: 12: Hoare triple {1868#(or (not (bvslt (_ bv2 32) ~SIZE~0)) (bvsge main_~i~0 (_ bv0 32)))} assume true; {1868#(or (not (bvslt (_ bv2 32) ~SIZE~0)) (bvsge main_~i~0 (_ bv0 32)))} is VALID [2018-11-14 17:57:09,867 INFO L273 TraceCheckUtils]: 11: Hoare triple {1878#(or (not (bvslt (_ bv2 32) ~SIZE~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {1868#(or (not (bvslt (_ bv2 32) ~SIZE~0)) (bvsge main_~i~0 (_ bv0 32)))} is VALID [2018-11-14 17:57:09,868 INFO L273 TraceCheckUtils]: 10: Hoare triple {1878#(or (not (bvslt (_ bv2 32) ~SIZE~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {1878#(or (not (bvslt (_ bv2 32) ~SIZE~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,869 INFO L273 TraceCheckUtils]: 9: Hoare triple {1885#(or (not (bvsge main_~i~0 (_ bv0 32))) (not (bvslt (_ bv2 32) ~SIZE~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~val1~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {1878#(or (not (bvslt (_ bv2 32) ~SIZE~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,870 INFO L273 TraceCheckUtils]: 8: Hoare triple {1885#(or (not (bvsge main_~i~0 (_ bv0 32))) (not (bvslt (_ bv2 32) ~SIZE~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~i~0, 4294967295bv32); {1885#(or (not (bvsge main_~i~0 (_ bv0 32))) (not (bvslt (_ bv2 32) ~SIZE~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,872 INFO L273 TraceCheckUtils]: 7: Hoare triple {1885#(or (not (bvsge main_~i~0 (_ bv0 32))) (not (bvslt (_ bv2 32) ~SIZE~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {1885#(or (not (bvsge main_~i~0 (_ bv0 32))) (not (bvslt (_ bv2 32) ~SIZE~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,876 INFO L273 TraceCheckUtils]: 6: Hoare triple {1636#true} assume ~bvsgt32(~SIZE~0, 1bv32);havoc ~i~0;call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~val2~0 := 3bv32;~val1~0 := 7bv32;~low~0 := 2bv32;~i~0 := ~bvsub32(~SIZE~0, 2bv32); {1885#(or (not (bvsge main_~i~0 (_ bv0 32))) (not (bvslt (_ bv2 32) ~SIZE~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:09,877 INFO L273 TraceCheckUtils]: 5: Hoare triple {1636#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1; {1636#true} is VALID [2018-11-14 17:57:09,877 INFO L256 TraceCheckUtils]: 4: Hoare triple {1636#true} call #t~ret5 := main(); {1636#true} is VALID [2018-11-14 17:57:09,877 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1636#true} {1636#true} #65#return; {1636#true} is VALID [2018-11-14 17:57:09,878 INFO L273 TraceCheckUtils]: 2: Hoare triple {1636#true} assume true; {1636#true} is VALID [2018-11-14 17:57:09,878 INFO L273 TraceCheckUtils]: 1: Hoare triple {1636#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {1636#true} is VALID [2018-11-14 17:57:09,878 INFO L256 TraceCheckUtils]: 0: Hoare triple {1636#true} call ULTIMATE.init(); {1636#true} is VALID [2018-11-14 17:57:09,882 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 12 proven. 12 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-14 17:57:09,883 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-14 17:57:09,884 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 16 [2018-11-14 17:57:09,886 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 44 [2018-11-14 17:57:09,886 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:57:09,886 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 16 states. [2018-11-14 17:57:10,074 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 72 edges. 72 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:57:10,074 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-11-14 17:57:10,074 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-11-14 17:57:10,075 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=79, Invalid=161, Unknown=0, NotChecked=0, Total=240 [2018-11-14 17:57:10,075 INFO L87 Difference]: Start difference. First operand 47 states and 49 transitions. Second operand 16 states. [2018-11-14 17:57:12,705 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:57:12,705 INFO L93 Difference]: Finished difference Result 104 states and 110 transitions. [2018-11-14 17:57:12,705 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-14 17:57:12,706 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 44 [2018-11-14 17:57:12,706 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:57:12,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2018-11-14 17:57:12,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 95 transitions. [2018-11-14 17:57:12,716 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2018-11-14 17:57:12,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 95 transitions. [2018-11-14 17:57:12,721 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 13 states and 95 transitions. [2018-11-14 17:57:12,924 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:57:12,926 INFO L225 Difference]: With dead ends: 104 [2018-11-14 17:57:12,927 INFO L226 Difference]: Without dead ends: 61 [2018-11-14 17:57:12,927 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 73 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 56 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=87, Invalid=185, Unknown=0, NotChecked=0, Total=272 [2018-11-14 17:57:12,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2018-11-14 17:57:13,055 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 52. [2018-11-14 17:57:13,055 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:57:13,055 INFO L82 GeneralOperation]: Start isEquivalent. First operand 61 states. Second operand 52 states. [2018-11-14 17:57:13,056 INFO L74 IsIncluded]: Start isIncluded. First operand 61 states. Second operand 52 states. [2018-11-14 17:57:13,056 INFO L87 Difference]: Start difference. First operand 61 states. Second operand 52 states. [2018-11-14 17:57:13,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:57:13,059 INFO L93 Difference]: Finished difference Result 61 states and 64 transitions. [2018-11-14 17:57:13,059 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 64 transitions. [2018-11-14 17:57:13,059 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:57:13,059 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:57:13,060 INFO L74 IsIncluded]: Start isIncluded. First operand 52 states. Second operand 61 states. [2018-11-14 17:57:13,060 INFO L87 Difference]: Start difference. First operand 52 states. Second operand 61 states. [2018-11-14 17:57:13,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:57:13,062 INFO L93 Difference]: Finished difference Result 61 states and 64 transitions. [2018-11-14 17:57:13,063 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 64 transitions. [2018-11-14 17:57:13,063 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:57:13,063 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:57:13,063 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:57:13,063 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:57:13,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. [2018-11-14 17:57:13,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 54 transitions. [2018-11-14 17:57:13,066 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 54 transitions. Word has length 44 [2018-11-14 17:57:13,066 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:57:13,066 INFO L480 AbstractCegarLoop]: Abstraction has 52 states and 54 transitions. [2018-11-14 17:57:13,066 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-11-14 17:57:13,066 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 54 transitions. [2018-11-14 17:57:13,067 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-14 17:57:13,067 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:57:13,067 INFO L375 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:57:13,068 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:57:13,068 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:57:13,068 INFO L82 PathProgramCache]: Analyzing trace with hash 1653942468, now seen corresponding path program 3 times [2018-11-14 17:57:13,068 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:57:13,068 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:57:13,099 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2018-11-14 17:57:13,302 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-11-14 17:57:13,302 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-14 17:57:13,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:57:13,338 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:57:13,389 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-14 17:57:13,398 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-14 17:57:13,402 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:57:13,407 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:13,426 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:13,427 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:30, output treesize:26 [2018-11-14 17:57:13,528 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 23 [2018-11-14 17:57:13,537 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:57:13,541 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 37 [2018-11-14 17:57:13,549 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:57:13,563 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:13,591 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:13,591 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:41, output treesize:26 [2018-11-14 17:57:13,602 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:57:13,623 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 24 [2018-11-14 17:57:13,634 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:57:13,635 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 39 [2018-11-14 17:57:13,637 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:57:13,654 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:13,686 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:13,687 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:42, output treesize:38 [2018-11-14 17:57:13,983 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 34 [2018-11-14 17:57:14,043 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:57:14,067 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:57:14,092 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:57:14,093 INFO L303 Elim1Store]: Index analysis took 104 ms [2018-11-14 17:57:14,094 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 79 [2018-11-14 17:57:14,122 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:57:14,245 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:14,283 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 17:57:14,284 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:56, output treesize:52 [2018-11-14 17:57:14,306 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:57:15,404 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2018-11-14 17:57:15,468 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:57:15,480 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 17:57:15,487 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:57:15,489 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:57:15,491 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 3 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 44 [2018-11-14 17:57:15,493 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:57:15,501 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:15,514 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:15,514 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:57, output treesize:11 [2018-11-14 17:57:15,522 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:57:15,682 INFO L256 TraceCheckUtils]: 0: Hoare triple {2243#true} call ULTIMATE.init(); {2243#true} is VALID [2018-11-14 17:57:15,683 INFO L273 TraceCheckUtils]: 1: Hoare triple {2243#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {2243#true} is VALID [2018-11-14 17:57:15,683 INFO L273 TraceCheckUtils]: 2: Hoare triple {2243#true} assume true; {2243#true} is VALID [2018-11-14 17:57:15,683 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2243#true} {2243#true} #65#return; {2243#true} is VALID [2018-11-14 17:57:15,683 INFO L256 TraceCheckUtils]: 4: Hoare triple {2243#true} call #t~ret5 := main(); {2243#true} is VALID [2018-11-14 17:57:15,684 INFO L273 TraceCheckUtils]: 5: Hoare triple {2243#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1; {2243#true} is VALID [2018-11-14 17:57:15,685 INFO L273 TraceCheckUtils]: 6: Hoare triple {2243#true} assume ~bvsgt32(~SIZE~0, 1bv32);havoc ~i~0;call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~val2~0 := 3bv32;~val1~0 := 7bv32;~low~0 := 2bv32;~i~0 := ~bvsub32(~SIZE~0, 2bv32); {2266#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:57:15,685 INFO L273 TraceCheckUtils]: 7: Hoare triple {2266#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} assume true; {2266#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:57:15,686 INFO L273 TraceCheckUtils]: 8: Hoare triple {2266#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} assume !!~bvsge32(~i~0, 4294967295bv32); {2266#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:57:15,686 INFO L273 TraceCheckUtils]: 9: Hoare triple {2266#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} assume ~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~val1~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2266#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:57:15,688 INFO L273 TraceCheckUtils]: 10: Hoare triple {2266#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {2279#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~val2~0))} is VALID [2018-11-14 17:57:17,696 INFO L273 TraceCheckUtils]: 11: Hoare triple {2279#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~val2~0))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {2283#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is UNKNOWN [2018-11-14 17:57:17,697 INFO L273 TraceCheckUtils]: 12: Hoare triple {2283#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} assume true; {2283#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is VALID [2018-11-14 17:57:17,697 INFO L273 TraceCheckUtils]: 13: Hoare triple {2283#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} assume !!~bvsge32(~i~0, 4294967295bv32); {2283#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is VALID [2018-11-14 17:57:17,699 INFO L273 TraceCheckUtils]: 14: Hoare triple {2283#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} assume ~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~val1~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2283#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is VALID [2018-11-14 17:57:17,702 INFO L273 TraceCheckUtils]: 15: Hoare triple {2283#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {2296#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~val2~0))} is VALID [2018-11-14 17:57:18,025 INFO L273 TraceCheckUtils]: 16: Hoare triple {2296#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~val2~0))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {2300#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is VALID [2018-11-14 17:57:18,026 INFO L273 TraceCheckUtils]: 17: Hoare triple {2300#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} assume true; {2300#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is VALID [2018-11-14 17:57:18,027 INFO L273 TraceCheckUtils]: 18: Hoare triple {2300#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} assume !!~bvsge32(~i~0, 4294967295bv32); {2307#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (bvsge main_~i~0 (_ bv4294967295 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is VALID [2018-11-14 17:57:18,028 INFO L273 TraceCheckUtils]: 19: Hoare triple {2307#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (bvsge main_~i~0 (_ bv4294967295 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} assume !~bvsge32(~i~0, 0bv32); {2311#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (not (bvsge main_~i~0 (_ bv0 32))) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (bvsge main_~i~0 (_ bv4294967295 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is VALID [2018-11-14 17:57:18,032 INFO L273 TraceCheckUtils]: 20: Hoare triple {2311#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (not (bvsge main_~i~0 (_ bv0 32))) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (bvsge main_~i~0 (_ bv4294967295 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {2315#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~i~0 (_ bv4294967295 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:57:18,033 INFO L273 TraceCheckUtils]: 21: Hoare triple {2315#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~i~0 (_ bv4294967295 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {2315#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~i~0 (_ bv4294967295 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:57:18,034 INFO L273 TraceCheckUtils]: 22: Hoare triple {2315#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~i~0 (_ bv4294967295 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} assume true; {2315#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~i~0 (_ bv4294967295 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:57:18,034 INFO L273 TraceCheckUtils]: 23: Hoare triple {2315#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~i~0 (_ bv4294967295 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} assume !~bvsge32(~i~0, 4294967295bv32); {2315#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~i~0 (_ bv4294967295 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:57:18,038 INFO L273 TraceCheckUtils]: 24: Hoare triple {2315#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~i~0 (_ bv4294967295 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} ~i~0 := 0bv32; {2328#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))))} is VALID [2018-11-14 17:57:18,041 INFO L273 TraceCheckUtils]: 25: Hoare triple {2328#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))))} assume true; {2328#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))))} is VALID [2018-11-14 17:57:18,046 INFO L273 TraceCheckUtils]: 26: Hoare triple {2328#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2328#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))))} is VALID [2018-11-14 17:57:18,051 INFO L256 TraceCheckUtils]: 27: Hoare triple {2328#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {2338#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_5 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32))))} is VALID [2018-11-14 17:57:18,052 INFO L273 TraceCheckUtils]: 28: Hoare triple {2338#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_5 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32))))} ~cond := #in~cond; {2338#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_5 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32))))} is VALID [2018-11-14 17:57:18,052 INFO L273 TraceCheckUtils]: 29: Hoare triple {2338#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_5 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32))))} assume !(~cond == 0bv32); {2338#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_5 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32))))} is VALID [2018-11-14 17:57:18,053 INFO L273 TraceCheckUtils]: 30: Hoare triple {2338#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_5 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32))))} assume true; {2338#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_5 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32))))} is VALID [2018-11-14 17:57:18,053 INFO L268 TraceCheckUtils]: 31: Hoare quadruple {2338#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_5 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32))))} {2328#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))))} #69#return; {2328#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))))} is VALID [2018-11-14 17:57:18,058 INFO L273 TraceCheckUtils]: 32: Hoare triple {2328#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))))} havoc #t~mem4; {2328#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))))} is VALID [2018-11-14 17:57:18,061 INFO L273 TraceCheckUtils]: 33: Hoare triple {2328#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {2357#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:18,062 INFO L273 TraceCheckUtils]: 34: Hoare triple {2357#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {2357#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:18,064 INFO L273 TraceCheckUtils]: 35: Hoare triple {2357#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2357#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:18,070 INFO L256 TraceCheckUtils]: 36: Hoare triple {2357#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {2338#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_5 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32))))} is VALID [2018-11-14 17:57:18,071 INFO L273 TraceCheckUtils]: 37: Hoare triple {2338#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_5 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32))))} ~cond := #in~cond; {2338#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_5 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32))))} is VALID [2018-11-14 17:57:18,071 INFO L273 TraceCheckUtils]: 38: Hoare triple {2338#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_5 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32))))} assume !(~cond == 0bv32); {2338#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_5 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32))))} is VALID [2018-11-14 17:57:18,072 INFO L273 TraceCheckUtils]: 39: Hoare triple {2338#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_5 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32))))} assume true; {2338#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_5 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32))))} is VALID [2018-11-14 17:57:18,072 INFO L268 TraceCheckUtils]: 40: Hoare quadruple {2338#(exists ((|v_main_~#a~0.base_BEFORE_CALL_3| (_ BitVec 32)) (v_prenex_5 (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32))) (_ bv4294967293 32)) (_ bv0 32))))} {2357#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #69#return; {2357#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:18,073 INFO L273 TraceCheckUtils]: 41: Hoare triple {2357#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} havoc #t~mem4; {2357#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:18,074 INFO L273 TraceCheckUtils]: 42: Hoare triple {2357#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {2385#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:57:18,078 INFO L273 TraceCheckUtils]: 43: Hoare triple {2385#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))) (= (_ bv2 32) main_~i~0))} assume true; {2385#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:57:18,081 INFO L273 TraceCheckUtils]: 44: Hoare triple {2385#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_5 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv8 32)))) (bvsge v_prenex_5 (_ bv4294967295 32)) (not (bvsge v_prenex_5 (_ bv0 32))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_5) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)))) (= (_ bv2 32) main_~i~0))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2392#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv3 32) |main_#t~mem4|))} is VALID [2018-11-14 17:57:18,082 INFO L256 TraceCheckUtils]: 45: Hoare triple {2392#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv3 32) |main_#t~mem4|))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {2396#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-14 17:57:18,085 INFO L273 TraceCheckUtils]: 46: Hoare triple {2396#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {2400#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-14 17:57:18,085 INFO L273 TraceCheckUtils]: 47: Hoare triple {2400#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume ~cond == 0bv32; {2244#false} is VALID [2018-11-14 17:57:18,086 INFO L273 TraceCheckUtils]: 48: Hoare triple {2244#false} assume !false; {2244#false} is VALID [2018-11-14 17:57:18,103 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 13 proven. 23 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-14 17:57:18,103 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-14 17:57:25,776 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 23 [2018-11-14 17:57:25,783 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 27 [2018-11-14 17:57:25,864 WARN L307 Elim1Store]: Array PQE input equivalent to true [2018-11-14 17:57:25,865 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-14 17:57:25,876 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:57:25,878 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 15 [2018-11-14 17:57:25,881 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-14 17:57:25,893 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:25,899 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:25,914 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:57:25,914 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:37, output treesize:3 [2018-11-14 17:57:25,928 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:57:25,992 INFO L273 TraceCheckUtils]: 48: Hoare triple {2244#false} assume !false; {2244#false} is VALID [2018-11-14 17:57:25,995 INFO L273 TraceCheckUtils]: 47: Hoare triple {2410#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} assume ~cond == 0bv32; {2244#false} is VALID [2018-11-14 17:57:25,996 INFO L273 TraceCheckUtils]: 46: Hoare triple {2414#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} ~cond := #in~cond; {2410#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} is VALID [2018-11-14 17:57:25,998 INFO L256 TraceCheckUtils]: 45: Hoare triple {2418#(bvsge |main_#t~mem4| main_~low~0)} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {2414#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-14 17:57:25,999 INFO L273 TraceCheckUtils]: 44: Hoare triple {2422#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~low~0)} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2418#(bvsge |main_#t~mem4| main_~low~0)} is VALID [2018-11-14 17:57:25,999 INFO L273 TraceCheckUtils]: 43: Hoare triple {2422#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~low~0)} assume true; {2422#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~low~0)} is VALID [2018-11-14 17:57:28,008 INFO L273 TraceCheckUtils]: 42: Hoare triple {2429#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~low~0)} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {2422#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~low~0)} is UNKNOWN [2018-11-14 17:57:28,009 INFO L273 TraceCheckUtils]: 41: Hoare triple {2429#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~low~0)} havoc #t~mem4; {2429#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~low~0)} is VALID [2018-11-14 17:57:28,009 INFO L268 TraceCheckUtils]: 40: Hoare quadruple {2243#true} {2429#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~low~0)} #69#return; {2429#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~low~0)} is VALID [2018-11-14 17:57:28,010 INFO L273 TraceCheckUtils]: 39: Hoare triple {2243#true} assume true; {2243#true} is VALID [2018-11-14 17:57:28,010 INFO L273 TraceCheckUtils]: 38: Hoare triple {2243#true} assume !(~cond == 0bv32); {2243#true} is VALID [2018-11-14 17:57:28,010 INFO L273 TraceCheckUtils]: 37: Hoare triple {2243#true} ~cond := #in~cond; {2243#true} is VALID [2018-11-14 17:57:28,010 INFO L256 TraceCheckUtils]: 36: Hoare triple {2429#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~low~0)} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {2243#true} is VALID [2018-11-14 17:57:28,010 INFO L273 TraceCheckUtils]: 35: Hoare triple {2429#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~low~0)} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2429#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~low~0)} is VALID [2018-11-14 17:57:28,011 INFO L273 TraceCheckUtils]: 34: Hoare triple {2429#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~low~0)} assume true; {2429#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~low~0)} is VALID [2018-11-14 17:57:30,034 INFO L273 TraceCheckUtils]: 33: Hoare triple {2457#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~low~0)} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {2429#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~low~0)} is UNKNOWN [2018-11-14 17:57:30,035 INFO L273 TraceCheckUtils]: 32: Hoare triple {2457#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~low~0)} havoc #t~mem4; {2457#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~low~0)} is VALID [2018-11-14 17:57:30,037 INFO L268 TraceCheckUtils]: 31: Hoare quadruple {2243#true} {2457#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~low~0)} #69#return; {2457#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~low~0)} is VALID [2018-11-14 17:57:30,037 INFO L273 TraceCheckUtils]: 30: Hoare triple {2243#true} assume true; {2243#true} is VALID [2018-11-14 17:57:30,037 INFO L273 TraceCheckUtils]: 29: Hoare triple {2243#true} assume !(~cond == 0bv32); {2243#true} is VALID [2018-11-14 17:57:30,037 INFO L273 TraceCheckUtils]: 28: Hoare triple {2243#true} ~cond := #in~cond; {2243#true} is VALID [2018-11-14 17:57:30,037 INFO L256 TraceCheckUtils]: 27: Hoare triple {2457#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~low~0)} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {2243#true} is VALID [2018-11-14 17:57:30,038 INFO L273 TraceCheckUtils]: 26: Hoare triple {2457#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~low~0)} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2457#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~low~0)} is VALID [2018-11-14 17:57:30,039 INFO L273 TraceCheckUtils]: 25: Hoare triple {2457#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~low~0)} assume true; {2457#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~low~0)} is VALID [2018-11-14 17:57:30,039 INFO L273 TraceCheckUtils]: 24: Hoare triple {2485#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0)} ~i~0 := 0bv32; {2457#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~low~0)} is VALID [2018-11-14 17:57:30,041 INFO L273 TraceCheckUtils]: 23: Hoare triple {2485#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0)} assume !~bvsge32(~i~0, 4294967295bv32); {2485#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0)} is VALID [2018-11-14 17:57:30,041 INFO L273 TraceCheckUtils]: 22: Hoare triple {2485#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0)} assume true; {2485#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0)} is VALID [2018-11-14 17:57:30,043 INFO L273 TraceCheckUtils]: 21: Hoare triple {2485#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0)} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {2485#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0)} is VALID [2018-11-14 17:57:30,085 INFO L273 TraceCheckUtils]: 20: Hoare triple {2498#(bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0)} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {2485#(bvsge (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0)} is VALID [2018-11-14 17:57:30,086 INFO L273 TraceCheckUtils]: 19: Hoare triple {2502#(or (bvsge main_~i~0 (_ bv0 32)) (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0))} assume !~bvsge32(~i~0, 0bv32); {2498#(bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0)} is VALID [2018-11-14 17:57:30,091 INFO L273 TraceCheckUtils]: 18: Hoare triple {2506#(or (bvsge main_~i~0 (_ bv0 32)) (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0) (not (bvsge main_~i~0 (_ bv4294967295 32))))} assume !!~bvsge32(~i~0, 4294967295bv32); {2502#(or (bvsge main_~i~0 (_ bv0 32)) (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0))} is VALID [2018-11-14 17:57:30,091 INFO L273 TraceCheckUtils]: 17: Hoare triple {2506#(or (bvsge main_~i~0 (_ bv0 32)) (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0) (not (bvsge main_~i~0 (_ bv4294967295 32))))} assume true; {2506#(or (bvsge main_~i~0 (_ bv0 32)) (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0) (not (bvsge main_~i~0 (_ bv4294967295 32))))} is VALID [2018-11-14 17:57:30,102 INFO L273 TraceCheckUtils]: 16: Hoare triple {2513#(or (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv4294967295 32))) (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {2506#(or (bvsge main_~i~0 (_ bv0 32)) (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0) (not (bvsge main_~i~0 (_ bv4294967295 32))))} is VALID [2018-11-14 17:57:30,114 INFO L273 TraceCheckUtils]: 15: Hoare triple {2513#(or (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv4294967295 32))) (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {2513#(or (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv4294967295 32))) (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:30,124 INFO L273 TraceCheckUtils]: 14: Hoare triple {2513#(or (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv4294967295 32))) (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~val1~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2513#(or (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv4294967295 32))) (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:30,124 INFO L273 TraceCheckUtils]: 13: Hoare triple {2513#(or (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv4294967295 32))) (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~i~0, 4294967295bv32); {2513#(or (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv4294967295 32))) (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:30,126 INFO L273 TraceCheckUtils]: 12: Hoare triple {2513#(or (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv4294967295 32))) (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {2513#(or (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv4294967295 32))) (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:30,138 INFO L273 TraceCheckUtils]: 11: Hoare triple {2529#(or (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4294967292 32)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0) (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32)) (not (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv4294967295 32))))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {2513#(or (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv4294967295 32))) (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:57:30,162 INFO L273 TraceCheckUtils]: 10: Hoare triple {2533#(bvsge main_~val2~0 main_~low~0)} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {2529#(or (bvsge (select (store (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4294967292 32)) main_~val2~0) (bvadd |main_~#a~0.offset| (_ bv8 32))) main_~low~0) (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32)) (not (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv4294967295 32))))} is VALID [2018-11-14 17:57:30,162 INFO L273 TraceCheckUtils]: 9: Hoare triple {2533#(bvsge main_~val2~0 main_~low~0)} assume ~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~val1~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2533#(bvsge main_~val2~0 main_~low~0)} is VALID [2018-11-14 17:57:30,164 INFO L273 TraceCheckUtils]: 8: Hoare triple {2533#(bvsge main_~val2~0 main_~low~0)} assume !!~bvsge32(~i~0, 4294967295bv32); {2533#(bvsge main_~val2~0 main_~low~0)} is VALID [2018-11-14 17:57:30,164 INFO L273 TraceCheckUtils]: 7: Hoare triple {2533#(bvsge main_~val2~0 main_~low~0)} assume true; {2533#(bvsge main_~val2~0 main_~low~0)} is VALID [2018-11-14 17:57:30,166 INFO L273 TraceCheckUtils]: 6: Hoare triple {2243#true} assume ~bvsgt32(~SIZE~0, 1bv32);havoc ~i~0;call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~val2~0 := 3bv32;~val1~0 := 7bv32;~low~0 := 2bv32;~i~0 := ~bvsub32(~SIZE~0, 2bv32); {2533#(bvsge main_~val2~0 main_~low~0)} is VALID [2018-11-14 17:57:30,166 INFO L273 TraceCheckUtils]: 5: Hoare triple {2243#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1; {2243#true} is VALID [2018-11-14 17:57:30,166 INFO L256 TraceCheckUtils]: 4: Hoare triple {2243#true} call #t~ret5 := main(); {2243#true} is VALID [2018-11-14 17:57:30,166 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2243#true} {2243#true} #65#return; {2243#true} is VALID [2018-11-14 17:57:30,167 INFO L273 TraceCheckUtils]: 2: Hoare triple {2243#true} assume true; {2243#true} is VALID [2018-11-14 17:57:30,167 INFO L273 TraceCheckUtils]: 1: Hoare triple {2243#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {2243#true} is VALID [2018-11-14 17:57:30,167 INFO L256 TraceCheckUtils]: 0: Hoare triple {2243#true} call ULTIMATE.init(); {2243#true} is VALID [2018-11-14 17:57:30,172 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 11 proven. 25 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-14 17:57:30,174 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-14 17:57:30,174 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 15] total 30 [2018-11-14 17:57:30,175 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 49 [2018-11-14 17:57:30,176 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:57:30,176 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 30 states. [2018-11-14 17:57:36,841 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 85 edges. 82 inductive. 0 not inductive. 3 times theorem prover too weak to decide inductivity. [2018-11-14 17:57:36,842 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-11-14 17:57:36,842 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-11-14 17:57:36,842 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=144, Invalid=724, Unknown=2, NotChecked=0, Total=870 [2018-11-14 17:57:36,843 INFO L87 Difference]: Start difference. First operand 52 states and 54 transitions. Second operand 30 states. [2018-11-14 17:57:48,081 WARN L179 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 37 [2018-11-14 17:57:53,649 WARN L179 SmtUtils]: Spent 136.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 40 [2018-11-14 17:57:54,224 WARN L179 SmtUtils]: Spent 183.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 40 [2018-11-14 17:57:54,904 WARN L179 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 39 DAG size of output: 37 [2018-11-14 17:58:00,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:58:00,634 INFO L93 Difference]: Finished difference Result 70 states and 73 transitions. [2018-11-14 17:58:00,634 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-11-14 17:58:00,634 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 49 [2018-11-14 17:58:00,634 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:58:00,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-11-14 17:58:00,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 67 transitions. [2018-11-14 17:58:00,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-11-14 17:58:00,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 67 transitions. [2018-11-14 17:58:00,639 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 26 states and 67 transitions. [2018-11-14 17:58:04,019 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 67 edges. 66 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2018-11-14 17:58:04,021 INFO L225 Difference]: With dead ends: 70 [2018-11-14 17:58:04,021 INFO L226 Difference]: Without dead ends: 68 [2018-11-14 17:58:04,022 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 120 GetRequests, 68 SyntacticMatches, 4 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 577 ImplicationChecksByTransitivity, 11.6s TimeCoverageRelationStatistics Valid=470, Invalid=1978, Unknown=2, NotChecked=0, Total=2450 [2018-11-14 17:58:04,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states. [2018-11-14 17:58:04,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 61. [2018-11-14 17:58:04,146 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:58:04,146 INFO L82 GeneralOperation]: Start isEquivalent. First operand 68 states. Second operand 61 states. [2018-11-14 17:58:04,147 INFO L74 IsIncluded]: Start isIncluded. First operand 68 states. Second operand 61 states. [2018-11-14 17:58:04,147 INFO L87 Difference]: Start difference. First operand 68 states. Second operand 61 states. [2018-11-14 17:58:04,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:58:04,150 INFO L93 Difference]: Finished difference Result 68 states and 71 transitions. [2018-11-14 17:58:04,150 INFO L276 IsEmpty]: Start isEmpty. Operand 68 states and 71 transitions. [2018-11-14 17:58:04,151 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:58:04,151 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:58:04,151 INFO L74 IsIncluded]: Start isIncluded. First operand 61 states. Second operand 68 states. [2018-11-14 17:58:04,151 INFO L87 Difference]: Start difference. First operand 61 states. Second operand 68 states. [2018-11-14 17:58:04,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:58:04,154 INFO L93 Difference]: Finished difference Result 68 states and 71 transitions. [2018-11-14 17:58:04,154 INFO L276 IsEmpty]: Start isEmpty. Operand 68 states and 71 transitions. [2018-11-14 17:58:04,154 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:58:04,154 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:58:04,155 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:58:04,155 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:58:04,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61 states. [2018-11-14 17:58:04,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 63 transitions. [2018-11-14 17:58:04,157 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 63 transitions. Word has length 49 [2018-11-14 17:58:04,157 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:58:04,157 INFO L480 AbstractCegarLoop]: Abstraction has 61 states and 63 transitions. [2018-11-14 17:58:04,157 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-11-14 17:58:04,158 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 63 transitions. [2018-11-14 17:58:04,158 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-11-14 17:58:04,158 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:58:04,158 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:58:04,159 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:58:04,159 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:58:04,159 INFO L82 PathProgramCache]: Analyzing trace with hash -1655617797, now seen corresponding path program 4 times [2018-11-14 17:58:04,159 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:58:04,160 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:58:04,188 INFO L101 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-14 17:58:04,245 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-14 17:58:04,245 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-14 17:58:04,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:58:04,266 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:58:04,632 INFO L256 TraceCheckUtils]: 0: Hoare triple {2916#true} call ULTIMATE.init(); {2916#true} is VALID [2018-11-14 17:58:04,632 INFO L273 TraceCheckUtils]: 1: Hoare triple {2916#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {2916#true} is VALID [2018-11-14 17:58:04,633 INFO L273 TraceCheckUtils]: 2: Hoare triple {2916#true} assume true; {2916#true} is VALID [2018-11-14 17:58:04,633 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2916#true} {2916#true} #65#return; {2916#true} is VALID [2018-11-14 17:58:04,633 INFO L256 TraceCheckUtils]: 4: Hoare triple {2916#true} call #t~ret5 := main(); {2916#true} is VALID [2018-11-14 17:58:04,633 INFO L273 TraceCheckUtils]: 5: Hoare triple {2916#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1; {2916#true} is VALID [2018-11-14 17:58:04,656 INFO L273 TraceCheckUtils]: 6: Hoare triple {2916#true} assume ~bvsgt32(~SIZE~0, 1bv32);havoc ~i~0;call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~val2~0 := 3bv32;~val1~0 := 7bv32;~low~0 := 2bv32;~i~0 := ~bvsub32(~SIZE~0, 2bv32); {2939#(= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0)} is VALID [2018-11-14 17:58:04,657 INFO L273 TraceCheckUtils]: 7: Hoare triple {2939#(= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0)} assume true; {2939#(= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0)} is VALID [2018-11-14 17:58:04,657 INFO L273 TraceCheckUtils]: 8: Hoare triple {2939#(= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0)} assume !!~bvsge32(~i~0, 4294967295bv32); {2939#(= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0)} is VALID [2018-11-14 17:58:04,657 INFO L273 TraceCheckUtils]: 9: Hoare triple {2939#(= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0)} assume ~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~val1~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2939#(= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0)} is VALID [2018-11-14 17:58:04,658 INFO L273 TraceCheckUtils]: 10: Hoare triple {2939#(= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0)} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {2939#(= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0)} is VALID [2018-11-14 17:58:04,678 INFO L273 TraceCheckUtils]: 11: Hoare triple {2939#(= (bvadd ~SIZE~0 (_ bv4294967294 32)) main_~i~0)} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {2955#(= (bvadd ~SIZE~0 (_ bv4294967293 32)) main_~i~0)} is VALID [2018-11-14 17:58:04,678 INFO L273 TraceCheckUtils]: 12: Hoare triple {2955#(= (bvadd ~SIZE~0 (_ bv4294967293 32)) main_~i~0)} assume true; {2955#(= (bvadd ~SIZE~0 (_ bv4294967293 32)) main_~i~0)} is VALID [2018-11-14 17:58:04,679 INFO L273 TraceCheckUtils]: 13: Hoare triple {2955#(= (bvadd ~SIZE~0 (_ bv4294967293 32)) main_~i~0)} assume !!~bvsge32(~i~0, 4294967295bv32); {2955#(= (bvadd ~SIZE~0 (_ bv4294967293 32)) main_~i~0)} is VALID [2018-11-14 17:58:04,679 INFO L273 TraceCheckUtils]: 14: Hoare triple {2955#(= (bvadd ~SIZE~0 (_ bv4294967293 32)) main_~i~0)} assume ~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~val1~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2965#(and (bvsge main_~i~0 (_ bv0 32)) (= (bvadd ~SIZE~0 (_ bv4294967293 32)) main_~i~0))} is VALID [2018-11-14 17:58:04,680 INFO L273 TraceCheckUtils]: 15: Hoare triple {2965#(and (bvsge main_~i~0 (_ bv0 32)) (= (bvadd ~SIZE~0 (_ bv4294967293 32)) main_~i~0))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {2965#(and (bvsge main_~i~0 (_ bv0 32)) (= (bvadd ~SIZE~0 (_ bv4294967293 32)) main_~i~0))} is VALID [2018-11-14 17:58:04,706 INFO L273 TraceCheckUtils]: 16: Hoare triple {2965#(and (bvsge main_~i~0 (_ bv0 32)) (= (bvadd ~SIZE~0 (_ bv4294967293 32)) main_~i~0))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {2972#(and (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd ~SIZE~0 (_ bv4294967292 32)) main_~i~0))} is VALID [2018-11-14 17:58:04,707 INFO L273 TraceCheckUtils]: 17: Hoare triple {2972#(and (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd ~SIZE~0 (_ bv4294967292 32)) main_~i~0))} assume true; {2972#(and (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd ~SIZE~0 (_ bv4294967292 32)) main_~i~0))} is VALID [2018-11-14 17:58:04,708 INFO L273 TraceCheckUtils]: 18: Hoare triple {2972#(and (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd ~SIZE~0 (_ bv4294967292 32)) main_~i~0))} assume !!~bvsge32(~i~0, 4294967295bv32); {2972#(and (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd ~SIZE~0 (_ bv4294967292 32)) main_~i~0))} is VALID [2018-11-14 17:58:04,711 INFO L273 TraceCheckUtils]: 19: Hoare triple {2972#(and (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (bvadd ~SIZE~0 (_ bv4294967292 32)) main_~i~0))} assume !~bvsge32(~i~0, 0bv32); {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,712 INFO L273 TraceCheckUtils]: 20: Hoare triple {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,713 INFO L273 TraceCheckUtils]: 21: Hoare triple {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,713 INFO L273 TraceCheckUtils]: 22: Hoare triple {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} assume true; {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,714 INFO L273 TraceCheckUtils]: 23: Hoare triple {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} assume !~bvsge32(~i~0, 4294967295bv32); {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,716 INFO L273 TraceCheckUtils]: 24: Hoare triple {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} ~i~0 := 0bv32; {2998#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,716 INFO L273 TraceCheckUtils]: 25: Hoare triple {2998#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} assume true; {2998#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,717 INFO L273 TraceCheckUtils]: 26: Hoare triple {2998#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2998#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,718 INFO L256 TraceCheckUtils]: 27: Hoare triple {2998#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,718 INFO L273 TraceCheckUtils]: 28: Hoare triple {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} ~cond := #in~cond; {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,719 INFO L273 TraceCheckUtils]: 29: Hoare triple {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} assume !(~cond == 0bv32); {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,720 INFO L273 TraceCheckUtils]: 30: Hoare triple {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} assume true; {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,720 INFO L268 TraceCheckUtils]: 31: Hoare quadruple {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} {2998#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} #69#return; {2998#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,721 INFO L273 TraceCheckUtils]: 32: Hoare triple {2998#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} havoc #t~mem4; {2998#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,722 INFO L273 TraceCheckUtils]: 33: Hoare triple {2998#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= main_~i~0 (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {3026#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,723 INFO L273 TraceCheckUtils]: 34: Hoare triple {3026#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {3026#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,724 INFO L273 TraceCheckUtils]: 35: Hoare triple {3026#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {3026#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,725 INFO L256 TraceCheckUtils]: 36: Hoare triple {3026#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,726 INFO L273 TraceCheckUtils]: 37: Hoare triple {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} ~cond := #in~cond; {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,726 INFO L273 TraceCheckUtils]: 38: Hoare triple {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} assume !(~cond == 0bv32); {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,727 INFO L273 TraceCheckUtils]: 39: Hoare triple {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} assume true; {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,728 INFO L268 TraceCheckUtils]: 40: Hoare quadruple {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} {3026#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #69#return; {3026#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,729 INFO L273 TraceCheckUtils]: 41: Hoare triple {3026#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} havoc #t~mem4; {3026#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,730 INFO L273 TraceCheckUtils]: 42: Hoare triple {3026#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {3054#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:58:04,730 INFO L273 TraceCheckUtils]: 43: Hoare triple {3054#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume true; {3054#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:58:04,731 INFO L273 TraceCheckUtils]: 44: Hoare triple {3054#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {3054#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:58:04,733 INFO L256 TraceCheckUtils]: 45: Hoare triple {3054#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,733 INFO L273 TraceCheckUtils]: 46: Hoare triple {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} ~cond := #in~cond; {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,734 INFO L273 TraceCheckUtils]: 47: Hoare triple {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} assume !(~cond == 0bv32); {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,735 INFO L273 TraceCheckUtils]: 48: Hoare triple {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} assume true; {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,736 INFO L268 TraceCheckUtils]: 49: Hoare quadruple {2982#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} {3054#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} #69#return; {3054#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:58:04,736 INFO L273 TraceCheckUtils]: 50: Hoare triple {3054#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} havoc #t~mem4; {3054#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:58:04,739 INFO L273 TraceCheckUtils]: 51: Hoare triple {3054#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {3082#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,740 INFO L273 TraceCheckUtils]: 52: Hoare triple {3082#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} assume true; {3082#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:04,743 INFO L273 TraceCheckUtils]: 53: Hoare triple {3082#(and (not (bvsge (bvadd ~SIZE~0 (_ bv4294967292 32)) (_ bv0 32))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd ~SIZE~0 (_ bv4294967293 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2917#false} is VALID [2018-11-14 17:58:04,743 INFO L256 TraceCheckUtils]: 54: Hoare triple {2917#false} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {2917#false} is VALID [2018-11-14 17:58:04,743 INFO L273 TraceCheckUtils]: 55: Hoare triple {2917#false} ~cond := #in~cond; {2917#false} is VALID [2018-11-14 17:58:04,744 INFO L273 TraceCheckUtils]: 56: Hoare triple {2917#false} assume ~cond == 0bv32; {2917#false} is VALID [2018-11-14 17:58:04,744 INFO L273 TraceCheckUtils]: 57: Hoare triple {2917#false} assume !false; {2917#false} is VALID [2018-11-14 17:58:04,751 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 9 proven. 42 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-14 17:58:04,751 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-14 17:58:05,332 INFO L273 TraceCheckUtils]: 57: Hoare triple {2917#false} assume !false; {2917#false} is VALID [2018-11-14 17:58:05,332 INFO L273 TraceCheckUtils]: 56: Hoare triple {2917#false} assume ~cond == 0bv32; {2917#false} is VALID [2018-11-14 17:58:05,332 INFO L273 TraceCheckUtils]: 55: Hoare triple {2917#false} ~cond := #in~cond; {2917#false} is VALID [2018-11-14 17:58:05,332 INFO L256 TraceCheckUtils]: 54: Hoare triple {2917#false} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {2917#false} is VALID [2018-11-14 17:58:05,333 INFO L273 TraceCheckUtils]: 53: Hoare triple {3113#(not (bvslt main_~i~0 ~SIZE~0))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {2917#false} is VALID [2018-11-14 17:58:05,333 INFO L273 TraceCheckUtils]: 52: Hoare triple {3113#(not (bvslt main_~i~0 ~SIZE~0))} assume true; {3113#(not (bvslt main_~i~0 ~SIZE~0))} is VALID [2018-11-14 17:58:05,335 INFO L273 TraceCheckUtils]: 51: Hoare triple {3120#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {3113#(not (bvslt main_~i~0 ~SIZE~0))} is VALID [2018-11-14 17:58:05,335 INFO L273 TraceCheckUtils]: 50: Hoare triple {3120#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} havoc #t~mem4; {3120#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} is VALID [2018-11-14 17:58:05,336 INFO L268 TraceCheckUtils]: 49: Hoare quadruple {2916#true} {3120#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} #69#return; {3120#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} is VALID [2018-11-14 17:58:05,336 INFO L273 TraceCheckUtils]: 48: Hoare triple {2916#true} assume true; {2916#true} is VALID [2018-11-14 17:58:05,336 INFO L273 TraceCheckUtils]: 47: Hoare triple {2916#true} assume !(~cond == 0bv32); {2916#true} is VALID [2018-11-14 17:58:05,336 INFO L273 TraceCheckUtils]: 46: Hoare triple {2916#true} ~cond := #in~cond; {2916#true} is VALID [2018-11-14 17:58:05,336 INFO L256 TraceCheckUtils]: 45: Hoare triple {3120#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {2916#true} is VALID [2018-11-14 17:58:05,337 INFO L273 TraceCheckUtils]: 44: Hoare triple {3120#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {3120#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} is VALID [2018-11-14 17:58:05,337 INFO L273 TraceCheckUtils]: 43: Hoare triple {3120#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} assume true; {3120#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} is VALID [2018-11-14 17:58:05,359 INFO L273 TraceCheckUtils]: 42: Hoare triple {3148#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {3120#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~SIZE~0))} is VALID [2018-11-14 17:58:05,359 INFO L273 TraceCheckUtils]: 41: Hoare triple {3148#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} havoc #t~mem4; {3148#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} is VALID [2018-11-14 17:58:05,360 INFO L268 TraceCheckUtils]: 40: Hoare quadruple {2916#true} {3148#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} #69#return; {3148#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} is VALID [2018-11-14 17:58:05,360 INFO L273 TraceCheckUtils]: 39: Hoare triple {2916#true} assume true; {2916#true} is VALID [2018-11-14 17:58:05,360 INFO L273 TraceCheckUtils]: 38: Hoare triple {2916#true} assume !(~cond == 0bv32); {2916#true} is VALID [2018-11-14 17:58:05,361 INFO L273 TraceCheckUtils]: 37: Hoare triple {2916#true} ~cond := #in~cond; {2916#true} is VALID [2018-11-14 17:58:05,361 INFO L256 TraceCheckUtils]: 36: Hoare triple {3148#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {2916#true} is VALID [2018-11-14 17:58:05,361 INFO L273 TraceCheckUtils]: 35: Hoare triple {3148#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {3148#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} is VALID [2018-11-14 17:58:05,362 INFO L273 TraceCheckUtils]: 34: Hoare triple {3148#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} assume true; {3148#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} is VALID [2018-11-14 17:58:05,390 INFO L273 TraceCheckUtils]: 33: Hoare triple {3176#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~SIZE~0))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {3148#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~SIZE~0))} is VALID [2018-11-14 17:58:05,391 INFO L273 TraceCheckUtils]: 32: Hoare triple {3176#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~SIZE~0))} havoc #t~mem4; {3176#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~SIZE~0))} is VALID [2018-11-14 17:58:05,391 INFO L268 TraceCheckUtils]: 31: Hoare quadruple {2916#true} {3176#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~SIZE~0))} #69#return; {3176#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~SIZE~0))} is VALID [2018-11-14 17:58:05,391 INFO L273 TraceCheckUtils]: 30: Hoare triple {2916#true} assume true; {2916#true} is VALID [2018-11-14 17:58:05,392 INFO L273 TraceCheckUtils]: 29: Hoare triple {2916#true} assume !(~cond == 0bv32); {2916#true} is VALID [2018-11-14 17:58:05,392 INFO L273 TraceCheckUtils]: 28: Hoare triple {2916#true} ~cond := #in~cond; {2916#true} is VALID [2018-11-14 17:58:05,392 INFO L256 TraceCheckUtils]: 27: Hoare triple {3176#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~SIZE~0))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {2916#true} is VALID [2018-11-14 17:58:05,392 INFO L273 TraceCheckUtils]: 26: Hoare triple {3176#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~SIZE~0))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {3176#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~SIZE~0))} is VALID [2018-11-14 17:58:05,393 INFO L273 TraceCheckUtils]: 25: Hoare triple {3176#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~SIZE~0))} assume true; {3176#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~SIZE~0))} is VALID [2018-11-14 17:58:05,393 INFO L273 TraceCheckUtils]: 24: Hoare triple {3204#(not (bvslt (_ bv3 32) ~SIZE~0))} ~i~0 := 0bv32; {3176#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~SIZE~0))} is VALID [2018-11-14 17:58:05,393 INFO L273 TraceCheckUtils]: 23: Hoare triple {3204#(not (bvslt (_ bv3 32) ~SIZE~0))} assume !~bvsge32(~i~0, 4294967295bv32); {3204#(not (bvslt (_ bv3 32) ~SIZE~0))} is VALID [2018-11-14 17:58:05,394 INFO L273 TraceCheckUtils]: 22: Hoare triple {3204#(not (bvslt (_ bv3 32) ~SIZE~0))} assume true; {3204#(not (bvslt (_ bv3 32) ~SIZE~0))} is VALID [2018-11-14 17:58:05,394 INFO L273 TraceCheckUtils]: 21: Hoare triple {3204#(not (bvslt (_ bv3 32) ~SIZE~0))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {3204#(not (bvslt (_ bv3 32) ~SIZE~0))} is VALID [2018-11-14 17:58:05,394 INFO L273 TraceCheckUtils]: 20: Hoare triple {3204#(not (bvslt (_ bv3 32) ~SIZE~0))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {3204#(not (bvslt (_ bv3 32) ~SIZE~0))} is VALID [2018-11-14 17:58:05,395 INFO L273 TraceCheckUtils]: 19: Hoare triple {3220#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (bvsge main_~i~0 (_ bv0 32)))} assume !~bvsge32(~i~0, 0bv32); {3204#(not (bvslt (_ bv3 32) ~SIZE~0))} is VALID [2018-11-14 17:58:05,396 INFO L273 TraceCheckUtils]: 18: Hoare triple {3220#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (bvsge main_~i~0 (_ bv0 32)))} assume !!~bvsge32(~i~0, 4294967295bv32); {3220#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (bvsge main_~i~0 (_ bv0 32)))} is VALID [2018-11-14 17:58:05,396 INFO L273 TraceCheckUtils]: 17: Hoare triple {3220#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (bvsge main_~i~0 (_ bv0 32)))} assume true; {3220#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (bvsge main_~i~0 (_ bv0 32)))} is VALID [2018-11-14 17:58:05,398 INFO L273 TraceCheckUtils]: 16: Hoare triple {3230#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {3220#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (bvsge main_~i~0 (_ bv0 32)))} is VALID [2018-11-14 17:58:05,399 INFO L273 TraceCheckUtils]: 15: Hoare triple {3230#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {3230#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:05,400 INFO L273 TraceCheckUtils]: 14: Hoare triple {3237#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (not (bvsge main_~i~0 (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~val1~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {3230#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:05,400 INFO L273 TraceCheckUtils]: 13: Hoare triple {3237#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (not (bvsge main_~i~0 (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~i~0, 4294967295bv32); {3237#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (not (bvsge main_~i~0 (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:05,400 INFO L273 TraceCheckUtils]: 12: Hoare triple {3237#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (not (bvsge main_~i~0 (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {3237#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (not (bvsge main_~i~0 (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:05,403 INFO L273 TraceCheckUtils]: 11: Hoare triple {3247#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {3237#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (not (bvsge main_~i~0 (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:05,403 INFO L273 TraceCheckUtils]: 10: Hoare triple {3247#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32)))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {3247#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:05,404 INFO L273 TraceCheckUtils]: 9: Hoare triple {3247#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32)))} assume ~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~val1~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {3247#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:05,404 INFO L273 TraceCheckUtils]: 8: Hoare triple {3247#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32)))} assume !!~bvsge32(~i~0, 4294967295bv32); {3247#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:05,404 INFO L273 TraceCheckUtils]: 7: Hoare triple {3247#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32)))} assume true; {3247#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:05,409 INFO L273 TraceCheckUtils]: 6: Hoare triple {2916#true} assume ~bvsgt32(~SIZE~0, 1bv32);havoc ~i~0;call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~val2~0 := 3bv32;~val1~0 := 7bv32;~low~0 := 2bv32;~i~0 := ~bvsub32(~SIZE~0, 2bv32); {3247#(or (not (bvslt (_ bv3 32) ~SIZE~0)) (not (bvsge (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) (bvsge (bvadd main_~i~0 (_ bv4294967294 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:05,409 INFO L273 TraceCheckUtils]: 5: Hoare triple {2916#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1; {2916#true} is VALID [2018-11-14 17:58:05,409 INFO L256 TraceCheckUtils]: 4: Hoare triple {2916#true} call #t~ret5 := main(); {2916#true} is VALID [2018-11-14 17:58:05,409 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2916#true} {2916#true} #65#return; {2916#true} is VALID [2018-11-14 17:58:05,409 INFO L273 TraceCheckUtils]: 2: Hoare triple {2916#true} assume true; {2916#true} is VALID [2018-11-14 17:58:05,409 INFO L273 TraceCheckUtils]: 1: Hoare triple {2916#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {2916#true} is VALID [2018-11-14 17:58:05,409 INFO L256 TraceCheckUtils]: 0: Hoare triple {2916#true} call ULTIMATE.init(); {2916#true} is VALID [2018-11-14 17:58:05,414 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 19 proven. 32 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-14 17:58:05,416 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-14 17:58:05,416 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 20 [2018-11-14 17:58:05,416 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 58 [2018-11-14 17:58:05,417 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 17:58:05,417 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 20 states. [2018-11-14 17:58:05,705 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 94 edges. 94 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:58:05,705 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-14 17:58:05,706 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-14 17:58:05,706 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=114, Invalid=266, Unknown=0, NotChecked=0, Total=380 [2018-11-14 17:58:05,706 INFO L87 Difference]: Start difference. First operand 61 states and 63 transitions. Second operand 20 states. [2018-11-14 17:58:10,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:58:10,358 INFO L93 Difference]: Finished difference Result 172 states and 182 transitions. [2018-11-14 17:58:10,358 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-11-14 17:58:10,359 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 58 [2018-11-14 17:58:10,359 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 17:58:10,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2018-11-14 17:58:10,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 153 transitions. [2018-11-14 17:58:10,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2018-11-14 17:58:10,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 153 transitions. [2018-11-14 17:58:10,369 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 26 states and 153 transitions. [2018-11-14 17:58:10,923 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 153 edges. 153 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 17:58:10,925 INFO L225 Difference]: With dead ends: 172 [2018-11-14 17:58:10,925 INFO L226 Difference]: Without dead ends: 81 [2018-11-14 17:58:10,926 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 125 GetRequests, 97 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 172 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=268, Invalid=602, Unknown=0, NotChecked=0, Total=870 [2018-11-14 17:58:10,926 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states. [2018-11-14 17:58:11,167 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 67. [2018-11-14 17:58:11,167 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 17:58:11,167 INFO L82 GeneralOperation]: Start isEquivalent. First operand 81 states. Second operand 67 states. [2018-11-14 17:58:11,167 INFO L74 IsIncluded]: Start isIncluded. First operand 81 states. Second operand 67 states. [2018-11-14 17:58:11,167 INFO L87 Difference]: Start difference. First operand 81 states. Second operand 67 states. [2018-11-14 17:58:11,170 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:58:11,171 INFO L93 Difference]: Finished difference Result 81 states and 85 transitions. [2018-11-14 17:58:11,171 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 85 transitions. [2018-11-14 17:58:11,171 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:58:11,171 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:58:11,171 INFO L74 IsIncluded]: Start isIncluded. First operand 67 states. Second operand 81 states. [2018-11-14 17:58:11,172 INFO L87 Difference]: Start difference. First operand 67 states. Second operand 81 states. [2018-11-14 17:58:11,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 17:58:11,175 INFO L93 Difference]: Finished difference Result 81 states and 85 transitions. [2018-11-14 17:58:11,175 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 85 transitions. [2018-11-14 17:58:11,175 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 17:58:11,175 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 17:58:11,175 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 17:58:11,175 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 17:58:11,175 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67 states. [2018-11-14 17:58:11,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 70 transitions. [2018-11-14 17:58:11,177 INFO L78 Accepts]: Start accepts. Automaton has 67 states and 70 transitions. Word has length 58 [2018-11-14 17:58:11,178 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 17:58:11,178 INFO L480 AbstractCegarLoop]: Abstraction has 67 states and 70 transitions. [2018-11-14 17:58:11,178 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-14 17:58:11,178 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 70 transitions. [2018-11-14 17:58:11,178 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-11-14 17:58:11,179 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 17:58:11,179 INFO L375 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 17:58:11,179 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 17:58:11,179 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 17:58:11,179 INFO L82 PathProgramCache]: Analyzing trace with hash -2108724814, now seen corresponding path program 5 times [2018-11-14 17:58:11,179 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 17:58:11,179 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 17:58:11,195 INFO L101 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2018-11-14 17:58:11,606 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2018-11-14 17:58:11,606 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-14 17:58:11,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 17:58:11,667 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 17:58:11,732 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-14 17:58:11,740 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-14 17:58:11,742 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:58:11,748 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:58:11,769 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:58:11,769 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:30, output treesize:26 [2018-11-14 17:58:11,878 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 23 [2018-11-14 17:58:11,887 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:11,895 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 37 [2018-11-14 17:58:11,898 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:58:11,915 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:58:11,942 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:58:11,943 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:41, output treesize:37 [2018-11-14 17:58:12,024 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 33 [2018-11-14 17:58:12,040 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:12,043 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:12,045 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:12,054 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 76 [2018-11-14 17:58:12,058 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:58:12,086 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:58:12,120 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:58:12,120 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:53, output treesize:49 [2018-11-14 17:58:12,340 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 49 treesize of output 40 [2018-11-14 17:58:12,356 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:12,359 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:12,362 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:12,365 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:12,367 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:12,369 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:12,387 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 126 [2018-11-14 17:58:12,390 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:58:12,429 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:58:12,474 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:58:12,474 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:65, output treesize:61 [2018-11-14 17:58:12,613 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 61 treesize of output 50 [2018-11-14 17:58:12,637 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:12,640 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:12,644 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:12,648 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:12,651 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:12,654 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:12,808 INFO L303 Elim1Store]: Index analysis took 179 ms [2018-11-14 17:58:12,809 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 50 treesize of output 129 [2018-11-14 17:58:12,813 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:58:12,851 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:58:12,889 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:58:12,889 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:77, output treesize:53 [2018-11-14 17:58:12,918 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:58:13,314 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 44 [2018-11-14 17:58:13,328 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:13,331 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:13,332 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:13,333 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:13,335 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:13,337 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:13,339 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 133 [2018-11-14 17:58:13,342 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:58:13,641 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:58:13,786 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 17:58:13,786 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:70, output treesize:66 [2018-11-14 17:58:13,812 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:58:15,603 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 48 [2018-11-14 17:58:15,620 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:15,621 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:15,622 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:15,622 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:15,624 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:15,626 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:15,627 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:15,629 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:15,630 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 17:58:15,631 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 17:58:15,634 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 6 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 112 [2018-11-14 17:58:15,641 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 17:58:15,661 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:58:15,676 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 17:58:15,676 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:72, output treesize:11 [2018-11-14 17:58:15,686 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 17:58:15,848 INFO L256 TraceCheckUtils]: 0: Hoare triple {3776#true} call ULTIMATE.init(); {3776#true} is VALID [2018-11-14 17:58:15,848 INFO L273 TraceCheckUtils]: 1: Hoare triple {3776#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~SIZE~0 := 0bv32; {3776#true} is VALID [2018-11-14 17:58:15,848 INFO L273 TraceCheckUtils]: 2: Hoare triple {3776#true} assume true; {3776#true} is VALID [2018-11-14 17:58:15,848 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {3776#true} {3776#true} #65#return; {3776#true} is VALID [2018-11-14 17:58:15,849 INFO L256 TraceCheckUtils]: 4: Hoare triple {3776#true} call #t~ret5 := main(); {3776#true} is VALID [2018-11-14 17:58:15,849 INFO L273 TraceCheckUtils]: 5: Hoare triple {3776#true} ~SIZE~0 := #t~nondet1;havoc #t~nondet1; {3776#true} is VALID [2018-11-14 17:58:15,849 INFO L273 TraceCheckUtils]: 6: Hoare triple {3776#true} assume ~bvsgt32(~SIZE~0, 1bv32);havoc ~i~0;call ~#a~0.base, ~#a~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~SIZE~0));~val2~0 := 3bv32;~val1~0 := 7bv32;~low~0 := 2bv32;~i~0 := ~bvsub32(~SIZE~0, 2bv32); {3799#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:58:15,850 INFO L273 TraceCheckUtils]: 7: Hoare triple {3799#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} assume true; {3799#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:58:15,850 INFO L273 TraceCheckUtils]: 8: Hoare triple {3799#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} assume !!~bvsge32(~i~0, 4294967295bv32); {3799#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:58:15,851 INFO L273 TraceCheckUtils]: 9: Hoare triple {3799#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} assume ~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~val1~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {3799#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:58:15,853 INFO L273 TraceCheckUtils]: 10: Hoare triple {3799#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {3812#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~val2~0))} is VALID [2018-11-14 17:58:17,862 INFO L273 TraceCheckUtils]: 11: Hoare triple {3812#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~val2~0))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {3816#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is UNKNOWN [2018-11-14 17:58:17,863 INFO L273 TraceCheckUtils]: 12: Hoare triple {3816#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} assume true; {3816#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is VALID [2018-11-14 17:58:17,864 INFO L273 TraceCheckUtils]: 13: Hoare triple {3816#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} assume !!~bvsge32(~i~0, 4294967295bv32); {3816#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is VALID [2018-11-14 17:58:17,867 INFO L273 TraceCheckUtils]: 14: Hoare triple {3816#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} assume ~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~val1~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {3826#(and (= main_~val1~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)))) (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is VALID [2018-11-14 17:58:17,872 INFO L273 TraceCheckUtils]: 15: Hoare triple {3826#(and (= main_~val1~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)))) (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {3830#(and (= main_~val1~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)))) (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~val2~0))} is VALID [2018-11-14 17:58:18,103 INFO L273 TraceCheckUtils]: 16: Hoare triple {3830#(and (= main_~val1~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)))) (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~val2~0))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {3834#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~val1~0) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is VALID [2018-11-14 17:58:18,104 INFO L273 TraceCheckUtils]: 17: Hoare triple {3834#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~val1~0) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} assume true; {3834#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~val1~0) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is VALID [2018-11-14 17:58:18,105 INFO L273 TraceCheckUtils]: 18: Hoare triple {3834#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~val1~0) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} assume !!~bvsge32(~i~0, 4294967295bv32); {3834#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~val1~0) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is VALID [2018-11-14 17:58:18,111 INFO L273 TraceCheckUtils]: 19: Hoare triple {3834#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~val1~0) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} assume ~bvsge32(~i~0, 0bv32);call write~intINTTYPE4(~val1~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {3844#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~i~0 (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)))) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is VALID [2018-11-14 17:58:18,114 INFO L273 TraceCheckUtils]: 20: Hoare triple {3844#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~i~0 (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0)))) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {3848#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~i~0 (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~val2~0))} is VALID [2018-11-14 17:58:18,417 INFO L273 TraceCheckUtils]: 21: Hoare triple {3848#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~i~0 (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~val2~0))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {3852#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv16 32))) main_~val2~0) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is VALID [2018-11-14 17:58:18,418 INFO L273 TraceCheckUtils]: 22: Hoare triple {3852#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv16 32))) main_~val2~0) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} assume true; {3852#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv16 32))) main_~val2~0) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is VALID [2018-11-14 17:58:18,419 INFO L273 TraceCheckUtils]: 23: Hoare triple {3852#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv16 32))) main_~val2~0) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} assume !!~bvsge32(~i~0, 4294967295bv32); {3852#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv16 32))) main_~val2~0) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is VALID [2018-11-14 17:58:18,421 INFO L273 TraceCheckUtils]: 24: Hoare triple {3852#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv16 32))) main_~val2~0) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} assume !~bvsge32(~i~0, 0bv32); {3862#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (not (bvsge main_~i~0 (_ bv0 32))) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv16 32))) main_~val2~0) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} is VALID [2018-11-14 17:58:18,428 INFO L273 TraceCheckUtils]: 25: Hoare triple {3862#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (not (bvsge main_~i~0 (_ bv0 32))) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32)))) (= (bvadd main_~val2~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv16 32))) main_~val2~0) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~val2~0 (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))))} call write~intINTTYPE4(~val2~0, ~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~bvadd32(1bv32, ~i~0))), 4bv32); {3866#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:58:18,432 INFO L273 TraceCheckUtils]: 26: Hoare triple {3866#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvsub32(#t~post2, 1bv32);havoc #t~post2; {3866#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:58:18,436 INFO L273 TraceCheckUtils]: 27: Hoare triple {3866#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} assume true; {3866#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:58:18,440 INFO L273 TraceCheckUtils]: 28: Hoare triple {3866#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} assume !~bvsge32(~i~0, 4294967295bv32); {3866#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} is VALID [2018-11-14 17:58:18,444 INFO L273 TraceCheckUtils]: 29: Hoare triple {3866#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((main_~i~0 (_ BitVec 32))) (and (not (bvsge main_~i~0 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd main_~i~0 (_ bv1 32)) (_ bv0 32)))) (= |main_~#a~0.offset| (_ bv0 32)))} ~i~0 := 0bv32; {3879#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))))} is VALID [2018-11-14 17:58:18,445 INFO L273 TraceCheckUtils]: 30: Hoare triple {3879#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))))} assume true; {3879#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))))} is VALID [2018-11-14 17:58:18,446 INFO L273 TraceCheckUtils]: 31: Hoare triple {3879#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {3879#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))))} is VALID [2018-11-14 17:58:18,450 INFO L256 TraceCheckUtils]: 32: Hoare triple {3879#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} is VALID [2018-11-14 17:58:18,451 INFO L273 TraceCheckUtils]: 33: Hoare triple {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} ~cond := #in~cond; {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} is VALID [2018-11-14 17:58:18,451 INFO L273 TraceCheckUtils]: 34: Hoare triple {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} assume !(~cond == 0bv32); {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} is VALID [2018-11-14 17:58:18,452 INFO L273 TraceCheckUtils]: 35: Hoare triple {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} assume true; {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} is VALID [2018-11-14 17:58:18,467 INFO L268 TraceCheckUtils]: 36: Hoare quadruple {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} {3879#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))))} #69#return; {3879#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))))} is VALID [2018-11-14 17:58:18,468 INFO L273 TraceCheckUtils]: 37: Hoare triple {3879#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))))} havoc #t~mem4; {3879#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))))} is VALID [2018-11-14 17:58:18,469 INFO L273 TraceCheckUtils]: 38: Hoare triple {3879#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {3908#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:18,473 INFO L273 TraceCheckUtils]: 39: Hoare triple {3908#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {3908#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:18,477 INFO L273 TraceCheckUtils]: 40: Hoare triple {3908#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {3908#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:18,482 INFO L256 TraceCheckUtils]: 41: Hoare triple {3908#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} is VALID [2018-11-14 17:58:18,483 INFO L273 TraceCheckUtils]: 42: Hoare triple {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} ~cond := #in~cond; {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} is VALID [2018-11-14 17:58:18,483 INFO L273 TraceCheckUtils]: 43: Hoare triple {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} assume !(~cond == 0bv32); {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} is VALID [2018-11-14 17:58:18,484 INFO L273 TraceCheckUtils]: 44: Hoare triple {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} assume true; {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} is VALID [2018-11-14 17:58:18,484 INFO L268 TraceCheckUtils]: 45: Hoare quadruple {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} {3908#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #69#return; {3908#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:18,489 INFO L273 TraceCheckUtils]: 46: Hoare triple {3908#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} havoc #t~mem4; {3908#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 17:58:18,490 INFO L273 TraceCheckUtils]: 47: Hoare triple {3908#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {3936#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:58:18,491 INFO L273 TraceCheckUtils]: 48: Hoare triple {3936#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))) (= (_ bv2 32) main_~i~0))} assume true; {3936#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:58:18,491 INFO L273 TraceCheckUtils]: 49: Hoare triple {3936#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))) (= (_ bv2 32) main_~i~0))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {3936#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:58:18,496 INFO L256 TraceCheckUtils]: 50: Hoare triple {3936#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))) (= (_ bv2 32) main_~i~0))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} is VALID [2018-11-14 17:58:18,497 INFO L273 TraceCheckUtils]: 51: Hoare triple {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} ~cond := #in~cond; {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} is VALID [2018-11-14 17:58:18,498 INFO L273 TraceCheckUtils]: 52: Hoare triple {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} assume !(~cond == 0bv32); {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} is VALID [2018-11-14 17:58:18,498 INFO L273 TraceCheckUtils]: 53: Hoare triple {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} assume true; {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} is VALID [2018-11-14 17:58:18,499 INFO L268 TraceCheckUtils]: 54: Hoare quadruple {3889#(exists ((v_prenex_8 (_ BitVec 32)) (|v_main_~#a~0.base_BEFORE_CALL_7| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32)))) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#a~0.base_BEFORE_CALL_7|) (bvadd (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))))))} {3936#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))) (= (_ bv2 32) main_~i~0))} #69#return; {3936#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:58:18,500 INFO L273 TraceCheckUtils]: 55: Hoare triple {3936#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))) (= (_ bv2 32) main_~i~0))} havoc #t~mem4; {3936#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 17:58:18,505 INFO L273 TraceCheckUtils]: 56: Hoare triple {3936#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))) (= (_ bv2 32) main_~i~0))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {3964#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))))} is VALID [2018-11-14 17:58:18,506 INFO L273 TraceCheckUtils]: 57: Hoare triple {3964#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))))} assume true; {3964#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))))} is VALID [2018-11-14 17:58:18,509 INFO L273 TraceCheckUtils]: 58: Hoare triple {3964#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#a~0.offset| (_ bv0 32)) (exists ((v_prenex_8 (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv12 32))) (_ bv4294967293 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_8 (_ bv1 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#a~0.base|) (bvadd |main_~#a~0.offset| (bvmul (_ bv4 32) v_prenex_8) (_ bv16 32))) (_ bv4294967293 32)) (_ bv0 32)) (not (bvsge v_prenex_8 (_ bv0 32))))))} assume !!~bvslt32(~i~0, ~SIZE~0);call #t~mem4 := read~intINTTYPE4(~#a~0.base, ~bvadd32(~#a~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32); {3971#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv3 32) |main_#t~mem4|))} is VALID [2018-11-14 17:58:18,510 INFO L256 TraceCheckUtils]: 59: Hoare triple {3971#(and (= (bvadd main_~low~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv3 32) |main_#t~mem4|))} call __VERIFIER_assert((if ~bvsge32(#t~mem4, ~low~0) then 1bv32 else 0bv32)); {3975#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-14 17:58:18,511 INFO L273 TraceCheckUtils]: 60: Hoare triple {3975#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {3979#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-14 17:58:18,511 INFO L273 TraceCheckUtils]: 61: Hoare triple {3979#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume ~cond == 0bv32; {3777#false} is VALID [2018-11-14 17:58:18,511 INFO L273 TraceCheckUtils]: 62: Hoare triple {3777#false} assume !false; {3777#false} is VALID [2018-11-14 17:58:18,544 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 20 proven. 48 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-14 17:58:18,545 INFO L316 TraceCheckSpWp]: Computing backward predicates...