java -ea -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf -i ../../../trunk/examples/svcomp/array-tiling/pr4_true-unreach-call.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-370d6ab [2018-11-14 16:05:31,139 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-14 16:05:31,144 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-14 16:05:31,162 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-14 16:05:31,162 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-14 16:05:31,163 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-14 16:05:31,165 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-14 16:05:31,166 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-14 16:05:31,168 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-14 16:05:31,169 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-14 16:05:31,170 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-14 16:05:31,170 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-14 16:05:31,171 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-14 16:05:31,172 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-14 16:05:31,173 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-14 16:05:31,174 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-14 16:05:31,175 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-14 16:05:31,177 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-14 16:05:31,179 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-14 16:05:31,183 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-14 16:05:31,184 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-14 16:05:31,185 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-14 16:05:31,191 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-14 16:05:31,192 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-14 16:05:31,192 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-14 16:05:31,193 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-14 16:05:31,194 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-14 16:05:31,194 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-14 16:05:31,195 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-14 16:05:31,196 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-14 16:05:31,196 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-14 16:05:31,197 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-14 16:05:31,197 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-14 16:05:31,198 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-14 16:05:31,198 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-14 16:05:31,199 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-14 16:05:31,199 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf [2018-11-14 16:05:31,215 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-14 16:05:31,215 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-14 16:05:31,216 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-14 16:05:31,216 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-11-14 16:05:31,217 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-14 16:05:31,217 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-14 16:05:31,217 INFO L133 SettingsManager]: * Use SBE=true [2018-11-14 16:05:31,217 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-14 16:05:31,217 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-14 16:05:31,218 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-14 16:05:31,218 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-14 16:05:31,218 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-14 16:05:31,218 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-14 16:05:31,218 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-14 16:05:31,218 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-14 16:05:31,219 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-14 16:05:31,219 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-14 16:05:31,219 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-14 16:05:31,219 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-14 16:05:31,219 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-14 16:05:31,220 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-14 16:05:31,220 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-14 16:05:31,220 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-14 16:05:31,220 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-14 16:05:31,220 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-14 16:05:31,221 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-14 16:05:31,221 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-14 16:05:31,221 INFO L133 SettingsManager]: * Trace refinement strategy=WOLF [2018-11-14 16:05:31,221 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-14 16:05:31,221 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-11-14 16:05:31,222 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-11-14 16:05:31,222 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-14 16:05:31,269 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-14 16:05:31,287 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-14 16:05:31,292 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-14 16:05:31,293 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-14 16:05:31,294 INFO L276 PluginConnector]: CDTParser initialized [2018-11-14 16:05:31,295 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-tiling/pr4_true-unreach-call.i [2018-11-14 16:05:31,360 INFO L218 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4507cc848/7883b5a6dfbe410b9611843a6b55bbfc/FLAGb39d32d78 [2018-11-14 16:05:31,816 INFO L298 CDTParser]: Found 1 translation units. [2018-11-14 16:05:31,817 INFO L158 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-tiling/pr4_true-unreach-call.i [2018-11-14 16:05:31,824 INFO L346 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4507cc848/7883b5a6dfbe410b9611843a6b55bbfc/FLAGb39d32d78 [2018-11-14 16:05:31,841 INFO L354 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4507cc848/7883b5a6dfbe410b9611843a6b55bbfc [2018-11-14 16:05:31,851 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-14 16:05:31,853 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-11-14 16:05:31,854 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-14 16:05:31,854 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-14 16:05:31,858 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-14 16:05:31,860 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.11 04:05:31" (1/1) ... [2018-11-14 16:05:31,863 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@c5c9c23 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:05:31, skipping insertion in model container [2018-11-14 16:05:31,863 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.11 04:05:31" (1/1) ... [2018-11-14 16:05:31,872 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-14 16:05:31,905 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-14 16:05:32,159 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-14 16:05:32,165 INFO L191 MainTranslator]: Completed pre-run [2018-11-14 16:05:32,200 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-14 16:05:32,231 INFO L195 MainTranslator]: Completed translation [2018-11-14 16:05:32,232 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:05:32 WrapperNode [2018-11-14 16:05:32,232 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-14 16:05:32,233 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-14 16:05:32,233 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-14 16:05:32,233 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-14 16:05:32,248 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:05:32" (1/1) ... [2018-11-14 16:05:32,249 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:05:32" (1/1) ... [2018-11-14 16:05:32,258 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:05:32" (1/1) ... [2018-11-14 16:05:32,259 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:05:32" (1/1) ... [2018-11-14 16:05:32,274 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:05:32" (1/1) ... [2018-11-14 16:05:32,282 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:05:32" (1/1) ... [2018-11-14 16:05:32,284 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:05:32" (1/1) ... [2018-11-14 16:05:32,287 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-14 16:05:32,288 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-14 16:05:32,288 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-14 16:05:32,288 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-14 16:05:32,289 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:05:32" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-14 16:05:32,417 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-14 16:05:32,417 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-14 16:05:32,417 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-11-14 16:05:32,417 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-14 16:05:32,418 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-11-14 16:05:32,418 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assume [2018-11-14 16:05:32,418 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-11-14 16:05:32,418 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-11-14 16:05:32,418 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-14 16:05:32,418 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-14 16:05:32,419 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-14 16:05:32,419 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE4 [2018-11-14 16:05:32,419 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE4 [2018-11-14 16:05:32,419 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-14 16:05:32,419 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-14 16:05:32,420 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~intINTTYPE4 [2018-11-14 16:05:33,228 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-14 16:05:33,229 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.11 04:05:33 BoogieIcfgContainer [2018-11-14 16:05:33,229 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-14 16:05:33,230 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-14 16:05:33,230 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-14 16:05:33,234 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-14 16:05:33,234 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 14.11 04:05:31" (1/3) ... [2018-11-14 16:05:33,235 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@46f989ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.11 04:05:33, skipping insertion in model container [2018-11-14 16:05:33,235 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:05:32" (2/3) ... [2018-11-14 16:05:33,236 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@46f989ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.11 04:05:33, skipping insertion in model container [2018-11-14 16:05:33,236 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.11 04:05:33" (3/3) ... [2018-11-14 16:05:33,238 INFO L112 eAbstractionObserver]: Analyzing ICFG pr4_true-unreach-call.i [2018-11-14 16:05:33,248 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-14 16:05:33,257 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-14 16:05:33,276 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-14 16:05:33,310 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-14 16:05:33,311 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-14 16:05:33,311 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-14 16:05:33,311 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-14 16:05:33,311 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-14 16:05:33,312 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-14 16:05:33,312 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-14 16:05:33,313 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-14 16:05:33,313 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-14 16:05:33,334 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states. [2018-11-14 16:05:33,339 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-14 16:05:33,339 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 16:05:33,340 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 16:05:33,343 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 16:05:33,348 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 16:05:33,349 INFO L82 PathProgramCache]: Analyzing trace with hash 1675708158, now seen corresponding path program 1 times [2018-11-14 16:05:33,353 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 16:05:33,353 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 16:05:33,371 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 16:05:33,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 16:05:33,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 16:05:33,456 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 16:05:33,666 INFO L256 TraceCheckUtils]: 0: Hoare triple {37#true} call ULTIMATE.init(); {37#true} is VALID [2018-11-14 16:05:33,670 INFO L273 TraceCheckUtils]: 1: Hoare triple {37#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {37#true} is VALID [2018-11-14 16:05:33,670 INFO L273 TraceCheckUtils]: 2: Hoare triple {37#true} assume true; {37#true} is VALID [2018-11-14 16:05:33,671 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {37#true} {37#true} #91#return; {37#true} is VALID [2018-11-14 16:05:33,671 INFO L256 TraceCheckUtils]: 4: Hoare triple {37#true} call #t~ret7 := main(); {37#true} is VALID [2018-11-14 16:05:33,671 INFO L273 TraceCheckUtils]: 5: Hoare triple {37#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {37#true} is VALID [2018-11-14 16:05:33,672 INFO L273 TraceCheckUtils]: 6: Hoare triple {37#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {37#true} is VALID [2018-11-14 16:05:33,672 INFO L273 TraceCheckUtils]: 7: Hoare triple {37#true} assume !(~bvsrem32(~CELLCOUNT~0, 4bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 4bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {37#true} is VALID [2018-11-14 16:05:33,673 INFO L273 TraceCheckUtils]: 8: Hoare triple {37#true} assume !true; {38#false} is VALID [2018-11-14 16:05:33,673 INFO L273 TraceCheckUtils]: 9: Hoare triple {38#false} ~i~0 := 0bv32; {38#false} is VALID [2018-11-14 16:05:33,674 INFO L273 TraceCheckUtils]: 10: Hoare triple {38#false} assume true; {38#false} is VALID [2018-11-14 16:05:33,674 INFO L273 TraceCheckUtils]: 11: Hoare triple {38#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {38#false} is VALID [2018-11-14 16:05:33,674 INFO L273 TraceCheckUtils]: 12: Hoare triple {38#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {38#false} is VALID [2018-11-14 16:05:33,674 INFO L256 TraceCheckUtils]: 13: Hoare triple {38#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {38#false} is VALID [2018-11-14 16:05:33,675 INFO L273 TraceCheckUtils]: 14: Hoare triple {38#false} ~cond := #in~cond; {38#false} is VALID [2018-11-14 16:05:33,675 INFO L273 TraceCheckUtils]: 15: Hoare triple {38#false} assume ~cond == 0bv32; {38#false} is VALID [2018-11-14 16:05:33,675 INFO L273 TraceCheckUtils]: 16: Hoare triple {38#false} assume !false; {38#false} is VALID [2018-11-14 16:05:33,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 16:05:33,679 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-14 16:05:33,686 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-14 16:05:33,686 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-14 16:05:33,692 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 17 [2018-11-14 16:05:33,699 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 16:05:33,705 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 2 states. [2018-11-14 16:05:33,792 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 17 edges. 17 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 16:05:33,792 INFO L459 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-11-14 16:05:33,800 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-11-14 16:05:33,801 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-14 16:05:33,803 INFO L87 Difference]: Start difference. First operand 34 states. Second operand 2 states. [2018-11-14 16:05:33,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 16:05:33,937 INFO L93 Difference]: Finished difference Result 53 states and 68 transitions. [2018-11-14 16:05:33,937 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-11-14 16:05:33,937 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 17 [2018-11-14 16:05:33,938 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 16:05:33,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2018-11-14 16:05:33,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 68 transitions. [2018-11-14 16:05:33,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2018-11-14 16:05:33,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 68 transitions. [2018-11-14 16:05:33,957 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 2 states and 68 transitions. [2018-11-14 16:05:34,288 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 68 edges. 68 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 16:05:34,300 INFO L225 Difference]: With dead ends: 53 [2018-11-14 16:05:34,300 INFO L226 Difference]: Without dead ends: 28 [2018-11-14 16:05:34,304 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 16 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-14 16:05:34,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2018-11-14 16:05:34,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 28. [2018-11-14 16:05:34,370 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 16:05:34,371 INFO L82 GeneralOperation]: Start isEquivalent. First operand 28 states. Second operand 28 states. [2018-11-14 16:05:34,371 INFO L74 IsIncluded]: Start isIncluded. First operand 28 states. Second operand 28 states. [2018-11-14 16:05:34,372 INFO L87 Difference]: Start difference. First operand 28 states. Second operand 28 states. [2018-11-14 16:05:34,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 16:05:34,377 INFO L93 Difference]: Finished difference Result 28 states and 34 transitions. [2018-11-14 16:05:34,377 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 34 transitions. [2018-11-14 16:05:34,378 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 16:05:34,378 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 16:05:34,378 INFO L74 IsIncluded]: Start isIncluded. First operand 28 states. Second operand 28 states. [2018-11-14 16:05:34,379 INFO L87 Difference]: Start difference. First operand 28 states. Second operand 28 states. [2018-11-14 16:05:34,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 16:05:34,383 INFO L93 Difference]: Finished difference Result 28 states and 34 transitions. [2018-11-14 16:05:34,383 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 34 transitions. [2018-11-14 16:05:34,384 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 16:05:34,384 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 16:05:34,384 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 16:05:34,385 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 16:05:34,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28 states. [2018-11-14 16:05:34,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 34 transitions. [2018-11-14 16:05:34,390 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 34 transitions. Word has length 17 [2018-11-14 16:05:34,390 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 16:05:34,390 INFO L480 AbstractCegarLoop]: Abstraction has 28 states and 34 transitions. [2018-11-14 16:05:34,391 INFO L481 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-11-14 16:05:34,391 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 34 transitions. [2018-11-14 16:05:34,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-11-14 16:05:34,392 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 16:05:34,392 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 16:05:34,392 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 16:05:34,393 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 16:05:34,393 INFO L82 PathProgramCache]: Analyzing trace with hash -391908819, now seen corresponding path program 1 times [2018-11-14 16:05:34,393 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 16:05:34,394 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 16:05:34,415 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 16:05:34,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 16:05:34,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 16:05:34,495 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 16:05:34,924 INFO L256 TraceCheckUtils]: 0: Hoare triple {245#true} call ULTIMATE.init(); {245#true} is VALID [2018-11-14 16:05:34,925 INFO L273 TraceCheckUtils]: 1: Hoare triple {245#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {245#true} is VALID [2018-11-14 16:05:34,925 INFO L273 TraceCheckUtils]: 2: Hoare triple {245#true} assume true; {245#true} is VALID [2018-11-14 16:05:34,925 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {245#true} {245#true} #91#return; {245#true} is VALID [2018-11-14 16:05:34,926 INFO L256 TraceCheckUtils]: 4: Hoare triple {245#true} call #t~ret7 := main(); {245#true} is VALID [2018-11-14 16:05:34,926 INFO L273 TraceCheckUtils]: 5: Hoare triple {245#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {245#true} is VALID [2018-11-14 16:05:34,933 INFO L273 TraceCheckUtils]: 6: Hoare triple {245#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {268#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} is VALID [2018-11-14 16:05:34,934 INFO L273 TraceCheckUtils]: 7: Hoare triple {268#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} assume !(~bvsrem32(~CELLCOUNT~0, 4bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 4bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {272#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:34,944 INFO L273 TraceCheckUtils]: 8: Hoare triple {272#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {272#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:34,959 INFO L273 TraceCheckUtils]: 9: Hoare triple {272#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {246#false} is VALID [2018-11-14 16:05:34,960 INFO L273 TraceCheckUtils]: 10: Hoare triple {246#false} ~i~0 := 0bv32; {246#false} is VALID [2018-11-14 16:05:34,960 INFO L273 TraceCheckUtils]: 11: Hoare triple {246#false} assume true; {246#false} is VALID [2018-11-14 16:05:34,960 INFO L273 TraceCheckUtils]: 12: Hoare triple {246#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {246#false} is VALID [2018-11-14 16:05:34,961 INFO L273 TraceCheckUtils]: 13: Hoare triple {246#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {246#false} is VALID [2018-11-14 16:05:34,961 INFO L256 TraceCheckUtils]: 14: Hoare triple {246#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {246#false} is VALID [2018-11-14 16:05:34,962 INFO L273 TraceCheckUtils]: 15: Hoare triple {246#false} ~cond := #in~cond; {246#false} is VALID [2018-11-14 16:05:34,962 INFO L273 TraceCheckUtils]: 16: Hoare triple {246#false} assume ~cond == 0bv32; {246#false} is VALID [2018-11-14 16:05:34,962 INFO L273 TraceCheckUtils]: 17: Hoare triple {246#false} assume !false; {246#false} is VALID [2018-11-14 16:05:34,965 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 16:05:34,965 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-14 16:05:34,970 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-14 16:05:34,970 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-14 16:05:34,972 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 18 [2018-11-14 16:05:34,972 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 16:05:34,973 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states. [2018-11-14 16:05:35,090 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 18 edges. 18 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 16:05:35,090 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-14 16:05:35,091 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-14 16:05:35,091 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-14 16:05:35,091 INFO L87 Difference]: Start difference. First operand 28 states and 34 transitions. Second operand 4 states. [2018-11-14 16:05:35,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 16:05:35,916 INFO L93 Difference]: Finished difference Result 48 states and 60 transitions. [2018-11-14 16:05:35,916 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-14 16:05:35,917 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 18 [2018-11-14 16:05:35,917 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 16:05:35,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-14 16:05:35,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 60 transitions. [2018-11-14 16:05:35,921 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-14 16:05:35,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 60 transitions. [2018-11-14 16:05:35,924 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states and 60 transitions. [2018-11-14 16:05:36,134 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 60 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 16:05:36,137 INFO L225 Difference]: With dead ends: 48 [2018-11-14 16:05:36,137 INFO L226 Difference]: Without dead ends: 35 [2018-11-14 16:05:36,138 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 15 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-14 16:05:36,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states. [2018-11-14 16:05:36,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 30. [2018-11-14 16:05:36,170 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 16:05:36,170 INFO L82 GeneralOperation]: Start isEquivalent. First operand 35 states. Second operand 30 states. [2018-11-14 16:05:36,171 INFO L74 IsIncluded]: Start isIncluded. First operand 35 states. Second operand 30 states. [2018-11-14 16:05:36,171 INFO L87 Difference]: Start difference. First operand 35 states. Second operand 30 states. [2018-11-14 16:05:36,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 16:05:36,174 INFO L93 Difference]: Finished difference Result 35 states and 45 transitions. [2018-11-14 16:05:36,174 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 45 transitions. [2018-11-14 16:05:36,175 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 16:05:36,175 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 16:05:36,175 INFO L74 IsIncluded]: Start isIncluded. First operand 30 states. Second operand 35 states. [2018-11-14 16:05:36,175 INFO L87 Difference]: Start difference. First operand 30 states. Second operand 35 states. [2018-11-14 16:05:36,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 16:05:36,178 INFO L93 Difference]: Finished difference Result 35 states and 45 transitions. [2018-11-14 16:05:36,179 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 45 transitions. [2018-11-14 16:05:36,179 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 16:05:36,179 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 16:05:36,179 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 16:05:36,180 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 16:05:36,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-11-14 16:05:36,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 36 transitions. [2018-11-14 16:05:36,182 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 36 transitions. Word has length 18 [2018-11-14 16:05:36,182 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 16:05:36,182 INFO L480 AbstractCegarLoop]: Abstraction has 30 states and 36 transitions. [2018-11-14 16:05:36,183 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-14 16:05:36,183 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 36 transitions. [2018-11-14 16:05:36,184 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-11-14 16:05:36,184 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 16:05:36,184 INFO L375 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 16:05:36,184 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 16:05:36,185 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 16:05:36,185 INFO L82 PathProgramCache]: Analyzing trace with hash 721099660, now seen corresponding path program 1 times [2018-11-14 16:05:36,186 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 16:05:36,186 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 16:05:36,203 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 16:05:36,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 16:05:36,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 16:05:36,261 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 16:05:36,391 INFO L256 TraceCheckUtils]: 0: Hoare triple {471#true} call ULTIMATE.init(); {471#true} is VALID [2018-11-14 16:05:36,392 INFO L273 TraceCheckUtils]: 1: Hoare triple {471#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {471#true} is VALID [2018-11-14 16:05:36,392 INFO L273 TraceCheckUtils]: 2: Hoare triple {471#true} assume true; {471#true} is VALID [2018-11-14 16:05:36,392 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {471#true} {471#true} #91#return; {471#true} is VALID [2018-11-14 16:05:36,393 INFO L256 TraceCheckUtils]: 4: Hoare triple {471#true} call #t~ret7 := main(); {471#true} is VALID [2018-11-14 16:05:36,393 INFO L273 TraceCheckUtils]: 5: Hoare triple {471#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {471#true} is VALID [2018-11-14 16:05:36,394 INFO L273 TraceCheckUtils]: 6: Hoare triple {471#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {494#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv5 32) main_~CCCELVOL4~0))} is VALID [2018-11-14 16:05:36,396 INFO L273 TraceCheckUtils]: 7: Hoare triple {494#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv5 32) main_~CCCELVOL4~0))} assume !(~bvsrem32(~CELLCOUNT~0, 4bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 4bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {494#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv5 32) main_~CCCELVOL4~0))} is VALID [2018-11-14 16:05:36,397 INFO L273 TraceCheckUtils]: 8: Hoare triple {494#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv5 32) main_~CCCELVOL4~0))} assume true; {494#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv5 32) main_~CCCELVOL4~0))} is VALID [2018-11-14 16:05:36,398 INFO L273 TraceCheckUtils]: 9: Hoare triple {494#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv5 32) main_~CCCELVOL4~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {494#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv5 32) main_~CCCELVOL4~0))} is VALID [2018-11-14 16:05:36,401 INFO L273 TraceCheckUtils]: 10: Hoare triple {494#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv5 32) main_~CCCELVOL4~0))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {507#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv7 32) main_~CCCELVOL3~0))} is VALID [2018-11-14 16:05:36,404 INFO L273 TraceCheckUtils]: 11: Hoare triple {507#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv7 32) main_~CCCELVOL3~0))} assume !~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {472#false} is VALID [2018-11-14 16:05:36,405 INFO L273 TraceCheckUtils]: 12: Hoare triple {472#false} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {472#false} is VALID [2018-11-14 16:05:36,405 INFO L273 TraceCheckUtils]: 13: Hoare triple {472#false} assume ~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL1~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {472#false} is VALID [2018-11-14 16:05:36,405 INFO L273 TraceCheckUtils]: 14: Hoare triple {472#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {472#false} is VALID [2018-11-14 16:05:36,406 INFO L273 TraceCheckUtils]: 15: Hoare triple {472#false} assume true; {472#false} is VALID [2018-11-14 16:05:36,406 INFO L273 TraceCheckUtils]: 16: Hoare triple {472#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {472#false} is VALID [2018-11-14 16:05:36,407 INFO L273 TraceCheckUtils]: 17: Hoare triple {472#false} ~i~0 := 0bv32; {472#false} is VALID [2018-11-14 16:05:36,407 INFO L273 TraceCheckUtils]: 18: Hoare triple {472#false} assume true; {472#false} is VALID [2018-11-14 16:05:36,408 INFO L273 TraceCheckUtils]: 19: Hoare triple {472#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {472#false} is VALID [2018-11-14 16:05:36,408 INFO L273 TraceCheckUtils]: 20: Hoare triple {472#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {472#false} is VALID [2018-11-14 16:05:36,408 INFO L256 TraceCheckUtils]: 21: Hoare triple {472#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {472#false} is VALID [2018-11-14 16:05:36,408 INFO L273 TraceCheckUtils]: 22: Hoare triple {472#false} ~cond := #in~cond; {472#false} is VALID [2018-11-14 16:05:36,409 INFO L273 TraceCheckUtils]: 23: Hoare triple {472#false} assume ~cond == 0bv32; {472#false} is VALID [2018-11-14 16:05:36,409 INFO L273 TraceCheckUtils]: 24: Hoare triple {472#false} assume !false; {472#false} is VALID [2018-11-14 16:05:36,411 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 16:05:36,411 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-14 16:05:36,414 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-14 16:05:36,414 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-14 16:05:36,415 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 25 [2018-11-14 16:05:36,415 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 16:05:36,415 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states. [2018-11-14 16:05:36,516 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 25 edges. 25 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 16:05:36,517 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-14 16:05:36,517 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-14 16:05:36,517 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-14 16:05:36,518 INFO L87 Difference]: Start difference. First operand 30 states and 36 transitions. Second operand 4 states. [2018-11-14 16:05:36,983 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 16:05:36,984 INFO L93 Difference]: Finished difference Result 64 states and 83 transitions. [2018-11-14 16:05:36,984 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-14 16:05:36,984 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 25 [2018-11-14 16:05:36,984 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 16:05:36,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-14 16:05:36,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 81 transitions. [2018-11-14 16:05:36,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-14 16:05:36,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 81 transitions. [2018-11-14 16:05:36,993 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states and 81 transitions. [2018-11-14 16:05:37,232 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 81 edges. 81 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 16:05:37,236 INFO L225 Difference]: With dead ends: 64 [2018-11-14 16:05:37,236 INFO L226 Difference]: Without dead ends: 44 [2018-11-14 16:05:37,236 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 22 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-14 16:05:37,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2018-11-14 16:05:37,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 37. [2018-11-14 16:05:37,270 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 16:05:37,270 INFO L82 GeneralOperation]: Start isEquivalent. First operand 44 states. Second operand 37 states. [2018-11-14 16:05:37,271 INFO L74 IsIncluded]: Start isIncluded. First operand 44 states. Second operand 37 states. [2018-11-14 16:05:37,271 INFO L87 Difference]: Start difference. First operand 44 states. Second operand 37 states. [2018-11-14 16:05:37,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 16:05:37,275 INFO L93 Difference]: Finished difference Result 44 states and 55 transitions. [2018-11-14 16:05:37,276 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 55 transitions. [2018-11-14 16:05:37,277 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 16:05:37,277 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 16:05:37,277 INFO L74 IsIncluded]: Start isIncluded. First operand 37 states. Second operand 44 states. [2018-11-14 16:05:37,277 INFO L87 Difference]: Start difference. First operand 37 states. Second operand 44 states. [2018-11-14 16:05:37,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 16:05:37,283 INFO L93 Difference]: Finished difference Result 44 states and 55 transitions. [2018-11-14 16:05:37,284 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 55 transitions. [2018-11-14 16:05:37,284 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 16:05:37,285 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 16:05:37,285 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 16:05:37,285 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 16:05:37,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2018-11-14 16:05:37,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 46 transitions. [2018-11-14 16:05:37,289 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 46 transitions. Word has length 25 [2018-11-14 16:05:37,289 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 16:05:37,289 INFO L480 AbstractCegarLoop]: Abstraction has 37 states and 46 transitions. [2018-11-14 16:05:37,289 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-14 16:05:37,289 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 46 transitions. [2018-11-14 16:05:37,290 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-11-14 16:05:37,291 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 16:05:37,291 INFO L375 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 16:05:37,291 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 16:05:37,291 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 16:05:37,292 INFO L82 PathProgramCache]: Analyzing trace with hash 1732216910, now seen corresponding path program 1 times [2018-11-14 16:05:37,292 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 16:05:37,292 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 16:05:37,308 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 16:05:37,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 16:05:37,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 16:05:37,400 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 16:05:37,751 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-14 16:05:37,791 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-14 16:05:37,819 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 16:05:37,857 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:05:37,944 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:05:37,945 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:34, output treesize:30 [2018-11-14 16:05:38,043 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 26 [2018-11-14 16:05:38,064 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 16:05:38,068 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 41 [2018-11-14 16:05:38,074 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 16:05:38,086 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:05:38,118 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:05:38,119 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:48, output treesize:32 [2018-11-14 16:05:38,132 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 16:05:38,158 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 26 [2018-11-14 16:05:38,170 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 16:05:38,172 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 16:05:38,174 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 54 [2018-11-14 16:05:38,178 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 16:05:38,191 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:05:38,218 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:05:38,218 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:48, output treesize:41 [2018-11-14 16:05:38,308 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 27 [2018-11-14 16:05:38,337 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 16:05:38,339 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 16:05:38,341 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 16:05:38,342 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 16:05:38,343 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 16:05:38,344 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 16:05:38,347 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 82 [2018-11-14 16:05:38,356 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 16:05:38,389 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:05:38,413 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:05:38,414 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:43, output treesize:36 [2018-11-14 16:05:38,748 INFO L256 TraceCheckUtils]: 0: Hoare triple {766#true} call ULTIMATE.init(); {766#true} is VALID [2018-11-14 16:05:38,748 INFO L273 TraceCheckUtils]: 1: Hoare triple {766#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {766#true} is VALID [2018-11-14 16:05:38,749 INFO L273 TraceCheckUtils]: 2: Hoare triple {766#true} assume true; {766#true} is VALID [2018-11-14 16:05:38,749 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {766#true} {766#true} #91#return; {766#true} is VALID [2018-11-14 16:05:38,750 INFO L256 TraceCheckUtils]: 4: Hoare triple {766#true} call #t~ret7 := main(); {766#true} is VALID [2018-11-14 16:05:38,750 INFO L273 TraceCheckUtils]: 5: Hoare triple {766#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {766#true} is VALID [2018-11-14 16:05:38,752 INFO L273 TraceCheckUtils]: 6: Hoare triple {766#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {789#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 16:05:38,752 INFO L273 TraceCheckUtils]: 7: Hoare triple {789#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !(~bvsrem32(~CELLCOUNT~0, 4bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 4bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {793#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:38,753 INFO L273 TraceCheckUtils]: 8: Hoare triple {793#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {793#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:38,754 INFO L273 TraceCheckUtils]: 9: Hoare triple {793#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {793#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:38,755 INFO L273 TraceCheckUtils]: 10: Hoare triple {793#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {803#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:38,759 INFO L273 TraceCheckUtils]: 11: Hoare triple {803#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {803#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:38,761 INFO L273 TraceCheckUtils]: 12: Hoare triple {803#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {810#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:38,766 INFO L273 TraceCheckUtils]: 13: Hoare triple {810#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL1~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {814#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 16:05:38,768 INFO L273 TraceCheckUtils]: 14: Hoare triple {814#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {814#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 16:05:38,773 INFO L273 TraceCheckUtils]: 15: Hoare triple {814#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume true; {814#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 16:05:38,786 INFO L273 TraceCheckUtils]: 16: Hoare triple {814#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {814#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 16:05:38,788 INFO L273 TraceCheckUtils]: 17: Hoare triple {814#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} ~i~0 := 0bv32; {827#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 16:05:38,789 INFO L273 TraceCheckUtils]: 18: Hoare triple {827#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume true; {827#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 16:05:38,791 INFO L273 TraceCheckUtils]: 19: Hoare triple {827#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {834#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) |main_#t~short6| (= main_~i~0 (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 16:05:38,791 INFO L273 TraceCheckUtils]: 20: Hoare triple {834#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) |main_#t~short6| (= main_~i~0 (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {767#false} is VALID [2018-11-14 16:05:38,792 INFO L256 TraceCheckUtils]: 21: Hoare triple {767#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {767#false} is VALID [2018-11-14 16:05:38,792 INFO L273 TraceCheckUtils]: 22: Hoare triple {767#false} ~cond := #in~cond; {767#false} is VALID [2018-11-14 16:05:38,792 INFO L273 TraceCheckUtils]: 23: Hoare triple {767#false} assume ~cond == 0bv32; {767#false} is VALID [2018-11-14 16:05:38,793 INFO L273 TraceCheckUtils]: 24: Hoare triple {767#false} assume !false; {767#false} is VALID [2018-11-14 16:05:38,799 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 16:05:38,800 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-14 16:05:39,606 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 63 treesize of output 59 [2018-11-14 16:05:39,615 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 59 treesize of output 54 [2018-11-14 16:05:39,663 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 16:05:39,669 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 54 treesize of output 62 [2018-11-14 16:05:39,794 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 16:05:41,862 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (= (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) |main_~#volArray~0.offset|) [2018-11-14 16:05:41,864 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 16:05:41,874 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 16:05:41,885 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 16:05:41,886 INFO L303 Elim1Store]: Index analysis took 2096 ms [2018-11-14 16:05:41,887 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 5 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 42 [2018-11-14 16:05:41,892 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 16:05:41,926 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 16:05:41,943 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 16:05:41,980 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 16:05:42,020 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-14 16:05:42,020 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:75, output treesize:27 [2018-11-14 16:05:42,033 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 16:05:42,195 INFO L273 TraceCheckUtils]: 24: Hoare triple {767#false} assume !false; {767#false} is VALID [2018-11-14 16:05:42,196 INFO L273 TraceCheckUtils]: 23: Hoare triple {853#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} assume ~cond == 0bv32; {767#false} is VALID [2018-11-14 16:05:42,197 INFO L273 TraceCheckUtils]: 22: Hoare triple {857#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} ~cond := #in~cond; {853#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} is VALID [2018-11-14 16:05:42,198 INFO L256 TraceCheckUtils]: 21: Hoare triple {861#|main_#t~short6|} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {857#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-14 16:05:42,199 INFO L273 TraceCheckUtils]: 20: Hoare triple {865#(or |main_#t~short6| (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {861#|main_#t~short6|} is VALID [2018-11-14 16:05:42,201 INFO L273 TraceCheckUtils]: 19: Hoare triple {869#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {865#(or |main_#t~short6| (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} is VALID [2018-11-14 16:05:42,202 INFO L273 TraceCheckUtils]: 18: Hoare triple {869#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} assume true; {869#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} is VALID [2018-11-14 16:05:42,203 INFO L273 TraceCheckUtils]: 17: Hoare triple {876#(or (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0))} ~i~0 := 0bv32; {869#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} is VALID [2018-11-14 16:05:42,204 INFO L273 TraceCheckUtils]: 16: Hoare triple {876#(or (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {876#(or (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0))} is VALID [2018-11-14 16:05:42,205 INFO L273 TraceCheckUtils]: 15: Hoare triple {876#(or (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0))} assume true; {876#(or (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0))} is VALID [2018-11-14 16:05:42,206 INFO L273 TraceCheckUtils]: 14: Hoare triple {876#(or (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {876#(or (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0))} is VALID [2018-11-14 16:05:42,216 INFO L273 TraceCheckUtils]: 13: Hoare triple {889#(or (= (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) (_ bv0 32)) (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)))} assume ~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL1~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {876#(or (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0))} is VALID [2018-11-14 16:05:42,228 INFO L273 TraceCheckUtils]: 12: Hoare triple {893#(or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) (_ bv0 32)) (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) main_~MINVAL~0))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {889#(or (= (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) (_ bv0 32)) (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)))} is VALID [2018-11-14 16:05:42,241 INFO L273 TraceCheckUtils]: 11: Hoare triple {893#(or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) (_ bv0 32)) (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) main_~MINVAL~0))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {893#(or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) (_ bv0 32)) (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) main_~MINVAL~0))} is VALID [2018-11-14 16:05:42,330 INFO L273 TraceCheckUtils]: 10: Hoare triple {900#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_6 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_6 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_6))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {893#(or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) (_ bv0 32)) (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) |main_~#volArray~0.offset|) main_~MINVAL~0))} is VALID [2018-11-14 16:05:42,333 INFO L273 TraceCheckUtils]: 9: Hoare triple {900#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_6 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_6 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_6))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {900#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_6 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_6 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_6))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:42,334 INFO L273 TraceCheckUtils]: 8: Hoare triple {900#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_6 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_6 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_6))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} assume true; {900#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_6 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_6 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_6))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:42,335 INFO L273 TraceCheckUtils]: 7: Hoare triple {766#true} assume !(~bvsrem32(~CELLCOUNT~0, 4bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 4bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {900#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_6 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_6 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_6))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:42,335 INFO L273 TraceCheckUtils]: 6: Hoare triple {766#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {766#true} is VALID [2018-11-14 16:05:42,336 INFO L273 TraceCheckUtils]: 5: Hoare triple {766#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {766#true} is VALID [2018-11-14 16:05:42,336 INFO L256 TraceCheckUtils]: 4: Hoare triple {766#true} call #t~ret7 := main(); {766#true} is VALID [2018-11-14 16:05:42,336 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {766#true} {766#true} #91#return; {766#true} is VALID [2018-11-14 16:05:42,336 INFO L273 TraceCheckUtils]: 2: Hoare triple {766#true} assume true; {766#true} is VALID [2018-11-14 16:05:42,337 INFO L273 TraceCheckUtils]: 1: Hoare triple {766#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {766#true} is VALID [2018-11-14 16:05:42,337 INFO L256 TraceCheckUtils]: 0: Hoare triple {766#true} call ULTIMATE.init(); {766#true} is VALID [2018-11-14 16:05:42,341 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 16:05:42,343 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-14 16:05:42,344 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 11] total 18 [2018-11-14 16:05:42,344 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 25 [2018-11-14 16:05:42,345 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 16:05:42,345 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 18 states. [2018-11-14 16:05:42,693 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 43 edges. 43 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 16:05:42,693 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-14 16:05:42,693 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-14 16:05:42,694 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=249, Unknown=0, NotChecked=0, Total=306 [2018-11-14 16:05:42,694 INFO L87 Difference]: Start difference. First operand 37 states and 46 transitions. Second operand 18 states. [2018-11-14 16:05:44,410 WARN L179 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 43 [2018-11-14 16:05:45,201 WARN L179 SmtUtils]: Spent 149.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 47 [2018-11-14 16:05:52,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 16:05:52,495 INFO L93 Difference]: Finished difference Result 136 states and 180 transitions. [2018-11-14 16:05:52,496 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-11-14 16:05:52,496 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 25 [2018-11-14 16:05:52,496 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 16:05:52,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2018-11-14 16:05:52,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 170 transitions. [2018-11-14 16:05:52,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2018-11-14 16:05:52,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 170 transitions. [2018-11-14 16:05:52,511 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 28 states and 170 transitions. [2018-11-14 16:05:53,613 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 170 edges. 170 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 16:05:53,619 INFO L225 Difference]: With dead ends: 136 [2018-11-14 16:05:53,620 INFO L226 Difference]: Without dead ends: 116 [2018-11-14 16:05:53,621 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 71 GetRequests, 32 SyntacticMatches, 1 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 268 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=343, Invalid=1217, Unknown=0, NotChecked=0, Total=1560 [2018-11-14 16:05:53,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states. [2018-11-14 16:05:53,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 70. [2018-11-14 16:05:53,798 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 16:05:53,798 INFO L82 GeneralOperation]: Start isEquivalent. First operand 116 states. Second operand 70 states. [2018-11-14 16:05:53,798 INFO L74 IsIncluded]: Start isIncluded. First operand 116 states. Second operand 70 states. [2018-11-14 16:05:53,799 INFO L87 Difference]: Start difference. First operand 116 states. Second operand 70 states. [2018-11-14 16:05:53,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 16:05:53,812 INFO L93 Difference]: Finished difference Result 116 states and 150 transitions. [2018-11-14 16:05:53,812 INFO L276 IsEmpty]: Start isEmpty. Operand 116 states and 150 transitions. [2018-11-14 16:05:53,814 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 16:05:53,814 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 16:05:53,814 INFO L74 IsIncluded]: Start isIncluded. First operand 70 states. Second operand 116 states. [2018-11-14 16:05:53,814 INFO L87 Difference]: Start difference. First operand 70 states. Second operand 116 states. [2018-11-14 16:05:53,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 16:05:53,831 INFO L93 Difference]: Finished difference Result 116 states and 150 transitions. [2018-11-14 16:05:53,832 INFO L276 IsEmpty]: Start isEmpty. Operand 116 states and 150 transitions. [2018-11-14 16:05:53,833 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 16:05:53,833 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 16:05:53,833 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 16:05:53,833 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 16:05:53,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-11-14 16:05:53,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 88 transitions. [2018-11-14 16:05:53,847 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 88 transitions. Word has length 25 [2018-11-14 16:05:53,848 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 16:05:53,848 INFO L480 AbstractCegarLoop]: Abstraction has 70 states and 88 transitions. [2018-11-14 16:05:53,848 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-14 16:05:53,848 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 88 transitions. [2018-11-14 16:05:53,849 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-11-14 16:05:53,849 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 16:05:53,849 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 16:05:53,850 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 16:05:53,850 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 16:05:53,850 INFO L82 PathProgramCache]: Analyzing trace with hash -500679399, now seen corresponding path program 1 times [2018-11-14 16:05:53,850 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 16:05:53,851 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 16:05:53,872 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 16:05:53,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 16:05:53,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 16:05:53,978 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 16:05:54,247 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-14 16:05:54,253 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-14 16:05:54,255 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 16:05:54,259 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:05:54,282 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:05:54,282 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:34, output treesize:30 [2018-11-14 16:05:54,347 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 24 [2018-11-14 16:05:54,363 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 16:05:54,365 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 16:05:54,366 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 52 [2018-11-14 16:05:54,369 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 16:05:54,379 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:05:54,407 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:05:54,407 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:46, output treesize:39 [2018-11-14 16:05:54,486 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 27 [2018-11-14 16:05:54,508 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 16:05:54,509 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 16:05:54,510 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 16:05:54,512 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 16:05:54,513 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 16:05:54,515 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 16:05:54,517 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 90 [2018-11-14 16:05:54,519 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 16:05:54,541 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:05:54,563 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:05:54,564 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:43, output treesize:36 [2018-11-14 16:05:55,151 INFO L256 TraceCheckUtils]: 0: Hoare triple {1465#true} call ULTIMATE.init(); {1465#true} is VALID [2018-11-14 16:05:55,152 INFO L273 TraceCheckUtils]: 1: Hoare triple {1465#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1465#true} is VALID [2018-11-14 16:05:55,152 INFO L273 TraceCheckUtils]: 2: Hoare triple {1465#true} assume true; {1465#true} is VALID [2018-11-14 16:05:55,152 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1465#true} {1465#true} #91#return; {1465#true} is VALID [2018-11-14 16:05:55,153 INFO L256 TraceCheckUtils]: 4: Hoare triple {1465#true} call #t~ret7 := main(); {1465#true} is VALID [2018-11-14 16:05:55,153 INFO L273 TraceCheckUtils]: 5: Hoare triple {1465#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1465#true} is VALID [2018-11-14 16:05:55,154 INFO L273 TraceCheckUtils]: 6: Hoare triple {1465#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {1488#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 16:05:55,155 INFO L273 TraceCheckUtils]: 7: Hoare triple {1488#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !(~bvsrem32(~CELLCOUNT~0, 4bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 4bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {1492#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:55,156 INFO L273 TraceCheckUtils]: 8: Hoare triple {1492#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {1492#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:55,156 INFO L273 TraceCheckUtils]: 9: Hoare triple {1492#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1492#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:55,157 INFO L273 TraceCheckUtils]: 10: Hoare triple {1492#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {1502#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:55,171 INFO L273 TraceCheckUtils]: 11: Hoare triple {1502#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {1506#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:55,175 INFO L273 TraceCheckUtils]: 12: Hoare triple {1506#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {1510#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:55,179 INFO L273 TraceCheckUtils]: 13: Hoare triple {1510#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL1~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {1514#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:55,180 INFO L273 TraceCheckUtils]: 14: Hoare triple {1514#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1514#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:55,182 INFO L273 TraceCheckUtils]: 15: Hoare triple {1514#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} assume true; {1514#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:55,196 INFO L273 TraceCheckUtils]: 16: Hoare triple {1514#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1514#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:55,198 INFO L273 TraceCheckUtils]: 17: Hoare triple {1514#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} ~i~0 := 0bv32; {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:55,202 INFO L273 TraceCheckUtils]: 18: Hoare triple {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} assume true; {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:55,204 INFO L273 TraceCheckUtils]: 19: Hoare triple {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:55,205 INFO L273 TraceCheckUtils]: 20: Hoare triple {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} assume #t~short6; {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:55,208 INFO L256 TraceCheckUtils]: 21: Hoare triple {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {1540#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} is VALID [2018-11-14 16:05:55,209 INFO L273 TraceCheckUtils]: 22: Hoare triple {1540#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} ~cond := #in~cond; {1540#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} is VALID [2018-11-14 16:05:55,209 INFO L273 TraceCheckUtils]: 23: Hoare triple {1540#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} assume !(~cond == 0bv32); {1540#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} is VALID [2018-11-14 16:05:55,210 INFO L273 TraceCheckUtils]: 24: Hoare triple {1540#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} assume true; {1540#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} is VALID [2018-11-14 16:05:55,210 INFO L268 TraceCheckUtils]: 25: Hoare quadruple {1540#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32))) (= (_ bv1 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} #95#return; {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:55,212 INFO L273 TraceCheckUtils]: 26: Hoare triple {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:55,213 INFO L273 TraceCheckUtils]: 27: Hoare triple {1527#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {1559#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:55,215 INFO L273 TraceCheckUtils]: 28: Hoare triple {1559#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {1559#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:55,217 INFO L273 TraceCheckUtils]: 29: Hoare triple {1559#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv1 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {1566#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) |main_#t~short6| (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:05:55,218 INFO L273 TraceCheckUtils]: 30: Hoare triple {1566#(and (= (_ bv1 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) |main_#t~short6| (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {1466#false} is VALID [2018-11-14 16:05:55,218 INFO L256 TraceCheckUtils]: 31: Hoare triple {1466#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {1466#false} is VALID [2018-11-14 16:05:55,219 INFO L273 TraceCheckUtils]: 32: Hoare triple {1466#false} ~cond := #in~cond; {1466#false} is VALID [2018-11-14 16:05:55,219 INFO L273 TraceCheckUtils]: 33: Hoare triple {1466#false} assume ~cond == 0bv32; {1466#false} is VALID [2018-11-14 16:05:55,219 INFO L273 TraceCheckUtils]: 34: Hoare triple {1466#false} assume !false; {1466#false} is VALID [2018-11-14 16:05:55,229 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 16:05:55,229 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-14 16:05:56,088 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 67 treesize of output 63 [2018-11-14 16:05:56,105 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 63 treesize of output 58 [2018-11-14 16:05:56,116 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 16:05:56,122 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 66 [2018-11-14 16:05:56,261 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 16:05:56,261 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 16:05:56,271 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 16:05:56,285 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 37 treesize of output 48 [2018-11-14 16:05:56,294 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-14 16:05:56,352 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-14 16:05:56,379 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-14 16:05:56,406 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-14 16:05:56,452 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-14 16:05:56,452 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 2 variables, input treesize:75, output treesize:41 [2018-11-14 16:05:56,469 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 16:05:56,909 INFO L273 TraceCheckUtils]: 34: Hoare triple {1466#false} assume !false; {1466#false} is VALID [2018-11-14 16:05:56,910 INFO L273 TraceCheckUtils]: 33: Hoare triple {1585#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} assume ~cond == 0bv32; {1466#false} is VALID [2018-11-14 16:05:56,911 INFO L273 TraceCheckUtils]: 32: Hoare triple {1589#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} ~cond := #in~cond; {1585#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} is VALID [2018-11-14 16:05:56,912 INFO L256 TraceCheckUtils]: 31: Hoare triple {1593#|main_#t~short6|} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {1589#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-14 16:05:56,913 INFO L273 TraceCheckUtils]: 30: Hoare triple {1597#(or |main_#t~short6| (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {1593#|main_#t~short6|} is VALID [2018-11-14 16:05:56,916 INFO L273 TraceCheckUtils]: 29: Hoare triple {1601#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {1597#(or |main_#t~short6| (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} is VALID [2018-11-14 16:05:56,938 INFO L273 TraceCheckUtils]: 28: Hoare triple {1601#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} assume true; {1601#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} is VALID [2018-11-14 16:05:58,978 INFO L273 TraceCheckUtils]: 27: Hoare triple {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {1601#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} is UNKNOWN [2018-11-14 16:05:58,980 INFO L273 TraceCheckUtils]: 26: Hoare triple {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} is VALID [2018-11-14 16:05:58,982 INFO L268 TraceCheckUtils]: 25: Hoare quadruple {1465#true} {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} #95#return; {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} is VALID [2018-11-14 16:05:58,982 INFO L273 TraceCheckUtils]: 24: Hoare triple {1465#true} assume true; {1465#true} is VALID [2018-11-14 16:05:58,982 INFO L273 TraceCheckUtils]: 23: Hoare triple {1465#true} assume !(~cond == 0bv32); {1465#true} is VALID [2018-11-14 16:05:58,982 INFO L273 TraceCheckUtils]: 22: Hoare triple {1465#true} ~cond := #in~cond; {1465#true} is VALID [2018-11-14 16:05:58,982 INFO L256 TraceCheckUtils]: 21: Hoare triple {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {1465#true} is VALID [2018-11-14 16:05:58,983 INFO L273 TraceCheckUtils]: 20: Hoare triple {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} assume #t~short6; {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} is VALID [2018-11-14 16:05:58,983 INFO L273 TraceCheckUtils]: 19: Hoare triple {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} is VALID [2018-11-14 16:05:58,984 INFO L273 TraceCheckUtils]: 18: Hoare triple {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} assume true; {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} is VALID [2018-11-14 16:05:58,984 INFO L273 TraceCheckUtils]: 17: Hoare triple {1639#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} ~i~0 := 0bv32; {1608#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32)))))} is VALID [2018-11-14 16:05:58,985 INFO L273 TraceCheckUtils]: 16: Hoare triple {1639#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1639#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 16:05:58,985 INFO L273 TraceCheckUtils]: 15: Hoare triple {1639#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume true; {1639#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 16:05:58,986 INFO L273 TraceCheckUtils]: 14: Hoare triple {1639#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1639#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 16:05:59,007 INFO L273 TraceCheckUtils]: 13: Hoare triple {1652#(or (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (= (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL1~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {1639#(or (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 16:05:59,018 INFO L273 TraceCheckUtils]: 12: Hoare triple {1656#(or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (= (_ bv0 32) (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {1652#(or (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (= (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-14 16:05:59,055 INFO L273 TraceCheckUtils]: 11: Hoare triple {1660#(and (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= (_ bv0 32) main_~CCCELVOL3~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (forall ((v_arrayElimCell_11 (_ BitVec 32))) (or (bvsge v_arrayElimCell_11 main_~MINVAL~0) (= (_ bv0 32) v_arrayElimCell_11))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {1656#(or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (= (_ bv0 32) (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) main_~CCCELVOL2~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)))} is VALID [2018-11-14 16:05:59,389 INFO L273 TraceCheckUtils]: 10: Hoare triple {1664#(and (or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_11 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_11 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_11))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (or (forall ((v_prenex_3 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 v_prenex_3)) (not (bvsge main_~CCCELVOL4~0 v_prenex_3)) (bvsge main_~CCCELVOL3~0 v_prenex_3) (not (bvsge main_~CCCELVOL1~0 v_prenex_3)))) (= (_ bv0 32) main_~CCCELVOL3~0)))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {1660#(and (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= (_ bv0 32) main_~CCCELVOL3~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (forall ((v_arrayElimCell_11 (_ BitVec 32))) (or (bvsge v_arrayElimCell_11 main_~MINVAL~0) (= (_ bv0 32) v_arrayElimCell_11))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))))} is VALID [2018-11-14 16:05:59,391 INFO L273 TraceCheckUtils]: 9: Hoare triple {1664#(and (or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_11 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_11 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_11))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (or (forall ((v_prenex_3 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 v_prenex_3)) (not (bvsge main_~CCCELVOL4~0 v_prenex_3)) (bvsge main_~CCCELVOL3~0 v_prenex_3) (not (bvsge main_~CCCELVOL1~0 v_prenex_3)))) (= (_ bv0 32) main_~CCCELVOL3~0)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1664#(and (or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_11 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_11 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_11))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (or (forall ((v_prenex_3 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 v_prenex_3)) (not (bvsge main_~CCCELVOL4~0 v_prenex_3)) (bvsge main_~CCCELVOL3~0 v_prenex_3) (not (bvsge main_~CCCELVOL1~0 v_prenex_3)))) (= (_ bv0 32) main_~CCCELVOL3~0)))} is VALID [2018-11-14 16:05:59,391 INFO L273 TraceCheckUtils]: 8: Hoare triple {1664#(and (or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_11 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_11 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_11))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (or (forall ((v_prenex_3 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 v_prenex_3)) (not (bvsge main_~CCCELVOL4~0 v_prenex_3)) (bvsge main_~CCCELVOL3~0 v_prenex_3) (not (bvsge main_~CCCELVOL1~0 v_prenex_3)))) (= (_ bv0 32) main_~CCCELVOL3~0)))} assume true; {1664#(and (or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_11 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_11 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_11))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (or (forall ((v_prenex_3 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 v_prenex_3)) (not (bvsge main_~CCCELVOL4~0 v_prenex_3)) (bvsge main_~CCCELVOL3~0 v_prenex_3) (not (bvsge main_~CCCELVOL1~0 v_prenex_3)))) (= (_ bv0 32) main_~CCCELVOL3~0)))} is VALID [2018-11-14 16:05:59,392 INFO L273 TraceCheckUtils]: 7: Hoare triple {1674#(or (forall ((v_prenex_3 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 v_prenex_3)) (not (bvsge main_~CCCELVOL4~0 v_prenex_3)) (bvsge main_~CCCELVOL3~0 v_prenex_3) (not (bvsge main_~CCCELVOL1~0 v_prenex_3)))) (= (_ bv0 32) main_~CCCELVOL3~0))} assume !(~bvsrem32(~CELLCOUNT~0, 4bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 4bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {1664#(and (or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_arrayElimCell_11 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge v_arrayElimCell_11 main_~MINVAL~0) (not (bvsge main_~CCCELVOL1~0 main_~MINVAL~0)) (= (_ bv0 32) v_arrayElimCell_11))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (or (forall ((v_prenex_3 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 v_prenex_3)) (not (bvsge main_~CCCELVOL4~0 v_prenex_3)) (bvsge main_~CCCELVOL3~0 v_prenex_3) (not (bvsge main_~CCCELVOL1~0 v_prenex_3)))) (= (_ bv0 32) main_~CCCELVOL3~0)))} is VALID [2018-11-14 16:05:59,394 INFO L273 TraceCheckUtils]: 6: Hoare triple {1465#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {1674#(or (forall ((v_prenex_3 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 v_prenex_3)) (not (bvsge main_~CCCELVOL4~0 v_prenex_3)) (bvsge main_~CCCELVOL3~0 v_prenex_3) (not (bvsge main_~CCCELVOL1~0 v_prenex_3)))) (= (_ bv0 32) main_~CCCELVOL3~0))} is VALID [2018-11-14 16:05:59,395 INFO L273 TraceCheckUtils]: 5: Hoare triple {1465#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1465#true} is VALID [2018-11-14 16:05:59,395 INFO L256 TraceCheckUtils]: 4: Hoare triple {1465#true} call #t~ret7 := main(); {1465#true} is VALID [2018-11-14 16:05:59,396 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1465#true} {1465#true} #91#return; {1465#true} is VALID [2018-11-14 16:05:59,396 INFO L273 TraceCheckUtils]: 2: Hoare triple {1465#true} assume true; {1465#true} is VALID [2018-11-14 16:05:59,396 INFO L273 TraceCheckUtils]: 1: Hoare triple {1465#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1465#true} is VALID [2018-11-14 16:05:59,397 INFO L256 TraceCheckUtils]: 0: Hoare triple {1465#true} call ULTIMATE.init(); {1465#true} is VALID [2018-11-14 16:05:59,403 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-14 16:05:59,405 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-14 16:05:59,405 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 14] total 24 [2018-11-14 16:05:59,406 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 35 [2018-11-14 16:05:59,406 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 16:05:59,406 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 24 states. [2018-11-14 16:06:02,380 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 63 edges. 62 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2018-11-14 16:06:02,380 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-14 16:06:02,381 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-14 16:06:02,381 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=87, Invalid=465, Unknown=0, NotChecked=0, Total=552 [2018-11-14 16:06:02,381 INFO L87 Difference]: Start difference. First operand 70 states and 88 transitions. Second operand 24 states. [2018-11-14 16:06:03,917 WARN L179 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 38 DAG size of output: 33 [2018-11-14 16:06:04,980 WARN L179 SmtUtils]: Spent 148.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 39 [2018-11-14 16:06:05,295 WARN L179 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 38 [2018-11-14 16:06:05,557 WARN L179 SmtUtils]: Spent 120.00 ms on a formula simplification. DAG size of input: 42 DAG size of output: 37 [2018-11-14 16:06:05,769 WARN L179 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 36 [2018-11-14 16:06:10,562 WARN L179 SmtUtils]: Spent 187.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 46 [2018-11-14 16:06:19,054 WARN L179 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 45 DAG size of output: 40 [2018-11-14 16:06:21,030 WARN L179 SmtUtils]: Spent 304.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 44 [2018-11-14 16:06:24,643 WARN L179 SmtUtils]: Spent 420.00 ms on a formula simplification that was a NOOP. DAG size: 44 [2018-11-14 16:06:25,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 16:06:25,666 INFO L93 Difference]: Finished difference Result 190 states and 239 transitions. [2018-11-14 16:06:25,666 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-11-14 16:06:25,666 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 35 [2018-11-14 16:06:25,667 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 16:06:25,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-11-14 16:06:25,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 199 transitions. [2018-11-14 16:06:25,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-11-14 16:06:25,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 199 transitions. [2018-11-14 16:06:25,681 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 43 states and 199 transitions. [2018-11-14 16:06:31,787 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 199 edges. 197 inductive. 0 not inductive. 2 times theorem prover too weak to decide inductivity. [2018-11-14 16:06:31,793 INFO L225 Difference]: With dead ends: 190 [2018-11-14 16:06:31,794 INFO L226 Difference]: Without dead ends: 167 [2018-11-14 16:06:31,795 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 106 GetRequests, 47 SyntacticMatches, 1 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 796 ImplicationChecksByTransitivity, 7.3s TimeCoverageRelationStatistics Valid=671, Invalid=2869, Unknown=0, NotChecked=0, Total=3540 [2018-11-14 16:06:31,796 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 167 states. [2018-11-14 16:06:32,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 167 to 114. [2018-11-14 16:06:32,051 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 16:06:32,051 INFO L82 GeneralOperation]: Start isEquivalent. First operand 167 states. Second operand 114 states. [2018-11-14 16:06:32,051 INFO L74 IsIncluded]: Start isIncluded. First operand 167 states. Second operand 114 states. [2018-11-14 16:06:32,051 INFO L87 Difference]: Start difference. First operand 167 states. Second operand 114 states. [2018-11-14 16:06:32,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 16:06:32,060 INFO L93 Difference]: Finished difference Result 167 states and 210 transitions. [2018-11-14 16:06:32,060 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 210 transitions. [2018-11-14 16:06:32,061 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 16:06:32,061 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 16:06:32,061 INFO L74 IsIncluded]: Start isIncluded. First operand 114 states. Second operand 167 states. [2018-11-14 16:06:32,061 INFO L87 Difference]: Start difference. First operand 114 states. Second operand 167 states. [2018-11-14 16:06:32,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 16:06:32,069 INFO L93 Difference]: Finished difference Result 167 states and 210 transitions. [2018-11-14 16:06:32,069 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 210 transitions. [2018-11-14 16:06:32,070 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 16:06:32,070 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 16:06:32,070 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 16:06:32,070 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 16:06:32,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-11-14 16:06:32,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 137 transitions. [2018-11-14 16:06:32,075 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 137 transitions. Word has length 35 [2018-11-14 16:06:32,076 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 16:06:32,076 INFO L480 AbstractCegarLoop]: Abstraction has 114 states and 137 transitions. [2018-11-14 16:06:32,076 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-14 16:06:32,076 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 137 transitions. [2018-11-14 16:06:32,077 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-11-14 16:06:32,077 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 16:06:32,077 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 16:06:32,078 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 16:06:32,078 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 16:06:32,078 INFO L82 PathProgramCache]: Analyzing trace with hash -2037277082, now seen corresponding path program 1 times [2018-11-14 16:06:32,078 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 16:06:32,078 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 16:06:32,108 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 16:06:32,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 16:06:32,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 16:06:32,223 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 16:06:32,314 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-14 16:06:32,351 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-14 16:06:32,363 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 16:06:32,369 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:06:32,380 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:06:32,381 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:25, output treesize:21 [2018-11-14 16:06:32,430 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 26 [2018-11-14 16:06:32,439 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 16:06:32,442 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 41 [2018-11-14 16:06:32,445 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 16:06:32,455 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:06:32,473 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:06:32,473 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:39, output treesize:23 [2018-11-14 16:06:32,484 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 16:06:32,509 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 26 [2018-11-14 16:06:32,517 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 16:06:32,521 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 41 [2018-11-14 16:06:32,524 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 16:06:32,534 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:06:32,553 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:06:32,554 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:39, output treesize:23 [2018-11-14 16:06:32,566 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 16:06:32,579 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 18 [2018-11-14 16:06:32,587 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 16:06:32,590 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 16:06:32,591 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 33 [2018-11-14 16:06:32,598 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 16:06:32,608 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:06:32,619 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:06:32,620 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:26, output treesize:22 [2018-11-14 16:06:32,753 INFO L256 TraceCheckUtils]: 0: Hoare triple {2489#true} call ULTIMATE.init(); {2489#true} is VALID [2018-11-14 16:06:32,754 INFO L273 TraceCheckUtils]: 1: Hoare triple {2489#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {2489#true} is VALID [2018-11-14 16:06:32,754 INFO L273 TraceCheckUtils]: 2: Hoare triple {2489#true} assume true; {2489#true} is VALID [2018-11-14 16:06:32,754 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2489#true} {2489#true} #91#return; {2489#true} is VALID [2018-11-14 16:06:32,755 INFO L256 TraceCheckUtils]: 4: Hoare triple {2489#true} call #t~ret7 := main(); {2489#true} is VALID [2018-11-14 16:06:32,755 INFO L273 TraceCheckUtils]: 5: Hoare triple {2489#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {2489#true} is VALID [2018-11-14 16:06:32,756 INFO L273 TraceCheckUtils]: 6: Hoare triple {2489#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {2512#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 16:06:32,757 INFO L273 TraceCheckUtils]: 7: Hoare triple {2512#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !(~bvsrem32(~CELLCOUNT~0, 4bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 4bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {2516#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:32,757 INFO L273 TraceCheckUtils]: 8: Hoare triple {2516#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {2516#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:32,758 INFO L273 TraceCheckUtils]: 9: Hoare triple {2516#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {2516#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:32,760 INFO L273 TraceCheckUtils]: 10: Hoare triple {2516#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {2526#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:32,764 INFO L273 TraceCheckUtils]: 11: Hoare triple {2526#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {2526#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:32,765 INFO L273 TraceCheckUtils]: 12: Hoare triple {2526#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {2526#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:32,769 INFO L273 TraceCheckUtils]: 13: Hoare triple {2526#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {2536#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 16:06:32,769 INFO L273 TraceCheckUtils]: 14: Hoare triple {2536#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {2536#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 16:06:32,770 INFO L273 TraceCheckUtils]: 15: Hoare triple {2536#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume true; {2536#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 16:06:32,770 INFO L273 TraceCheckUtils]: 16: Hoare triple {2536#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {2536#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 16:06:32,771 INFO L273 TraceCheckUtils]: 17: Hoare triple {2536#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} ~i~0 := 0bv32; {2549#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 16:06:32,778 INFO L273 TraceCheckUtils]: 18: Hoare triple {2549#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume true; {2549#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 16:06:32,780 INFO L273 TraceCheckUtils]: 19: Hoare triple {2549#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {2549#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 16:06:32,781 INFO L273 TraceCheckUtils]: 20: Hoare triple {2549#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {2559#(not |main_#t~short6|)} is VALID [2018-11-14 16:06:32,781 INFO L256 TraceCheckUtils]: 21: Hoare triple {2559#(not |main_#t~short6|)} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {2489#true} is VALID [2018-11-14 16:06:32,782 INFO L273 TraceCheckUtils]: 22: Hoare triple {2489#true} ~cond := #in~cond; {2566#(= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)} is VALID [2018-11-14 16:06:32,789 INFO L273 TraceCheckUtils]: 23: Hoare triple {2566#(= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)} assume !(~cond == 0bv32); {2570#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-14 16:06:32,790 INFO L273 TraceCheckUtils]: 24: Hoare triple {2570#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} assume true; {2570#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-14 16:06:32,790 INFO L268 TraceCheckUtils]: 25: Hoare quadruple {2570#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} {2559#(not |main_#t~short6|)} #95#return; {2490#false} is VALID [2018-11-14 16:06:32,790 INFO L273 TraceCheckUtils]: 26: Hoare triple {2490#false} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {2490#false} is VALID [2018-11-14 16:06:32,791 INFO L273 TraceCheckUtils]: 27: Hoare triple {2490#false} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {2490#false} is VALID [2018-11-14 16:06:32,791 INFO L273 TraceCheckUtils]: 28: Hoare triple {2490#false} assume true; {2490#false} is VALID [2018-11-14 16:06:32,791 INFO L273 TraceCheckUtils]: 29: Hoare triple {2490#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {2490#false} is VALID [2018-11-14 16:06:32,791 INFO L273 TraceCheckUtils]: 30: Hoare triple {2490#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {2490#false} is VALID [2018-11-14 16:06:32,791 INFO L256 TraceCheckUtils]: 31: Hoare triple {2490#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {2490#false} is VALID [2018-11-14 16:06:32,791 INFO L273 TraceCheckUtils]: 32: Hoare triple {2490#false} ~cond := #in~cond; {2490#false} is VALID [2018-11-14 16:06:32,791 INFO L273 TraceCheckUtils]: 33: Hoare triple {2490#false} assume !(~cond == 0bv32); {2490#false} is VALID [2018-11-14 16:06:32,792 INFO L273 TraceCheckUtils]: 34: Hoare triple {2490#false} assume true; {2490#false} is VALID [2018-11-14 16:06:32,792 INFO L268 TraceCheckUtils]: 35: Hoare quadruple {2490#false} {2490#false} #95#return; {2490#false} is VALID [2018-11-14 16:06:32,792 INFO L273 TraceCheckUtils]: 36: Hoare triple {2490#false} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {2490#false} is VALID [2018-11-14 16:06:32,792 INFO L273 TraceCheckUtils]: 37: Hoare triple {2490#false} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {2490#false} is VALID [2018-11-14 16:06:32,792 INFO L273 TraceCheckUtils]: 38: Hoare triple {2490#false} assume true; {2490#false} is VALID [2018-11-14 16:06:32,792 INFO L273 TraceCheckUtils]: 39: Hoare triple {2490#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {2490#false} is VALID [2018-11-14 16:06:32,793 INFO L273 TraceCheckUtils]: 40: Hoare triple {2490#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {2490#false} is VALID [2018-11-14 16:06:32,793 INFO L256 TraceCheckUtils]: 41: Hoare triple {2490#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {2490#false} is VALID [2018-11-14 16:06:32,793 INFO L273 TraceCheckUtils]: 42: Hoare triple {2490#false} ~cond := #in~cond; {2490#false} is VALID [2018-11-14 16:06:32,793 INFO L273 TraceCheckUtils]: 43: Hoare triple {2490#false} assume ~cond == 0bv32; {2490#false} is VALID [2018-11-14 16:06:32,793 INFO L273 TraceCheckUtils]: 44: Hoare triple {2490#false} assume !false; {2490#false} is VALID [2018-11-14 16:06:32,797 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 2 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-11-14 16:06:32,797 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-14 16:06:33,122 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2018-11-14 16:06:33,154 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 7 [2018-11-14 16:06:33,156 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 16:06:33,167 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-14 16:06:33,174 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 2 xjuncts. [2018-11-14 16:06:33,175 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:12 [2018-11-14 16:06:33,179 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 16:06:33,247 INFO L273 TraceCheckUtils]: 44: Hoare triple {2490#false} assume !false; {2490#false} is VALID [2018-11-14 16:06:33,248 INFO L273 TraceCheckUtils]: 43: Hoare triple {2490#false} assume ~cond == 0bv32; {2490#false} is VALID [2018-11-14 16:06:33,248 INFO L273 TraceCheckUtils]: 42: Hoare triple {2490#false} ~cond := #in~cond; {2490#false} is VALID [2018-11-14 16:06:33,248 INFO L256 TraceCheckUtils]: 41: Hoare triple {2490#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {2490#false} is VALID [2018-11-14 16:06:33,248 INFO L273 TraceCheckUtils]: 40: Hoare triple {2490#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {2490#false} is VALID [2018-11-14 16:06:33,249 INFO L273 TraceCheckUtils]: 39: Hoare triple {2490#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {2490#false} is VALID [2018-11-14 16:06:33,249 INFO L273 TraceCheckUtils]: 38: Hoare triple {2490#false} assume true; {2490#false} is VALID [2018-11-14 16:06:33,249 INFO L273 TraceCheckUtils]: 37: Hoare triple {2490#false} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {2490#false} is VALID [2018-11-14 16:06:33,249 INFO L273 TraceCheckUtils]: 36: Hoare triple {2490#false} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {2490#false} is VALID [2018-11-14 16:06:33,249 INFO L268 TraceCheckUtils]: 35: Hoare quadruple {2489#true} {2490#false} #95#return; {2490#false} is VALID [2018-11-14 16:06:33,249 INFO L273 TraceCheckUtils]: 34: Hoare triple {2489#true} assume true; {2489#true} is VALID [2018-11-14 16:06:33,250 INFO L273 TraceCheckUtils]: 33: Hoare triple {2489#true} assume !(~cond == 0bv32); {2489#true} is VALID [2018-11-14 16:06:33,250 INFO L273 TraceCheckUtils]: 32: Hoare triple {2489#true} ~cond := #in~cond; {2489#true} is VALID [2018-11-14 16:06:33,250 INFO L256 TraceCheckUtils]: 31: Hoare triple {2490#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {2489#true} is VALID [2018-11-14 16:06:33,250 INFO L273 TraceCheckUtils]: 30: Hoare triple {2490#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {2490#false} is VALID [2018-11-14 16:06:33,250 INFO L273 TraceCheckUtils]: 29: Hoare triple {2490#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {2490#false} is VALID [2018-11-14 16:06:33,250 INFO L273 TraceCheckUtils]: 28: Hoare triple {2490#false} assume true; {2490#false} is VALID [2018-11-14 16:06:33,250 INFO L273 TraceCheckUtils]: 27: Hoare triple {2490#false} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {2490#false} is VALID [2018-11-14 16:06:33,251 INFO L273 TraceCheckUtils]: 26: Hoare triple {2490#false} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {2490#false} is VALID [2018-11-14 16:06:33,251 INFO L268 TraceCheckUtils]: 25: Hoare quadruple {2570#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} {2559#(not |main_#t~short6|)} #95#return; {2490#false} is VALID [2018-11-14 16:06:33,252 INFO L273 TraceCheckUtils]: 24: Hoare triple {2570#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} assume true; {2570#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-14 16:06:33,252 INFO L273 TraceCheckUtils]: 23: Hoare triple {2700#(or (= (_ bv0 32) __VERIFIER_assert_~cond) (not (= |__VERIFIER_assert_#in~cond| (_ bv0 32))))} assume !(~cond == 0bv32); {2570#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-14 16:06:33,252 INFO L273 TraceCheckUtils]: 22: Hoare triple {2489#true} ~cond := #in~cond; {2700#(or (= (_ bv0 32) __VERIFIER_assert_~cond) (not (= |__VERIFIER_assert_#in~cond| (_ bv0 32))))} is VALID [2018-11-14 16:06:33,253 INFO L256 TraceCheckUtils]: 21: Hoare triple {2559#(not |main_#t~short6|)} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {2489#true} is VALID [2018-11-14 16:06:33,255 INFO L273 TraceCheckUtils]: 20: Hoare triple {2707#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {2559#(not |main_#t~short6|)} is VALID [2018-11-14 16:06:33,256 INFO L273 TraceCheckUtils]: 19: Hoare triple {2707#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {2707#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} is VALID [2018-11-14 16:06:33,257 INFO L273 TraceCheckUtils]: 18: Hoare triple {2707#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} assume true; {2707#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} is VALID [2018-11-14 16:06:33,257 INFO L273 TraceCheckUtils]: 17: Hoare triple {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} ~i~0 := 0bv32; {2707#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0)))))} is VALID [2018-11-14 16:06:33,258 INFO L273 TraceCheckUtils]: 16: Hoare triple {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} is VALID [2018-11-14 16:06:33,261 INFO L273 TraceCheckUtils]: 15: Hoare triple {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} assume true; {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} is VALID [2018-11-14 16:06:33,264 INFO L273 TraceCheckUtils]: 14: Hoare triple {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} is VALID [2018-11-14 16:06:33,268 INFO L273 TraceCheckUtils]: 13: Hoare triple {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} is VALID [2018-11-14 16:06:33,270 INFO L273 TraceCheckUtils]: 12: Hoare triple {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} is VALID [2018-11-14 16:06:33,273 INFO L273 TraceCheckUtils]: 11: Hoare triple {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} is VALID [2018-11-14 16:06:33,275 INFO L273 TraceCheckUtils]: 10: Hoare triple {2739#(and (not (= (_ bv0 32) main_~CCCELVOL4~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {2717#(not (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))} is VALID [2018-11-14 16:06:33,276 INFO L273 TraceCheckUtils]: 9: Hoare triple {2739#(and (not (= (_ bv0 32) main_~CCCELVOL4~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {2739#(and (not (= (_ bv0 32) main_~CCCELVOL4~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:33,277 INFO L273 TraceCheckUtils]: 8: Hoare triple {2739#(and (not (= (_ bv0 32) main_~CCCELVOL4~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} assume true; {2739#(and (not (= (_ bv0 32) main_~CCCELVOL4~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:33,277 INFO L273 TraceCheckUtils]: 7: Hoare triple {2749#(not (= (_ bv0 32) main_~CCCELVOL4~0))} assume !(~bvsrem32(~CELLCOUNT~0, 4bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 4bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {2739#(and (not (= (_ bv0 32) main_~CCCELVOL4~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:33,278 INFO L273 TraceCheckUtils]: 6: Hoare triple {2489#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {2749#(not (= (_ bv0 32) main_~CCCELVOL4~0))} is VALID [2018-11-14 16:06:33,279 INFO L273 TraceCheckUtils]: 5: Hoare triple {2489#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {2489#true} is VALID [2018-11-14 16:06:33,279 INFO L256 TraceCheckUtils]: 4: Hoare triple {2489#true} call #t~ret7 := main(); {2489#true} is VALID [2018-11-14 16:06:33,279 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2489#true} {2489#true} #91#return; {2489#true} is VALID [2018-11-14 16:06:33,280 INFO L273 TraceCheckUtils]: 2: Hoare triple {2489#true} assume true; {2489#true} is VALID [2018-11-14 16:06:33,280 INFO L273 TraceCheckUtils]: 1: Hoare triple {2489#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {2489#true} is VALID [2018-11-14 16:06:33,280 INFO L256 TraceCheckUtils]: 0: Hoare triple {2489#true} call ULTIMATE.init(); {2489#true} is VALID [2018-11-14 16:06:33,282 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 12 proven. 5 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (7)] Exception during sending of exit command (exit): Broken pipe [2018-11-14 16:06:33,284 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-14 16:06:33,284 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 15 [2018-11-14 16:06:33,285 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 45 [2018-11-14 16:06:33,286 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 16:06:33,286 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 15 states. [2018-11-14 16:06:33,423 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 60 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 16:06:33,424 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-11-14 16:06:33,424 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-11-14 16:06:33,424 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=171, Unknown=0, NotChecked=0, Total=210 [2018-11-14 16:06:33,424 INFO L87 Difference]: Start difference. First operand 114 states and 137 transitions. Second operand 15 states. [2018-11-14 16:06:37,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 16:06:37,922 INFO L93 Difference]: Finished difference Result 204 states and 256 transitions. [2018-11-14 16:06:37,922 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-14 16:06:37,922 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 45 [2018-11-14 16:06:37,922 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-14 16:06:37,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2018-11-14 16:06:37,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 131 transitions. [2018-11-14 16:06:37,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2018-11-14 16:06:37,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 131 transitions. [2018-11-14 16:06:37,930 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 14 states and 131 transitions. [2018-11-14 16:06:38,281 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 131 edges. 131 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-14 16:06:38,288 INFO L225 Difference]: With dead ends: 204 [2018-11-14 16:06:38,288 INFO L226 Difference]: Without dead ends: 175 [2018-11-14 16:06:38,289 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 73 SyntacticMatches, 3 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 72 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=118, Invalid=434, Unknown=0, NotChecked=0, Total=552 [2018-11-14 16:06:38,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175 states. [2018-11-14 16:06:38,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175 to 125. [2018-11-14 16:06:38,604 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-14 16:06:38,604 INFO L82 GeneralOperation]: Start isEquivalent. First operand 175 states. Second operand 125 states. [2018-11-14 16:06:38,604 INFO L74 IsIncluded]: Start isIncluded. First operand 175 states. Second operand 125 states. [2018-11-14 16:06:38,604 INFO L87 Difference]: Start difference. First operand 175 states. Second operand 125 states. [2018-11-14 16:06:38,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 16:06:38,613 INFO L93 Difference]: Finished difference Result 175 states and 221 transitions. [2018-11-14 16:06:38,613 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 221 transitions. [2018-11-14 16:06:38,614 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 16:06:38,614 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 16:06:38,614 INFO L74 IsIncluded]: Start isIncluded. First operand 125 states. Second operand 175 states. [2018-11-14 16:06:38,614 INFO L87 Difference]: Start difference. First operand 125 states. Second operand 175 states. [2018-11-14 16:06:38,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-14 16:06:38,622 INFO L93 Difference]: Finished difference Result 175 states and 221 transitions. [2018-11-14 16:06:38,623 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 221 transitions. [2018-11-14 16:06:38,623 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-14 16:06:38,624 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-14 16:06:38,624 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-14 16:06:38,624 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-14 16:06:38,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2018-11-14 16:06:38,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 151 transitions. [2018-11-14 16:06:38,629 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 151 transitions. Word has length 45 [2018-11-14 16:06:38,629 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-14 16:06:38,629 INFO L480 AbstractCegarLoop]: Abstraction has 125 states and 151 transitions. [2018-11-14 16:06:38,629 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-11-14 16:06:38,630 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 151 transitions. [2018-11-14 16:06:38,631 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-11-14 16:06:38,631 INFO L367 BasicCegarLoop]: Found error trace [2018-11-14 16:06:38,631 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-14 16:06:38,631 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-14 16:06:38,631 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-14 16:06:38,631 INFO L82 PathProgramCache]: Analyzing trace with hash 2117141604, now seen corresponding path program 1 times [2018-11-14 16:06:38,632 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-14 16:06:38,632 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-14 16:06:38,663 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-14 16:06:38,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 16:06:38,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-14 16:06:38,793 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-14 16:06:38,907 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-14 16:06:38,915 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-14 16:06:38,917 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 16:06:38,922 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:06:38,944 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:06:38,945 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:34, output treesize:27 [2018-11-14 16:06:39,032 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 20 [2018-11-14 16:06:39,045 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 16:06:39,047 INFO L700 Elim1Store]: detected not equals via solver [2018-11-14 16:06:39,048 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 39 [2018-11-14 16:06:39,055 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-14 16:06:39,070 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:06:39,096 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-14 16:06:39,097 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:35, output treesize:31 [2018-11-14 16:06:39,661 INFO L256 TraceCheckUtils]: 0: Hoare triple {3567#true} call ULTIMATE.init(); {3567#true} is VALID [2018-11-14 16:06:39,661 INFO L273 TraceCheckUtils]: 1: Hoare triple {3567#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {3567#true} is VALID [2018-11-14 16:06:39,662 INFO L273 TraceCheckUtils]: 2: Hoare triple {3567#true} assume true; {3567#true} is VALID [2018-11-14 16:06:39,662 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {3567#true} {3567#true} #91#return; {3567#true} is VALID [2018-11-14 16:06:39,662 INFO L256 TraceCheckUtils]: 4: Hoare triple {3567#true} call #t~ret7 := main(); {3567#true} is VALID [2018-11-14 16:06:39,662 INFO L273 TraceCheckUtils]: 5: Hoare triple {3567#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {3567#true} is VALID [2018-11-14 16:06:39,664 INFO L273 TraceCheckUtils]: 6: Hoare triple {3567#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {3590#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-14 16:06:39,665 INFO L273 TraceCheckUtils]: 7: Hoare triple {3590#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !(~bvsrem32(~CELLCOUNT~0, 4bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 4bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {3594#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:39,665 INFO L273 TraceCheckUtils]: 8: Hoare triple {3594#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {3594#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:39,666 INFO L273 TraceCheckUtils]: 9: Hoare triple {3594#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3594#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:39,666 INFO L273 TraceCheckUtils]: 10: Hoare triple {3594#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {3604#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:39,667 INFO L273 TraceCheckUtils]: 11: Hoare triple {3604#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {3604#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:39,670 INFO L273 TraceCheckUtils]: 12: Hoare triple {3604#(and (bvsge (_ bv5 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {3611#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:39,672 INFO L273 TraceCheckUtils]: 13: Hoare triple {3611#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv1 32) main_~CCCELVOL1~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {3615#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 16:06:39,674 INFO L273 TraceCheckUtils]: 14: Hoare triple {3615#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3615#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 16:06:39,676 INFO L273 TraceCheckUtils]: 15: Hoare triple {3615#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume true; {3615#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 16:06:39,692 INFO L273 TraceCheckUtils]: 16: Hoare triple {3615#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3615#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 16:06:39,693 INFO L273 TraceCheckUtils]: 17: Hoare triple {3615#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} ~i~0 := 0bv32; {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 16:06:39,693 INFO L273 TraceCheckUtils]: 18: Hoare triple {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume true; {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 16:06:39,694 INFO L273 TraceCheckUtils]: 19: Hoare triple {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 16:06:39,695 INFO L273 TraceCheckUtils]: 20: Hoare triple {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} assume #t~short6; {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 16:06:39,697 INFO L256 TraceCheckUtils]: 21: Hoare triple {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} is VALID [2018-11-14 16:06:39,698 INFO L273 TraceCheckUtils]: 22: Hoare triple {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} ~cond := #in~cond; {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} is VALID [2018-11-14 16:06:39,699 INFO L273 TraceCheckUtils]: 23: Hoare triple {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} assume !(~cond == 0bv32); {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} is VALID [2018-11-14 16:06:39,699 INFO L273 TraceCheckUtils]: 24: Hoare triple {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} assume true; {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} is VALID [2018-11-14 16:06:39,700 INFO L268 TraceCheckUtils]: 25: Hoare quadruple {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} #95#return; {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 16:06:39,701 INFO L273 TraceCheckUtils]: 26: Hoare triple {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} is VALID [2018-11-14 16:06:39,702 INFO L273 TraceCheckUtils]: 27: Hoare triple {3628#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:39,704 INFO L273 TraceCheckUtils]: 28: Hoare triple {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:39,706 INFO L273 TraceCheckUtils]: 29: Hoare triple {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:39,713 INFO L273 TraceCheckUtils]: 30: Hoare triple {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:39,715 INFO L256 TraceCheckUtils]: 31: Hoare triple {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} is VALID [2018-11-14 16:06:39,716 INFO L273 TraceCheckUtils]: 32: Hoare triple {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} ~cond := #in~cond; {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} is VALID [2018-11-14 16:06:39,716 INFO L273 TraceCheckUtils]: 33: Hoare triple {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} assume !(~cond == 0bv32); {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} is VALID [2018-11-14 16:06:39,717 INFO L273 TraceCheckUtils]: 34: Hoare triple {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} assume true; {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} is VALID [2018-11-14 16:06:39,718 INFO L268 TraceCheckUtils]: 35: Hoare quadruple {3641#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv12 32)))))} {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #95#return; {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:39,720 INFO L273 TraceCheckUtils]: 36: Hoare triple {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:39,721 INFO L273 TraceCheckUtils]: 37: Hoare triple {3660#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {3691#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 16:06:39,722 INFO L273 TraceCheckUtils]: 38: Hoare triple {3691#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~i~0))} assume true; {3691#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-14 16:06:39,724 INFO L273 TraceCheckUtils]: 39: Hoare triple {3691#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge (_ bv3 32) main_~MINVAL~0) (not (bvsge (_ bv1 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~i~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3698#|main_#t~short6|} is VALID [2018-11-14 16:06:39,725 INFO L273 TraceCheckUtils]: 40: Hoare triple {3698#|main_#t~short6|} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {3568#false} is VALID [2018-11-14 16:06:39,726 INFO L256 TraceCheckUtils]: 41: Hoare triple {3568#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3568#false} is VALID [2018-11-14 16:06:39,726 INFO L273 TraceCheckUtils]: 42: Hoare triple {3568#false} ~cond := #in~cond; {3568#false} is VALID [2018-11-14 16:06:39,727 INFO L273 TraceCheckUtils]: 43: Hoare triple {3568#false} assume ~cond == 0bv32; {3568#false} is VALID [2018-11-14 16:06:39,727 INFO L273 TraceCheckUtils]: 44: Hoare triple {3568#false} assume !false; {3568#false} is VALID [2018-11-14 16:06:39,735 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 6 proven. 14 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-14 16:06:39,736 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-14 16:06:40,168 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 23 [2018-11-14 16:06:40,176 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 27 [2018-11-14 16:06:42,410 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (= (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) [2018-11-14 16:06:42,419 INFO L682 Elim1Store]: detected equality via solver [2018-11-14 16:06:42,420 INFO L303 Elim1Store]: Index analysis took 2172 ms [2018-11-14 16:06:42,420 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 17 [2018-11-14 16:06:42,423 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 16:06:42,444 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 16:06:42,456 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 16:06:42,476 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-14 16:06:42,477 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 2 variables, input treesize:33, output treesize:21 [2018-11-14 16:06:42,493 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-14 16:06:42,826 INFO L273 TraceCheckUtils]: 44: Hoare triple {3568#false} assume !false; {3568#false} is VALID [2018-11-14 16:06:42,826 INFO L273 TraceCheckUtils]: 43: Hoare triple {3568#false} assume ~cond == 0bv32; {3568#false} is VALID [2018-11-14 16:06:42,826 INFO L273 TraceCheckUtils]: 42: Hoare triple {3568#false} ~cond := #in~cond; {3568#false} is VALID [2018-11-14 16:06:42,827 INFO L256 TraceCheckUtils]: 41: Hoare triple {3568#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3568#false} is VALID [2018-11-14 16:06:42,827 INFO L273 TraceCheckUtils]: 40: Hoare triple {3698#|main_#t~short6|} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {3568#false} is VALID [2018-11-14 16:06:42,830 INFO L273 TraceCheckUtils]: 39: Hoare triple {3729#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3698#|main_#t~short6|} is VALID [2018-11-14 16:06:42,830 INFO L273 TraceCheckUtils]: 38: Hoare triple {3729#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume true; {3729#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is VALID [2018-11-14 16:06:44,859 INFO L273 TraceCheckUtils]: 37: Hoare triple {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {3729#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is UNKNOWN [2018-11-14 16:06:44,859 INFO L273 TraceCheckUtils]: 36: Hoare triple {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 16:06:44,860 INFO L268 TraceCheckUtils]: 35: Hoare quadruple {3567#true} {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} #95#return; {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 16:06:44,860 INFO L273 TraceCheckUtils]: 34: Hoare triple {3567#true} assume true; {3567#true} is VALID [2018-11-14 16:06:44,860 INFO L273 TraceCheckUtils]: 33: Hoare triple {3567#true} assume !(~cond == 0bv32); {3567#true} is VALID [2018-11-14 16:06:44,861 INFO L273 TraceCheckUtils]: 32: Hoare triple {3567#true} ~cond := #in~cond; {3567#true} is VALID [2018-11-14 16:06:44,861 INFO L256 TraceCheckUtils]: 31: Hoare triple {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3567#true} is VALID [2018-11-14 16:06:44,861 INFO L273 TraceCheckUtils]: 30: Hoare triple {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := #t~mem5 == 0bv32; {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 16:06:44,861 INFO L273 TraceCheckUtils]: 29: Hoare triple {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 16:06:44,862 INFO L273 TraceCheckUtils]: 28: Hoare triple {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} assume true; {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-14 16:06:46,881 INFO L273 TraceCheckUtils]: 27: Hoare triple {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {3736#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is UNKNOWN [2018-11-14 16:06:46,882 INFO L273 TraceCheckUtils]: 26: Hoare triple {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} havoc #t~mem5;havoc #t~short6;havoc #t~mem4; {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 16:06:46,883 INFO L268 TraceCheckUtils]: 25: Hoare quadruple {3567#true} {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} #95#return; {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 16:06:46,883 INFO L273 TraceCheckUtils]: 24: Hoare triple {3567#true} assume true; {3567#true} is VALID [2018-11-14 16:06:46,883 INFO L273 TraceCheckUtils]: 23: Hoare triple {3567#true} assume !(~cond == 0bv32); {3567#true} is VALID [2018-11-14 16:06:46,883 INFO L273 TraceCheckUtils]: 22: Hoare triple {3567#true} ~cond := #in~cond; {3567#true} is VALID [2018-11-14 16:06:46,883 INFO L256 TraceCheckUtils]: 21: Hoare triple {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3567#true} is VALID [2018-11-14 16:06:46,884 INFO L273 TraceCheckUtils]: 20: Hoare triple {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} assume #t~short6; {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 16:06:46,884 INFO L273 TraceCheckUtils]: 19: Hoare triple {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 16:06:46,884 INFO L273 TraceCheckUtils]: 18: Hoare triple {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} assume true; {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 16:06:46,885 INFO L273 TraceCheckUtils]: 17: Hoare triple {3798#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} ~i~0 := 0bv32; {3767#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 16:06:46,885 INFO L273 TraceCheckUtils]: 16: Hoare triple {3798#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3798#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 16:06:46,886 INFO L273 TraceCheckUtils]: 15: Hoare triple {3798#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} assume true; {3798#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 16:06:46,886 INFO L273 TraceCheckUtils]: 14: Hoare triple {3798#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3798#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 16:06:46,897 INFO L273 TraceCheckUtils]: 13: Hoare triple {3811#(or (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {3798#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-14 16:06:46,916 INFO L273 TraceCheckUtils]: 12: Hoare triple {3815#(or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {3811#(or (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0))} is VALID [2018-11-14 16:06:46,917 INFO L273 TraceCheckUtils]: 11: Hoare triple {3815#(or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {3815#(or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:46,984 INFO L273 TraceCheckUtils]: 10: Hoare triple {3822#(or (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {3815#(or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:46,984 INFO L273 TraceCheckUtils]: 9: Hoare triple {3822#(or (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3822#(or (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:46,985 INFO L273 TraceCheckUtils]: 8: Hoare triple {3822#(or (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} assume true; {3822#(or (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:46,985 INFO L273 TraceCheckUtils]: 7: Hoare triple {3567#true} assume !(~bvsrem32(~CELLCOUNT~0, 4bv32) != 0bv32);assume (if ~bvsrem32(~CELLCOUNT~0, 4bv32) == 0bv32 then 1bv32 else 0bv32) != 0bv32;~i~0 := 1bv32; {3822#(or (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL4~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL1~0 main_~MINVAL~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)))} is VALID [2018-11-14 16:06:46,985 INFO L273 TraceCheckUtils]: 6: Hoare triple {3567#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {3567#true} is VALID [2018-11-14 16:06:46,986 INFO L273 TraceCheckUtils]: 5: Hoare triple {3567#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {3567#true} is VALID [2018-11-14 16:06:46,986 INFO L256 TraceCheckUtils]: 4: Hoare triple {3567#true} call #t~ret7 := main(); {3567#true} is VALID [2018-11-14 16:06:46,986 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {3567#true} {3567#true} #91#return; {3567#true} is VALID [2018-11-14 16:06:46,986 INFO L273 TraceCheckUtils]: 2: Hoare triple {3567#true} assume true; {3567#true} is VALID [2018-11-14 16:06:46,986 INFO L273 TraceCheckUtils]: 1: Hoare triple {3567#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {3567#true} is VALID [2018-11-14 16:06:46,986 INFO L256 TraceCheckUtils]: 0: Hoare triple {3567#true} call ULTIMATE.init(); {3567#true} is VALID [2018-11-14 16:06:46,990 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 6 proven. 14 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-14 16:06:46,992 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-14 16:06:46,992 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 10] total 19 [2018-11-14 16:06:46,993 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 45 [2018-11-14 16:06:46,993 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-14 16:06:46,993 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 19 states. [2018-11-14 16:06:51,392 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 73 edges. 71 inductive. 0 not inductive. 2 times theorem prover too weak to decide inductivity. [2018-11-14 16:06:51,393 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-11-14 16:06:51,393 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-11-14 16:06:51,393 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=276, Unknown=0, NotChecked=0, Total=342 [2018-11-14 16:06:51,393 INFO L87 Difference]: Start difference. First operand 125 states and 151 transitions. Second operand 19 states.