java -ea -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf -i ../../../trunk/examples/svcomp/array-tiling/mbpr4_true-unreach-call.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-18e5b2d-m [2018-11-18 21:05:46,090 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 21:05:46,092 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 21:05:46,114 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 21:05:46,114 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 21:05:46,115 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 21:05:46,117 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 21:05:46,118 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 21:05:46,120 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 21:05:46,121 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 21:05:46,122 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 21:05:46,125 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 21:05:46,126 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 21:05:46,127 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 21:05:46,128 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 21:05:46,131 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 21:05:46,132 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 21:05:46,134 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 21:05:46,136 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 21:05:46,137 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 21:05:46,138 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 21:05:46,140 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 21:05:46,142 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 21:05:46,143 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 21:05:46,143 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 21:05:46,144 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 21:05:46,145 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 21:05:46,145 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 21:05:46,146 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 21:05:46,147 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 21:05:46,148 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 21:05:46,148 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 21:05:46,149 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 21:05:46,149 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 21:05:46,150 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 21:05:46,151 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 21:05:46,151 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf [2018-11-18 21:05:46,167 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 21:05:46,167 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 21:05:46,168 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-18 21:05:46,168 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-11-18 21:05:46,169 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 21:05:46,169 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 21:05:46,169 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 21:05:46,169 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 21:05:46,169 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 21:05:46,170 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 21:05:46,170 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 21:05:46,170 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-18 21:05:46,170 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-18 21:05:46,170 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-18 21:05:46,170 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-18 21:05:46,171 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-18 21:05:46,171 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 21:05:46,171 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 21:05:46,171 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 21:05:46,171 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-18 21:05:46,172 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 21:05:46,172 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 21:05:46,172 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-18 21:05:46,172 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-18 21:05:46,172 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 21:05:46,173 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 21:05:46,173 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-18 21:05:46,173 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-18 21:05:46,173 INFO L133 SettingsManager]: * Trace refinement strategy=WOLF [2018-11-18 21:05:46,173 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-18 21:05:46,174 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-11-18 21:05:46,174 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-11-18 21:05:46,174 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-18 21:05:46,216 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 21:05:46,234 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 21:05:46,239 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 21:05:46,241 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 21:05:46,241 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 21:05:46,242 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-tiling/mbpr4_true-unreach-call.i [2018-11-18 21:05:46,293 INFO L221 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/bd1c862c7/81348e9730434112a492f21e6c0bca0f/FLAG7096ee6ad [2018-11-18 21:05:46,715 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 21:05:46,716 INFO L161 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-tiling/mbpr4_true-unreach-call.i [2018-11-18 21:05:46,724 INFO L355 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/bd1c862c7/81348e9730434112a492f21e6c0bca0f/FLAG7096ee6ad [2018-11-18 21:05:47,078 INFO L363 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/bd1c862c7/81348e9730434112a492f21e6c0bca0f [2018-11-18 21:05:47,088 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 21:05:47,089 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-11-18 21:05:47,091 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 21:05:47,091 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 21:05:47,095 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 21:05:47,097 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 09:05:47" (1/1) ... [2018-11-18 21:05:47,100 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6b7f50e5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:05:47, skipping insertion in model container [2018-11-18 21:05:47,100 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 09:05:47" (1/1) ... [2018-11-18 21:05:47,111 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 21:05:47,137 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 21:05:47,384 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 21:05:47,389 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 21:05:47,439 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 21:05:47,465 INFO L195 MainTranslator]: Completed translation [2018-11-18 21:05:47,466 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:05:47 WrapperNode [2018-11-18 21:05:47,466 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 21:05:47,467 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 21:05:47,467 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 21:05:47,467 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 21:05:47,483 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:05:47" (1/1) ... [2018-11-18 21:05:47,483 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:05:47" (1/1) ... [2018-11-18 21:05:47,508 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:05:47" (1/1) ... [2018-11-18 21:05:47,508 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:05:47" (1/1) ... [2018-11-18 21:05:47,563 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:05:47" (1/1) ... [2018-11-18 21:05:47,580 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:05:47" (1/1) ... [2018-11-18 21:05:47,589 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:05:47" (1/1) ... [2018-11-18 21:05:47,593 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 21:05:47,593 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 21:05:47,594 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 21:05:47,594 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 21:05:47,595 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:05:47" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 21:05:47,797 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-18 21:05:47,798 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 21:05:47,798 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-11-18 21:05:47,798 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-18 21:05:47,798 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-11-18 21:05:47,798 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assume [2018-11-18 21:05:47,799 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-11-18 21:05:47,799 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-11-18 21:05:47,799 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-18 21:05:47,799 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-18 21:05:47,799 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-18 21:05:47,799 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE4 [2018-11-18 21:05:47,800 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE4 [2018-11-18 21:05:47,800 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-18 21:05:47,800 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 21:05:47,800 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~intINTTYPE4 [2018-11-18 21:05:49,012 INFO L280 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 21:05:49,012 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 09:05:49 BoogieIcfgContainer [2018-11-18 21:05:49,013 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 21:05:49,014 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-18 21:05:49,014 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-18 21:05:49,016 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-18 21:05:49,017 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 18.11 09:05:47" (1/3) ... [2018-11-18 21:05:49,017 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@386138e9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 09:05:49, skipping insertion in model container [2018-11-18 21:05:49,018 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:05:47" (2/3) ... [2018-11-18 21:05:49,018 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@386138e9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 09:05:49, skipping insertion in model container [2018-11-18 21:05:49,018 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 09:05:49" (3/3) ... [2018-11-18 21:05:49,020 INFO L112 eAbstractionObserver]: Analyzing ICFG mbpr4_true-unreach-call.i [2018-11-18 21:05:49,028 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-18 21:05:49,037 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-18 21:05:49,054 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-18 21:05:49,086 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 21:05:49,087 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-18 21:05:49,088 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-18 21:05:49,088 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-18 21:05:49,088 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 21:05:49,088 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 21:05:49,089 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-18 21:05:49,089 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 21:05:49,089 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-18 21:05:49,110 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states. [2018-11-18 21:05:49,117 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-11-18 21:05:49,117 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:05:49,119 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:05:49,121 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:05:49,128 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:05:49,128 INFO L82 PathProgramCache]: Analyzing trace with hash -1557951846, now seen corresponding path program 1 times [2018-11-18 21:05:49,134 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:05:49,134 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:05:49,168 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:05:49,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:05:49,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:05:49,263 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:05:49,352 INFO L256 TraceCheckUtils]: 0: Hoare triple {53#true} call ULTIMATE.init(); {53#true} is VALID [2018-11-18 21:05:49,355 INFO L273 TraceCheckUtils]: 1: Hoare triple {53#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {53#true} is VALID [2018-11-18 21:05:49,356 INFO L273 TraceCheckUtils]: 2: Hoare triple {53#true} assume true; {53#true} is VALID [2018-11-18 21:05:49,357 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {53#true} {53#true} #141#return; {53#true} is VALID [2018-11-18 21:05:49,357 INFO L256 TraceCheckUtils]: 4: Hoare triple {53#true} call #t~ret22 := main(); {53#true} is VALID [2018-11-18 21:05:49,357 INFO L273 TraceCheckUtils]: 5: Hoare triple {53#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {53#true} is VALID [2018-11-18 21:05:49,357 INFO L273 TraceCheckUtils]: 6: Hoare triple {53#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {53#true} is VALID [2018-11-18 21:05:49,358 INFO L273 TraceCheckUtils]: 7: Hoare triple {53#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {53#true} is VALID [2018-11-18 21:05:49,359 INFO L273 TraceCheckUtils]: 8: Hoare triple {53#true} assume !true; {54#false} is VALID [2018-11-18 21:05:49,360 INFO L273 TraceCheckUtils]: 9: Hoare triple {54#false} ~i~0 := 1bv32; {54#false} is VALID [2018-11-18 21:05:49,360 INFO L273 TraceCheckUtils]: 10: Hoare triple {54#false} assume !true; {54#false} is VALID [2018-11-18 21:05:49,360 INFO L273 TraceCheckUtils]: 11: Hoare triple {54#false} ~i~0 := 1bv32; {54#false} is VALID [2018-11-18 21:05:49,361 INFO L273 TraceCheckUtils]: 12: Hoare triple {54#false} assume !true; {54#false} is VALID [2018-11-18 21:05:49,361 INFO L273 TraceCheckUtils]: 13: Hoare triple {54#false} ~i~0 := 1bv32; {54#false} is VALID [2018-11-18 21:05:49,362 INFO L273 TraceCheckUtils]: 14: Hoare triple {54#false} assume !true; {54#false} is VALID [2018-11-18 21:05:49,362 INFO L273 TraceCheckUtils]: 15: Hoare triple {54#false} ~i~0 := 0bv32; {54#false} is VALID [2018-11-18 21:05:49,362 INFO L273 TraceCheckUtils]: 16: Hoare triple {54#false} assume true; {54#false} is VALID [2018-11-18 21:05:49,363 INFO L273 TraceCheckUtils]: 17: Hoare triple {54#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {54#false} is VALID [2018-11-18 21:05:49,363 INFO L273 TraceCheckUtils]: 18: Hoare triple {54#false} assume #t~short21; {54#false} is VALID [2018-11-18 21:05:49,363 INFO L256 TraceCheckUtils]: 19: Hoare triple {54#false} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {54#false} is VALID [2018-11-18 21:05:49,364 INFO L273 TraceCheckUtils]: 20: Hoare triple {54#false} ~cond := #in~cond; {54#false} is VALID [2018-11-18 21:05:49,364 INFO L273 TraceCheckUtils]: 21: Hoare triple {54#false} assume 0bv32 == ~cond; {54#false} is VALID [2018-11-18 21:05:49,365 INFO L273 TraceCheckUtils]: 22: Hoare triple {54#false} assume !false; {54#false} is VALID [2018-11-18 21:05:49,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:05:49,370 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (2)] Exception during sending of exit command (exit): Broken pipe [2018-11-18 21:05:49,376 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 21:05:49,377 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 21:05:49,388 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 23 [2018-11-18 21:05:49,393 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:05:49,401 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 2 states. [2018-11-18 21:05:49,482 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 23 edges. 23 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:05:49,483 INFO L459 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-11-18 21:05:49,491 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-11-18 21:05:49,492 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-18 21:05:49,494 INFO L87 Difference]: Start difference. First operand 50 states. Second operand 2 states. [2018-11-18 21:05:49,851 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:05:49,851 INFO L93 Difference]: Finished difference Result 87 states and 117 transitions. [2018-11-18 21:05:49,852 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-11-18 21:05:49,852 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 23 [2018-11-18 21:05:49,852 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:05:49,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2018-11-18 21:05:49,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 117 transitions. [2018-11-18 21:05:49,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2018-11-18 21:05:49,872 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 117 transitions. [2018-11-18 21:05:49,873 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 2 states and 117 transitions. [2018-11-18 21:05:51,026 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 117 edges. 117 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:05:51,041 INFO L225 Difference]: With dead ends: 87 [2018-11-18 21:05:51,041 INFO L226 Difference]: Without dead ends: 44 [2018-11-18 21:05:51,045 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 22 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-18 21:05:51,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2018-11-18 21:05:51,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 44. [2018-11-18 21:05:51,110 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:05:51,111 INFO L82 GeneralOperation]: Start isEquivalent. First operand 44 states. Second operand 44 states. [2018-11-18 21:05:51,111 INFO L74 IsIncluded]: Start isIncluded. First operand 44 states. Second operand 44 states. [2018-11-18 21:05:51,112 INFO L87 Difference]: Start difference. First operand 44 states. Second operand 44 states. [2018-11-18 21:05:51,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:05:51,118 INFO L93 Difference]: Finished difference Result 44 states and 53 transitions. [2018-11-18 21:05:51,118 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 53 transitions. [2018-11-18 21:05:51,119 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:05:51,119 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:05:51,119 INFO L74 IsIncluded]: Start isIncluded. First operand 44 states. Second operand 44 states. [2018-11-18 21:05:51,120 INFO L87 Difference]: Start difference. First operand 44 states. Second operand 44 states. [2018-11-18 21:05:51,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:05:51,125 INFO L93 Difference]: Finished difference Result 44 states and 53 transitions. [2018-11-18 21:05:51,126 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 53 transitions. [2018-11-18 21:05:51,126 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:05:51,127 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:05:51,127 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:05:51,127 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:05:51,128 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2018-11-18 21:05:51,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 53 transitions. [2018-11-18 21:05:51,133 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 53 transitions. Word has length 23 [2018-11-18 21:05:51,133 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:05:51,134 INFO L480 AbstractCegarLoop]: Abstraction has 44 states and 53 transitions. [2018-11-18 21:05:51,134 INFO L481 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-11-18 21:05:51,134 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 53 transitions. [2018-11-18 21:05:51,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-11-18 21:05:51,135 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:05:51,136 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:05:51,136 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:05:51,136 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:05:51,137 INFO L82 PathProgramCache]: Analyzing trace with hash -2008134730, now seen corresponding path program 1 times [2018-11-18 21:05:51,137 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:05:51,137 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:05:51,165 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:05:51,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:05:51,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:05:51,211 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:05:51,438 INFO L256 TraceCheckUtils]: 0: Hoare triple {370#true} call ULTIMATE.init(); {370#true} is VALID [2018-11-18 21:05:51,439 INFO L273 TraceCheckUtils]: 1: Hoare triple {370#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {370#true} is VALID [2018-11-18 21:05:51,439 INFO L273 TraceCheckUtils]: 2: Hoare triple {370#true} assume true; {370#true} is VALID [2018-11-18 21:05:51,439 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {370#true} {370#true} #141#return; {370#true} is VALID [2018-11-18 21:05:51,439 INFO L256 TraceCheckUtils]: 4: Hoare triple {370#true} call #t~ret22 := main(); {370#true} is VALID [2018-11-18 21:05:51,440 INFO L273 TraceCheckUtils]: 5: Hoare triple {370#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {370#true} is VALID [2018-11-18 21:05:51,440 INFO L273 TraceCheckUtils]: 6: Hoare triple {370#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {370#true} is VALID [2018-11-18 21:05:51,440 INFO L273 TraceCheckUtils]: 7: Hoare triple {370#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {370#true} is VALID [2018-11-18 21:05:51,441 INFO L273 TraceCheckUtils]: 8: Hoare triple {370#true} assume true; {370#true} is VALID [2018-11-18 21:05:51,441 INFO L273 TraceCheckUtils]: 9: Hoare triple {370#true} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {370#true} is VALID [2018-11-18 21:05:51,441 INFO L273 TraceCheckUtils]: 10: Hoare triple {370#true} ~i~0 := 1bv32; {370#true} is VALID [2018-11-18 21:05:51,442 INFO L273 TraceCheckUtils]: 11: Hoare triple {370#true} assume true; {370#true} is VALID [2018-11-18 21:05:51,442 INFO L273 TraceCheckUtils]: 12: Hoare triple {370#true} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {370#true} is VALID [2018-11-18 21:05:51,442 INFO L273 TraceCheckUtils]: 13: Hoare triple {370#true} ~i~0 := 1bv32; {370#true} is VALID [2018-11-18 21:05:51,442 INFO L273 TraceCheckUtils]: 14: Hoare triple {370#true} assume true; {370#true} is VALID [2018-11-18 21:05:51,443 INFO L273 TraceCheckUtils]: 15: Hoare triple {370#true} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {370#true} is VALID [2018-11-18 21:05:51,443 INFO L273 TraceCheckUtils]: 16: Hoare triple {370#true} ~i~0 := 1bv32; {370#true} is VALID [2018-11-18 21:05:51,443 INFO L273 TraceCheckUtils]: 17: Hoare triple {370#true} assume true; {370#true} is VALID [2018-11-18 21:05:51,444 INFO L273 TraceCheckUtils]: 18: Hoare triple {370#true} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {370#true} is VALID [2018-11-18 21:05:51,444 INFO L273 TraceCheckUtils]: 19: Hoare triple {370#true} ~i~0 := 0bv32; {370#true} is VALID [2018-11-18 21:05:51,444 INFO L273 TraceCheckUtils]: 20: Hoare triple {370#true} assume true; {370#true} is VALID [2018-11-18 21:05:51,445 INFO L273 TraceCheckUtils]: 21: Hoare triple {370#true} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {370#true} is VALID [2018-11-18 21:05:51,446 INFO L273 TraceCheckUtils]: 22: Hoare triple {370#true} assume #t~short21; {441#|main_#t~short21|} is VALID [2018-11-18 21:05:51,447 INFO L256 TraceCheckUtils]: 23: Hoare triple {441#|main_#t~short21|} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {445#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-18 21:05:51,448 INFO L273 TraceCheckUtils]: 24: Hoare triple {445#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {449#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-18 21:05:51,448 INFO L273 TraceCheckUtils]: 25: Hoare triple {449#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 == ~cond; {371#false} is VALID [2018-11-18 21:05:51,449 INFO L273 TraceCheckUtils]: 26: Hoare triple {371#false} assume !false; {371#false} is VALID [2018-11-18 21:05:51,451 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:05:51,451 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-18 21:05:51,454 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 21:05:51,454 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 21:05:51,456 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 27 [2018-11-18 21:05:51,456 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:05:51,456 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states. [2018-11-18 21:05:51,566 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 27 edges. 27 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:05:51,566 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 21:05:51,567 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 21:05:51,567 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 21:05:51,568 INFO L87 Difference]: Start difference. First operand 44 states and 53 transitions. Second operand 5 states. [2018-11-18 21:05:52,556 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:05:52,556 INFO L93 Difference]: Finished difference Result 52 states and 61 transitions. [2018-11-18 21:05:52,556 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 21:05:52,557 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 27 [2018-11-18 21:05:52,557 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:05:52,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-18 21:05:52,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 61 transitions. [2018-11-18 21:05:52,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-18 21:05:52,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 61 transitions. [2018-11-18 21:05:52,563 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states and 61 transitions. [2018-11-18 21:05:52,762 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 61 edges. 61 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:05:52,767 INFO L225 Difference]: With dead ends: 52 [2018-11-18 21:05:52,767 INFO L226 Difference]: Without dead ends: 50 [2018-11-18 21:05:52,768 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 23 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 21:05:52,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2018-11-18 21:05:52,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 49. [2018-11-18 21:05:52,787 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:05:52,787 INFO L82 GeneralOperation]: Start isEquivalent. First operand 50 states. Second operand 49 states. [2018-11-18 21:05:52,788 INFO L74 IsIncluded]: Start isIncluded. First operand 50 states. Second operand 49 states. [2018-11-18 21:05:52,788 INFO L87 Difference]: Start difference. First operand 50 states. Second operand 49 states. [2018-11-18 21:05:52,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:05:52,792 INFO L93 Difference]: Finished difference Result 50 states and 59 transitions. [2018-11-18 21:05:52,793 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 59 transitions. [2018-11-18 21:05:52,793 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:05:52,794 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:05:52,794 INFO L74 IsIncluded]: Start isIncluded. First operand 49 states. Second operand 50 states. [2018-11-18 21:05:52,794 INFO L87 Difference]: Start difference. First operand 49 states. Second operand 50 states. [2018-11-18 21:05:52,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:05:52,798 INFO L93 Difference]: Finished difference Result 50 states and 59 transitions. [2018-11-18 21:05:52,798 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 59 transitions. [2018-11-18 21:05:52,799 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:05:52,799 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:05:52,799 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:05:52,800 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:05:52,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2018-11-18 21:05:52,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 58 transitions. [2018-11-18 21:05:52,803 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 58 transitions. Word has length 27 [2018-11-18 21:05:52,803 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:05:52,803 INFO L480 AbstractCegarLoop]: Abstraction has 49 states and 58 transitions. [2018-11-18 21:05:52,803 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 21:05:52,804 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 58 transitions. [2018-11-18 21:05:52,805 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-11-18 21:05:52,805 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:05:52,805 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:05:52,805 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:05:52,806 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:05:52,806 INFO L82 PathProgramCache]: Analyzing trace with hash -2006287688, now seen corresponding path program 1 times [2018-11-18 21:05:52,806 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:05:52,807 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:05:52,834 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:05:52,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:05:52,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:05:52,919 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:05:53,106 INFO L256 TraceCheckUtils]: 0: Hoare triple {684#true} call ULTIMATE.init(); {684#true} is VALID [2018-11-18 21:05:53,107 INFO L273 TraceCheckUtils]: 1: Hoare triple {684#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {684#true} is VALID [2018-11-18 21:05:53,107 INFO L273 TraceCheckUtils]: 2: Hoare triple {684#true} assume true; {684#true} is VALID [2018-11-18 21:05:53,108 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {684#true} {684#true} #141#return; {684#true} is VALID [2018-11-18 21:05:53,108 INFO L256 TraceCheckUtils]: 4: Hoare triple {684#true} call #t~ret22 := main(); {684#true} is VALID [2018-11-18 21:05:53,108 INFO L273 TraceCheckUtils]: 5: Hoare triple {684#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {684#true} is VALID [2018-11-18 21:05:53,118 INFO L273 TraceCheckUtils]: 6: Hoare triple {684#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {707#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} is VALID [2018-11-18 21:05:53,119 INFO L273 TraceCheckUtils]: 7: Hoare triple {707#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {711#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:05:53,120 INFO L273 TraceCheckUtils]: 8: Hoare triple {711#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {711#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:05:53,135 INFO L273 TraceCheckUtils]: 9: Hoare triple {711#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {685#false} is VALID [2018-11-18 21:05:53,136 INFO L273 TraceCheckUtils]: 10: Hoare triple {685#false} ~i~0 := 1bv32; {685#false} is VALID [2018-11-18 21:05:53,136 INFO L273 TraceCheckUtils]: 11: Hoare triple {685#false} assume true; {685#false} is VALID [2018-11-18 21:05:53,136 INFO L273 TraceCheckUtils]: 12: Hoare triple {685#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {685#false} is VALID [2018-11-18 21:05:53,137 INFO L273 TraceCheckUtils]: 13: Hoare triple {685#false} ~i~0 := 1bv32; {685#false} is VALID [2018-11-18 21:05:53,137 INFO L273 TraceCheckUtils]: 14: Hoare triple {685#false} assume true; {685#false} is VALID [2018-11-18 21:05:53,137 INFO L273 TraceCheckUtils]: 15: Hoare triple {685#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {685#false} is VALID [2018-11-18 21:05:53,138 INFO L273 TraceCheckUtils]: 16: Hoare triple {685#false} ~i~0 := 1bv32; {685#false} is VALID [2018-11-18 21:05:53,138 INFO L273 TraceCheckUtils]: 17: Hoare triple {685#false} assume true; {685#false} is VALID [2018-11-18 21:05:53,138 INFO L273 TraceCheckUtils]: 18: Hoare triple {685#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {685#false} is VALID [2018-11-18 21:05:53,139 INFO L273 TraceCheckUtils]: 19: Hoare triple {685#false} ~i~0 := 0bv32; {685#false} is VALID [2018-11-18 21:05:53,139 INFO L273 TraceCheckUtils]: 20: Hoare triple {685#false} assume true; {685#false} is VALID [2018-11-18 21:05:53,139 INFO L273 TraceCheckUtils]: 21: Hoare triple {685#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {685#false} is VALID [2018-11-18 21:05:53,139 INFO L273 TraceCheckUtils]: 22: Hoare triple {685#false} assume !#t~short21;call #t~mem20 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := 0bv32 == #t~mem20; {685#false} is VALID [2018-11-18 21:05:53,140 INFO L256 TraceCheckUtils]: 23: Hoare triple {685#false} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {685#false} is VALID [2018-11-18 21:05:53,140 INFO L273 TraceCheckUtils]: 24: Hoare triple {685#false} ~cond := #in~cond; {685#false} is VALID [2018-11-18 21:05:53,140 INFO L273 TraceCheckUtils]: 25: Hoare triple {685#false} assume 0bv32 == ~cond; {685#false} is VALID [2018-11-18 21:05:53,141 INFO L273 TraceCheckUtils]: 26: Hoare triple {685#false} assume !false; {685#false} is VALID [2018-11-18 21:05:53,143 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:05:53,143 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-18 21:05:53,148 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 21:05:53,148 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 21:05:53,148 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 27 [2018-11-18 21:05:53,149 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:05:53,149 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states. [2018-11-18 21:05:53,270 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 27 edges. 27 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:05:53,270 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 21:05:53,270 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 21:05:53,270 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-18 21:05:53,271 INFO L87 Difference]: Start difference. First operand 49 states and 58 transitions. Second operand 4 states. [2018-11-18 21:05:54,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:05:54,107 INFO L93 Difference]: Finished difference Result 90 states and 108 transitions. [2018-11-18 21:05:54,108 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 21:05:54,108 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 27 [2018-11-18 21:05:54,108 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:05:54,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-18 21:05:54,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 98 transitions. [2018-11-18 21:05:54,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-18 21:05:54,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 98 transitions. [2018-11-18 21:05:54,115 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states and 98 transitions. [2018-11-18 21:05:54,548 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 98 edges. 98 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:05:54,551 INFO L225 Difference]: With dead ends: 90 [2018-11-18 21:05:54,551 INFO L226 Difference]: Without dead ends: 54 [2018-11-18 21:05:54,552 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 24 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-18 21:05:54,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-11-18 21:05:54,595 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 51. [2018-11-18 21:05:54,595 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:05:54,596 INFO L82 GeneralOperation]: Start isEquivalent. First operand 54 states. Second operand 51 states. [2018-11-18 21:05:54,596 INFO L74 IsIncluded]: Start isIncluded. First operand 54 states. Second operand 51 states. [2018-11-18 21:05:54,596 INFO L87 Difference]: Start difference. First operand 54 states. Second operand 51 states. [2018-11-18 21:05:54,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:05:54,599 INFO L93 Difference]: Finished difference Result 54 states and 64 transitions. [2018-11-18 21:05:54,600 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 64 transitions. [2018-11-18 21:05:54,600 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:05:54,601 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:05:54,601 INFO L74 IsIncluded]: Start isIncluded. First operand 51 states. Second operand 54 states. [2018-11-18 21:05:54,601 INFO L87 Difference]: Start difference. First operand 51 states. Second operand 54 states. [2018-11-18 21:05:54,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:05:54,604 INFO L93 Difference]: Finished difference Result 54 states and 64 transitions. [2018-11-18 21:05:54,605 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 64 transitions. [2018-11-18 21:05:54,605 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:05:54,606 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:05:54,606 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:05:54,606 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:05:54,606 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-11-18 21:05:54,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 60 transitions. [2018-11-18 21:05:54,609 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 60 transitions. Word has length 27 [2018-11-18 21:05:54,609 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:05:54,609 INFO L480 AbstractCegarLoop]: Abstraction has 51 states and 60 transitions. [2018-11-18 21:05:54,609 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 21:05:54,609 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 60 transitions. [2018-11-18 21:05:54,610 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-11-18 21:05:54,611 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:05:54,611 INFO L375 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:05:54,611 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:05:54,611 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:05:54,612 INFO L82 PathProgramCache]: Analyzing trace with hash -1952533285, now seen corresponding path program 1 times [2018-11-18 21:05:54,612 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:05:54,612 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:05:54,629 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:05:54,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:05:54,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:05:54,693 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:05:55,438 INFO L256 TraceCheckUtils]: 0: Hoare triple {1053#true} call ULTIMATE.init(); {1053#true} is VALID [2018-11-18 21:05:55,439 INFO L273 TraceCheckUtils]: 1: Hoare triple {1053#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1053#true} is VALID [2018-11-18 21:05:55,440 INFO L273 TraceCheckUtils]: 2: Hoare triple {1053#true} assume true; {1053#true} is VALID [2018-11-18 21:05:55,440 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1053#true} {1053#true} #141#return; {1053#true} is VALID [2018-11-18 21:05:55,441 INFO L256 TraceCheckUtils]: 4: Hoare triple {1053#true} call #t~ret22 := main(); {1053#true} is VALID [2018-11-18 21:05:55,441 INFO L273 TraceCheckUtils]: 5: Hoare triple {1053#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1053#true} is VALID [2018-11-18 21:05:55,441 INFO L273 TraceCheckUtils]: 6: Hoare triple {1053#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {1053#true} is VALID [2018-11-18 21:05:55,442 INFO L273 TraceCheckUtils]: 7: Hoare triple {1053#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1079#(= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-18 21:05:55,443 INFO L273 TraceCheckUtils]: 8: Hoare triple {1079#(= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))} assume true; {1079#(= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-18 21:05:55,443 INFO L273 TraceCheckUtils]: 9: Hoare triple {1079#(= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1086#(and (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:05:55,444 INFO L273 TraceCheckUtils]: 10: Hoare triple {1086#(and (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {1086#(and (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:05:55,445 INFO L273 TraceCheckUtils]: 11: Hoare triple {1086#(and (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call #t~mem3 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem3, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem3;call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem4, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem4;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem5, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem5; {1086#(and (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:05:55,448 INFO L273 TraceCheckUtils]: 12: Hoare triple {1086#(and (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1096#(and (bvsle (bvadd main_~i~0 (_ bv4294967295 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-18 21:05:55,449 INFO L273 TraceCheckUtils]: 13: Hoare triple {1096#(and (bvsle (bvadd main_~i~0 (_ bv4294967295 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (= (_ bv2 32) main_~i~0))} assume true; {1096#(and (bvsle (bvadd main_~i~0 (_ bv4294967295 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-18 21:05:55,464 INFO L273 TraceCheckUtils]: 14: Hoare triple {1096#(and (bvsle (bvadd main_~i~0 (_ bv4294967295 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (= (_ bv2 32) main_~i~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1103#(and (bvsle (_ bv1 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:05:55,465 INFO L273 TraceCheckUtils]: 15: Hoare triple {1103#(and (bvsle (_ bv1 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} ~i~0 := 1bv32; {1107#(and (bvsle (_ bv1 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:05:55,465 INFO L273 TraceCheckUtils]: 16: Hoare triple {1107#(and (bvsle (_ bv1 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {1107#(and (bvsle (_ bv1 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:05:55,466 INFO L273 TraceCheckUtils]: 17: Hoare triple {1107#(and (bvsle (_ bv1 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1054#false} is VALID [2018-11-18 21:05:55,466 INFO L273 TraceCheckUtils]: 18: Hoare triple {1054#false} ~i~0 := 1bv32; {1054#false} is VALID [2018-11-18 21:05:55,466 INFO L273 TraceCheckUtils]: 19: Hoare triple {1054#false} assume true; {1054#false} is VALID [2018-11-18 21:05:55,467 INFO L273 TraceCheckUtils]: 20: Hoare triple {1054#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1054#false} is VALID [2018-11-18 21:05:55,467 INFO L273 TraceCheckUtils]: 21: Hoare triple {1054#false} ~i~0 := 1bv32; {1054#false} is VALID [2018-11-18 21:05:55,467 INFO L273 TraceCheckUtils]: 22: Hoare triple {1054#false} assume true; {1054#false} is VALID [2018-11-18 21:05:55,467 INFO L273 TraceCheckUtils]: 23: Hoare triple {1054#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1054#false} is VALID [2018-11-18 21:05:55,468 INFO L273 TraceCheckUtils]: 24: Hoare triple {1054#false} ~i~0 := 0bv32; {1054#false} is VALID [2018-11-18 21:05:55,468 INFO L273 TraceCheckUtils]: 25: Hoare triple {1054#false} assume true; {1054#false} is VALID [2018-11-18 21:05:55,468 INFO L273 TraceCheckUtils]: 26: Hoare triple {1054#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {1054#false} is VALID [2018-11-18 21:05:55,468 INFO L273 TraceCheckUtils]: 27: Hoare triple {1054#false} assume !#t~short21;call #t~mem20 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := 0bv32 == #t~mem20; {1054#false} is VALID [2018-11-18 21:05:55,469 INFO L256 TraceCheckUtils]: 28: Hoare triple {1054#false} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {1054#false} is VALID [2018-11-18 21:05:55,469 INFO L273 TraceCheckUtils]: 29: Hoare triple {1054#false} ~cond := #in~cond; {1054#false} is VALID [2018-11-18 21:05:55,469 INFO L273 TraceCheckUtils]: 30: Hoare triple {1054#false} assume 0bv32 == ~cond; {1054#false} is VALID [2018-11-18 21:05:55,469 INFO L273 TraceCheckUtils]: 31: Hoare triple {1054#false} assume !false; {1054#false} is VALID [2018-11-18 21:05:55,473 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:05:55,473 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 21:05:56,961 INFO L273 TraceCheckUtils]: 31: Hoare triple {1054#false} assume !false; {1054#false} is VALID [2018-11-18 21:05:56,962 INFO L273 TraceCheckUtils]: 30: Hoare triple {1054#false} assume 0bv32 == ~cond; {1054#false} is VALID [2018-11-18 21:05:56,962 INFO L273 TraceCheckUtils]: 29: Hoare triple {1054#false} ~cond := #in~cond; {1054#false} is VALID [2018-11-18 21:05:56,962 INFO L256 TraceCheckUtils]: 28: Hoare triple {1054#false} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {1054#false} is VALID [2018-11-18 21:05:56,963 INFO L273 TraceCheckUtils]: 27: Hoare triple {1054#false} assume !#t~short21;call #t~mem20 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := 0bv32 == #t~mem20; {1054#false} is VALID [2018-11-18 21:05:56,963 INFO L273 TraceCheckUtils]: 26: Hoare triple {1054#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {1054#false} is VALID [2018-11-18 21:05:56,963 INFO L273 TraceCheckUtils]: 25: Hoare triple {1054#false} assume true; {1054#false} is VALID [2018-11-18 21:05:56,964 INFO L273 TraceCheckUtils]: 24: Hoare triple {1054#false} ~i~0 := 0bv32; {1054#false} is VALID [2018-11-18 21:05:56,964 INFO L273 TraceCheckUtils]: 23: Hoare triple {1054#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1054#false} is VALID [2018-11-18 21:05:56,964 INFO L273 TraceCheckUtils]: 22: Hoare triple {1054#false} assume true; {1054#false} is VALID [2018-11-18 21:05:56,964 INFO L273 TraceCheckUtils]: 21: Hoare triple {1054#false} ~i~0 := 1bv32; {1054#false} is VALID [2018-11-18 21:05:56,964 INFO L273 TraceCheckUtils]: 20: Hoare triple {1054#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1054#false} is VALID [2018-11-18 21:05:56,965 INFO L273 TraceCheckUtils]: 19: Hoare triple {1054#false} assume true; {1054#false} is VALID [2018-11-18 21:05:56,965 INFO L273 TraceCheckUtils]: 18: Hoare triple {1054#false} ~i~0 := 1bv32; {1054#false} is VALID [2018-11-18 21:05:56,980 INFO L273 TraceCheckUtils]: 17: Hoare triple {1198#(bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1054#false} is VALID [2018-11-18 21:05:56,980 INFO L273 TraceCheckUtils]: 16: Hoare triple {1198#(bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))} assume true; {1198#(bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))} is VALID [2018-11-18 21:05:56,981 INFO L273 TraceCheckUtils]: 15: Hoare triple {1205#(bvsle (_ bv1 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))} ~i~0 := 1bv32; {1198#(bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))} is VALID [2018-11-18 21:05:56,983 INFO L273 TraceCheckUtils]: 14: Hoare triple {1209#(or (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (bvsle (_ bv1 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1205#(bvsle (_ bv1 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))} is VALID [2018-11-18 21:05:56,983 INFO L273 TraceCheckUtils]: 13: Hoare triple {1209#(or (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (bvsle (_ bv1 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))))} assume true; {1209#(or (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (bvsle (_ bv1 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))))} is VALID [2018-11-18 21:05:56,998 INFO L273 TraceCheckUtils]: 12: Hoare triple {1216#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (bvsle (_ bv1 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1209#(or (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (bvsle (_ bv1 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))))} is VALID [2018-11-18 21:05:56,999 INFO L273 TraceCheckUtils]: 11: Hoare triple {1216#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (bvsle (_ bv1 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))))} call #t~mem3 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem3, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem3;call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem4, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem4;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem5, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem5; {1216#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (bvsle (_ bv1 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))))} is VALID [2018-11-18 21:05:57,000 INFO L273 TraceCheckUtils]: 10: Hoare triple {1216#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (bvsle (_ bv1 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {1216#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (bvsle (_ bv1 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))))} is VALID [2018-11-18 21:05:57,014 INFO L273 TraceCheckUtils]: 9: Hoare triple {1226#(forall ((~CELLCOUNT~0 (_ BitVec 32))) (or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (not (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))) (bvsle (_ bv1 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1216#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (bvsle (_ bv1 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))))} is VALID [2018-11-18 21:05:57,015 INFO L273 TraceCheckUtils]: 8: Hoare triple {1226#(forall ((~CELLCOUNT~0 (_ BitVec 32))) (or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (not (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))) (bvsle (_ bv1 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume true; {1226#(forall ((~CELLCOUNT~0 (_ BitVec 32))) (or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (not (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))) (bvsle (_ bv1 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:05:57,015 INFO L273 TraceCheckUtils]: 7: Hoare triple {1053#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1226#(forall ((~CELLCOUNT~0 (_ BitVec 32))) (or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (not (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))) (bvsle (_ bv1 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:05:57,016 INFO L273 TraceCheckUtils]: 6: Hoare triple {1053#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {1053#true} is VALID [2018-11-18 21:05:57,016 INFO L273 TraceCheckUtils]: 5: Hoare triple {1053#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1053#true} is VALID [2018-11-18 21:05:57,016 INFO L256 TraceCheckUtils]: 4: Hoare triple {1053#true} call #t~ret22 := main(); {1053#true} is VALID [2018-11-18 21:05:57,017 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1053#true} {1053#true} #141#return; {1053#true} is VALID [2018-11-18 21:05:57,017 INFO L273 TraceCheckUtils]: 2: Hoare triple {1053#true} assume true; {1053#true} is VALID [2018-11-18 21:05:57,017 INFO L273 TraceCheckUtils]: 1: Hoare triple {1053#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1053#true} is VALID [2018-11-18 21:05:57,017 INFO L256 TraceCheckUtils]: 0: Hoare triple {1053#true} call ULTIMATE.init(); {1053#true} is VALID [2018-11-18 21:05:57,021 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:05:57,027 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 21:05:57,028 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 12 [2018-11-18 21:05:57,028 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 32 [2018-11-18 21:05:57,029 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:05:57,029 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 12 states. [2018-11-18 21:05:57,349 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 43 edges. 43 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:05:57,350 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-18 21:05:57,350 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-18 21:05:57,350 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-11-18 21:05:57,350 INFO L87 Difference]: Start difference. First operand 51 states and 60 transitions. Second operand 12 states. [2018-11-18 21:05:59,217 WARN L180 SmtUtils]: Spent 168.00 ms on a formula simplification. DAG size of input: 14 DAG size of output: 11 [2018-11-18 21:05:59,632 WARN L180 SmtUtils]: Spent 178.00 ms on a formula simplification. DAG size of input: 11 DAG size of output: 8 [2018-11-18 21:06:01,153 WARN L180 SmtUtils]: Spent 230.00 ms on a formula simplification that was a NOOP. DAG size: 13 [2018-11-18 21:06:02,116 WARN L180 SmtUtils]: Spent 258.00 ms on a formula simplification that was a NOOP. DAG size: 13 [2018-11-18 21:06:29,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:06:29,232 INFO L93 Difference]: Finished difference Result 200 states and 255 transitions. [2018-11-18 21:06:29,232 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-18 21:06:29,232 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 32 [2018-11-18 21:06:29,232 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:06:29,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2018-11-18 21:06:29,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 236 transitions. [2018-11-18 21:06:29,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2018-11-18 21:06:29,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 236 transitions. [2018-11-18 21:06:29,245 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 14 states and 236 transitions. [2018-11-18 21:06:32,852 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 236 edges. 236 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:06:32,859 INFO L225 Difference]: With dead ends: 200 [2018-11-18 21:06:32,860 INFO L226 Difference]: Without dead ends: 165 [2018-11-18 21:06:32,861 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 69 GetRequests, 53 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 52 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=103, Invalid=203, Unknown=0, NotChecked=0, Total=306 [2018-11-18 21:06:32,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165 states. [2018-11-18 21:06:32,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165 to 96. [2018-11-18 21:06:32,969 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:06:32,969 INFO L82 GeneralOperation]: Start isEquivalent. First operand 165 states. Second operand 96 states. [2018-11-18 21:06:32,970 INFO L74 IsIncluded]: Start isIncluded. First operand 165 states. Second operand 96 states. [2018-11-18 21:06:32,970 INFO L87 Difference]: Start difference. First operand 165 states. Second operand 96 states. [2018-11-18 21:06:32,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:06:32,995 INFO L93 Difference]: Finished difference Result 165 states and 204 transitions. [2018-11-18 21:06:32,996 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 204 transitions. [2018-11-18 21:06:32,997 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:06:32,997 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:06:32,998 INFO L74 IsIncluded]: Start isIncluded. First operand 96 states. Second operand 165 states. [2018-11-18 21:06:32,998 INFO L87 Difference]: Start difference. First operand 96 states. Second operand 165 states. [2018-11-18 21:06:33,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:06:33,015 INFO L93 Difference]: Finished difference Result 165 states and 204 transitions. [2018-11-18 21:06:33,015 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 204 transitions. [2018-11-18 21:06:33,017 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:06:33,018 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:06:33,018 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:06:33,018 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:06:33,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 96 states. [2018-11-18 21:06:33,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96 states to 96 states and 114 transitions. [2018-11-18 21:06:33,024 INFO L78 Accepts]: Start accepts. Automaton has 96 states and 114 transitions. Word has length 32 [2018-11-18 21:06:33,024 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:06:33,024 INFO L480 AbstractCegarLoop]: Abstraction has 96 states and 114 transitions. [2018-11-18 21:06:33,024 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-18 21:06:33,025 INFO L276 IsEmpty]: Start isEmpty. Operand 96 states and 114 transitions. [2018-11-18 21:06:33,028 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-11-18 21:06:33,028 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:06:33,028 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:06:33,029 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:06:33,030 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:06:33,031 INFO L82 PathProgramCache]: Analyzing trace with hash 1408747134, now seen corresponding path program 1 times [2018-11-18 21:06:33,031 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:06:33,032 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:06:33,055 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:06:33,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:06:33,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:06:33,130 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:06:33,225 INFO L256 TraceCheckUtils]: 0: Hoare triple {1970#true} call ULTIMATE.init(); {1970#true} is VALID [2018-11-18 21:06:33,225 INFO L273 TraceCheckUtils]: 1: Hoare triple {1970#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1970#true} is VALID [2018-11-18 21:06:33,226 INFO L273 TraceCheckUtils]: 2: Hoare triple {1970#true} assume true; {1970#true} is VALID [2018-11-18 21:06:33,226 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1970#true} {1970#true} #141#return; {1970#true} is VALID [2018-11-18 21:06:33,226 INFO L256 TraceCheckUtils]: 4: Hoare triple {1970#true} call #t~ret22 := main(); {1970#true} is VALID [2018-11-18 21:06:33,226 INFO L273 TraceCheckUtils]: 5: Hoare triple {1970#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1970#true} is VALID [2018-11-18 21:06:33,227 INFO L273 TraceCheckUtils]: 6: Hoare triple {1970#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:33,227 INFO L273 TraceCheckUtils]: 7: Hoare triple {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:33,228 INFO L273 TraceCheckUtils]: 8: Hoare triple {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} assume true; {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:33,228 INFO L273 TraceCheckUtils]: 9: Hoare triple {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:33,229 INFO L273 TraceCheckUtils]: 10: Hoare triple {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:33,230 INFO L273 TraceCheckUtils]: 11: Hoare triple {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} call #t~mem3 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem3, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem3;call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem4, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem4;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem5, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem5; {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:33,230 INFO L273 TraceCheckUtils]: 12: Hoare triple {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:33,231 INFO L273 TraceCheckUtils]: 13: Hoare triple {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} assume true; {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:33,232 INFO L273 TraceCheckUtils]: 14: Hoare triple {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:33,233 INFO L273 TraceCheckUtils]: 15: Hoare triple {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 1bv32; {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:33,233 INFO L273 TraceCheckUtils]: 16: Hoare triple {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} assume true; {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:33,234 INFO L273 TraceCheckUtils]: 17: Hoare triple {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:33,235 INFO L273 TraceCheckUtils]: 18: Hoare triple {1993#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {1971#false} is VALID [2018-11-18 21:06:33,236 INFO L273 TraceCheckUtils]: 19: Hoare triple {1971#false} call #t~mem7 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem7, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem7;call #t~mem8 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem8, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem8;call #t~mem9 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem9, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem9; {1971#false} is VALID [2018-11-18 21:06:33,236 INFO L273 TraceCheckUtils]: 20: Hoare triple {1971#false} #t~post6 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post6);havoc #t~post6; {1971#false} is VALID [2018-11-18 21:06:33,236 INFO L273 TraceCheckUtils]: 21: Hoare triple {1971#false} assume true; {1971#false} is VALID [2018-11-18 21:06:33,237 INFO L273 TraceCheckUtils]: 22: Hoare triple {1971#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1971#false} is VALID [2018-11-18 21:06:33,237 INFO L273 TraceCheckUtils]: 23: Hoare triple {1971#false} ~i~0 := 1bv32; {1971#false} is VALID [2018-11-18 21:06:33,238 INFO L273 TraceCheckUtils]: 24: Hoare triple {1971#false} assume true; {1971#false} is VALID [2018-11-18 21:06:33,238 INFO L273 TraceCheckUtils]: 25: Hoare triple {1971#false} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1971#false} is VALID [2018-11-18 21:06:33,239 INFO L273 TraceCheckUtils]: 26: Hoare triple {1971#false} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {1971#false} is VALID [2018-11-18 21:06:33,239 INFO L273 TraceCheckUtils]: 27: Hoare triple {1971#false} call #t~mem11 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem11, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem11;call #t~mem12 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem12, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem12;call #t~mem13 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem13, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem13; {1971#false} is VALID [2018-11-18 21:06:33,240 INFO L273 TraceCheckUtils]: 28: Hoare triple {1971#false} #t~post10 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post10);havoc #t~post10; {1971#false} is VALID [2018-11-18 21:06:33,240 INFO L273 TraceCheckUtils]: 29: Hoare triple {1971#false} assume true; {1971#false} is VALID [2018-11-18 21:06:33,240 INFO L273 TraceCheckUtils]: 30: Hoare triple {1971#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1971#false} is VALID [2018-11-18 21:06:33,240 INFO L273 TraceCheckUtils]: 31: Hoare triple {1971#false} ~i~0 := 1bv32; {1971#false} is VALID [2018-11-18 21:06:33,241 INFO L273 TraceCheckUtils]: 32: Hoare triple {1971#false} assume true; {1971#false} is VALID [2018-11-18 21:06:33,241 INFO L273 TraceCheckUtils]: 33: Hoare triple {1971#false} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1971#false} is VALID [2018-11-18 21:06:33,241 INFO L273 TraceCheckUtils]: 34: Hoare triple {1971#false} assume ~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL1~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {1971#false} is VALID [2018-11-18 21:06:33,241 INFO L273 TraceCheckUtils]: 35: Hoare triple {1971#false} call #t~mem15 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem15, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem15;call #t~mem16 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem16, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem16;call #t~mem17 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem17, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem17; {1971#false} is VALID [2018-11-18 21:06:33,242 INFO L273 TraceCheckUtils]: 36: Hoare triple {1971#false} #t~post14 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post14);havoc #t~post14; {1971#false} is VALID [2018-11-18 21:06:33,242 INFO L273 TraceCheckUtils]: 37: Hoare triple {1971#false} assume true; {1971#false} is VALID [2018-11-18 21:06:33,242 INFO L273 TraceCheckUtils]: 38: Hoare triple {1971#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1971#false} is VALID [2018-11-18 21:06:33,242 INFO L273 TraceCheckUtils]: 39: Hoare triple {1971#false} ~i~0 := 0bv32; {1971#false} is VALID [2018-11-18 21:06:33,243 INFO L273 TraceCheckUtils]: 40: Hoare triple {1971#false} assume true; {1971#false} is VALID [2018-11-18 21:06:33,243 INFO L273 TraceCheckUtils]: 41: Hoare triple {1971#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {1971#false} is VALID [2018-11-18 21:06:33,243 INFO L273 TraceCheckUtils]: 42: Hoare triple {1971#false} assume !#t~short21;call #t~mem20 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := 0bv32 == #t~mem20; {1971#false} is VALID [2018-11-18 21:06:33,243 INFO L256 TraceCheckUtils]: 43: Hoare triple {1971#false} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {1971#false} is VALID [2018-11-18 21:06:33,244 INFO L273 TraceCheckUtils]: 44: Hoare triple {1971#false} ~cond := #in~cond; {1971#false} is VALID [2018-11-18 21:06:33,244 INFO L273 TraceCheckUtils]: 45: Hoare triple {1971#false} assume 0bv32 == ~cond; {1971#false} is VALID [2018-11-18 21:06:33,244 INFO L273 TraceCheckUtils]: 46: Hoare triple {1971#false} assume !false; {1971#false} is VALID [2018-11-18 21:06:33,247 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-18 21:06:33,247 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-18 21:06:33,251 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 21:06:33,251 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 21:06:33,251 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2018-11-18 21:06:33,252 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:06:33,252 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2018-11-18 21:06:33,436 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 44 edges. 44 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:06:33,437 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 21:06:33,437 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 21:06:33,437 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 21:06:33,437 INFO L87 Difference]: Start difference. First operand 96 states and 114 transitions. Second operand 3 states. [2018-11-18 21:06:33,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:06:33,879 INFO L93 Difference]: Finished difference Result 164 states and 194 transitions. [2018-11-18 21:06:33,879 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 21:06:33,879 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2018-11-18 21:06:33,880 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:06:33,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-18 21:06:33,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 90 transitions. [2018-11-18 21:06:33,882 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-18 21:06:33,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 90 transitions. [2018-11-18 21:06:33,884 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states and 90 transitions. [2018-11-18 21:06:34,198 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 90 edges. 90 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:06:34,201 INFO L225 Difference]: With dead ends: 164 [2018-11-18 21:06:34,201 INFO L226 Difference]: Without dead ends: 96 [2018-11-18 21:06:34,202 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 45 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 21:06:34,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-11-18 21:06:34,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 96. [2018-11-18 21:06:34,339 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:06:34,339 INFO L82 GeneralOperation]: Start isEquivalent. First operand 96 states. Second operand 96 states. [2018-11-18 21:06:34,339 INFO L74 IsIncluded]: Start isIncluded. First operand 96 states. Second operand 96 states. [2018-11-18 21:06:34,339 INFO L87 Difference]: Start difference. First operand 96 states. Second operand 96 states. [2018-11-18 21:06:34,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:06:34,344 INFO L93 Difference]: Finished difference Result 96 states and 111 transitions. [2018-11-18 21:06:34,344 INFO L276 IsEmpty]: Start isEmpty. Operand 96 states and 111 transitions. [2018-11-18 21:06:34,344 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:06:34,344 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:06:34,345 INFO L74 IsIncluded]: Start isIncluded. First operand 96 states. Second operand 96 states. [2018-11-18 21:06:34,345 INFO L87 Difference]: Start difference. First operand 96 states. Second operand 96 states. [2018-11-18 21:06:34,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:06:34,348 INFO L93 Difference]: Finished difference Result 96 states and 111 transitions. [2018-11-18 21:06:34,349 INFO L276 IsEmpty]: Start isEmpty. Operand 96 states and 111 transitions. [2018-11-18 21:06:34,349 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:06:34,349 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:06:34,349 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:06:34,349 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:06:34,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 96 states. [2018-11-18 21:06:34,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96 states to 96 states and 111 transitions. [2018-11-18 21:06:34,353 INFO L78 Accepts]: Start accepts. Automaton has 96 states and 111 transitions. Word has length 47 [2018-11-18 21:06:34,353 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:06:34,353 INFO L480 AbstractCegarLoop]: Abstraction has 96 states and 111 transitions. [2018-11-18 21:06:34,353 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 21:06:34,353 INFO L276 IsEmpty]: Start isEmpty. Operand 96 states and 111 transitions. [2018-11-18 21:06:34,354 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-11-18 21:06:34,355 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:06:34,355 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:06:34,355 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:06:34,355 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:06:34,355 INFO L82 PathProgramCache]: Analyzing trace with hash 22543740, now seen corresponding path program 1 times [2018-11-18 21:06:34,356 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:06:34,356 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:06:34,386 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:06:34,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:06:34,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:06:34,470 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:06:34,565 INFO L256 TraceCheckUtils]: 0: Hoare triple {2634#true} call ULTIMATE.init(); {2634#true} is VALID [2018-11-18 21:06:34,566 INFO L273 TraceCheckUtils]: 1: Hoare triple {2634#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {2634#true} is VALID [2018-11-18 21:06:34,566 INFO L273 TraceCheckUtils]: 2: Hoare triple {2634#true} assume true; {2634#true} is VALID [2018-11-18 21:06:34,566 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2634#true} {2634#true} #141#return; {2634#true} is VALID [2018-11-18 21:06:34,566 INFO L256 TraceCheckUtils]: 4: Hoare triple {2634#true} call #t~ret22 := main(); {2634#true} is VALID [2018-11-18 21:06:34,567 INFO L273 TraceCheckUtils]: 5: Hoare triple {2634#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {2634#true} is VALID [2018-11-18 21:06:34,569 INFO L273 TraceCheckUtils]: 6: Hoare triple {2634#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,569 INFO L273 TraceCheckUtils]: 7: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,578 INFO L273 TraceCheckUtils]: 8: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} assume true; {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,579 INFO L273 TraceCheckUtils]: 9: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,581 INFO L273 TraceCheckUtils]: 10: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,581 INFO L273 TraceCheckUtils]: 11: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} call #t~mem3 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem3, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem3;call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem4, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem4;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem5, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem5; {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,582 INFO L273 TraceCheckUtils]: 12: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,582 INFO L273 TraceCheckUtils]: 13: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} assume true; {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,583 INFO L273 TraceCheckUtils]: 14: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,583 INFO L273 TraceCheckUtils]: 15: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 1bv32; {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,591 INFO L273 TraceCheckUtils]: 16: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} assume true; {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,592 INFO L273 TraceCheckUtils]: 17: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,592 INFO L273 TraceCheckUtils]: 18: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,593 INFO L273 TraceCheckUtils]: 19: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} call #t~mem7 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem7, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem7;call #t~mem8 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem8, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem8;call #t~mem9 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem9, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem9; {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,593 INFO L273 TraceCheckUtils]: 20: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} #t~post6 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post6);havoc #t~post6; {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,602 INFO L273 TraceCheckUtils]: 21: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} assume true; {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,618 INFO L273 TraceCheckUtils]: 22: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,633 INFO L273 TraceCheckUtils]: 23: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 1bv32; {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,635 INFO L273 TraceCheckUtils]: 24: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} assume true; {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,635 INFO L273 TraceCheckUtils]: 25: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,636 INFO L273 TraceCheckUtils]: 26: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,637 INFO L273 TraceCheckUtils]: 27: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} call #t~mem11 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem11, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem11;call #t~mem12 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem12, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem12;call #t~mem13 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem13, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem13; {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,638 INFO L273 TraceCheckUtils]: 28: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} #t~post10 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post10);havoc #t~post10; {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,642 INFO L273 TraceCheckUtils]: 29: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} assume true; {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,642 INFO L273 TraceCheckUtils]: 30: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,644 INFO L273 TraceCheckUtils]: 31: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 1bv32; {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,644 INFO L273 TraceCheckUtils]: 32: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} assume true; {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,647 INFO L273 TraceCheckUtils]: 33: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:34,648 INFO L273 TraceCheckUtils]: 34: Hoare triple {2657#(and (= (_ bv1 32) main_~CCCELVOL1~0) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL1~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {2635#false} is VALID [2018-11-18 21:06:34,648 INFO L273 TraceCheckUtils]: 35: Hoare triple {2635#false} call #t~mem15 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem15, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem15;call #t~mem16 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem16, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem16;call #t~mem17 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem17, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem17; {2635#false} is VALID [2018-11-18 21:06:34,648 INFO L273 TraceCheckUtils]: 36: Hoare triple {2635#false} #t~post14 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post14);havoc #t~post14; {2635#false} is VALID [2018-11-18 21:06:34,649 INFO L273 TraceCheckUtils]: 37: Hoare triple {2635#false} assume true; {2635#false} is VALID [2018-11-18 21:06:34,649 INFO L273 TraceCheckUtils]: 38: Hoare triple {2635#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {2635#false} is VALID [2018-11-18 21:06:34,649 INFO L273 TraceCheckUtils]: 39: Hoare triple {2635#false} ~i~0 := 0bv32; {2635#false} is VALID [2018-11-18 21:06:34,649 INFO L273 TraceCheckUtils]: 40: Hoare triple {2635#false} assume true; {2635#false} is VALID [2018-11-18 21:06:34,650 INFO L273 TraceCheckUtils]: 41: Hoare triple {2635#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {2635#false} is VALID [2018-11-18 21:06:34,650 INFO L273 TraceCheckUtils]: 42: Hoare triple {2635#false} assume !#t~short21;call #t~mem20 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := 0bv32 == #t~mem20; {2635#false} is VALID [2018-11-18 21:06:34,650 INFO L256 TraceCheckUtils]: 43: Hoare triple {2635#false} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {2635#false} is VALID [2018-11-18 21:06:34,651 INFO L273 TraceCheckUtils]: 44: Hoare triple {2635#false} ~cond := #in~cond; {2635#false} is VALID [2018-11-18 21:06:34,651 INFO L273 TraceCheckUtils]: 45: Hoare triple {2635#false} assume 0bv32 == ~cond; {2635#false} is VALID [2018-11-18 21:06:34,651 INFO L273 TraceCheckUtils]: 46: Hoare triple {2635#false} assume !false; {2635#false} is VALID [2018-11-18 21:06:34,655 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-18 21:06:34,655 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-18 21:06:34,658 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 21:06:34,659 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 21:06:34,659 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2018-11-18 21:06:34,659 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:06:34,660 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2018-11-18 21:06:34,835 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 44 edges. 44 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:06:34,835 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 21:06:34,835 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 21:06:34,836 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 21:06:34,836 INFO L87 Difference]: Start difference. First operand 96 states and 111 transitions. Second operand 3 states. [2018-11-18 21:06:35,248 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:06:35,249 INFO L93 Difference]: Finished difference Result 123 states and 141 transitions. [2018-11-18 21:06:35,249 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 21:06:35,249 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2018-11-18 21:06:35,249 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:06:35,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-18 21:06:35,251 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 73 transitions. [2018-11-18 21:06:35,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-18 21:06:35,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 73 transitions. [2018-11-18 21:06:35,253 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states and 73 transitions. [2018-11-18 21:06:35,501 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 73 edges. 73 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:06:35,503 INFO L225 Difference]: With dead ends: 123 [2018-11-18 21:06:35,503 INFO L226 Difference]: Without dead ends: 96 [2018-11-18 21:06:35,504 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 45 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 21:06:35,504 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-11-18 21:06:35,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 96. [2018-11-18 21:06:35,671 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:06:35,671 INFO L82 GeneralOperation]: Start isEquivalent. First operand 96 states. Second operand 96 states. [2018-11-18 21:06:35,671 INFO L74 IsIncluded]: Start isIncluded. First operand 96 states. Second operand 96 states. [2018-11-18 21:06:35,671 INFO L87 Difference]: Start difference. First operand 96 states. Second operand 96 states. [2018-11-18 21:06:35,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:06:35,676 INFO L93 Difference]: Finished difference Result 96 states and 109 transitions. [2018-11-18 21:06:35,676 INFO L276 IsEmpty]: Start isEmpty. Operand 96 states and 109 transitions. [2018-11-18 21:06:35,677 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:06:35,677 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:06:35,677 INFO L74 IsIncluded]: Start isIncluded. First operand 96 states. Second operand 96 states. [2018-11-18 21:06:35,677 INFO L87 Difference]: Start difference. First operand 96 states. Second operand 96 states. [2018-11-18 21:06:35,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:06:35,681 INFO L93 Difference]: Finished difference Result 96 states and 109 transitions. [2018-11-18 21:06:35,681 INFO L276 IsEmpty]: Start isEmpty. Operand 96 states and 109 transitions. [2018-11-18 21:06:35,681 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:06:35,681 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:06:35,681 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:06:35,682 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:06:35,682 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 96 states. [2018-11-18 21:06:35,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96 states to 96 states and 109 transitions. [2018-11-18 21:06:35,687 INFO L78 Accepts]: Start accepts. Automaton has 96 states and 109 transitions. Word has length 47 [2018-11-18 21:06:35,687 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:06:35,687 INFO L480 AbstractCegarLoop]: Abstraction has 96 states and 109 transitions. [2018-11-18 21:06:35,687 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 21:06:35,688 INFO L276 IsEmpty]: Start isEmpty. Operand 96 states and 109 transitions. [2018-11-18 21:06:35,688 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-11-18 21:06:35,688 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:06:35,689 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:06:35,689 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:06:35,689 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:06:35,689 INFO L82 PathProgramCache]: Analyzing trace with hash -564262274, now seen corresponding path program 1 times [2018-11-18 21:06:35,690 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:06:35,690 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:06:35,711 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:06:35,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:06:35,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:06:35,867 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:06:36,000 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-18 21:06:36,028 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-18 21:06:36,032 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:06:36,035 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:36,052 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:36,053 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:28, output treesize:24 [2018-11-18 21:06:36,104 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:06:36,106 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 95 treesize of output 142 [2018-11-18 21:06:36,152 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:36,153 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:36,154 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:36,173 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 67 [2018-11-18 21:06:36,228 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:36,229 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:36,230 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:36,243 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 47 [2018-11-18 21:06:36,253 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:36,257 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 23 [2018-11-18 21:06:36,260 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-18 21:06:36,271 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:36,274 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:36,278 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:36,289 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:36,290 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 1 variables, input treesize:101, output treesize:14 [2018-11-18 21:06:36,379 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 26 [2018-11-18 21:06:36,390 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:36,395 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 41 [2018-11-18 21:06:36,397 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:06:36,409 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:36,432 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:36,432 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:42, output treesize:26 [2018-11-18 21:06:36,444 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-18 21:06:36,466 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:06:36,467 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 79 treesize of output 110 [2018-11-18 21:06:36,560 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:36,565 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 50 treesize of output 44 [2018-11-18 21:06:36,619 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:36,620 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:36,621 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:36,632 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 49 [2018-11-18 21:06:36,657 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:36,661 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 25 [2018-11-18 21:06:36,664 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-18 21:06:36,673 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:36,677 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:36,680 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:36,691 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:36,692 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 1 variables, input treesize:85, output treesize:16 [2018-11-18 21:06:36,778 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 26 [2018-11-18 21:06:36,792 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:36,797 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 41 [2018-11-18 21:06:36,800 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:06:36,814 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:36,842 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:36,843 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:42, output treesize:26 [2018-11-18 21:06:36,855 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-18 21:06:36,881 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:06:36,883 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 79 treesize of output 110 [2018-11-18 21:06:36,930 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:36,935 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 50 treesize of output 44 [2018-11-18 21:06:37,011 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:37,031 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:37,035 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:37,046 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 49 [2018-11-18 21:06:37,055 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:37,060 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 25 [2018-11-18 21:06:37,063 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-18 21:06:37,071 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:37,075 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:37,080 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:37,091 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:37,091 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 1 variables, input treesize:85, output treesize:16 [2018-11-18 21:06:37,183 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 26 [2018-11-18 21:06:37,194 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:37,196 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:37,198 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 54 [2018-11-18 21:06:37,210 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:06:37,220 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:37,242 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:37,243 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:42, output treesize:38 [2018-11-18 21:06:37,306 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:06:37,307 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 88 treesize of output 117 [2018-11-18 21:06:37,410 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:37,411 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:37,412 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:37,419 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:37,421 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 73 [2018-11-18 21:06:37,471 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:37,472 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:37,473 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:37,475 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:37,477 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:37,478 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:37,487 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:37,498 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 88 [2018-11-18 21:06:37,513 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:37,514 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:37,524 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 62 [2018-11-18 21:06:37,557 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-18 21:06:37,696 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:37,703 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:37,712 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:37,725 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:37,726 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 1 variables, input treesize:94, output treesize:25 [2018-11-18 21:06:37,892 INFO L256 TraceCheckUtils]: 0: Hoare triple {3247#true} call ULTIMATE.init(); {3247#true} is VALID [2018-11-18 21:06:37,893 INFO L273 TraceCheckUtils]: 1: Hoare triple {3247#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {3247#true} is VALID [2018-11-18 21:06:37,893 INFO L273 TraceCheckUtils]: 2: Hoare triple {3247#true} assume true; {3247#true} is VALID [2018-11-18 21:06:37,893 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {3247#true} {3247#true} #141#return; {3247#true} is VALID [2018-11-18 21:06:37,894 INFO L256 TraceCheckUtils]: 4: Hoare triple {3247#true} call #t~ret22 := main(); {3247#true} is VALID [2018-11-18 21:06:37,894 INFO L273 TraceCheckUtils]: 5: Hoare triple {3247#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {3247#true} is VALID [2018-11-18 21:06:37,900 INFO L273 TraceCheckUtils]: 6: Hoare triple {3247#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {3270#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:37,901 INFO L273 TraceCheckUtils]: 7: Hoare triple {3270#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {3274#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:06:37,902 INFO L273 TraceCheckUtils]: 8: Hoare triple {3274#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {3274#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:06:37,902 INFO L273 TraceCheckUtils]: 9: Hoare triple {3274#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3274#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:06:37,904 INFO L273 TraceCheckUtils]: 10: Hoare triple {3274#(and (= (_ bv5 32) main_~CCCELVOL4~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:06:37,904 INFO L273 TraceCheckUtils]: 11: Hoare triple {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call #t~mem3 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem3, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem3;call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem4, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem4;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem5, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem5; {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:37,905 INFO L273 TraceCheckUtils]: 12: Hoare triple {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:37,906 INFO L273 TraceCheckUtils]: 13: Hoare triple {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume true; {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:37,907 INFO L273 TraceCheckUtils]: 14: Hoare triple {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:37,908 INFO L273 TraceCheckUtils]: 15: Hoare triple {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 1bv32; {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:06:37,910 INFO L273 TraceCheckUtils]: 16: Hoare triple {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:06:37,911 INFO L273 TraceCheckUtils]: 17: Hoare triple {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:06:37,916 INFO L273 TraceCheckUtils]: 18: Hoare triple {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:06:37,920 INFO L273 TraceCheckUtils]: 19: Hoare triple {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call #t~mem7 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem7, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem7;call #t~mem8 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem8, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem8;call #t~mem9 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem9, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem9; {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:37,925 INFO L273 TraceCheckUtils]: 20: Hoare triple {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post6 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post6);havoc #t~post6; {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:37,934 INFO L273 TraceCheckUtils]: 21: Hoare triple {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume true; {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:37,935 INFO L273 TraceCheckUtils]: 22: Hoare triple {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:37,936 INFO L273 TraceCheckUtils]: 23: Hoare triple {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 1bv32; {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:06:37,936 INFO L273 TraceCheckUtils]: 24: Hoare triple {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:06:37,937 INFO L273 TraceCheckUtils]: 25: Hoare triple {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:06:37,940 INFO L273 TraceCheckUtils]: 26: Hoare triple {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:06:37,941 INFO L273 TraceCheckUtils]: 27: Hoare triple {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call #t~mem11 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem11, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem11;call #t~mem12 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem12, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem12;call #t~mem13 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem13, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem13; {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:37,942 INFO L273 TraceCheckUtils]: 28: Hoare triple {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post10 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post10);havoc #t~post10; {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:37,943 INFO L273 TraceCheckUtils]: 29: Hoare triple {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume true; {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:37,943 INFO L273 TraceCheckUtils]: 30: Hoare triple {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:37,944 INFO L273 TraceCheckUtils]: 31: Hoare triple {3288#(and (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 1bv32; {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:06:37,944 INFO L273 TraceCheckUtils]: 32: Hoare triple {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:06:37,945 INFO L273 TraceCheckUtils]: 33: Hoare triple {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:06:37,951 INFO L273 TraceCheckUtils]: 34: Hoare triple {3284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {3358#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:06:37,952 INFO L273 TraceCheckUtils]: 35: Hoare triple {3358#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call #t~mem15 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem15, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem15;call #t~mem16 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem16, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem16;call #t~mem17 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem17, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem17; {3362#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:37,953 INFO L273 TraceCheckUtils]: 36: Hoare triple {3362#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post14 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post14);havoc #t~post14; {3362#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:37,953 INFO L273 TraceCheckUtils]: 37: Hoare triple {3362#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume true; {3362#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:37,954 INFO L273 TraceCheckUtils]: 38: Hoare triple {3362#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3362#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:37,955 INFO L273 TraceCheckUtils]: 39: Hoare triple {3362#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 0bv32; {3375#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:37,956 INFO L273 TraceCheckUtils]: 40: Hoare triple {3375#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume true; {3375#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:37,959 INFO L273 TraceCheckUtils]: 41: Hoare triple {3375#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {3382#|main_#t~short21|} is VALID [2018-11-18 21:06:37,960 INFO L273 TraceCheckUtils]: 42: Hoare triple {3382#|main_#t~short21|} assume !#t~short21;call #t~mem20 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := 0bv32 == #t~mem20; {3248#false} is VALID [2018-11-18 21:06:37,960 INFO L256 TraceCheckUtils]: 43: Hoare triple {3248#false} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {3248#false} is VALID [2018-11-18 21:06:37,960 INFO L273 TraceCheckUtils]: 44: Hoare triple {3248#false} ~cond := #in~cond; {3248#false} is VALID [2018-11-18 21:06:37,960 INFO L273 TraceCheckUtils]: 45: Hoare triple {3248#false} assume 0bv32 == ~cond; {3248#false} is VALID [2018-11-18 21:06:37,961 INFO L273 TraceCheckUtils]: 46: Hoare triple {3248#false} assume !false; {3248#false} is VALID [2018-11-18 21:06:37,969 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:06:37,969 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 21:06:38,370 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 13 [2018-11-18 21:06:38,470 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 3 [2018-11-18 21:06:38,495 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-18 21:06:38,521 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 3 xjuncts. [2018-11-18 21:06:38,557 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 3 xjuncts. [2018-11-18 21:06:38,560 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:15, output treesize:31 [2018-11-18 21:06:38,577 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-18 21:06:38,729 INFO L273 TraceCheckUtils]: 46: Hoare triple {3248#false} assume !false; {3248#false} is VALID [2018-11-18 21:06:38,729 INFO L273 TraceCheckUtils]: 45: Hoare triple {3248#false} assume 0bv32 == ~cond; {3248#false} is VALID [2018-11-18 21:06:38,729 INFO L273 TraceCheckUtils]: 44: Hoare triple {3248#false} ~cond := #in~cond; {3248#false} is VALID [2018-11-18 21:06:38,730 INFO L256 TraceCheckUtils]: 43: Hoare triple {3248#false} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {3248#false} is VALID [2018-11-18 21:06:38,730 INFO L273 TraceCheckUtils]: 42: Hoare triple {3382#|main_#t~short21|} assume !#t~short21;call #t~mem20 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := 0bv32 == #t~mem20; {3248#false} is VALID [2018-11-18 21:06:38,731 INFO L273 TraceCheckUtils]: 41: Hoare triple {3413#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {3382#|main_#t~short21|} is VALID [2018-11-18 21:06:38,732 INFO L273 TraceCheckUtils]: 40: Hoare triple {3413#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume true; {3413#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,734 INFO L273 TraceCheckUtils]: 39: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} ~i~0 := 0bv32; {3413#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,735 INFO L273 TraceCheckUtils]: 38: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,735 INFO L273 TraceCheckUtils]: 37: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume true; {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,736 INFO L273 TraceCheckUtils]: 36: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post14 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post14);havoc #t~post14; {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,737 INFO L273 TraceCheckUtils]: 35: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} call #t~mem15 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem15, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem15;call #t~mem16 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem16, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem16;call #t~mem17 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem17, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem17; {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,748 INFO L273 TraceCheckUtils]: 34: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,749 INFO L273 TraceCheckUtils]: 33: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,749 INFO L273 TraceCheckUtils]: 32: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume true; {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,750 INFO L273 TraceCheckUtils]: 31: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} ~i~0 := 1bv32; {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,750 INFO L273 TraceCheckUtils]: 30: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,751 INFO L273 TraceCheckUtils]: 29: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume true; {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,752 INFO L273 TraceCheckUtils]: 28: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post10 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post10);havoc #t~post10; {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,753 INFO L273 TraceCheckUtils]: 27: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} call #t~mem11 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem11, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem11;call #t~mem12 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem12, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem12;call #t~mem13 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem13, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem13; {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,765 INFO L273 TraceCheckUtils]: 26: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,766 INFO L273 TraceCheckUtils]: 25: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,766 INFO L273 TraceCheckUtils]: 24: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume true; {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,767 INFO L273 TraceCheckUtils]: 23: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} ~i~0 := 1bv32; {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,767 INFO L273 TraceCheckUtils]: 22: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,767 INFO L273 TraceCheckUtils]: 21: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume true; {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,768 INFO L273 TraceCheckUtils]: 20: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post6 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post6);havoc #t~post6; {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,770 INFO L273 TraceCheckUtils]: 19: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} call #t~mem7 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem7, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem7;call #t~mem8 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem8, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem8;call #t~mem9 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem9, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem9; {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,781 INFO L273 TraceCheckUtils]: 18: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,782 INFO L273 TraceCheckUtils]: 17: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,782 INFO L273 TraceCheckUtils]: 16: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume true; {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,782 INFO L273 TraceCheckUtils]: 15: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} ~i~0 := 1bv32; {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,783 INFO L273 TraceCheckUtils]: 14: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,783 INFO L273 TraceCheckUtils]: 13: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume true; {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,783 INFO L273 TraceCheckUtils]: 12: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,784 INFO L273 TraceCheckUtils]: 11: Hoare triple {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} call #t~mem3 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem3, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem3;call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem4, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem4;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem5, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem5; {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,804 INFO L273 TraceCheckUtils]: 10: Hoare triple {3508#(and (or (forall ((v_arrayElimCell_19 (_ BitVec 32))) (bvsge v_arrayElimCell_19 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (bvsge main_~CCCELVOL4~0 main_~MINVAL~0))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {3420#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,805 INFO L273 TraceCheckUtils]: 9: Hoare triple {3508#(and (or (forall ((v_arrayElimCell_19 (_ BitVec 32))) (bvsge v_arrayElimCell_19 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (bvsge main_~CCCELVOL4~0 main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3508#(and (or (forall ((v_arrayElimCell_19 (_ BitVec 32))) (bvsge v_arrayElimCell_19 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (bvsge main_~CCCELVOL4~0 main_~MINVAL~0))} is VALID [2018-11-18 21:06:38,805 INFO L273 TraceCheckUtils]: 8: Hoare triple {3508#(and (or (forall ((v_arrayElimCell_19 (_ BitVec 32))) (bvsge v_arrayElimCell_19 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (bvsge main_~CCCELVOL4~0 main_~MINVAL~0))} assume true; {3508#(and (or (forall ((v_arrayElimCell_19 (_ BitVec 32))) (bvsge v_arrayElimCell_19 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (bvsge main_~CCCELVOL4~0 main_~MINVAL~0))} is VALID [2018-11-18 21:06:38,806 INFO L273 TraceCheckUtils]: 7: Hoare triple {3518#(bvsge main_~CCCELVOL4~0 main_~MINVAL~0)} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {3508#(and (or (forall ((v_arrayElimCell_19 (_ BitVec 32))) (bvsge v_arrayElimCell_19 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (bvsge main_~CCCELVOL4~0 main_~MINVAL~0))} is VALID [2018-11-18 21:06:38,807 INFO L273 TraceCheckUtils]: 6: Hoare triple {3247#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {3518#(bvsge main_~CCCELVOL4~0 main_~MINVAL~0)} is VALID [2018-11-18 21:06:38,807 INFO L273 TraceCheckUtils]: 5: Hoare triple {3247#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {3247#true} is VALID [2018-11-18 21:06:38,807 INFO L256 TraceCheckUtils]: 4: Hoare triple {3247#true} call #t~ret22 := main(); {3247#true} is VALID [2018-11-18 21:06:38,808 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {3247#true} {3247#true} #141#return; {3247#true} is VALID [2018-11-18 21:06:38,808 INFO L273 TraceCheckUtils]: 2: Hoare triple {3247#true} assume true; {3247#true} is VALID [2018-11-18 21:06:38,808 INFO L273 TraceCheckUtils]: 1: Hoare triple {3247#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {3247#true} is VALID [2018-11-18 21:06:38,808 INFO L256 TraceCheckUtils]: 0: Hoare triple {3247#true} call ULTIMATE.init(); {3247#true} is VALID [2018-11-18 21:06:38,812 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-18 21:06:38,814 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 21:06:38,814 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 7] total 14 [2018-11-18 21:06:38,815 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 47 [2018-11-18 21:06:38,815 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:06:38,815 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 14 states. [2018-11-18 21:06:39,219 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 80 edges. 80 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:06:39,219 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-18 21:06:39,220 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-18 21:06:39,220 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=139, Unknown=0, NotChecked=0, Total=182 [2018-11-18 21:06:39,220 INFO L87 Difference]: Start difference. First operand 96 states and 109 transitions. Second operand 14 states. [2018-11-18 21:06:43,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:06:43,692 INFO L93 Difference]: Finished difference Result 199 states and 229 transitions. [2018-11-18 21:06:43,693 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-18 21:06:43,693 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 47 [2018-11-18 21:06:43,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:06:43,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2018-11-18 21:06:43,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 138 transitions. [2018-11-18 21:06:43,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2018-11-18 21:06:43,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 138 transitions. [2018-11-18 21:06:43,702 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 13 states and 138 transitions. [2018-11-18 21:06:44,238 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 138 edges. 138 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:06:44,241 INFO L225 Difference]: With dead ends: 199 [2018-11-18 21:06:44,241 INFO L226 Difference]: Without dead ends: 114 [2018-11-18 21:06:44,242 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 102 GetRequests, 71 SyntacticMatches, 10 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 135 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=145, Invalid=361, Unknown=0, NotChecked=0, Total=506 [2018-11-18 21:06:44,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-11-18 21:06:44,418 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 99. [2018-11-18 21:06:44,418 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:06:44,418 INFO L82 GeneralOperation]: Start isEquivalent. First operand 114 states. Second operand 99 states. [2018-11-18 21:06:44,419 INFO L74 IsIncluded]: Start isIncluded. First operand 114 states. Second operand 99 states. [2018-11-18 21:06:44,419 INFO L87 Difference]: Start difference. First operand 114 states. Second operand 99 states. [2018-11-18 21:06:44,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:06:44,423 INFO L93 Difference]: Finished difference Result 114 states and 129 transitions. [2018-11-18 21:06:44,423 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 129 transitions. [2018-11-18 21:06:44,425 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:06:44,425 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:06:44,426 INFO L74 IsIncluded]: Start isIncluded. First operand 99 states. Second operand 114 states. [2018-11-18 21:06:44,426 INFO L87 Difference]: Start difference. First operand 99 states. Second operand 114 states. [2018-11-18 21:06:44,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:06:44,433 INFO L93 Difference]: Finished difference Result 114 states and 129 transitions. [2018-11-18 21:06:44,433 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 129 transitions. [2018-11-18 21:06:44,434 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:06:44,434 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:06:44,434 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:06:44,434 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:06:44,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2018-11-18 21:06:44,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 110 transitions. [2018-11-18 21:06:44,438 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 110 transitions. Word has length 47 [2018-11-18 21:06:44,456 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:06:44,456 INFO L480 AbstractCegarLoop]: Abstraction has 99 states and 110 transitions. [2018-11-18 21:06:44,456 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-18 21:06:44,456 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 110 transitions. [2018-11-18 21:06:44,457 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-11-18 21:06:44,457 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:06:44,457 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:06:44,457 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:06:44,458 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:06:44,458 INFO L82 PathProgramCache]: Analyzing trace with hash 1010844297, now seen corresponding path program 1 times [2018-11-18 21:06:44,458 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:06:44,459 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:06:44,485 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:06:44,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:06:44,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:06:44,639 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:06:44,810 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-18 21:06:44,814 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-18 21:06:44,816 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:06:44,820 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:44,836 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:44,836 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:28, output treesize:24 [2018-11-18 21:06:45,053 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:06:45,054 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 79 treesize of output 110 [2018-11-18 21:06:45,183 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:45,197 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:45,218 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:45,287 INFO L303 Elim1Store]: Index analysis took 145 ms [2018-11-18 21:06:45,288 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 50 treesize of output 65 [2018-11-18 21:06:45,318 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:45,319 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:45,320 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:45,332 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 55 [2018-11-18 21:06:45,337 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:45,343 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 29 [2018-11-18 21:06:45,347 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-18 21:06:45,357 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:45,361 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:45,365 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:45,375 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:45,376 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 1 variables, input treesize:85, output treesize:18 [2018-11-18 21:06:45,496 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 21 [2018-11-18 21:06:45,512 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:45,515 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 33 [2018-11-18 21:06:45,521 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:06:45,553 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:45,581 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:45,581 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:32, output treesize:16 [2018-11-18 21:06:45,592 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-18 21:06:45,655 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:06:45,656 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 137 treesize of output 226 [2018-11-18 21:06:45,700 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:45,702 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:45,733 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 2 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 90 treesize of output 95 [2018-11-18 21:06:45,778 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:45,785 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:45,941 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 2 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 43 treesize of output 63 [2018-11-18 21:06:45,950 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:45,958 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 33 [2018-11-18 21:06:45,960 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-18 21:06:45,970 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:45,974 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:45,978 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:45,989 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:45,989 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 2 variables, input treesize:143, output treesize:16 [2018-11-18 21:06:46,043 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 21 [2018-11-18 21:06:46,051 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:46,053 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:46,055 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 43 [2018-11-18 21:06:46,078 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:06:46,094 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:46,114 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:46,114 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:32, output treesize:28 [2018-11-18 21:06:46,219 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:06:46,220 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 151 treesize of output 238 [2018-11-18 21:06:46,384 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 33 DAG size of output: 32 [2018-11-18 21:06:46,391 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:46,392 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:46,393 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:46,395 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:46,405 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:46,415 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:46,434 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 98 treesize of output 157 [2018-11-18 21:06:46,515 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:46,518 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:46,522 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:46,524 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:46,526 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:46,528 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:47,198 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 55 treesize of output 123 [2018-11-18 21:06:47,211 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:47,213 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:06:47,227 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 49 treesize of output 83 [2018-11-18 21:06:47,232 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-18 21:06:47,255 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:47,265 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:47,276 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:06:47,297 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-18 21:06:47,298 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 2 variables, input treesize:157, output treesize:28 [2018-11-18 21:06:47,308 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-18 21:06:49,693 INFO L256 TraceCheckUtils]: 0: Hoare triple {4165#true} call ULTIMATE.init(); {4165#true} is VALID [2018-11-18 21:06:49,694 INFO L273 TraceCheckUtils]: 1: Hoare triple {4165#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {4165#true} is VALID [2018-11-18 21:06:49,694 INFO L273 TraceCheckUtils]: 2: Hoare triple {4165#true} assume true; {4165#true} is VALID [2018-11-18 21:06:49,694 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {4165#true} {4165#true} #141#return; {4165#true} is VALID [2018-11-18 21:06:49,695 INFO L256 TraceCheckUtils]: 4: Hoare triple {4165#true} call #t~ret22 := main(); {4165#true} is VALID [2018-11-18 21:06:49,695 INFO L273 TraceCheckUtils]: 5: Hoare triple {4165#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {4165#true} is VALID [2018-11-18 21:06:49,696 INFO L273 TraceCheckUtils]: 6: Hoare triple {4165#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {4188#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,697 INFO L273 TraceCheckUtils]: 7: Hoare triple {4188#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {4188#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,697 INFO L273 TraceCheckUtils]: 8: Hoare triple {4188#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume true; {4188#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,698 INFO L273 TraceCheckUtils]: 9: Hoare triple {4188#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {4188#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,698 INFO L273 TraceCheckUtils]: 10: Hoare triple {4188#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {4188#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,699 INFO L273 TraceCheckUtils]: 11: Hoare triple {4188#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} call #t~mem3 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem3, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem3;call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem4, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem4;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem5, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem5; {4188#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,699 INFO L273 TraceCheckUtils]: 12: Hoare triple {4188#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {4188#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,700 INFO L273 TraceCheckUtils]: 13: Hoare triple {4188#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume true; {4188#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,700 INFO L273 TraceCheckUtils]: 14: Hoare triple {4188#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {4188#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,701 INFO L273 TraceCheckUtils]: 15: Hoare triple {4188#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 1bv32; {4216#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:06:49,702 INFO L273 TraceCheckUtils]: 16: Hoare triple {4216#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {4216#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:06:49,703 INFO L273 TraceCheckUtils]: 17: Hoare triple {4216#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {4216#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:06:49,705 INFO L273 TraceCheckUtils]: 18: Hoare triple {4216#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {4226#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:06:49,706 INFO L273 TraceCheckUtils]: 19: Hoare triple {4226#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call #t~mem7 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem7, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem7;call #t~mem8 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem8, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem8;call #t~mem9 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem9, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem9; {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,707 INFO L273 TraceCheckUtils]: 20: Hoare triple {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} #t~post6 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post6);havoc #t~post6; {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,708 INFO L273 TraceCheckUtils]: 21: Hoare triple {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume true; {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,709 INFO L273 TraceCheckUtils]: 22: Hoare triple {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,727 INFO L273 TraceCheckUtils]: 23: Hoare triple {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 1bv32; {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,728 INFO L273 TraceCheckUtils]: 24: Hoare triple {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume true; {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,729 INFO L273 TraceCheckUtils]: 25: Hoare triple {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,731 INFO L273 TraceCheckUtils]: 26: Hoare triple {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,732 INFO L273 TraceCheckUtils]: 27: Hoare triple {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} call #t~mem11 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem11, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem11;call #t~mem12 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem12, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem12;call #t~mem13 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem13, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem13; {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,732 INFO L273 TraceCheckUtils]: 28: Hoare triple {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} #t~post10 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post10);havoc #t~post10; {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,733 INFO L273 TraceCheckUtils]: 29: Hoare triple {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume true; {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,733 INFO L273 TraceCheckUtils]: 30: Hoare triple {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,734 INFO L273 TraceCheckUtils]: 31: Hoare triple {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 1bv32; {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,734 INFO L273 TraceCheckUtils]: 32: Hoare triple {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume true; {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,735 INFO L273 TraceCheckUtils]: 33: Hoare triple {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,739 INFO L273 TraceCheckUtils]: 34: Hoare triple {4230#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {4276#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,741 INFO L273 TraceCheckUtils]: 35: Hoare triple {4276#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} call #t~mem15 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem15, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem15;call #t~mem16 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem16, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem16;call #t~mem17 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem17, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem17; {4280#(and (exists ((main_~i~0 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,743 INFO L273 TraceCheckUtils]: 36: Hoare triple {4280#(and (exists ((main_~i~0 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post14 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post14);havoc #t~post14; {4280#(and (exists ((main_~i~0 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,745 INFO L273 TraceCheckUtils]: 37: Hoare triple {4280#(and (exists ((main_~i~0 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume true; {4280#(and (exists ((main_~i~0 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,763 INFO L273 TraceCheckUtils]: 38: Hoare triple {4280#(and (exists ((main_~i~0 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {4280#(and (exists ((main_~i~0 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,765 INFO L273 TraceCheckUtils]: 39: Hoare triple {4280#(and (exists ((main_~i~0 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 0bv32; {4293#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (exists ((v_prenex_2 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,766 INFO L273 TraceCheckUtils]: 40: Hoare triple {4293#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (exists ((v_prenex_2 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))))) (= (_ bv2 32) main_~MINVAL~0))} assume true; {4293#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (exists ((v_prenex_2 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,766 INFO L273 TraceCheckUtils]: 41: Hoare triple {4293#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (exists ((v_prenex_2 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))))) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {4293#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (exists ((v_prenex_2 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,767 INFO L273 TraceCheckUtils]: 42: Hoare triple {4293#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (exists ((v_prenex_2 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))))) (= (_ bv2 32) main_~MINVAL~0))} assume #t~short21; {4293#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (exists ((v_prenex_2 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,769 INFO L256 TraceCheckUtils]: 43: Hoare triple {4293#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (exists ((v_prenex_2 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))))) (= (_ bv2 32) main_~MINVAL~0))} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {4306#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_2 (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} is VALID [2018-11-18 21:06:49,770 INFO L273 TraceCheckUtils]: 44: Hoare triple {4306#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_2 (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} ~cond := #in~cond; {4306#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_2 (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} is VALID [2018-11-18 21:06:49,770 INFO L273 TraceCheckUtils]: 45: Hoare triple {4306#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_2 (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} assume !(0bv32 == ~cond); {4306#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_2 (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} is VALID [2018-11-18 21:06:49,771 INFO L273 TraceCheckUtils]: 46: Hoare triple {4306#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_2 (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} assume true; {4306#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_2 (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} is VALID [2018-11-18 21:06:49,772 INFO L268 TraceCheckUtils]: 47: Hoare quadruple {4306#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32)) (v_prenex_2 (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (bvadd (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32)))))} {4293#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (exists ((v_prenex_2 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))))) (= (_ bv2 32) main_~MINVAL~0))} #145#return; {4293#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (exists ((v_prenex_2 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,772 INFO L273 TraceCheckUtils]: 48: Hoare triple {4293#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (exists ((v_prenex_2 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))))) (= (_ bv2 32) main_~MINVAL~0))} havoc #t~mem19;havoc #t~mem20;havoc #t~short21; {4293#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (exists ((v_prenex_2 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:06:49,775 INFO L273 TraceCheckUtils]: 49: Hoare triple {4293#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (exists ((v_prenex_2 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))))) (= (_ bv2 32) main_~MINVAL~0))} #t~post18 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post18);havoc #t~post18; {4325#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (exists ((v_prenex_2 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:06:49,778 INFO L273 TraceCheckUtils]: 50: Hoare triple {4325#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (exists ((v_prenex_2 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {4325#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (exists ((v_prenex_2 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:06:49,784 INFO L273 TraceCheckUtils]: 51: Hoare triple {4325#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967289 32)) (_ bv0 32)) (exists ((v_prenex_2 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_2) (_ bv4294967292 32))))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {4332#|main_#t~short21|} is VALID [2018-11-18 21:06:49,785 INFO L273 TraceCheckUtils]: 52: Hoare triple {4332#|main_#t~short21|} assume !#t~short21;call #t~mem20 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := 0bv32 == #t~mem20; {4166#false} is VALID [2018-11-18 21:06:49,785 INFO L256 TraceCheckUtils]: 53: Hoare triple {4166#false} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {4166#false} is VALID [2018-11-18 21:06:49,785 INFO L273 TraceCheckUtils]: 54: Hoare triple {4166#false} ~cond := #in~cond; {4166#false} is VALID [2018-11-18 21:06:49,786 INFO L273 TraceCheckUtils]: 55: Hoare triple {4166#false} assume 0bv32 == ~cond; {4166#false} is VALID [2018-11-18 21:06:49,786 INFO L273 TraceCheckUtils]: 56: Hoare triple {4166#false} assume !false; {4166#false} is VALID [2018-11-18 21:06:49,799 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 5 proven. 5 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-18 21:06:49,799 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 21:06:50,290 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 15 [2018-11-18 21:06:50,348 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 3 [2018-11-18 21:06:50,349 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-18 21:06:50,372 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 3 xjuncts. [2018-11-18 21:06:50,405 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 3 xjuncts. [2018-11-18 21:06:50,406 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:17, output treesize:31 [2018-11-18 21:06:50,425 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-18 21:06:50,641 INFO L273 TraceCheckUtils]: 56: Hoare triple {4166#false} assume !false; {4166#false} is VALID [2018-11-18 21:06:50,641 INFO L273 TraceCheckUtils]: 55: Hoare triple {4166#false} assume 0bv32 == ~cond; {4166#false} is VALID [2018-11-18 21:06:50,641 INFO L273 TraceCheckUtils]: 54: Hoare triple {4166#false} ~cond := #in~cond; {4166#false} is VALID [2018-11-18 21:06:50,642 INFO L256 TraceCheckUtils]: 53: Hoare triple {4166#false} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {4166#false} is VALID [2018-11-18 21:06:50,643 INFO L273 TraceCheckUtils]: 52: Hoare triple {4332#|main_#t~short21|} assume !#t~short21;call #t~mem20 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := 0bv32 == #t~mem20; {4166#false} is VALID [2018-11-18 21:06:50,643 INFO L273 TraceCheckUtils]: 51: Hoare triple {4363#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {4332#|main_#t~short21|} is VALID [2018-11-18 21:06:50,645 INFO L273 TraceCheckUtils]: 50: Hoare triple {4363#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume true; {4363#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,684 INFO L273 TraceCheckUtils]: 49: Hoare triple {4370#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} #t~post18 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post18);havoc #t~post18; {4363#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is UNKNOWN [2018-11-18 21:06:52,685 INFO L273 TraceCheckUtils]: 48: Hoare triple {4370#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} havoc #t~mem19;havoc #t~mem20;havoc #t~short21; {4370#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,686 INFO L268 TraceCheckUtils]: 47: Hoare quadruple {4165#true} {4370#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} #145#return; {4370#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,686 INFO L273 TraceCheckUtils]: 46: Hoare triple {4165#true} assume true; {4165#true} is VALID [2018-11-18 21:06:52,686 INFO L273 TraceCheckUtils]: 45: Hoare triple {4165#true} assume !(0bv32 == ~cond); {4165#true} is VALID [2018-11-18 21:06:52,686 INFO L273 TraceCheckUtils]: 44: Hoare triple {4165#true} ~cond := #in~cond; {4165#true} is VALID [2018-11-18 21:06:52,686 INFO L256 TraceCheckUtils]: 43: Hoare triple {4370#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {4165#true} is VALID [2018-11-18 21:06:52,687 INFO L273 TraceCheckUtils]: 42: Hoare triple {4370#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} assume #t~short21; {4370#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,687 INFO L273 TraceCheckUtils]: 41: Hoare triple {4370#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {4370#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,687 INFO L273 TraceCheckUtils]: 40: Hoare triple {4370#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} assume true; {4370#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,688 INFO L273 TraceCheckUtils]: 39: Hoare triple {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} ~i~0 := 0bv32; {4370#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,688 INFO L273 TraceCheckUtils]: 38: Hoare triple {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,689 INFO L273 TraceCheckUtils]: 37: Hoare triple {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume true; {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,689 INFO L273 TraceCheckUtils]: 36: Hoare triple {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} #t~post14 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post14);havoc #t~post14; {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,690 INFO L273 TraceCheckUtils]: 35: Hoare triple {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} call #t~mem15 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem15, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem15;call #t~mem16 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem16, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem16;call #t~mem17 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem17, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem17; {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,702 INFO L273 TraceCheckUtils]: 34: Hoare triple {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,702 INFO L273 TraceCheckUtils]: 33: Hoare triple {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,703 INFO L273 TraceCheckUtils]: 32: Hoare triple {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume true; {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,703 INFO L273 TraceCheckUtils]: 31: Hoare triple {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} ~i~0 := 1bv32; {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,703 INFO L273 TraceCheckUtils]: 30: Hoare triple {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,704 INFO L273 TraceCheckUtils]: 29: Hoare triple {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume true; {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,704 INFO L273 TraceCheckUtils]: 28: Hoare triple {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} #t~post10 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post10);havoc #t~post10; {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,705 INFO L273 TraceCheckUtils]: 27: Hoare triple {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} call #t~mem11 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem11, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem11;call #t~mem12 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem12, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem12;call #t~mem13 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem13, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem13; {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,715 INFO L273 TraceCheckUtils]: 26: Hoare triple {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,716 INFO L273 TraceCheckUtils]: 25: Hoare triple {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,716 INFO L273 TraceCheckUtils]: 24: Hoare triple {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume true; {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,717 INFO L273 TraceCheckUtils]: 23: Hoare triple {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} ~i~0 := 1bv32; {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,717 INFO L273 TraceCheckUtils]: 22: Hoare triple {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,717 INFO L273 TraceCheckUtils]: 21: Hoare triple {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume true; {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,718 INFO L273 TraceCheckUtils]: 20: Hoare triple {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} #t~post6 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post6);havoc #t~post6; {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,720 INFO L273 TraceCheckUtils]: 19: Hoare triple {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} call #t~mem7 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem7, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem7;call #t~mem8 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem8, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem8;call #t~mem9 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem9, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem9; {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,747 INFO L273 TraceCheckUtils]: 18: Hoare triple {4465#(and (or (forall ((v_prenex_4 (_ BitVec 32))) (bvsge v_prenex_4 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {4401#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,747 INFO L273 TraceCheckUtils]: 17: Hoare triple {4465#(and (or (forall ((v_prenex_4 (_ BitVec 32))) (bvsge v_prenex_4 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {4465#(and (or (forall ((v_prenex_4 (_ BitVec 32))) (bvsge v_prenex_4 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0))} is VALID [2018-11-18 21:06:52,748 INFO L273 TraceCheckUtils]: 16: Hoare triple {4465#(and (or (forall ((v_prenex_4 (_ BitVec 32))) (bvsge v_prenex_4 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0))} assume true; {4465#(and (or (forall ((v_prenex_4 (_ BitVec 32))) (bvsge v_prenex_4 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0))} is VALID [2018-11-18 21:06:52,748 INFO L273 TraceCheckUtils]: 15: Hoare triple {4475#(bvsge main_~CCCELVOL3~0 main_~MINVAL~0)} ~i~0 := 1bv32; {4465#(and (or (forall ((v_prenex_4 (_ BitVec 32))) (bvsge v_prenex_4 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0))} is VALID [2018-11-18 21:06:52,749 INFO L273 TraceCheckUtils]: 14: Hoare triple {4475#(bvsge main_~CCCELVOL3~0 main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {4475#(bvsge main_~CCCELVOL3~0 main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,750 INFO L273 TraceCheckUtils]: 13: Hoare triple {4475#(bvsge main_~CCCELVOL3~0 main_~MINVAL~0)} assume true; {4475#(bvsge main_~CCCELVOL3~0 main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,750 INFO L273 TraceCheckUtils]: 12: Hoare triple {4475#(bvsge main_~CCCELVOL3~0 main_~MINVAL~0)} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {4475#(bvsge main_~CCCELVOL3~0 main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,751 INFO L273 TraceCheckUtils]: 11: Hoare triple {4475#(bvsge main_~CCCELVOL3~0 main_~MINVAL~0)} call #t~mem3 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem3, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem3;call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem4, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem4;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem5, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem5; {4475#(bvsge main_~CCCELVOL3~0 main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,751 INFO L273 TraceCheckUtils]: 10: Hoare triple {4475#(bvsge main_~CCCELVOL3~0 main_~MINVAL~0)} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {4475#(bvsge main_~CCCELVOL3~0 main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,752 INFO L273 TraceCheckUtils]: 9: Hoare triple {4475#(bvsge main_~CCCELVOL3~0 main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {4475#(bvsge main_~CCCELVOL3~0 main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,752 INFO L273 TraceCheckUtils]: 8: Hoare triple {4475#(bvsge main_~CCCELVOL3~0 main_~MINVAL~0)} assume true; {4475#(bvsge main_~CCCELVOL3~0 main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,753 INFO L273 TraceCheckUtils]: 7: Hoare triple {4475#(bvsge main_~CCCELVOL3~0 main_~MINVAL~0)} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {4475#(bvsge main_~CCCELVOL3~0 main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,754 INFO L273 TraceCheckUtils]: 6: Hoare triple {4165#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {4475#(bvsge main_~CCCELVOL3~0 main_~MINVAL~0)} is VALID [2018-11-18 21:06:52,754 INFO L273 TraceCheckUtils]: 5: Hoare triple {4165#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {4165#true} is VALID [2018-11-18 21:06:52,754 INFO L256 TraceCheckUtils]: 4: Hoare triple {4165#true} call #t~ret22 := main(); {4165#true} is VALID [2018-11-18 21:06:52,755 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {4165#true} {4165#true} #141#return; {4165#true} is VALID [2018-11-18 21:06:52,755 INFO L273 TraceCheckUtils]: 2: Hoare triple {4165#true} assume true; {4165#true} is VALID [2018-11-18 21:06:52,755 INFO L273 TraceCheckUtils]: 1: Hoare triple {4165#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {4165#true} is VALID [2018-11-18 21:06:52,755 INFO L256 TraceCheckUtils]: 0: Hoare triple {4165#true} call ULTIMATE.init(); {4165#true} is VALID [2018-11-18 21:06:52,761 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-18 21:06:52,763 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 21:06:52,763 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8] total 17 [2018-11-18 21:06:52,764 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 57 [2018-11-18 21:06:52,765 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:06:52,765 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 17 states. [2018-11-18 21:06:55,229 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 98 edges. 97 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2018-11-18 21:06:55,230 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-11-18 21:06:55,230 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-11-18 21:06:55,230 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=214, Unknown=0, NotChecked=0, Total=272 [2018-11-18 21:06:55,230 INFO L87 Difference]: Start difference. First operand 99 states and 110 transitions. Second operand 17 states. [2018-11-18 21:08:08,822 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:08,822 INFO L93 Difference]: Finished difference Result 141 states and 158 transitions. [2018-11-18 21:08:08,822 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-18 21:08:08,823 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 57 [2018-11-18 21:08:08,823 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:08:08,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17 states. [2018-11-18 21:08:08,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 112 transitions. [2018-11-18 21:08:08,826 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17 states. [2018-11-18 21:08:08,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 112 transitions. [2018-11-18 21:08:08,829 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 17 states and 112 transitions. [2018-11-18 21:08:09,301 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 112 edges. 112 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:08:09,303 INFO L225 Difference]: With dead ends: 141 [2018-11-18 21:08:09,303 INFO L226 Difference]: Without dead ends: 124 [2018-11-18 21:08:09,304 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 125 GetRequests, 90 SyntacticMatches, 8 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 192 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=213, Invalid=599, Unknown=0, NotChecked=0, Total=812 [2018-11-18 21:08:09,304 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124 states. [2018-11-18 21:08:09,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124 to 105. [2018-11-18 21:08:09,560 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:08:09,560 INFO L82 GeneralOperation]: Start isEquivalent. First operand 124 states. Second operand 105 states. [2018-11-18 21:08:09,560 INFO L74 IsIncluded]: Start isIncluded. First operand 124 states. Second operand 105 states. [2018-11-18 21:08:09,560 INFO L87 Difference]: Start difference. First operand 124 states. Second operand 105 states. [2018-11-18 21:08:09,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:09,565 INFO L93 Difference]: Finished difference Result 124 states and 139 transitions. [2018-11-18 21:08:09,565 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 139 transitions. [2018-11-18 21:08:09,565 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:08:09,566 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:08:09,566 INFO L74 IsIncluded]: Start isIncluded. First operand 105 states. Second operand 124 states. [2018-11-18 21:08:09,566 INFO L87 Difference]: Start difference. First operand 105 states. Second operand 124 states. [2018-11-18 21:08:09,570 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:09,571 INFO L93 Difference]: Finished difference Result 124 states and 139 transitions. [2018-11-18 21:08:09,571 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 139 transitions. [2018-11-18 21:08:09,571 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:08:09,571 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:08:09,572 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:08:09,572 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:08:09,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-11-18 21:08:09,575 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 117 transitions. [2018-11-18 21:08:09,575 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 117 transitions. Word has length 57 [2018-11-18 21:08:09,576 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:08:09,576 INFO L480 AbstractCegarLoop]: Abstraction has 105 states and 117 transitions. [2018-11-18 21:08:09,576 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-11-18 21:08:09,576 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 117 transitions. [2018-11-18 21:08:09,577 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-11-18 21:08:09,577 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:08:09,577 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:08:09,577 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:08:09,578 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:08:09,578 INFO L82 PathProgramCache]: Analyzing trace with hash -1802491692, now seen corresponding path program 2 times [2018-11-18 21:08:09,578 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:08:09,578 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:08:09,606 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-18 21:08:09,760 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 21:08:09,760 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 21:08:09,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:08:09,803 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:08:09,928 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-18 21:08:09,933 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-18 21:08:09,936 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:08:09,940 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:09,955 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:09,956 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:28, output treesize:24 [2018-11-18 21:08:10,011 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:10,012 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 81 treesize of output 112 [2018-11-18 21:08:10,048 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:10,049 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:10,050 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:10,061 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 67 [2018-11-18 21:08:10,086 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:10,087 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:10,088 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:10,101 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 55 [2018-11-18 21:08:10,110 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:10,116 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 29 [2018-11-18 21:08:10,119 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-18 21:08:10,131 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:10,142 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:10,146 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:10,158 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:10,159 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 1 variables, input treesize:87, output treesize:18 [2018-11-18 21:08:10,233 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 21 [2018-11-18 21:08:10,245 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:10,246 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:10,247 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 43 [2018-11-18 21:08:10,251 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:08:10,269 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:10,291 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:10,292 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:32, output treesize:28 [2018-11-18 21:08:10,367 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:10,369 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 149 treesize of output 236 [2018-11-18 21:08:10,441 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:10,442 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:10,444 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:10,446 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:10,448 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:10,450 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:10,466 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:10,480 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 100 treesize of output 170 [2018-11-18 21:08:10,566 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:10,568 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:10,570 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:10,572 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:10,574 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:10,585 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:10,610 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 53 treesize of output 127 [2018-11-18 21:08:10,628 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:10,678 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 3 case distinctions, treesize of input 53 treesize of output 87 [2018-11-18 21:08:10,686 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 2 xjuncts. [2018-11-18 21:08:10,745 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:10,759 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:10,772 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:10,794 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-18 21:08:10,794 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 2 variables, input treesize:155, output treesize:28 [2018-11-18 21:08:10,806 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-18 21:08:13,722 INFO L256 TraceCheckUtils]: 0: Hoare triple {5107#true} call ULTIMATE.init(); {5107#true} is VALID [2018-11-18 21:08:13,722 INFO L273 TraceCheckUtils]: 1: Hoare triple {5107#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {5107#true} is VALID [2018-11-18 21:08:13,722 INFO L273 TraceCheckUtils]: 2: Hoare triple {5107#true} assume true; {5107#true} is VALID [2018-11-18 21:08:13,722 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {5107#true} {5107#true} #141#return; {5107#true} is VALID [2018-11-18 21:08:13,723 INFO L256 TraceCheckUtils]: 4: Hoare triple {5107#true} call #t~ret22 := main(); {5107#true} is VALID [2018-11-18 21:08:13,723 INFO L273 TraceCheckUtils]: 5: Hoare triple {5107#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {5107#true} is VALID [2018-11-18 21:08:13,724 INFO L273 TraceCheckUtils]: 6: Hoare triple {5107#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,724 INFO L273 TraceCheckUtils]: 7: Hoare triple {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,725 INFO L273 TraceCheckUtils]: 8: Hoare triple {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume true; {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,725 INFO L273 TraceCheckUtils]: 9: Hoare triple {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,726 INFO L273 TraceCheckUtils]: 10: Hoare triple {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,727 INFO L273 TraceCheckUtils]: 11: Hoare triple {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} call #t~mem3 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem3, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem3;call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem4, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem4;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem5, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem5; {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,728 INFO L273 TraceCheckUtils]: 12: Hoare triple {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,728 INFO L273 TraceCheckUtils]: 13: Hoare triple {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume true; {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,729 INFO L273 TraceCheckUtils]: 14: Hoare triple {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,730 INFO L273 TraceCheckUtils]: 15: Hoare triple {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 1bv32; {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,730 INFO L273 TraceCheckUtils]: 16: Hoare triple {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume true; {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,731 INFO L273 TraceCheckUtils]: 17: Hoare triple {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,732 INFO L273 TraceCheckUtils]: 18: Hoare triple {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,733 INFO L273 TraceCheckUtils]: 19: Hoare triple {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} call #t~mem7 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem7, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem7;call #t~mem8 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem8, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem8;call #t~mem9 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem9, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem9; {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,734 INFO L273 TraceCheckUtils]: 20: Hoare triple {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post6 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post6);havoc #t~post6; {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,735 INFO L273 TraceCheckUtils]: 21: Hoare triple {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume true; {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,735 INFO L273 TraceCheckUtils]: 22: Hoare triple {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,736 INFO L273 TraceCheckUtils]: 23: Hoare triple {5130#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 1bv32; {5182#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:13,737 INFO L273 TraceCheckUtils]: 24: Hoare triple {5182#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {5182#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:13,738 INFO L273 TraceCheckUtils]: 25: Hoare triple {5182#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {5182#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:13,741 INFO L273 TraceCheckUtils]: 26: Hoare triple {5182#(and (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {5192#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:13,743 INFO L273 TraceCheckUtils]: 27: Hoare triple {5192#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call #t~mem11 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem11, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem11;call #t~mem12 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem12, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem12;call #t~mem13 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem13, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem13; {5196#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,743 INFO L273 TraceCheckUtils]: 28: Hoare triple {5196#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} #t~post10 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post10);havoc #t~post10; {5196#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,744 INFO L273 TraceCheckUtils]: 29: Hoare triple {5196#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume true; {5196#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,744 INFO L273 TraceCheckUtils]: 30: Hoare triple {5196#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {5196#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,745 INFO L273 TraceCheckUtils]: 31: Hoare triple {5196#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 1bv32; {5196#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,745 INFO L273 TraceCheckUtils]: 32: Hoare triple {5196#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume true; {5196#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,746 INFO L273 TraceCheckUtils]: 33: Hoare triple {5196#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {5196#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,750 INFO L273 TraceCheckUtils]: 34: Hoare triple {5196#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {5218#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,752 INFO L273 TraceCheckUtils]: 35: Hoare triple {5218#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} call #t~mem15 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem15, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem15;call #t~mem16 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem16, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem16;call #t~mem17 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem17, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem17; {5222#(and (exists ((main_~i~0 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,755 INFO L273 TraceCheckUtils]: 36: Hoare triple {5222#(and (exists ((main_~i~0 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} #t~post14 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post14);havoc #t~post14; {5222#(and (exists ((main_~i~0 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,757 INFO L273 TraceCheckUtils]: 37: Hoare triple {5222#(and (exists ((main_~i~0 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume true; {5222#(and (exists ((main_~i~0 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,774 INFO L273 TraceCheckUtils]: 38: Hoare triple {5222#(and (exists ((main_~i~0 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {5222#(and (exists ((main_~i~0 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,776 INFO L273 TraceCheckUtils]: 39: Hoare triple {5222#(and (exists ((main_~i~0 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 0bv32; {5235#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,776 INFO L273 TraceCheckUtils]: 40: Hoare triple {5235#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume true; {5235#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,777 INFO L273 TraceCheckUtils]: 41: Hoare triple {5235#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {5235#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,778 INFO L273 TraceCheckUtils]: 42: Hoare triple {5235#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume #t~short21; {5235#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,781 INFO L256 TraceCheckUtils]: 43: Hoare triple {5235#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {5248#(exists ((v_prenex_5 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32)))))} is VALID [2018-11-18 21:08:13,782 INFO L273 TraceCheckUtils]: 44: Hoare triple {5248#(exists ((v_prenex_5 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32)))))} ~cond := #in~cond; {5248#(exists ((v_prenex_5 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32)))))} is VALID [2018-11-18 21:08:13,782 INFO L273 TraceCheckUtils]: 45: Hoare triple {5248#(exists ((v_prenex_5 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32)))))} assume !(0bv32 == ~cond); {5248#(exists ((v_prenex_5 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32)))))} is VALID [2018-11-18 21:08:13,783 INFO L273 TraceCheckUtils]: 46: Hoare triple {5248#(exists ((v_prenex_5 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32)))))} assume true; {5248#(exists ((v_prenex_5 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32)))))} is VALID [2018-11-18 21:08:13,784 INFO L268 TraceCheckUtils]: 47: Hoare quadruple {5248#(exists ((v_prenex_5 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32)))))} {5235#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} #145#return; {5235#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,784 INFO L273 TraceCheckUtils]: 48: Hoare triple {5235#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} havoc #t~mem19;havoc #t~mem20;havoc #t~short21; {5235#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,785 INFO L273 TraceCheckUtils]: 49: Hoare triple {5235#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} #t~post18 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post18);havoc #t~post18; {5267#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:13,785 INFO L273 TraceCheckUtils]: 50: Hoare triple {5267#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {5267#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:13,786 INFO L273 TraceCheckUtils]: 51: Hoare triple {5267#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {5267#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:13,788 INFO L273 TraceCheckUtils]: 52: Hoare triple {5267#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume #t~short21; {5267#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:13,791 INFO L256 TraceCheckUtils]: 53: Hoare triple {5267#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {5248#(exists ((v_prenex_5 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32)))))} is VALID [2018-11-18 21:08:13,792 INFO L273 TraceCheckUtils]: 54: Hoare triple {5248#(exists ((v_prenex_5 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32)))))} ~cond := #in~cond; {5248#(exists ((v_prenex_5 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32)))))} is VALID [2018-11-18 21:08:13,792 INFO L273 TraceCheckUtils]: 55: Hoare triple {5248#(exists ((v_prenex_5 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32)))))} assume !(0bv32 == ~cond); {5248#(exists ((v_prenex_5 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32)))))} is VALID [2018-11-18 21:08:13,793 INFO L273 TraceCheckUtils]: 56: Hoare triple {5248#(exists ((v_prenex_5 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32)))))} assume true; {5248#(exists ((v_prenex_5 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32)))))} is VALID [2018-11-18 21:08:13,793 INFO L268 TraceCheckUtils]: 57: Hoare quadruple {5248#(exists ((v_prenex_5 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv8 32)))))} {5267#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #145#return; {5267#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:13,794 INFO L273 TraceCheckUtils]: 58: Hoare triple {5267#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} havoc #t~mem19;havoc #t~mem20;havoc #t~short21; {5267#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:13,795 INFO L273 TraceCheckUtils]: 59: Hoare triple {5267#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post18 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post18);havoc #t~post18; {5298#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,798 INFO L273 TraceCheckUtils]: 60: Hoare triple {5298#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} assume true; {5298#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:13,801 INFO L273 TraceCheckUtils]: 61: Hoare triple {5298#(and (exists ((v_prenex_5 (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) v_prenex_5) (_ bv4294967292 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {5305#|main_#t~short21|} is VALID [2018-11-18 21:08:13,802 INFO L273 TraceCheckUtils]: 62: Hoare triple {5305#|main_#t~short21|} assume !#t~short21;call #t~mem20 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := 0bv32 == #t~mem20; {5108#false} is VALID [2018-11-18 21:08:13,802 INFO L256 TraceCheckUtils]: 63: Hoare triple {5108#false} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {5108#false} is VALID [2018-11-18 21:08:13,803 INFO L273 TraceCheckUtils]: 64: Hoare triple {5108#false} ~cond := #in~cond; {5108#false} is VALID [2018-11-18 21:08:13,803 INFO L273 TraceCheckUtils]: 65: Hoare triple {5108#false} assume 0bv32 == ~cond; {5108#false} is VALID [2018-11-18 21:08:13,803 INFO L273 TraceCheckUtils]: 66: Hoare triple {5108#false} assume !false; {5108#false} is VALID [2018-11-18 21:08:13,819 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 8 proven. 14 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-11-18 21:08:13,819 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 21:08:14,319 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 15 [2018-11-18 21:08:14,386 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 3 [2018-11-18 21:08:14,387 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-18 21:08:14,411 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 3 xjuncts. [2018-11-18 21:08:14,445 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 3 xjuncts. [2018-11-18 21:08:14,445 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:17, output treesize:31 [2018-11-18 21:08:14,477 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-18 21:08:14,685 INFO L273 TraceCheckUtils]: 66: Hoare triple {5108#false} assume !false; {5108#false} is VALID [2018-11-18 21:08:14,686 INFO L273 TraceCheckUtils]: 65: Hoare triple {5108#false} assume 0bv32 == ~cond; {5108#false} is VALID [2018-11-18 21:08:14,686 INFO L273 TraceCheckUtils]: 64: Hoare triple {5108#false} ~cond := #in~cond; {5108#false} is VALID [2018-11-18 21:08:14,687 INFO L256 TraceCheckUtils]: 63: Hoare triple {5108#false} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {5108#false} is VALID [2018-11-18 21:08:14,702 INFO L273 TraceCheckUtils]: 62: Hoare triple {5305#|main_#t~short21|} assume !#t~short21;call #t~mem20 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := 0bv32 == #t~mem20; {5108#false} is VALID [2018-11-18 21:08:14,703 INFO L273 TraceCheckUtils]: 61: Hoare triple {5336#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {5305#|main_#t~short21|} is VALID [2018-11-18 21:08:14,704 INFO L273 TraceCheckUtils]: 60: Hoare triple {5336#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume true; {5336#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:16,744 INFO L273 TraceCheckUtils]: 59: Hoare triple {5343#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} #t~post18 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post18);havoc #t~post18; {5336#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is UNKNOWN [2018-11-18 21:08:16,745 INFO L273 TraceCheckUtils]: 58: Hoare triple {5343#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} havoc #t~mem19;havoc #t~mem20;havoc #t~short21; {5343#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:16,745 INFO L268 TraceCheckUtils]: 57: Hoare quadruple {5107#true} {5343#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} #145#return; {5343#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:16,746 INFO L273 TraceCheckUtils]: 56: Hoare triple {5107#true} assume true; {5107#true} is VALID [2018-11-18 21:08:16,746 INFO L273 TraceCheckUtils]: 55: Hoare triple {5107#true} assume !(0bv32 == ~cond); {5107#true} is VALID [2018-11-18 21:08:16,746 INFO L273 TraceCheckUtils]: 54: Hoare triple {5107#true} ~cond := #in~cond; {5107#true} is VALID [2018-11-18 21:08:16,746 INFO L256 TraceCheckUtils]: 53: Hoare triple {5343#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {5107#true} is VALID [2018-11-18 21:08:16,746 INFO L273 TraceCheckUtils]: 52: Hoare triple {5343#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} assume #t~short21; {5343#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:16,747 INFO L273 TraceCheckUtils]: 51: Hoare triple {5343#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {5343#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:16,747 INFO L273 TraceCheckUtils]: 50: Hoare triple {5343#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} assume true; {5343#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,766 INFO L273 TraceCheckUtils]: 49: Hoare triple {5374#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} #t~post18 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post18);havoc #t~post18; {5343#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is UNKNOWN [2018-11-18 21:08:18,766 INFO L273 TraceCheckUtils]: 48: Hoare triple {5374#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} havoc #t~mem19;havoc #t~mem20;havoc #t~short21; {5374#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,767 INFO L268 TraceCheckUtils]: 47: Hoare quadruple {5107#true} {5374#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} #145#return; {5374#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,767 INFO L273 TraceCheckUtils]: 46: Hoare triple {5107#true} assume true; {5107#true} is VALID [2018-11-18 21:08:18,767 INFO L273 TraceCheckUtils]: 45: Hoare triple {5107#true} assume !(0bv32 == ~cond); {5107#true} is VALID [2018-11-18 21:08:18,767 INFO L273 TraceCheckUtils]: 44: Hoare triple {5107#true} ~cond := #in~cond; {5107#true} is VALID [2018-11-18 21:08:18,768 INFO L256 TraceCheckUtils]: 43: Hoare triple {5374#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {5107#true} is VALID [2018-11-18 21:08:18,768 INFO L273 TraceCheckUtils]: 42: Hoare triple {5374#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} assume #t~short21; {5374#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,768 INFO L273 TraceCheckUtils]: 41: Hoare triple {5374#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {5374#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,769 INFO L273 TraceCheckUtils]: 40: Hoare triple {5374#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} assume true; {5374#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,769 INFO L273 TraceCheckUtils]: 39: Hoare triple {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} ~i~0 := 0bv32; {5374#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,769 INFO L273 TraceCheckUtils]: 38: Hoare triple {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,770 INFO L273 TraceCheckUtils]: 37: Hoare triple {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} assume true; {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,770 INFO L273 TraceCheckUtils]: 36: Hoare triple {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} #t~post14 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post14);havoc #t~post14; {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,771 INFO L273 TraceCheckUtils]: 35: Hoare triple {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} call #t~mem15 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem15, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem15;call #t~mem16 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem16, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem16;call #t~mem17 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem17, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem17; {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,783 INFO L273 TraceCheckUtils]: 34: Hoare triple {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,783 INFO L273 TraceCheckUtils]: 33: Hoare triple {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,784 INFO L273 TraceCheckUtils]: 32: Hoare triple {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} assume true; {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,784 INFO L273 TraceCheckUtils]: 31: Hoare triple {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} ~i~0 := 1bv32; {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,784 INFO L273 TraceCheckUtils]: 30: Hoare triple {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,785 INFO L273 TraceCheckUtils]: 29: Hoare triple {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} assume true; {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,785 INFO L273 TraceCheckUtils]: 28: Hoare triple {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} #t~post10 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post10);havoc #t~post10; {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,786 INFO L273 TraceCheckUtils]: 27: Hoare triple {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} call #t~mem11 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem11, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem11;call #t~mem12 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem12, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem12;call #t~mem13 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem13, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem13; {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,808 INFO L273 TraceCheckUtils]: 26: Hoare triple {5445#(and (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (or (forall ((v_prenex_8 (_ BitVec 32))) (bvsge v_prenex_8 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {5405#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,809 INFO L273 TraceCheckUtils]: 25: Hoare triple {5445#(and (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (or (forall ((v_prenex_8 (_ BitVec 32))) (bvsge v_prenex_8 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {5445#(and (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (or (forall ((v_prenex_8 (_ BitVec 32))) (bvsge v_prenex_8 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))))} is VALID [2018-11-18 21:08:18,810 INFO L273 TraceCheckUtils]: 24: Hoare triple {5445#(and (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (or (forall ((v_prenex_8 (_ BitVec 32))) (bvsge v_prenex_8 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))))} assume true; {5445#(and (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (or (forall ((v_prenex_8 (_ BitVec 32))) (bvsge v_prenex_8 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))))} is VALID [2018-11-18 21:08:18,810 INFO L273 TraceCheckUtils]: 23: Hoare triple {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} ~i~0 := 1bv32; {5445#(and (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (or (forall ((v_prenex_8 (_ BitVec 32))) (bvsge v_prenex_8 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))))} is VALID [2018-11-18 21:08:18,811 INFO L273 TraceCheckUtils]: 22: Hoare triple {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,812 INFO L273 TraceCheckUtils]: 21: Hoare triple {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} assume true; {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,812 INFO L273 TraceCheckUtils]: 20: Hoare triple {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} #t~post6 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post6);havoc #t~post6; {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,813 INFO L273 TraceCheckUtils]: 19: Hoare triple {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} call #t~mem7 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem7, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem7;call #t~mem8 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem8, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem8;call #t~mem9 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem9, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem9; {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,813 INFO L273 TraceCheckUtils]: 18: Hoare triple {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,814 INFO L273 TraceCheckUtils]: 17: Hoare triple {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,814 INFO L273 TraceCheckUtils]: 16: Hoare triple {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} assume true; {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,815 INFO L273 TraceCheckUtils]: 15: Hoare triple {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} ~i~0 := 1bv32; {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,815 INFO L273 TraceCheckUtils]: 14: Hoare triple {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,816 INFO L273 TraceCheckUtils]: 13: Hoare triple {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} assume true; {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,816 INFO L273 TraceCheckUtils]: 12: Hoare triple {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,817 INFO L273 TraceCheckUtils]: 11: Hoare triple {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} call #t~mem3 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem3, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem3;call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem4, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem4;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem5, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem5; {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,817 INFO L273 TraceCheckUtils]: 10: Hoare triple {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,818 INFO L273 TraceCheckUtils]: 9: Hoare triple {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,818 INFO L273 TraceCheckUtils]: 8: Hoare triple {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} assume true; {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,819 INFO L273 TraceCheckUtils]: 7: Hoare triple {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,820 INFO L273 TraceCheckUtils]: 6: Hoare triple {5107#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {5455#(bvsge main_~CCCELVOL2~0 main_~MINVAL~0)} is VALID [2018-11-18 21:08:18,820 INFO L273 TraceCheckUtils]: 5: Hoare triple {5107#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {5107#true} is VALID [2018-11-18 21:08:18,820 INFO L256 TraceCheckUtils]: 4: Hoare triple {5107#true} call #t~ret22 := main(); {5107#true} is VALID [2018-11-18 21:08:18,821 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {5107#true} {5107#true} #141#return; {5107#true} is VALID [2018-11-18 21:08:18,821 INFO L273 TraceCheckUtils]: 2: Hoare triple {5107#true} assume true; {5107#true} is VALID [2018-11-18 21:08:18,821 INFO L273 TraceCheckUtils]: 1: Hoare triple {5107#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {5107#true} is VALID [2018-11-18 21:08:18,821 INFO L256 TraceCheckUtils]: 0: Hoare triple {5107#true} call ULTIMATE.init(); {5107#true} is VALID [2018-11-18 21:08:18,829 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 6 proven. 14 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 21:08:18,836 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 21:08:18,836 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 9] total 19 [2018-11-18 21:08:18,837 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 67 [2018-11-18 21:08:18,837 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:08:18,837 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 19 states. [2018-11-18 21:08:23,335 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 112 edges. 110 inductive. 0 not inductive. 2 times theorem prover too weak to decide inductivity. [2018-11-18 21:08:23,335 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-11-18 21:08:23,336 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-11-18 21:08:23,336 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=275, Unknown=0, NotChecked=0, Total=342 [2018-11-18 21:08:23,336 INFO L87 Difference]: Start difference. First operand 105 states and 117 transitions. Second operand 19 states. [2018-11-18 21:08:46,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:46,698 INFO L93 Difference]: Finished difference Result 183 states and 206 transitions. [2018-11-18 21:08:46,698 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-11-18 21:08:46,698 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 67 [2018-11-18 21:08:46,699 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:08:46,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19 states. [2018-11-18 21:08:46,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 139 transitions. [2018-11-18 21:08:46,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19 states. [2018-11-18 21:08:46,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 139 transitions. [2018-11-18 21:08:46,705 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 20 states and 139 transitions. [2018-11-18 21:08:47,624 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 139 edges. 139 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:08:47,627 INFO L225 Difference]: With dead ends: 183 [2018-11-18 21:08:47,627 INFO L226 Difference]: Without dead ends: 127 [2018-11-18 21:08:47,628 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 149 GetRequests, 111 SyntacticMatches, 6 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 274 ImplicationChecksByTransitivity, 4.2s TimeCoverageRelationStatistics Valid=256, Invalid=866, Unknown=0, NotChecked=0, Total=1122 [2018-11-18 21:08:47,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2018-11-18 21:08:47,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 111. [2018-11-18 21:08:47,947 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:08:47,947 INFO L82 GeneralOperation]: Start isEquivalent. First operand 127 states. Second operand 111 states. [2018-11-18 21:08:47,947 INFO L74 IsIncluded]: Start isIncluded. First operand 127 states. Second operand 111 states. [2018-11-18 21:08:47,948 INFO L87 Difference]: Start difference. First operand 127 states. Second operand 111 states. [2018-11-18 21:08:47,953 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:47,953 INFO L93 Difference]: Finished difference Result 127 states and 139 transitions. [2018-11-18 21:08:47,953 INFO L276 IsEmpty]: Start isEmpty. Operand 127 states and 139 transitions. [2018-11-18 21:08:47,954 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:08:47,954 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:08:47,954 INFO L74 IsIncluded]: Start isIncluded. First operand 111 states. Second operand 127 states. [2018-11-18 21:08:47,954 INFO L87 Difference]: Start difference. First operand 111 states. Second operand 127 states. [2018-11-18 21:08:47,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:47,959 INFO L93 Difference]: Finished difference Result 127 states and 139 transitions. [2018-11-18 21:08:47,959 INFO L276 IsEmpty]: Start isEmpty. Operand 127 states and 139 transitions. [2018-11-18 21:08:47,959 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:08:47,959 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:08:47,960 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:08:47,960 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:08:47,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-11-18 21:08:47,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 121 transitions. [2018-11-18 21:08:47,964 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 121 transitions. Word has length 67 [2018-11-18 21:08:47,964 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:08:47,964 INFO L480 AbstractCegarLoop]: Abstraction has 111 states and 121 transitions. [2018-11-18 21:08:47,964 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-11-18 21:08:47,964 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 121 transitions. [2018-11-18 21:08:47,965 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-11-18 21:08:47,965 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:08:47,966 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:08:47,966 INFO L423 AbstractCegarLoop]: === Iteration 10 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:08:47,966 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:08:47,966 INFO L82 PathProgramCache]: Analyzing trace with hash 767094111, now seen corresponding path program 3 times [2018-11-18 21:08:47,967 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:08:47,967 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:08:48,000 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2018-11-18 21:08:48,542 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-11-18 21:08:48,542 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 21:08:48,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:08:48,629 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:08:48,818 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-18 21:08:48,823 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-18 21:08:48,827 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:08:48,830 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:48,843 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:48,843 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:25, output treesize:21 [2018-11-18 21:08:48,884 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:48,885 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 79 treesize of output 110 [2018-11-18 21:08:48,923 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:48,925 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:48,926 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:48,938 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 50 treesize of output 65 [2018-11-18 21:08:48,960 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:48,962 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:48,963 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:48,975 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 53 [2018-11-18 21:08:48,987 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:48,991 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 27 [2018-11-18 21:08:48,994 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-18 21:08:49,004 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:49,007 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:49,011 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:49,020 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:49,021 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 1 variables, input treesize:82, output treesize:13 [2018-11-18 21:08:49,425 INFO L256 TraceCheckUtils]: 0: Hoare triple {6185#true} call ULTIMATE.init(); {6185#true} is VALID [2018-11-18 21:08:49,425 INFO L273 TraceCheckUtils]: 1: Hoare triple {6185#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {6185#true} is VALID [2018-11-18 21:08:49,425 INFO L273 TraceCheckUtils]: 2: Hoare triple {6185#true} assume true; {6185#true} is VALID [2018-11-18 21:08:49,426 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {6185#true} {6185#true} #141#return; {6185#true} is VALID [2018-11-18 21:08:49,426 INFO L256 TraceCheckUtils]: 4: Hoare triple {6185#true} call #t~ret22 := main(); {6185#true} is VALID [2018-11-18 21:08:49,426 INFO L273 TraceCheckUtils]: 5: Hoare triple {6185#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {6185#true} is VALID [2018-11-18 21:08:49,427 INFO L273 TraceCheckUtils]: 6: Hoare triple {6185#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,427 INFO L273 TraceCheckUtils]: 7: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,428 INFO L273 TraceCheckUtils]: 8: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} assume true; {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,428 INFO L273 TraceCheckUtils]: 9: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,428 INFO L273 TraceCheckUtils]: 10: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,429 INFO L273 TraceCheckUtils]: 11: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} call #t~mem3 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem3, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem3;call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem4, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem4;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem5, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem5; {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,429 INFO L273 TraceCheckUtils]: 12: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,429 INFO L273 TraceCheckUtils]: 13: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} assume true; {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,429 INFO L273 TraceCheckUtils]: 14: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,430 INFO L273 TraceCheckUtils]: 15: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} ~i~0 := 1bv32; {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,430 INFO L273 TraceCheckUtils]: 16: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} assume true; {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,431 INFO L273 TraceCheckUtils]: 17: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,431 INFO L273 TraceCheckUtils]: 18: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,432 INFO L273 TraceCheckUtils]: 19: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} call #t~mem7 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem7, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem7;call #t~mem8 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem8, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem8;call #t~mem9 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem9, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem9; {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,432 INFO L273 TraceCheckUtils]: 20: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} #t~post6 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post6);havoc #t~post6; {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,433 INFO L273 TraceCheckUtils]: 21: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} assume true; {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,433 INFO L273 TraceCheckUtils]: 22: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,434 INFO L273 TraceCheckUtils]: 23: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} ~i~0 := 1bv32; {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,434 INFO L273 TraceCheckUtils]: 24: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} assume true; {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,435 INFO L273 TraceCheckUtils]: 25: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,435 INFO L273 TraceCheckUtils]: 26: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,436 INFO L273 TraceCheckUtils]: 27: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} call #t~mem11 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem11, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem11;call #t~mem12 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem12, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem12;call #t~mem13 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem13, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem13; {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,436 INFO L273 TraceCheckUtils]: 28: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} #t~post10 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post10);havoc #t~post10; {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,437 INFO L273 TraceCheckUtils]: 29: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} assume true; {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,437 INFO L273 TraceCheckUtils]: 30: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:08:49,438 INFO L273 TraceCheckUtils]: 31: Hoare triple {6208#(= |main_~#volArray~0.offset| (_ bv0 32))} ~i~0 := 1bv32; {6284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:49,439 INFO L273 TraceCheckUtils]: 32: Hoare triple {6284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {6284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:49,440 INFO L273 TraceCheckUtils]: 33: Hoare triple {6284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {6284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:49,443 INFO L273 TraceCheckUtils]: 34: Hoare triple {6284#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {6294#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:49,445 INFO L273 TraceCheckUtils]: 35: Hoare triple {6294#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call #t~mem15 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem15, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem15;call #t~mem16 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem16, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem16;call #t~mem17 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem17, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem17; {6298#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-18 21:08:49,445 INFO L273 TraceCheckUtils]: 36: Hoare triple {6298#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)))} #t~post14 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post14);havoc #t~post14; {6298#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-18 21:08:49,446 INFO L273 TraceCheckUtils]: 37: Hoare triple {6298#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume true; {6298#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-18 21:08:49,446 INFO L273 TraceCheckUtils]: 38: Hoare triple {6298#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {6298#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-18 21:08:49,447 INFO L273 TraceCheckUtils]: 39: Hoare triple {6298#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)))} ~i~0 := 0bv32; {6311#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-18 21:08:49,447 INFO L273 TraceCheckUtils]: 40: Hoare triple {6311#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume true; {6311#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-18 21:08:49,448 INFO L273 TraceCheckUtils]: 41: Hoare triple {6311#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {6311#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-18 21:08:49,449 INFO L273 TraceCheckUtils]: 42: Hoare triple {6311#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume #t~short21; {6311#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-18 21:08:49,451 INFO L256 TraceCheckUtils]: 43: Hoare triple {6311#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)))} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} is VALID [2018-11-18 21:08:49,452 INFO L273 TraceCheckUtils]: 44: Hoare triple {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} ~cond := #in~cond; {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} is VALID [2018-11-18 21:08:49,452 INFO L273 TraceCheckUtils]: 45: Hoare triple {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} assume !(0bv32 == ~cond); {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} is VALID [2018-11-18 21:08:49,453 INFO L273 TraceCheckUtils]: 46: Hoare triple {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} assume true; {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} is VALID [2018-11-18 21:08:49,454 INFO L268 TraceCheckUtils]: 47: Hoare quadruple {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} {6311#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)))} #145#return; {6311#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-18 21:08:49,455 INFO L273 TraceCheckUtils]: 48: Hoare triple {6311#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)))} havoc #t~mem19;havoc #t~mem20;havoc #t~short21; {6311#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-18 21:08:49,455 INFO L273 TraceCheckUtils]: 49: Hoare triple {6311#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)))} #t~post18 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post18);havoc #t~post18; {6294#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:49,456 INFO L273 TraceCheckUtils]: 50: Hoare triple {6294#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {6294#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:49,457 INFO L273 TraceCheckUtils]: 51: Hoare triple {6294#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {6294#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:49,458 INFO L273 TraceCheckUtils]: 52: Hoare triple {6294#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume #t~short21; {6294#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:49,460 INFO L256 TraceCheckUtils]: 53: Hoare triple {6294#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} is VALID [2018-11-18 21:08:49,461 INFO L273 TraceCheckUtils]: 54: Hoare triple {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} ~cond := #in~cond; {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} is VALID [2018-11-18 21:08:49,461 INFO L273 TraceCheckUtils]: 55: Hoare triple {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} assume !(0bv32 == ~cond); {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} is VALID [2018-11-18 21:08:49,462 INFO L273 TraceCheckUtils]: 56: Hoare triple {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} assume true; {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} is VALID [2018-11-18 21:08:49,463 INFO L268 TraceCheckUtils]: 57: Hoare quadruple {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} {6294#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #145#return; {6294#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:49,464 INFO L273 TraceCheckUtils]: 58: Hoare triple {6294#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} havoc #t~mem19;havoc #t~mem20;havoc #t~short21; {6294#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:49,465 INFO L273 TraceCheckUtils]: 59: Hoare triple {6294#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post18 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post18);havoc #t~post18; {6373#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))))} is VALID [2018-11-18 21:08:49,466 INFO L273 TraceCheckUtils]: 60: Hoare triple {6373#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))))} assume true; {6373#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))))} is VALID [2018-11-18 21:08:49,467 INFO L273 TraceCheckUtils]: 61: Hoare triple {6373#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {6373#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))))} is VALID [2018-11-18 21:08:49,468 INFO L273 TraceCheckUtils]: 62: Hoare triple {6373#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))))} assume #t~short21; {6373#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))))} is VALID [2018-11-18 21:08:49,470 INFO L256 TraceCheckUtils]: 63: Hoare triple {6373#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))))} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} is VALID [2018-11-18 21:08:49,471 INFO L273 TraceCheckUtils]: 64: Hoare triple {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} ~cond := #in~cond; {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} is VALID [2018-11-18 21:08:49,471 INFO L273 TraceCheckUtils]: 65: Hoare triple {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} assume !(0bv32 == ~cond); {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} is VALID [2018-11-18 21:08:49,472 INFO L273 TraceCheckUtils]: 66: Hoare triple {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} assume true; {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} is VALID [2018-11-18 21:08:49,473 INFO L268 TraceCheckUtils]: 67: Hoare quadruple {6324#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_7| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_7|) (_ bv12 32))))} {6373#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))))} #145#return; {6373#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))))} is VALID [2018-11-18 21:08:49,474 INFO L273 TraceCheckUtils]: 68: Hoare triple {6373#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))))} havoc #t~mem19;havoc #t~mem20;havoc #t~short21; {6373#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))))} is VALID [2018-11-18 21:08:49,476 INFO L273 TraceCheckUtils]: 69: Hoare triple {6373#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))))} #t~post18 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post18);havoc #t~post18; {6404#(and (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967260 32))) (_ bv0 32)))} is VALID [2018-11-18 21:08:49,477 INFO L273 TraceCheckUtils]: 70: Hoare triple {6404#(and (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967260 32))) (_ bv0 32)))} assume true; {6404#(and (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967260 32))) (_ bv0 32)))} is VALID [2018-11-18 21:08:49,478 INFO L273 TraceCheckUtils]: 71: Hoare triple {6404#(and (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967260 32))) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {6404#(and (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967260 32))) (_ bv0 32)))} is VALID [2018-11-18 21:08:49,479 INFO L273 TraceCheckUtils]: 72: Hoare triple {6404#(and (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967260 32))) (_ bv0 32)))} assume !#t~short21;call #t~mem20 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := 0bv32 == #t~mem20; {6414#|main_#t~short21|} is VALID [2018-11-18 21:08:49,480 INFO L256 TraceCheckUtils]: 73: Hoare triple {6414#|main_#t~short21|} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {6418#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:49,480 INFO L273 TraceCheckUtils]: 74: Hoare triple {6418#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {6422#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:49,481 INFO L273 TraceCheckUtils]: 75: Hoare triple {6422#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 == ~cond; {6186#false} is VALID [2018-11-18 21:08:49,481 INFO L273 TraceCheckUtils]: 76: Hoare triple {6186#false} assume !false; {6186#false} is VALID [2018-11-18 21:08:49,493 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-11-18 21:08:49,493 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 21:08:49,924 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 15 [2018-11-18 21:08:49,963 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 3 [2018-11-18 21:08:49,965 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:08:49,967 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:49,970 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:49,971 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:17, output treesize:7 [2018-11-18 21:08:49,976 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-18 21:08:50,038 INFO L273 TraceCheckUtils]: 76: Hoare triple {6186#false} assume !false; {6186#false} is VALID [2018-11-18 21:08:50,039 INFO L273 TraceCheckUtils]: 75: Hoare triple {6432#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} assume 0bv32 == ~cond; {6186#false} is VALID [2018-11-18 21:08:50,039 INFO L273 TraceCheckUtils]: 74: Hoare triple {6436#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} ~cond := #in~cond; {6432#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} is VALID [2018-11-18 21:08:50,040 INFO L256 TraceCheckUtils]: 73: Hoare triple {6414#|main_#t~short21|} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {6436#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-18 21:08:50,041 INFO L273 TraceCheckUtils]: 72: Hoare triple {6443#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume !#t~short21;call #t~mem20 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := 0bv32 == #t~mem20; {6414#|main_#t~short21|} is VALID [2018-11-18 21:08:50,041 INFO L273 TraceCheckUtils]: 71: Hoare triple {6443#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {6443#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-18 21:08:50,042 INFO L273 TraceCheckUtils]: 70: Hoare triple {6443#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume true; {6443#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-18 21:08:50,267 INFO L273 TraceCheckUtils]: 69: Hoare triple {6453#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} #t~post18 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post18);havoc #t~post18; {6443#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-18 21:08:50,288 INFO L273 TraceCheckUtils]: 68: Hoare triple {6453#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} havoc #t~mem19;havoc #t~mem20;havoc #t~short21; {6453#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-18 21:08:50,289 INFO L268 TraceCheckUtils]: 67: Hoare quadruple {6185#true} {6453#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} #145#return; {6453#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-18 21:08:50,290 INFO L273 TraceCheckUtils]: 66: Hoare triple {6185#true} assume true; {6185#true} is VALID [2018-11-18 21:08:50,290 INFO L273 TraceCheckUtils]: 65: Hoare triple {6185#true} assume !(0bv32 == ~cond); {6185#true} is VALID [2018-11-18 21:08:50,290 INFO L273 TraceCheckUtils]: 64: Hoare triple {6185#true} ~cond := #in~cond; {6185#true} is VALID [2018-11-18 21:08:50,290 INFO L256 TraceCheckUtils]: 63: Hoare triple {6453#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {6185#true} is VALID [2018-11-18 21:08:50,290 INFO L273 TraceCheckUtils]: 62: Hoare triple {6453#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} assume #t~short21; {6453#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-18 21:08:50,291 INFO L273 TraceCheckUtils]: 61: Hoare triple {6453#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {6453#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-18 21:08:50,291 INFO L273 TraceCheckUtils]: 60: Hoare triple {6453#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} assume true; {6453#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-18 21:08:50,603 INFO L273 TraceCheckUtils]: 59: Hoare triple {6484#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} #t~post18 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post18);havoc #t~post18; {6453#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-18 21:08:50,604 INFO L273 TraceCheckUtils]: 58: Hoare triple {6484#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} havoc #t~mem19;havoc #t~mem20;havoc #t~short21; {6484#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} is VALID [2018-11-18 21:08:50,624 INFO L268 TraceCheckUtils]: 57: Hoare quadruple {6185#true} {6484#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} #145#return; {6484#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} is VALID [2018-11-18 21:08:50,624 INFO L273 TraceCheckUtils]: 56: Hoare triple {6185#true} assume true; {6185#true} is VALID [2018-11-18 21:08:50,624 INFO L273 TraceCheckUtils]: 55: Hoare triple {6185#true} assume !(0bv32 == ~cond); {6185#true} is VALID [2018-11-18 21:08:50,624 INFO L273 TraceCheckUtils]: 54: Hoare triple {6185#true} ~cond := #in~cond; {6185#true} is VALID [2018-11-18 21:08:50,625 INFO L256 TraceCheckUtils]: 53: Hoare triple {6484#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {6185#true} is VALID [2018-11-18 21:08:50,644 INFO L273 TraceCheckUtils]: 52: Hoare triple {6484#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} assume #t~short21; {6484#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} is VALID [2018-11-18 21:08:50,657 INFO L273 TraceCheckUtils]: 51: Hoare triple {6484#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {6484#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} is VALID [2018-11-18 21:08:50,664 INFO L273 TraceCheckUtils]: 50: Hoare triple {6484#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} assume true; {6484#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} is VALID [2018-11-18 21:08:50,986 INFO L273 TraceCheckUtils]: 49: Hoare triple {6515#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} #t~post18 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post18);havoc #t~post18; {6484#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} is VALID [2018-11-18 21:08:50,986 INFO L273 TraceCheckUtils]: 48: Hoare triple {6515#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} havoc #t~mem19;havoc #t~mem20;havoc #t~short21; {6515#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} is VALID [2018-11-18 21:08:50,987 INFO L268 TraceCheckUtils]: 47: Hoare quadruple {6185#true} {6515#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} #145#return; {6515#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} is VALID [2018-11-18 21:08:50,987 INFO L273 TraceCheckUtils]: 46: Hoare triple {6185#true} assume true; {6185#true} is VALID [2018-11-18 21:08:50,988 INFO L273 TraceCheckUtils]: 45: Hoare triple {6185#true} assume !(0bv32 == ~cond); {6185#true} is VALID [2018-11-18 21:08:50,988 INFO L273 TraceCheckUtils]: 44: Hoare triple {6185#true} ~cond := #in~cond; {6185#true} is VALID [2018-11-18 21:08:50,988 INFO L256 TraceCheckUtils]: 43: Hoare triple {6515#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {6185#true} is VALID [2018-11-18 21:08:50,989 INFO L273 TraceCheckUtils]: 42: Hoare triple {6515#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} assume #t~short21; {6515#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} is VALID [2018-11-18 21:08:50,989 INFO L273 TraceCheckUtils]: 41: Hoare triple {6515#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {6515#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} is VALID [2018-11-18 21:08:50,990 INFO L273 TraceCheckUtils]: 40: Hoare triple {6515#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} assume true; {6515#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} is VALID [2018-11-18 21:08:50,990 INFO L273 TraceCheckUtils]: 39: Hoare triple {6546#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))))} ~i~0 := 0bv32; {6515#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} is VALID [2018-11-18 21:08:50,990 INFO L273 TraceCheckUtils]: 38: Hoare triple {6546#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {6546#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))))} is VALID [2018-11-18 21:08:50,991 INFO L273 TraceCheckUtils]: 37: Hoare triple {6546#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))))} assume true; {6546#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))))} is VALID [2018-11-18 21:08:50,991 INFO L273 TraceCheckUtils]: 36: Hoare triple {6546#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))))} #t~post14 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post14);havoc #t~post14; {6546#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))))} is VALID [2018-11-18 21:08:50,992 INFO L273 TraceCheckUtils]: 35: Hoare triple {6546#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))))} call #t~mem15 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem15, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem15;call #t~mem16 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem16, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem16;call #t~mem17 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem17, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem17; {6546#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))))} is VALID [2018-11-18 21:08:50,994 INFO L273 TraceCheckUtils]: 34: Hoare triple {6562#(= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {6546#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))))} is VALID [2018-11-18 21:08:50,995 INFO L273 TraceCheckUtils]: 33: Hoare triple {6562#(= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {6562#(= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:50,995 INFO L273 TraceCheckUtils]: 32: Hoare triple {6562#(= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))} assume true; {6562#(= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:50,996 INFO L273 TraceCheckUtils]: 31: Hoare triple {6185#true} ~i~0 := 1bv32; {6562#(= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:50,996 INFO L273 TraceCheckUtils]: 30: Hoare triple {6185#true} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {6185#true} is VALID [2018-11-18 21:08:50,996 INFO L273 TraceCheckUtils]: 29: Hoare triple {6185#true} assume true; {6185#true} is VALID [2018-11-18 21:08:50,997 INFO L273 TraceCheckUtils]: 28: Hoare triple {6185#true} #t~post10 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post10);havoc #t~post10; {6185#true} is VALID [2018-11-18 21:08:50,997 INFO L273 TraceCheckUtils]: 27: Hoare triple {6185#true} call #t~mem11 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem11, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem11;call #t~mem12 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem12, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem12;call #t~mem13 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem13, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem13; {6185#true} is VALID [2018-11-18 21:08:50,997 INFO L273 TraceCheckUtils]: 26: Hoare triple {6185#true} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {6185#true} is VALID [2018-11-18 21:08:50,997 INFO L273 TraceCheckUtils]: 25: Hoare triple {6185#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {6185#true} is VALID [2018-11-18 21:08:50,997 INFO L273 TraceCheckUtils]: 24: Hoare triple {6185#true} assume true; {6185#true} is VALID [2018-11-18 21:08:50,998 INFO L273 TraceCheckUtils]: 23: Hoare triple {6185#true} ~i~0 := 1bv32; {6185#true} is VALID [2018-11-18 21:08:50,998 INFO L273 TraceCheckUtils]: 22: Hoare triple {6185#true} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {6185#true} is VALID [2018-11-18 21:08:50,998 INFO L273 TraceCheckUtils]: 21: Hoare triple {6185#true} assume true; {6185#true} is VALID [2018-11-18 21:08:50,998 INFO L273 TraceCheckUtils]: 20: Hoare triple {6185#true} #t~post6 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post6);havoc #t~post6; {6185#true} is VALID [2018-11-18 21:08:50,998 INFO L273 TraceCheckUtils]: 19: Hoare triple {6185#true} call #t~mem7 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem7, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem7;call #t~mem8 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem8, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem8;call #t~mem9 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem9, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem9; {6185#true} is VALID [2018-11-18 21:08:50,999 INFO L273 TraceCheckUtils]: 18: Hoare triple {6185#true} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {6185#true} is VALID [2018-11-18 21:08:50,999 INFO L273 TraceCheckUtils]: 17: Hoare triple {6185#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {6185#true} is VALID [2018-11-18 21:08:50,999 INFO L273 TraceCheckUtils]: 16: Hoare triple {6185#true} assume true; {6185#true} is VALID [2018-11-18 21:08:50,999 INFO L273 TraceCheckUtils]: 15: Hoare triple {6185#true} ~i~0 := 1bv32; {6185#true} is VALID [2018-11-18 21:08:50,999 INFO L273 TraceCheckUtils]: 14: Hoare triple {6185#true} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {6185#true} is VALID [2018-11-18 21:08:50,999 INFO L273 TraceCheckUtils]: 13: Hoare triple {6185#true} assume true; {6185#true} is VALID [2018-11-18 21:08:51,000 INFO L273 TraceCheckUtils]: 12: Hoare triple {6185#true} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {6185#true} is VALID [2018-11-18 21:08:51,000 INFO L273 TraceCheckUtils]: 11: Hoare triple {6185#true} call #t~mem3 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem3, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem3;call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem4, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem4;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem5, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem5; {6185#true} is VALID [2018-11-18 21:08:51,000 INFO L273 TraceCheckUtils]: 10: Hoare triple {6185#true} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {6185#true} is VALID [2018-11-18 21:08:51,000 INFO L273 TraceCheckUtils]: 9: Hoare triple {6185#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {6185#true} is VALID [2018-11-18 21:08:51,000 INFO L273 TraceCheckUtils]: 8: Hoare triple {6185#true} assume true; {6185#true} is VALID [2018-11-18 21:08:51,000 INFO L273 TraceCheckUtils]: 7: Hoare triple {6185#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {6185#true} is VALID [2018-11-18 21:08:51,000 INFO L273 TraceCheckUtils]: 6: Hoare triple {6185#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {6185#true} is VALID [2018-11-18 21:08:51,001 INFO L273 TraceCheckUtils]: 5: Hoare triple {6185#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {6185#true} is VALID [2018-11-18 21:08:51,001 INFO L256 TraceCheckUtils]: 4: Hoare triple {6185#true} call #t~ret22 := main(); {6185#true} is VALID [2018-11-18 21:08:51,001 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {6185#true} {6185#true} #141#return; {6185#true} is VALID [2018-11-18 21:08:51,001 INFO L273 TraceCheckUtils]: 2: Hoare triple {6185#true} assume true; {6185#true} is VALID [2018-11-18 21:08:51,001 INFO L273 TraceCheckUtils]: 1: Hoare triple {6185#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {6185#true} is VALID [2018-11-18 21:08:51,001 INFO L256 TraceCheckUtils]: 0: Hoare triple {6185#true} call ULTIMATE.init(); {6185#true} is VALID [2018-11-18 21:08:51,008 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 6 proven. 32 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-11-18 21:08:51,010 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 21:08:51,010 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 11] total 21 [2018-11-18 21:08:51,011 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 77 [2018-11-18 21:08:51,011 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:08:51,012 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 21 states. [2018-11-18 21:08:52,386 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 129 edges. 129 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:08:52,386 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-18 21:08:52,386 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-18 21:08:52,387 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=352, Unknown=0, NotChecked=0, Total=420 [2018-11-18 21:08:52,387 INFO L87 Difference]: Start difference. First operand 111 states and 121 transitions. Second operand 21 states. [2018-11-18 21:09:09,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:09,407 INFO L93 Difference]: Finished difference Result 143 states and 158 transitions. [2018-11-18 21:09:09,407 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-11-18 21:09:09,408 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 77 [2018-11-18 21:09:09,408 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:09:09,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2018-11-18 21:09:09,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 120 transitions. [2018-11-18 21:09:09,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2018-11-18 21:09:09,412 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 120 transitions. [2018-11-18 21:09:09,412 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 18 states and 120 transitions. [2018-11-18 21:09:09,854 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 120 edges. 120 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:09:09,858 INFO L225 Difference]: With dead ends: 143 [2018-11-18 21:09:09,858 INFO L226 Difference]: Without dead ends: 141 [2018-11-18 21:09:09,859 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 162 GetRequests, 128 SyntacticMatches, 7 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 211 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=135, Invalid=677, Unknown=0, NotChecked=0, Total=812 [2018-11-18 21:09:09,859 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2018-11-18 21:09:10,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 122. [2018-11-18 21:09:10,300 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:09:10,300 INFO L82 GeneralOperation]: Start isEquivalent. First operand 141 states. Second operand 122 states. [2018-11-18 21:09:10,300 INFO L74 IsIncluded]: Start isIncluded. First operand 141 states. Second operand 122 states. [2018-11-18 21:09:10,300 INFO L87 Difference]: Start difference. First operand 141 states. Second operand 122 states. [2018-11-18 21:09:10,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:10,305 INFO L93 Difference]: Finished difference Result 141 states and 156 transitions. [2018-11-18 21:09:10,305 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 156 transitions. [2018-11-18 21:09:10,305 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:09:10,305 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:09:10,306 INFO L74 IsIncluded]: Start isIncluded. First operand 122 states. Second operand 141 states. [2018-11-18 21:09:10,306 INFO L87 Difference]: Start difference. First operand 122 states. Second operand 141 states. [2018-11-18 21:09:10,309 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:10,309 INFO L93 Difference]: Finished difference Result 141 states and 156 transitions. [2018-11-18 21:09:10,309 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 156 transitions. [2018-11-18 21:09:10,310 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:09:10,310 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:09:10,310 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:09:10,310 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:09:10,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 122 states. [2018-11-18 21:09:10,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 134 transitions. [2018-11-18 21:09:10,313 INFO L78 Accepts]: Start accepts. Automaton has 122 states and 134 transitions. Word has length 77 [2018-11-18 21:09:10,313 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:09:10,314 INFO L480 AbstractCegarLoop]: Abstraction has 122 states and 134 transitions. [2018-11-18 21:09:10,314 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-18 21:09:10,314 INFO L276 IsEmpty]: Start isEmpty. Operand 122 states and 134 transitions. [2018-11-18 21:09:10,315 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-11-18 21:09:10,315 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:09:10,315 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:09:10,315 INFO L423 AbstractCegarLoop]: === Iteration 11 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:09:10,315 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:09:10,316 INFO L82 PathProgramCache]: Analyzing trace with hash 1709817898, now seen corresponding path program 4 times [2018-11-18 21:09:10,316 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:09:10,316 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:09:10,336 INFO L101 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 21:09:10,451 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 21:09:10,452 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 21:09:10,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:09:10,514 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:09:11,132 WARN L180 SmtUtils]: Spent 100.00 ms on a formula simplification that was a NOOP. DAG size: 14 [2018-11-18 21:09:11,436 WARN L180 SmtUtils]: Spent 113.00 ms on a formula simplification that was a NOOP. DAG size: 16 [2018-11-18 21:09:11,782 WARN L180 SmtUtils]: Spent 126.00 ms on a formula simplification that was a NOOP. DAG size: 14 [2018-11-18 21:09:12,457 INFO L256 TraceCheckUtils]: 0: Hoare triple {7304#true} call ULTIMATE.init(); {7304#true} is VALID [2018-11-18 21:09:12,458 INFO L273 TraceCheckUtils]: 1: Hoare triple {7304#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {7304#true} is VALID [2018-11-18 21:09:12,458 INFO L273 TraceCheckUtils]: 2: Hoare triple {7304#true} assume true; {7304#true} is VALID [2018-11-18 21:09:12,458 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {7304#true} {7304#true} #141#return; {7304#true} is VALID [2018-11-18 21:09:12,458 INFO L256 TraceCheckUtils]: 4: Hoare triple {7304#true} call #t~ret22 := main(); {7304#true} is VALID [2018-11-18 21:09:12,458 INFO L273 TraceCheckUtils]: 5: Hoare triple {7304#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {7304#true} is VALID [2018-11-18 21:09:12,458 INFO L273 TraceCheckUtils]: 6: Hoare triple {7304#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {7327#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} is VALID [2018-11-18 21:09:12,459 INFO L273 TraceCheckUtils]: 7: Hoare triple {7327#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {7331#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:12,459 INFO L273 TraceCheckUtils]: 8: Hoare triple {7331#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {7331#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:12,460 INFO L273 TraceCheckUtils]: 9: Hoare triple {7331#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {7331#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:12,460 INFO L273 TraceCheckUtils]: 10: Hoare triple {7331#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {7331#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:12,461 INFO L273 TraceCheckUtils]: 11: Hoare triple {7331#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call #t~mem3 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem3, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem3;call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem4, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem4;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem5, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem5; {7331#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:12,462 INFO L273 TraceCheckUtils]: 12: Hoare triple {7331#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {7347#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-18 21:09:12,463 INFO L273 TraceCheckUtils]: 13: Hoare triple {7347#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (_ bv2 32) main_~i~0))} assume true; {7347#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-18 21:09:12,463 INFO L273 TraceCheckUtils]: 14: Hoare triple {7347#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (_ bv2 32) main_~i~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,464 INFO L273 TraceCheckUtils]: 15: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} ~i~0 := 1bv32; {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,465 INFO L273 TraceCheckUtils]: 16: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume true; {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,466 INFO L273 TraceCheckUtils]: 17: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,467 INFO L273 TraceCheckUtils]: 18: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,468 INFO L273 TraceCheckUtils]: 19: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} call #t~mem7 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem7, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem7;call #t~mem8 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem8, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem8;call #t~mem9 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem9, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem9; {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,469 INFO L273 TraceCheckUtils]: 20: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} #t~post6 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post6);havoc #t~post6; {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,469 INFO L273 TraceCheckUtils]: 21: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume true; {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,470 INFO L273 TraceCheckUtils]: 22: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,471 INFO L273 TraceCheckUtils]: 23: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} ~i~0 := 1bv32; {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,472 INFO L273 TraceCheckUtils]: 24: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume true; {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,472 INFO L273 TraceCheckUtils]: 25: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,473 INFO L273 TraceCheckUtils]: 26: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,474 INFO L273 TraceCheckUtils]: 27: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} call #t~mem11 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem11, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem11;call #t~mem12 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem12, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem12;call #t~mem13 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem13, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem13; {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,475 INFO L273 TraceCheckUtils]: 28: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} #t~post10 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post10);havoc #t~post10; {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,476 INFO L273 TraceCheckUtils]: 29: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume true; {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,477 INFO L273 TraceCheckUtils]: 30: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,477 INFO L273 TraceCheckUtils]: 31: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} ~i~0 := 1bv32; {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,478 INFO L273 TraceCheckUtils]: 32: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume true; {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,479 INFO L273 TraceCheckUtils]: 33: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,480 INFO L273 TraceCheckUtils]: 34: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,481 INFO L273 TraceCheckUtils]: 35: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} call #t~mem15 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem15, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem15;call #t~mem16 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem16, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem16;call #t~mem17 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem17, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem17; {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,482 INFO L273 TraceCheckUtils]: 36: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} #t~post14 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post14);havoc #t~post14; {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,482 INFO L273 TraceCheckUtils]: 37: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume true; {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,483 INFO L273 TraceCheckUtils]: 38: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,484 INFO L273 TraceCheckUtils]: 39: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} ~i~0 := 0bv32; {7430#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,485 INFO L273 TraceCheckUtils]: 40: Hoare triple {7430#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume true; {7430#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,486 INFO L273 TraceCheckUtils]: 41: Hoare triple {7430#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {7430#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,487 INFO L273 TraceCheckUtils]: 42: Hoare triple {7430#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume #t~short21; {7430#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,488 INFO L256 TraceCheckUtils]: 43: Hoare triple {7430#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,489 INFO L273 TraceCheckUtils]: 44: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} ~cond := #in~cond; {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,489 INFO L273 TraceCheckUtils]: 45: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume !(0bv32 == ~cond); {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,490 INFO L273 TraceCheckUtils]: 46: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume true; {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,509 INFO L268 TraceCheckUtils]: 47: Hoare quadruple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} {7430#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} #145#return; {7430#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,523 INFO L273 TraceCheckUtils]: 48: Hoare triple {7430#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} havoc #t~mem19;havoc #t~mem20;havoc #t~short21; {7430#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,539 INFO L273 TraceCheckUtils]: 49: Hoare triple {7430#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} #t~post18 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post18);havoc #t~post18; {7461#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:12,554 INFO L273 TraceCheckUtils]: 50: Hoare triple {7461#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {7461#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:12,563 INFO L273 TraceCheckUtils]: 51: Hoare triple {7461#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {7461#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:12,578 INFO L273 TraceCheckUtils]: 52: Hoare triple {7461#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume #t~short21; {7461#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:12,592 INFO L256 TraceCheckUtils]: 53: Hoare triple {7461#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,599 INFO L273 TraceCheckUtils]: 54: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} ~cond := #in~cond; {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,600 INFO L273 TraceCheckUtils]: 55: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume !(0bv32 == ~cond); {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,604 INFO L273 TraceCheckUtils]: 56: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume true; {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,604 INFO L268 TraceCheckUtils]: 57: Hoare quadruple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} {7461#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #145#return; {7461#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:12,605 INFO L273 TraceCheckUtils]: 58: Hoare triple {7461#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} havoc #t~mem19;havoc #t~mem20;havoc #t~short21; {7461#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:12,606 INFO L273 TraceCheckUtils]: 59: Hoare triple {7461#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post18 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post18);havoc #t~post18; {7492#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (_ bv2 32) main_~i~0) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,606 INFO L273 TraceCheckUtils]: 60: Hoare triple {7492#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (_ bv2 32) main_~i~0) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume true; {7492#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (_ bv2 32) main_~i~0) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,607 INFO L273 TraceCheckUtils]: 61: Hoare triple {7492#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (_ bv2 32) main_~i~0) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {7492#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (_ bv2 32) main_~i~0) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,607 INFO L273 TraceCheckUtils]: 62: Hoare triple {7492#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (_ bv2 32) main_~i~0) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume #t~short21; {7492#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (_ bv2 32) main_~i~0) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,608 INFO L256 TraceCheckUtils]: 63: Hoare triple {7492#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (_ bv2 32) main_~i~0) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,609 INFO L273 TraceCheckUtils]: 64: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} ~cond := #in~cond; {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,610 INFO L273 TraceCheckUtils]: 65: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume !(0bv32 == ~cond); {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,610 INFO L273 TraceCheckUtils]: 66: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume true; {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,611 INFO L268 TraceCheckUtils]: 67: Hoare quadruple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} {7492#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (_ bv2 32) main_~i~0) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} #145#return; {7492#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (_ bv2 32) main_~i~0) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,612 INFO L273 TraceCheckUtils]: 68: Hoare triple {7492#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (_ bv2 32) main_~i~0) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} havoc #t~mem19;havoc #t~mem20;havoc #t~short21; {7492#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (_ bv2 32) main_~i~0) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,613 INFO L273 TraceCheckUtils]: 69: Hoare triple {7492#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (_ bv2 32) main_~i~0) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} #t~post18 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post18);havoc #t~post18; {7523#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,614 INFO L273 TraceCheckUtils]: 70: Hoare triple {7523#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume true; {7523#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,615 INFO L273 TraceCheckUtils]: 71: Hoare triple {7523#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {7523#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,616 INFO L273 TraceCheckUtils]: 72: Hoare triple {7523#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume #t~short21; {7523#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,617 INFO L256 TraceCheckUtils]: 73: Hoare triple {7523#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,618 INFO L273 TraceCheckUtils]: 74: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} ~cond := #in~cond; {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,618 INFO L273 TraceCheckUtils]: 75: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume !(0bv32 == ~cond); {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,619 INFO L273 TraceCheckUtils]: 76: Hoare triple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume true; {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,620 INFO L268 TraceCheckUtils]: 77: Hoare quadruple {7354#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} {7523#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} #145#return; {7523#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,621 INFO L273 TraceCheckUtils]: 78: Hoare triple {7523#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} havoc #t~mem19;havoc #t~mem20;havoc #t~short21; {7523#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,622 INFO L273 TraceCheckUtils]: 79: Hoare triple {7523#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} #t~post18 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post18);havoc #t~post18; {7554#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (= (_ bv4 32) main_~i~0) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,622 INFO L273 TraceCheckUtils]: 80: Hoare triple {7554#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (= (_ bv4 32) main_~i~0) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume true; {7554#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (= (_ bv4 32) main_~i~0) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:12,643 INFO L273 TraceCheckUtils]: 81: Hoare triple {7554#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (= (_ bv4 32) main_~i~0) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {7305#false} is VALID [2018-11-18 21:09:12,643 INFO L273 TraceCheckUtils]: 82: Hoare triple {7305#false} assume !#t~short21;call #t~mem20 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := 0bv32 == #t~mem20; {7305#false} is VALID [2018-11-18 21:09:12,643 INFO L256 TraceCheckUtils]: 83: Hoare triple {7305#false} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {7305#false} is VALID [2018-11-18 21:09:12,644 INFO L273 TraceCheckUtils]: 84: Hoare triple {7305#false} ~cond := #in~cond; {7305#false} is VALID [2018-11-18 21:09:12,644 INFO L273 TraceCheckUtils]: 85: Hoare triple {7305#false} assume 0bv32 == ~cond; {7305#false} is VALID [2018-11-18 21:09:12,644 INFO L273 TraceCheckUtils]: 86: Hoare triple {7305#false} assume !false; {7305#false} is VALID [2018-11-18 21:09:12,665 INFO L134 CoverageAnalysis]: Checked inductivity of 92 backedges. 16 proven. 46 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-11-18 21:09:12,665 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 21:09:14,988 INFO L273 TraceCheckUtils]: 86: Hoare triple {7305#false} assume !false; {7305#false} is VALID [2018-11-18 21:09:14,989 INFO L273 TraceCheckUtils]: 85: Hoare triple {7305#false} assume 0bv32 == ~cond; {7305#false} is VALID [2018-11-18 21:09:14,989 INFO L273 TraceCheckUtils]: 84: Hoare triple {7305#false} ~cond := #in~cond; {7305#false} is VALID [2018-11-18 21:09:14,989 INFO L256 TraceCheckUtils]: 83: Hoare triple {7305#false} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {7305#false} is VALID [2018-11-18 21:09:14,989 INFO L273 TraceCheckUtils]: 82: Hoare triple {7305#false} assume !#t~short21;call #t~mem20 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := 0bv32 == #t~mem20; {7305#false} is VALID [2018-11-18 21:09:14,990 INFO L273 TraceCheckUtils]: 81: Hoare triple {7591#(not (bvslt main_~i~0 ~CELLCOUNT~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {7305#false} is VALID [2018-11-18 21:09:14,990 INFO L273 TraceCheckUtils]: 80: Hoare triple {7591#(not (bvslt main_~i~0 ~CELLCOUNT~0))} assume true; {7591#(not (bvslt main_~i~0 ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:14,992 INFO L273 TraceCheckUtils]: 79: Hoare triple {7598#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} #t~post18 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post18);havoc #t~post18; {7591#(not (bvslt main_~i~0 ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:14,992 INFO L273 TraceCheckUtils]: 78: Hoare triple {7598#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} havoc #t~mem19;havoc #t~mem20;havoc #t~short21; {7598#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:14,993 INFO L268 TraceCheckUtils]: 77: Hoare quadruple {7304#true} {7598#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} #145#return; {7598#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:14,993 INFO L273 TraceCheckUtils]: 76: Hoare triple {7304#true} assume true; {7304#true} is VALID [2018-11-18 21:09:14,993 INFO L273 TraceCheckUtils]: 75: Hoare triple {7304#true} assume !(0bv32 == ~cond); {7304#true} is VALID [2018-11-18 21:09:14,993 INFO L273 TraceCheckUtils]: 74: Hoare triple {7304#true} ~cond := #in~cond; {7304#true} is VALID [2018-11-18 21:09:14,993 INFO L256 TraceCheckUtils]: 73: Hoare triple {7598#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {7304#true} is VALID [2018-11-18 21:09:14,994 INFO L273 TraceCheckUtils]: 72: Hoare triple {7598#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} assume #t~short21; {7598#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:14,994 INFO L273 TraceCheckUtils]: 71: Hoare triple {7598#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {7598#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:14,995 INFO L273 TraceCheckUtils]: 70: Hoare triple {7598#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} assume true; {7598#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,017 INFO L273 TraceCheckUtils]: 69: Hoare triple {7629#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} #t~post18 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post18);havoc #t~post18; {7598#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,018 INFO L273 TraceCheckUtils]: 68: Hoare triple {7629#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} havoc #t~mem19;havoc #t~mem20;havoc #t~short21; {7629#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,019 INFO L268 TraceCheckUtils]: 67: Hoare quadruple {7304#true} {7629#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} #145#return; {7629#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,019 INFO L273 TraceCheckUtils]: 66: Hoare triple {7304#true} assume true; {7304#true} is VALID [2018-11-18 21:09:15,019 INFO L273 TraceCheckUtils]: 65: Hoare triple {7304#true} assume !(0bv32 == ~cond); {7304#true} is VALID [2018-11-18 21:09:15,019 INFO L273 TraceCheckUtils]: 64: Hoare triple {7304#true} ~cond := #in~cond; {7304#true} is VALID [2018-11-18 21:09:15,019 INFO L256 TraceCheckUtils]: 63: Hoare triple {7629#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {7304#true} is VALID [2018-11-18 21:09:15,019 INFO L273 TraceCheckUtils]: 62: Hoare triple {7629#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} assume #t~short21; {7629#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,020 INFO L273 TraceCheckUtils]: 61: Hoare triple {7629#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {7629#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,020 INFO L273 TraceCheckUtils]: 60: Hoare triple {7629#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} assume true; {7629#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,051 INFO L273 TraceCheckUtils]: 59: Hoare triple {7660#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~CELLCOUNT~0))} #t~post18 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post18);havoc #t~post18; {7629#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,052 INFO L273 TraceCheckUtils]: 58: Hoare triple {7660#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~CELLCOUNT~0))} havoc #t~mem19;havoc #t~mem20;havoc #t~short21; {7660#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,053 INFO L268 TraceCheckUtils]: 57: Hoare quadruple {7304#true} {7660#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~CELLCOUNT~0))} #145#return; {7660#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,053 INFO L273 TraceCheckUtils]: 56: Hoare triple {7304#true} assume true; {7304#true} is VALID [2018-11-18 21:09:15,053 INFO L273 TraceCheckUtils]: 55: Hoare triple {7304#true} assume !(0bv32 == ~cond); {7304#true} is VALID [2018-11-18 21:09:15,053 INFO L273 TraceCheckUtils]: 54: Hoare triple {7304#true} ~cond := #in~cond; {7304#true} is VALID [2018-11-18 21:09:15,053 INFO L256 TraceCheckUtils]: 53: Hoare triple {7660#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~CELLCOUNT~0))} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {7304#true} is VALID [2018-11-18 21:09:15,053 INFO L273 TraceCheckUtils]: 52: Hoare triple {7660#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~CELLCOUNT~0))} assume #t~short21; {7660#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,054 INFO L273 TraceCheckUtils]: 51: Hoare triple {7660#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~CELLCOUNT~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {7660#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,054 INFO L273 TraceCheckUtils]: 50: Hoare triple {7660#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~CELLCOUNT~0))} assume true; {7660#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,077 INFO L273 TraceCheckUtils]: 49: Hoare triple {7691#(not (bvslt (bvadd main_~i~0 (_ bv4 32)) ~CELLCOUNT~0))} #t~post18 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post18);havoc #t~post18; {7660#(not (bvslt (bvadd main_~i~0 (_ bv3 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,078 INFO L273 TraceCheckUtils]: 48: Hoare triple {7691#(not (bvslt (bvadd main_~i~0 (_ bv4 32)) ~CELLCOUNT~0))} havoc #t~mem19;havoc #t~mem20;havoc #t~short21; {7691#(not (bvslt (bvadd main_~i~0 (_ bv4 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,078 INFO L268 TraceCheckUtils]: 47: Hoare quadruple {7304#true} {7691#(not (bvslt (bvadd main_~i~0 (_ bv4 32)) ~CELLCOUNT~0))} #145#return; {7691#(not (bvslt (bvadd main_~i~0 (_ bv4 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,078 INFO L273 TraceCheckUtils]: 46: Hoare triple {7304#true} assume true; {7304#true} is VALID [2018-11-18 21:09:15,079 INFO L273 TraceCheckUtils]: 45: Hoare triple {7304#true} assume !(0bv32 == ~cond); {7304#true} is VALID [2018-11-18 21:09:15,079 INFO L273 TraceCheckUtils]: 44: Hoare triple {7304#true} ~cond := #in~cond; {7304#true} is VALID [2018-11-18 21:09:15,079 INFO L256 TraceCheckUtils]: 43: Hoare triple {7691#(not (bvslt (bvadd main_~i~0 (_ bv4 32)) ~CELLCOUNT~0))} call __VERIFIER_assert((if #t~short21 then 1bv32 else 0bv32)); {7304#true} is VALID [2018-11-18 21:09:15,079 INFO L273 TraceCheckUtils]: 42: Hoare triple {7691#(not (bvslt (bvadd main_~i~0 (_ bv4 32)) ~CELLCOUNT~0))} assume #t~short21; {7691#(not (bvslt (bvadd main_~i~0 (_ bv4 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,079 INFO L273 TraceCheckUtils]: 41: Hoare triple {7691#(not (bvslt (bvadd main_~i~0 (_ bv4 32)) ~CELLCOUNT~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem19 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short21 := ~bvsge32(#t~mem19, ~MINVAL~0); {7691#(not (bvslt (bvadd main_~i~0 (_ bv4 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,080 INFO L273 TraceCheckUtils]: 40: Hoare triple {7691#(not (bvslt (bvadd main_~i~0 (_ bv4 32)) ~CELLCOUNT~0))} assume true; {7691#(not (bvslt (bvadd main_~i~0 (_ bv4 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,080 INFO L273 TraceCheckUtils]: 39: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} ~i~0 := 0bv32; {7691#(not (bvslt (bvadd main_~i~0 (_ bv4 32)) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,080 INFO L273 TraceCheckUtils]: 38: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,081 INFO L273 TraceCheckUtils]: 37: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} assume true; {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,081 INFO L273 TraceCheckUtils]: 36: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} #t~post14 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post14);havoc #t~post14; {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,082 INFO L273 TraceCheckUtils]: 35: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} call #t~mem15 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem15, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem15;call #t~mem16 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem16, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem16;call #t~mem17 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem17, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem17; {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,082 INFO L273 TraceCheckUtils]: 34: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32); {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,083 INFO L273 TraceCheckUtils]: 33: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,083 INFO L273 TraceCheckUtils]: 32: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} assume true; {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,084 INFO L273 TraceCheckUtils]: 31: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} ~i~0 := 1bv32; {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,084 INFO L273 TraceCheckUtils]: 30: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,085 INFO L273 TraceCheckUtils]: 29: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} assume true; {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,085 INFO L273 TraceCheckUtils]: 28: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} #t~post10 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post10);havoc #t~post10; {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,086 INFO L273 TraceCheckUtils]: 27: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} call #t~mem11 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem11, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem11;call #t~mem12 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem12, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem12;call #t~mem13 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem13, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem13; {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,087 INFO L273 TraceCheckUtils]: 26: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32); {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,088 INFO L273 TraceCheckUtils]: 25: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,088 INFO L273 TraceCheckUtils]: 24: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} assume true; {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,089 INFO L273 TraceCheckUtils]: 23: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} ~i~0 := 1bv32; {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,089 INFO L273 TraceCheckUtils]: 22: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,090 INFO L273 TraceCheckUtils]: 21: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} assume true; {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,090 INFO L273 TraceCheckUtils]: 20: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} #t~post6 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post6);havoc #t~post6; {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,090 INFO L273 TraceCheckUtils]: 19: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} call #t~mem7 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);call write~intINTTYPE4(#t~mem7, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32);havoc #t~mem7;call #t~mem8 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem8, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem8;call #t~mem9 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem9, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem9; {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,091 INFO L273 TraceCheckUtils]: 18: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32); {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,091 INFO L273 TraceCheckUtils]: 17: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,091 INFO L273 TraceCheckUtils]: 16: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} assume true; {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,092 INFO L273 TraceCheckUtils]: 15: Hoare triple {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} ~i~0 := 1bv32; {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,092 INFO L273 TraceCheckUtils]: 14: Hoare triple {7798#(or (not (bvslt (_ bv4 32) ~CELLCOUNT~0)) (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32))))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {7722#(not (bvslt (_ bv4 32) ~CELLCOUNT~0))} is VALID [2018-11-18 21:09:15,093 INFO L273 TraceCheckUtils]: 13: Hoare triple {7798#(or (not (bvslt (_ bv4 32) ~CELLCOUNT~0)) (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32))))} assume true; {7798#(or (not (bvslt (_ bv4 32) ~CELLCOUNT~0)) (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32))))} is VALID [2018-11-18 21:09:15,110 INFO L273 TraceCheckUtils]: 12: Hoare triple {7805#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (not (bvslt (_ bv4 32) ~CELLCOUNT~0)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {7798#(or (not (bvslt (_ bv4 32) ~CELLCOUNT~0)) (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32))))} is VALID [2018-11-18 21:09:15,110 INFO L273 TraceCheckUtils]: 11: Hoare triple {7805#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (not (bvslt (_ bv4 32) ~CELLCOUNT~0)))} call #t~mem3 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);call write~intINTTYPE4(#t~mem3, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 3bv32))), 4bv32);havoc #t~mem3;call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);call write~intINTTYPE4(#t~mem4, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 2bv32))), 4bv32);havoc #t~mem4;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);call write~intINTTYPE4(#t~mem5, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 1bv32))), 4bv32);havoc #t~mem5; {7805#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (not (bvslt (_ bv4 32) ~CELLCOUNT~0)))} is VALID [2018-11-18 21:09:15,111 INFO L273 TraceCheckUtils]: 10: Hoare triple {7805#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (not (bvslt (_ bv4 32) ~CELLCOUNT~0)))} assume ~bvsge32(~CCCELVOL4~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL4~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), 4bv32))), 4bv32); {7805#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (not (bvslt (_ bv4 32) ~CELLCOUNT~0)))} is VALID [2018-11-18 21:09:15,111 INFO L273 TraceCheckUtils]: 9: Hoare triple {7815#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (not (bvslt (_ bv4 32) ~CELLCOUNT~0)) (not (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {7805#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (not (bvslt (_ bv4 32) ~CELLCOUNT~0)))} is VALID [2018-11-18 21:09:15,111 INFO L273 TraceCheckUtils]: 8: Hoare triple {7815#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (not (bvslt (_ bv4 32) ~CELLCOUNT~0)) (not (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} assume true; {7815#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (not (bvslt (_ bv4 32) ~CELLCOUNT~0)) (not (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:15,130 INFO L273 TraceCheckUtils]: 7: Hoare triple {7304#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {7815#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv4 32))) (not (bvslt (_ bv4 32) ~CELLCOUNT~0)) (not (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv4 32)))))} is VALID [2018-11-18 21:09:15,131 INFO L273 TraceCheckUtils]: 6: Hoare triple {7304#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL4~0 := 5bv32;~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {7304#true} is VALID [2018-11-18 21:09:15,131 INFO L273 TraceCheckUtils]: 5: Hoare triple {7304#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {7304#true} is VALID [2018-11-18 21:09:15,131 INFO L256 TraceCheckUtils]: 4: Hoare triple {7304#true} call #t~ret22 := main(); {7304#true} is VALID [2018-11-18 21:09:15,131 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {7304#true} {7304#true} #141#return; {7304#true} is VALID [2018-11-18 21:09:15,131 INFO L273 TraceCheckUtils]: 2: Hoare triple {7304#true} assume true; {7304#true} is VALID [2018-11-18 21:09:15,131 INFO L273 TraceCheckUtils]: 1: Hoare triple {7304#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {7304#true} is VALID [2018-11-18 21:09:15,131 INFO L256 TraceCheckUtils]: 0: Hoare triple {7304#true} call ULTIMATE.init(); {7304#true} is VALID [2018-11-18 21:09:15,139 INFO L134 CoverageAnalysis]: Checked inductivity of 92 backedges. 16 proven. 46 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-11-18 21:09:15,144 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 21:09:15,144 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 20 [2018-11-18 21:09:15,145 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 87 [2018-11-18 21:09:15,145 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:09:15,145 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 20 states. [2018-11-18 21:09:16,563 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 139 edges. 139 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:09:16,564 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-18 21:09:16,564 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-18 21:09:16,564 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=103, Invalid=277, Unknown=0, NotChecked=0, Total=380 [2018-11-18 21:09:16,564 INFO L87 Difference]: Start difference. First operand 122 states and 134 transitions. Second operand 20 states. [2018-11-18 21:09:22,413 WARN L180 SmtUtils]: Spent 171.00 ms on a formula simplification that was a NOOP. DAG size: 14 [2018-11-18 21:09:22,879 WARN L180 SmtUtils]: Spent 145.00 ms on a formula simplification that was a NOOP. DAG size: 11