java -ea -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf -i ../../../trunk/examples/svcomp/array-tiling/nr5_true-unreach-call.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-18e5b2d-m [2018-11-18 21:08:28,778 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 21:08:28,780 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 21:08:28,792 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 21:08:28,792 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 21:08:28,793 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 21:08:28,795 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 21:08:28,797 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 21:08:28,798 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 21:08:28,799 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 21:08:28,800 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 21:08:28,801 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 21:08:28,802 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 21:08:28,803 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 21:08:28,804 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 21:08:28,805 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 21:08:28,806 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 21:08:28,808 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 21:08:28,810 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 21:08:28,811 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 21:08:28,813 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 21:08:28,814 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 21:08:28,816 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2018-11-18 21:08:28,824 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 21:08:28,824 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 21:08:28,825 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 21:08:28,826 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 21:08:28,826 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf [2018-11-18 21:08:28,842 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 21:08:28,842 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 21:08:28,843 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-18 21:08:28,843 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-11-18 21:08:28,844 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 21:08:28,844 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 21:08:28,844 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 21:08:28,845 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 21:08:28,845 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 21:08:28,845 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 21:08:28,845 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 21:08:28,845 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-18 21:08:28,846 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-18 21:08:28,846 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-18 21:08:28,846 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-18 21:08:28,846 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-18 21:08:28,846 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 21:08:28,847 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 21:08:28,847 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 21:08:28,847 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-18 21:08:28,847 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 21:08:28,847 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 21:08:28,848 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-18 21:08:28,848 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-18 21:08:28,848 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 21:08:28,848 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 21:08:28,848 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-18 21:08:28,849 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-18 21:08:28,849 INFO L133 SettingsManager]: * Trace refinement strategy=WOLF [2018-11-18 21:08:28,849 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-18 21:08:28,849 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-11-18 21:08:28,850 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-11-18 21:08:28,850 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-18 21:08:28,917 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 21:08:28,938 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 21:08:28,942 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 21:08:28,944 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 21:08:28,945 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 21:08:28,946 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-tiling/nr5_true-unreach-call.i [2018-11-18 21:08:29,018 INFO L221 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/63ce7a089/2ff9d1cab7284a40a7898715c1b6fd84/FLAG621ef29c9 [2018-11-18 21:08:29,468 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 21:08:29,469 INFO L161 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-tiling/nr5_true-unreach-call.i [2018-11-18 21:08:29,476 INFO L355 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/63ce7a089/2ff9d1cab7284a40a7898715c1b6fd84/FLAG621ef29c9 [2018-11-18 21:08:29,830 INFO L363 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/63ce7a089/2ff9d1cab7284a40a7898715c1b6fd84 [2018-11-18 21:08:29,842 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 21:08:29,844 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-11-18 21:08:29,845 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 21:08:29,845 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 21:08:29,849 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 21:08:29,851 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 09:08:29" (1/1) ... [2018-11-18 21:08:29,854 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@337f61be and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:08:29, skipping insertion in model container [2018-11-18 21:08:29,855 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 09:08:29" (1/1) ... [2018-11-18 21:08:29,866 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 21:08:29,897 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 21:08:30,183 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 21:08:30,189 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 21:08:30,219 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 21:08:30,251 INFO L195 MainTranslator]: Completed translation [2018-11-18 21:08:30,252 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:08:30 WrapperNode [2018-11-18 21:08:30,252 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 21:08:30,253 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 21:08:30,253 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 21:08:30,255 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 21:08:30,268 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:08:30" (1/1) ... [2018-11-18 21:08:30,268 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:08:30" (1/1) ... [2018-11-18 21:08:30,277 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:08:30" (1/1) ... [2018-11-18 21:08:30,278 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:08:30" (1/1) ... [2018-11-18 21:08:30,291 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:08:30" (1/1) ... [2018-11-18 21:08:30,298 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:08:30" (1/1) ... [2018-11-18 21:08:30,302 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:08:30" (1/1) ... [2018-11-18 21:08:30,305 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 21:08:30,306 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 21:08:30,306 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 21:08:30,306 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 21:08:30,307 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:08:30" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 21:08:30,440 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-18 21:08:30,441 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 21:08:30,441 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-11-18 21:08:30,441 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-18 21:08:30,441 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-11-18 21:08:30,442 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assume [2018-11-18 21:08:30,442 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-11-18 21:08:30,442 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-11-18 21:08:30,442 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-18 21:08:30,442 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-18 21:08:30,443 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-18 21:08:30,443 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE4 [2018-11-18 21:08:30,443 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE4 [2018-11-18 21:08:30,443 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-18 21:08:30,444 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 21:08:30,444 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~intINTTYPE4 [2018-11-18 21:08:31,162 INFO L280 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 21:08:31,163 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 09:08:31 BoogieIcfgContainer [2018-11-18 21:08:31,163 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 21:08:31,164 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-18 21:08:31,165 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-18 21:08:31,168 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-18 21:08:31,169 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 18.11 09:08:29" (1/3) ... [2018-11-18 21:08:31,170 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7c88e3b5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 09:08:31, skipping insertion in model container [2018-11-18 21:08:31,170 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:08:30" (2/3) ... [2018-11-18 21:08:31,170 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7c88e3b5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 09:08:31, skipping insertion in model container [2018-11-18 21:08:31,171 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 09:08:31" (3/3) ... [2018-11-18 21:08:31,172 INFO L112 eAbstractionObserver]: Analyzing ICFG nr5_true-unreach-call.i [2018-11-18 21:08:31,182 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-18 21:08:31,190 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-18 21:08:31,206 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-18 21:08:31,240 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 21:08:31,241 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-18 21:08:31,241 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-18 21:08:31,242 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-18 21:08:31,242 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 21:08:31,243 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 21:08:31,243 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-18 21:08:31,243 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 21:08:31,244 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-18 21:08:31,263 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states. [2018-11-18 21:08:31,271 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-18 21:08:31,272 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:08:31,273 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:08:31,275 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:08:31,281 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:08:31,281 INFO L82 PathProgramCache]: Analyzing trace with hash -1065126958, now seen corresponding path program 1 times [2018-11-18 21:08:31,285 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:08:31,286 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:08:31,306 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:08:31,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:08:31,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:08:31,389 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:08:31,686 INFO L256 TraceCheckUtils]: 0: Hoare triple {37#true} call ULTIMATE.init(); {37#true} is VALID [2018-11-18 21:08:31,689 INFO L273 TraceCheckUtils]: 1: Hoare triple {37#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {37#true} is VALID [2018-11-18 21:08:31,690 INFO L273 TraceCheckUtils]: 2: Hoare triple {37#true} assume true; {37#true} is VALID [2018-11-18 21:08:31,691 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {37#true} {37#true} #86#return; {37#true} is VALID [2018-11-18 21:08:31,691 INFO L256 TraceCheckUtils]: 4: Hoare triple {37#true} call #t~ret8 := main(); {37#true} is VALID [2018-11-18 21:08:31,691 INFO L273 TraceCheckUtils]: 5: Hoare triple {37#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {37#true} is VALID [2018-11-18 21:08:31,692 INFO L273 TraceCheckUtils]: 6: Hoare triple {37#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {37#true} is VALID [2018-11-18 21:08:31,692 INFO L273 TraceCheckUtils]: 7: Hoare triple {37#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {37#true} is VALID [2018-11-18 21:08:31,693 INFO L273 TraceCheckUtils]: 8: Hoare triple {37#true} assume !true; {38#false} is VALID [2018-11-18 21:08:31,693 INFO L273 TraceCheckUtils]: 9: Hoare triple {38#false} ~i~0 := 0bv32; {38#false} is VALID [2018-11-18 21:08:31,693 INFO L273 TraceCheckUtils]: 10: Hoare triple {38#false} assume true; {38#false} is VALID [2018-11-18 21:08:31,694 INFO L273 TraceCheckUtils]: 11: Hoare triple {38#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {38#false} is VALID [2018-11-18 21:08:31,694 INFO L273 TraceCheckUtils]: 12: Hoare triple {38#false} assume #t~short7; {38#false} is VALID [2018-11-18 21:08:31,694 INFO L256 TraceCheckUtils]: 13: Hoare triple {38#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {38#false} is VALID [2018-11-18 21:08:31,694 INFO L273 TraceCheckUtils]: 14: Hoare triple {38#false} ~cond := #in~cond; {38#false} is VALID [2018-11-18 21:08:31,695 INFO L273 TraceCheckUtils]: 15: Hoare triple {38#false} assume 0bv32 == ~cond; {38#false} is VALID [2018-11-18 21:08:31,695 INFO L273 TraceCheckUtils]: 16: Hoare triple {38#false} assume !false; {38#false} is VALID [2018-11-18 21:08:31,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:08:31,699 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-18 21:08:31,706 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 21:08:31,706 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 21:08:31,713 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 17 [2018-11-18 21:08:31,718 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:08:31,722 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 2 states. [2018-11-18 21:08:31,843 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 17 edges. 17 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:08:31,844 INFO L459 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-11-18 21:08:31,851 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-11-18 21:08:31,852 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-18 21:08:31,854 INFO L87 Difference]: Start difference. First operand 34 states. Second operand 2 states. [2018-11-18 21:08:32,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:32,080 INFO L93 Difference]: Finished difference Result 60 states and 79 transitions. [2018-11-18 21:08:32,081 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-11-18 21:08:32,081 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 17 [2018-11-18 21:08:32,081 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:08:32,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2018-11-18 21:08:32,094 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 79 transitions. [2018-11-18 21:08:32,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2018-11-18 21:08:32,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 79 transitions. [2018-11-18 21:08:32,100 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 2 states and 79 transitions. [2018-11-18 21:08:32,470 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 79 edges. 79 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:08:32,484 INFO L225 Difference]: With dead ends: 60 [2018-11-18 21:08:32,484 INFO L226 Difference]: Without dead ends: 28 [2018-11-18 21:08:32,488 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 16 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-18 21:08:32,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2018-11-18 21:08:32,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 28. [2018-11-18 21:08:32,541 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:08:32,541 INFO L82 GeneralOperation]: Start isEquivalent. First operand 28 states. Second operand 28 states. [2018-11-18 21:08:32,542 INFO L74 IsIncluded]: Start isIncluded. First operand 28 states. Second operand 28 states. [2018-11-18 21:08:32,542 INFO L87 Difference]: Start difference. First operand 28 states. Second operand 28 states. [2018-11-18 21:08:32,546 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:32,546 INFO L93 Difference]: Finished difference Result 28 states and 32 transitions. [2018-11-18 21:08:32,547 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 32 transitions. [2018-11-18 21:08:32,547 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:08:32,547 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:08:32,548 INFO L74 IsIncluded]: Start isIncluded. First operand 28 states. Second operand 28 states. [2018-11-18 21:08:32,548 INFO L87 Difference]: Start difference. First operand 28 states. Second operand 28 states. [2018-11-18 21:08:32,552 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:32,552 INFO L93 Difference]: Finished difference Result 28 states and 32 transitions. [2018-11-18 21:08:32,553 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 32 transitions. [2018-11-18 21:08:32,553 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:08:32,553 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:08:32,554 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:08:32,554 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:08:32,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28 states. [2018-11-18 21:08:32,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 32 transitions. [2018-11-18 21:08:32,559 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 32 transitions. Word has length 17 [2018-11-18 21:08:32,559 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:08:32,560 INFO L480 AbstractCegarLoop]: Abstraction has 28 states and 32 transitions. [2018-11-18 21:08:32,560 INFO L481 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-11-18 21:08:32,560 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 32 transitions. [2018-11-18 21:08:32,561 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-11-18 21:08:32,561 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:08:32,561 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:08:32,562 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:08:32,562 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:08:32,562 INFO L82 PathProgramCache]: Analyzing trace with hash -832945488, now seen corresponding path program 1 times [2018-11-18 21:08:32,563 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:08:32,563 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:08:32,583 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:08:32,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:08:32,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:08:32,635 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:08:33,028 INFO L256 TraceCheckUtils]: 0: Hoare triple {256#true} call ULTIMATE.init(); {256#true} is VALID [2018-11-18 21:08:33,029 INFO L273 TraceCheckUtils]: 1: Hoare triple {256#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {256#true} is VALID [2018-11-18 21:08:33,029 INFO L273 TraceCheckUtils]: 2: Hoare triple {256#true} assume true; {256#true} is VALID [2018-11-18 21:08:33,029 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {256#true} {256#true} #86#return; {256#true} is VALID [2018-11-18 21:08:33,030 INFO L256 TraceCheckUtils]: 4: Hoare triple {256#true} call #t~ret8 := main(); {256#true} is VALID [2018-11-18 21:08:33,030 INFO L273 TraceCheckUtils]: 5: Hoare triple {256#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {256#true} is VALID [2018-11-18 21:08:33,030 INFO L273 TraceCheckUtils]: 6: Hoare triple {256#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {256#true} is VALID [2018-11-18 21:08:33,030 INFO L273 TraceCheckUtils]: 7: Hoare triple {256#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {256#true} is VALID [2018-11-18 21:08:33,031 INFO L273 TraceCheckUtils]: 8: Hoare triple {256#true} assume true; {256#true} is VALID [2018-11-18 21:08:33,031 INFO L273 TraceCheckUtils]: 9: Hoare triple {256#true} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {256#true} is VALID [2018-11-18 21:08:33,032 INFO L273 TraceCheckUtils]: 10: Hoare triple {256#true} ~i~0 := 0bv32; {256#true} is VALID [2018-11-18 21:08:33,032 INFO L273 TraceCheckUtils]: 11: Hoare triple {256#true} assume true; {256#true} is VALID [2018-11-18 21:08:33,033 INFO L273 TraceCheckUtils]: 12: Hoare triple {256#true} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {256#true} is VALID [2018-11-18 21:08:33,034 INFO L273 TraceCheckUtils]: 13: Hoare triple {256#true} assume #t~short7; {300#|main_#t~short7|} is VALID [2018-11-18 21:08:33,034 INFO L256 TraceCheckUtils]: 14: Hoare triple {300#|main_#t~short7|} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {304#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:33,035 INFO L273 TraceCheckUtils]: 15: Hoare triple {304#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {308#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:33,037 INFO L273 TraceCheckUtils]: 16: Hoare triple {308#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 == ~cond; {257#false} is VALID [2018-11-18 21:08:33,038 INFO L273 TraceCheckUtils]: 17: Hoare triple {257#false} assume !false; {257#false} is VALID [2018-11-18 21:08:33,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:08:33,040 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-18 21:08:33,045 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 21:08:33,045 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 21:08:33,046 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 18 [2018-11-18 21:08:33,047 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:08:33,047 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states. [2018-11-18 21:08:33,116 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 18 edges. 18 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:08:33,116 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 21:08:33,116 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 21:08:33,117 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 21:08:33,117 INFO L87 Difference]: Start difference. First operand 28 states and 32 transitions. Second operand 5 states. [2018-11-18 21:08:33,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:33,807 INFO L93 Difference]: Finished difference Result 36 states and 40 transitions. [2018-11-18 21:08:33,808 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 21:08:33,808 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 18 [2018-11-18 21:08:33,808 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:08:33,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-18 21:08:33,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 40 transitions. [2018-11-18 21:08:33,811 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-18 21:08:33,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 40 transitions. [2018-11-18 21:08:33,814 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states and 40 transitions. [2018-11-18 21:08:33,931 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 40 edges. 40 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:08:33,934 INFO L225 Difference]: With dead ends: 36 [2018-11-18 21:08:33,934 INFO L226 Difference]: Without dead ends: 34 [2018-11-18 21:08:33,935 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 14 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 21:08:33,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-11-18 21:08:33,960 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 33. [2018-11-18 21:08:33,960 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:08:33,961 INFO L82 GeneralOperation]: Start isEquivalent. First operand 34 states. Second operand 33 states. [2018-11-18 21:08:33,961 INFO L74 IsIncluded]: Start isIncluded. First operand 34 states. Second operand 33 states. [2018-11-18 21:08:33,961 INFO L87 Difference]: Start difference. First operand 34 states. Second operand 33 states. [2018-11-18 21:08:33,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:33,964 INFO L93 Difference]: Finished difference Result 34 states and 38 transitions. [2018-11-18 21:08:33,964 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 38 transitions. [2018-11-18 21:08:33,965 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:08:33,965 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:08:33,965 INFO L74 IsIncluded]: Start isIncluded. First operand 33 states. Second operand 34 states. [2018-11-18 21:08:33,966 INFO L87 Difference]: Start difference. First operand 33 states. Second operand 34 states. [2018-11-18 21:08:33,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:33,969 INFO L93 Difference]: Finished difference Result 34 states and 38 transitions. [2018-11-18 21:08:33,969 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 38 transitions. [2018-11-18 21:08:33,970 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:08:33,970 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:08:33,970 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:08:33,970 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:08:33,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33 states. [2018-11-18 21:08:33,973 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 37 transitions. [2018-11-18 21:08:33,974 INFO L78 Accepts]: Start accepts. Automaton has 33 states and 37 transitions. Word has length 18 [2018-11-18 21:08:33,974 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:08:33,974 INFO L480 AbstractCegarLoop]: Abstraction has 33 states and 37 transitions. [2018-11-18 21:08:33,974 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 21:08:33,974 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 37 transitions. [2018-11-18 21:08:33,975 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-11-18 21:08:33,975 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:08:33,975 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:08:33,976 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:08:33,976 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:08:33,976 INFO L82 PathProgramCache]: Analyzing trace with hash -831098446, now seen corresponding path program 1 times [2018-11-18 21:08:33,977 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:08:33,977 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:08:33,997 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:08:34,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:08:34,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:08:34,210 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:08:34,505 WARN L180 SmtUtils]: Spent 134.00 ms on a formula simplification that was a NOOP. DAG size: 12 [2018-11-18 21:08:34,544 INFO L256 TraceCheckUtils]: 0: Hoare triple {475#true} call ULTIMATE.init(); {475#true} is VALID [2018-11-18 21:08:34,545 INFO L273 TraceCheckUtils]: 1: Hoare triple {475#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {475#true} is VALID [2018-11-18 21:08:34,545 INFO L273 TraceCheckUtils]: 2: Hoare triple {475#true} assume true; {475#true} is VALID [2018-11-18 21:08:34,546 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {475#true} {475#true} #86#return; {475#true} is VALID [2018-11-18 21:08:34,546 INFO L256 TraceCheckUtils]: 4: Hoare triple {475#true} call #t~ret8 := main(); {475#true} is VALID [2018-11-18 21:08:34,546 INFO L273 TraceCheckUtils]: 5: Hoare triple {475#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {475#true} is VALID [2018-11-18 21:08:34,547 INFO L273 TraceCheckUtils]: 6: Hoare triple {475#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {498#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} is VALID [2018-11-18 21:08:34,548 INFO L273 TraceCheckUtils]: 7: Hoare triple {498#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {502#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv5 32))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:34,549 INFO L273 TraceCheckUtils]: 8: Hoare triple {502#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv5 32))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {502#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv5 32))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:34,574 INFO L273 TraceCheckUtils]: 9: Hoare triple {502#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv5 32))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {476#false} is VALID [2018-11-18 21:08:34,574 INFO L273 TraceCheckUtils]: 10: Hoare triple {476#false} ~i~0 := 0bv32; {476#false} is VALID [2018-11-18 21:08:34,574 INFO L273 TraceCheckUtils]: 11: Hoare triple {476#false} assume true; {476#false} is VALID [2018-11-18 21:08:34,575 INFO L273 TraceCheckUtils]: 12: Hoare triple {476#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {476#false} is VALID [2018-11-18 21:08:34,575 INFO L273 TraceCheckUtils]: 13: Hoare triple {476#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {476#false} is VALID [2018-11-18 21:08:34,575 INFO L256 TraceCheckUtils]: 14: Hoare triple {476#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {476#false} is VALID [2018-11-18 21:08:34,576 INFO L273 TraceCheckUtils]: 15: Hoare triple {476#false} ~cond := #in~cond; {476#false} is VALID [2018-11-18 21:08:34,576 INFO L273 TraceCheckUtils]: 16: Hoare triple {476#false} assume 0bv32 == ~cond; {476#false} is VALID [2018-11-18 21:08:34,576 INFO L273 TraceCheckUtils]: 17: Hoare triple {476#false} assume !false; {476#false} is VALID [2018-11-18 21:08:34,578 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:08:34,578 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-18 21:08:34,582 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 21:08:34,582 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 21:08:34,583 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 18 [2018-11-18 21:08:34,583 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:08:34,583 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states. [2018-11-18 21:08:34,664 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 18 edges. 18 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:08:34,665 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 21:08:34,665 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 21:08:34,665 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-18 21:08:34,666 INFO L87 Difference]: Start difference. First operand 33 states and 37 transitions. Second operand 4 states. [2018-11-18 21:08:35,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:35,887 INFO L93 Difference]: Finished difference Result 58 states and 66 transitions. [2018-11-18 21:08:35,887 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 21:08:35,888 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 18 [2018-11-18 21:08:35,888 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:08:35,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-18 21:08:35,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 56 transitions. [2018-11-18 21:08:35,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-18 21:08:35,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 56 transitions. [2018-11-18 21:08:35,895 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states and 56 transitions. [2018-11-18 21:08:36,174 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 56 edges. 56 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:08:36,177 INFO L225 Difference]: With dead ends: 58 [2018-11-18 21:08:36,178 INFO L226 Difference]: Without dead ends: 40 [2018-11-18 21:08:36,178 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 15 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-18 21:08:36,179 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-11-18 21:08:36,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 35. [2018-11-18 21:08:36,206 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:08:36,206 INFO L82 GeneralOperation]: Start isEquivalent. First operand 40 states. Second operand 35 states. [2018-11-18 21:08:36,206 INFO L74 IsIncluded]: Start isIncluded. First operand 40 states. Second operand 35 states. [2018-11-18 21:08:36,206 INFO L87 Difference]: Start difference. First operand 40 states. Second operand 35 states. [2018-11-18 21:08:36,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:36,209 INFO L93 Difference]: Finished difference Result 40 states and 46 transitions. [2018-11-18 21:08:36,210 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 46 transitions. [2018-11-18 21:08:36,210 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:08:36,210 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:08:36,211 INFO L74 IsIncluded]: Start isIncluded. First operand 35 states. Second operand 40 states. [2018-11-18 21:08:36,211 INFO L87 Difference]: Start difference. First operand 35 states. Second operand 40 states. [2018-11-18 21:08:36,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:36,214 INFO L93 Difference]: Finished difference Result 40 states and 46 transitions. [2018-11-18 21:08:36,214 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 46 transitions. [2018-11-18 21:08:36,215 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:08:36,215 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:08:36,216 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:08:36,216 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:08:36,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35 states. [2018-11-18 21:08:36,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 39 transitions. [2018-11-18 21:08:36,218 INFO L78 Accepts]: Start accepts. Automaton has 35 states and 39 transitions. Word has length 18 [2018-11-18 21:08:36,219 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:08:36,219 INFO L480 AbstractCegarLoop]: Abstraction has 35 states and 39 transitions. [2018-11-18 21:08:36,219 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 21:08:36,219 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 39 transitions. [2018-11-18 21:08:36,220 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-11-18 21:08:36,220 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:08:36,220 INFO L375 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:08:36,221 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:08:36,221 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:08:36,221 INFO L82 PathProgramCache]: Analyzing trace with hash 1996039917, now seen corresponding path program 1 times [2018-11-18 21:08:36,222 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:08:36,222 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:08:36,252 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:08:36,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:08:36,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:08:36,379 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:08:36,429 INFO L256 TraceCheckUtils]: 0: Hoare triple {735#true} call ULTIMATE.init(); {735#true} is VALID [2018-11-18 21:08:36,429 INFO L273 TraceCheckUtils]: 1: Hoare triple {735#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {735#true} is VALID [2018-11-18 21:08:36,430 INFO L273 TraceCheckUtils]: 2: Hoare triple {735#true} assume true; {735#true} is VALID [2018-11-18 21:08:36,430 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {735#true} {735#true} #86#return; {735#true} is VALID [2018-11-18 21:08:36,430 INFO L256 TraceCheckUtils]: 4: Hoare triple {735#true} call #t~ret8 := main(); {735#true} is VALID [2018-11-18 21:08:36,430 INFO L273 TraceCheckUtils]: 5: Hoare triple {735#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {735#true} is VALID [2018-11-18 21:08:36,431 INFO L273 TraceCheckUtils]: 6: Hoare triple {735#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {735#true} is VALID [2018-11-18 21:08:36,431 INFO L273 TraceCheckUtils]: 7: Hoare triple {735#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {735#true} is VALID [2018-11-18 21:08:36,431 INFO L273 TraceCheckUtils]: 8: Hoare triple {735#true} assume true; {735#true} is VALID [2018-11-18 21:08:36,433 INFO L273 TraceCheckUtils]: 9: Hoare triple {735#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {767#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:36,434 INFO L273 TraceCheckUtils]: 10: Hoare triple {767#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} assume true; {767#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:36,435 INFO L273 TraceCheckUtils]: 11: Hoare triple {767#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} assume !~bvsge32(~j~0, 1bv32); {736#false} is VALID [2018-11-18 21:08:36,436 INFO L273 TraceCheckUtils]: 12: Hoare triple {736#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {736#false} is VALID [2018-11-18 21:08:36,436 INFO L273 TraceCheckUtils]: 13: Hoare triple {736#false} assume true; {736#false} is VALID [2018-11-18 21:08:36,436 INFO L273 TraceCheckUtils]: 14: Hoare triple {736#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {736#false} is VALID [2018-11-18 21:08:36,437 INFO L273 TraceCheckUtils]: 15: Hoare triple {736#false} ~i~0 := 0bv32; {736#false} is VALID [2018-11-18 21:08:36,437 INFO L273 TraceCheckUtils]: 16: Hoare triple {736#false} assume true; {736#false} is VALID [2018-11-18 21:08:36,437 INFO L273 TraceCheckUtils]: 17: Hoare triple {736#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {736#false} is VALID [2018-11-18 21:08:36,437 INFO L273 TraceCheckUtils]: 18: Hoare triple {736#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {736#false} is VALID [2018-11-18 21:08:36,438 INFO L256 TraceCheckUtils]: 19: Hoare triple {736#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {736#false} is VALID [2018-11-18 21:08:36,438 INFO L273 TraceCheckUtils]: 20: Hoare triple {736#false} ~cond := #in~cond; {736#false} is VALID [2018-11-18 21:08:36,438 INFO L273 TraceCheckUtils]: 21: Hoare triple {736#false} assume 0bv32 == ~cond; {736#false} is VALID [2018-11-18 21:08:36,438 INFO L273 TraceCheckUtils]: 22: Hoare triple {736#false} assume !false; {736#false} is VALID [2018-11-18 21:08:36,440 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:08:36,440 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-18 21:08:36,442 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 21:08:36,442 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 21:08:36,443 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 23 [2018-11-18 21:08:36,443 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:08:36,443 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2018-11-18 21:08:36,514 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 23 edges. 23 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:08:36,514 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 21:08:36,514 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 21:08:36,515 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 21:08:36,515 INFO L87 Difference]: Start difference. First operand 35 states and 39 transitions. Second operand 3 states. [2018-11-18 21:08:36,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:36,764 INFO L93 Difference]: Finished difference Result 64 states and 74 transitions. [2018-11-18 21:08:36,765 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 21:08:36,765 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 23 [2018-11-18 21:08:36,765 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:08:36,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-18 21:08:36,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 62 transitions. [2018-11-18 21:08:36,768 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-18 21:08:36,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 62 transitions. [2018-11-18 21:08:36,771 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states and 62 transitions. [2018-11-18 21:08:36,955 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 62 edges. 62 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:08:36,957 INFO L225 Difference]: With dead ends: 64 [2018-11-18 21:08:36,957 INFO L226 Difference]: Without dead ends: 39 [2018-11-18 21:08:36,958 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 21 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 21:08:36,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states. [2018-11-18 21:08:37,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 37. [2018-11-18 21:08:37,032 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:08:37,032 INFO L82 GeneralOperation]: Start isEquivalent. First operand 39 states. Second operand 37 states. [2018-11-18 21:08:37,032 INFO L74 IsIncluded]: Start isIncluded. First operand 39 states. Second operand 37 states. [2018-11-18 21:08:37,033 INFO L87 Difference]: Start difference. First operand 39 states. Second operand 37 states. [2018-11-18 21:08:37,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:37,035 INFO L93 Difference]: Finished difference Result 39 states and 44 transitions. [2018-11-18 21:08:37,035 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 44 transitions. [2018-11-18 21:08:37,036 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:08:37,036 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:08:37,036 INFO L74 IsIncluded]: Start isIncluded. First operand 37 states. Second operand 39 states. [2018-11-18 21:08:37,037 INFO L87 Difference]: Start difference. First operand 37 states. Second operand 39 states. [2018-11-18 21:08:37,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:37,039 INFO L93 Difference]: Finished difference Result 39 states and 44 transitions. [2018-11-18 21:08:37,039 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 44 transitions. [2018-11-18 21:08:37,040 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:08:37,040 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:08:37,040 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:08:37,041 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:08:37,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2018-11-18 21:08:37,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 41 transitions. [2018-11-18 21:08:37,043 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 41 transitions. Word has length 23 [2018-11-18 21:08:37,043 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:08:37,044 INFO L480 AbstractCegarLoop]: Abstraction has 37 states and 41 transitions. [2018-11-18 21:08:37,044 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 21:08:37,044 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 41 transitions. [2018-11-18 21:08:37,045 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-11-18 21:08:37,045 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:08:37,045 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:08:37,045 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:08:37,046 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:08:37,046 INFO L82 PathProgramCache]: Analyzing trace with hash -995813500, now seen corresponding path program 1 times [2018-11-18 21:08:37,046 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:08:37,047 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:08:37,064 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:08:37,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:08:37,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:08:37,198 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:08:37,433 INFO L256 TraceCheckUtils]: 0: Hoare triple {1018#true} call ULTIMATE.init(); {1018#true} is VALID [2018-11-18 21:08:37,433 INFO L273 TraceCheckUtils]: 1: Hoare triple {1018#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1018#true} is VALID [2018-11-18 21:08:37,434 INFO L273 TraceCheckUtils]: 2: Hoare triple {1018#true} assume true; {1018#true} is VALID [2018-11-18 21:08:37,434 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1018#true} {1018#true} #86#return; {1018#true} is VALID [2018-11-18 21:08:37,434 INFO L256 TraceCheckUtils]: 4: Hoare triple {1018#true} call #t~ret8 := main(); {1018#true} is VALID [2018-11-18 21:08:37,434 INFO L273 TraceCheckUtils]: 5: Hoare triple {1018#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1018#true} is VALID [2018-11-18 21:08:37,435 INFO L273 TraceCheckUtils]: 6: Hoare triple {1018#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1018#true} is VALID [2018-11-18 21:08:37,435 INFO L273 TraceCheckUtils]: 7: Hoare triple {1018#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1018#true} is VALID [2018-11-18 21:08:37,435 INFO L273 TraceCheckUtils]: 8: Hoare triple {1018#true} assume true; {1018#true} is VALID [2018-11-18 21:08:37,436 INFO L273 TraceCheckUtils]: 9: Hoare triple {1018#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {1050#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:37,437 INFO L273 TraceCheckUtils]: 10: Hoare triple {1050#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} assume true; {1050#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:37,445 INFO L273 TraceCheckUtils]: 11: Hoare triple {1050#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {1050#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:37,446 INFO L273 TraceCheckUtils]: 12: Hoare triple {1050#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1050#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:37,447 INFO L273 TraceCheckUtils]: 13: Hoare triple {1050#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1063#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:37,447 INFO L273 TraceCheckUtils]: 14: Hoare triple {1063#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} assume true; {1063#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:37,448 INFO L273 TraceCheckUtils]: 15: Hoare triple {1063#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} assume !~bvsge32(~j~0, 1bv32); {1019#false} is VALID [2018-11-18 21:08:37,448 INFO L273 TraceCheckUtils]: 16: Hoare triple {1019#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1019#false} is VALID [2018-11-18 21:08:37,449 INFO L273 TraceCheckUtils]: 17: Hoare triple {1019#false} assume true; {1019#false} is VALID [2018-11-18 21:08:37,449 INFO L273 TraceCheckUtils]: 18: Hoare triple {1019#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {1019#false} is VALID [2018-11-18 21:08:37,450 INFO L273 TraceCheckUtils]: 19: Hoare triple {1019#false} ~i~0 := 0bv32; {1019#false} is VALID [2018-11-18 21:08:37,450 INFO L273 TraceCheckUtils]: 20: Hoare triple {1019#false} assume true; {1019#false} is VALID [2018-11-18 21:08:37,451 INFO L273 TraceCheckUtils]: 21: Hoare triple {1019#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1019#false} is VALID [2018-11-18 21:08:37,451 INFO L273 TraceCheckUtils]: 22: Hoare triple {1019#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1019#false} is VALID [2018-11-18 21:08:37,451 INFO L256 TraceCheckUtils]: 23: Hoare triple {1019#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1019#false} is VALID [2018-11-18 21:08:37,452 INFO L273 TraceCheckUtils]: 24: Hoare triple {1019#false} ~cond := #in~cond; {1019#false} is VALID [2018-11-18 21:08:37,452 INFO L273 TraceCheckUtils]: 25: Hoare triple {1019#false} assume 0bv32 == ~cond; {1019#false} is VALID [2018-11-18 21:08:37,452 INFO L273 TraceCheckUtils]: 26: Hoare triple {1019#false} assume !false; {1019#false} is VALID [2018-11-18 21:08:37,454 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:08:37,454 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 21:08:37,560 INFO L273 TraceCheckUtils]: 26: Hoare triple {1019#false} assume !false; {1019#false} is VALID [2018-11-18 21:08:37,560 INFO L273 TraceCheckUtils]: 25: Hoare triple {1019#false} assume 0bv32 == ~cond; {1019#false} is VALID [2018-11-18 21:08:37,561 INFO L273 TraceCheckUtils]: 24: Hoare triple {1019#false} ~cond := #in~cond; {1019#false} is VALID [2018-11-18 21:08:37,561 INFO L256 TraceCheckUtils]: 23: Hoare triple {1019#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1019#false} is VALID [2018-11-18 21:08:37,562 INFO L273 TraceCheckUtils]: 22: Hoare triple {1019#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1019#false} is VALID [2018-11-18 21:08:37,562 INFO L273 TraceCheckUtils]: 21: Hoare triple {1019#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1019#false} is VALID [2018-11-18 21:08:37,563 INFO L273 TraceCheckUtils]: 20: Hoare triple {1019#false} assume true; {1019#false} is VALID [2018-11-18 21:08:37,563 INFO L273 TraceCheckUtils]: 19: Hoare triple {1019#false} ~i~0 := 0bv32; {1019#false} is VALID [2018-11-18 21:08:37,563 INFO L273 TraceCheckUtils]: 18: Hoare triple {1019#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {1019#false} is VALID [2018-11-18 21:08:37,563 INFO L273 TraceCheckUtils]: 17: Hoare triple {1019#false} assume true; {1019#false} is VALID [2018-11-18 21:08:37,564 INFO L273 TraceCheckUtils]: 16: Hoare triple {1019#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1019#false} is VALID [2018-11-18 21:08:37,567 INFO L273 TraceCheckUtils]: 15: Hoare triple {1136#(bvsge main_~j~0 (_ bv1 32))} assume !~bvsge32(~j~0, 1bv32); {1019#false} is VALID [2018-11-18 21:08:37,568 INFO L273 TraceCheckUtils]: 14: Hoare triple {1136#(bvsge main_~j~0 (_ bv1 32))} assume true; {1136#(bvsge main_~j~0 (_ bv1 32))} is VALID [2018-11-18 21:08:37,570 INFO L273 TraceCheckUtils]: 13: Hoare triple {1143#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1136#(bvsge main_~j~0 (_ bv1 32))} is VALID [2018-11-18 21:08:37,570 INFO L273 TraceCheckUtils]: 12: Hoare triple {1143#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1143#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-18 21:08:37,571 INFO L273 TraceCheckUtils]: 11: Hoare triple {1143#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} assume !!~bvsge32(~j~0, 1bv32); {1143#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-18 21:08:37,571 INFO L273 TraceCheckUtils]: 10: Hoare triple {1143#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} assume true; {1143#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-18 21:08:37,572 INFO L273 TraceCheckUtils]: 9: Hoare triple {1018#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {1143#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-18 21:08:37,573 INFO L273 TraceCheckUtils]: 8: Hoare triple {1018#true} assume true; {1018#true} is VALID [2018-11-18 21:08:37,573 INFO L273 TraceCheckUtils]: 7: Hoare triple {1018#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1018#true} is VALID [2018-11-18 21:08:37,574 INFO L273 TraceCheckUtils]: 6: Hoare triple {1018#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1018#true} is VALID [2018-11-18 21:08:37,574 INFO L273 TraceCheckUtils]: 5: Hoare triple {1018#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1018#true} is VALID [2018-11-18 21:08:37,575 INFO L256 TraceCheckUtils]: 4: Hoare triple {1018#true} call #t~ret8 := main(); {1018#true} is VALID [2018-11-18 21:08:37,575 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1018#true} {1018#true} #86#return; {1018#true} is VALID [2018-11-18 21:08:37,576 INFO L273 TraceCheckUtils]: 2: Hoare triple {1018#true} assume true; {1018#true} is VALID [2018-11-18 21:08:37,576 INFO L273 TraceCheckUtils]: 1: Hoare triple {1018#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1018#true} is VALID [2018-11-18 21:08:37,577 INFO L256 TraceCheckUtils]: 0: Hoare triple {1018#true} call ULTIMATE.init(); {1018#true} is VALID [2018-11-18 21:08:37,578 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:08:37,583 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 21:08:37,583 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 6 [2018-11-18 21:08:37,584 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 27 [2018-11-18 21:08:37,584 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:08:37,585 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 6 states. [2018-11-18 21:08:37,686 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 34 edges. 34 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:08:37,686 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 21:08:37,686 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 21:08:37,687 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-11-18 21:08:37,687 INFO L87 Difference]: Start difference. First operand 37 states and 41 transitions. Second operand 6 states. [2018-11-18 21:08:38,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:38,342 INFO L93 Difference]: Finished difference Result 76 states and 90 transitions. [2018-11-18 21:08:38,342 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 21:08:38,342 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 27 [2018-11-18 21:08:38,343 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:08:38,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6 states. [2018-11-18 21:08:38,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 76 transitions. [2018-11-18 21:08:38,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6 states. [2018-11-18 21:08:38,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 76 transitions. [2018-11-18 21:08:38,348 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 6 states and 76 transitions. [2018-11-18 21:08:38,630 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 76 edges. 76 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:08:38,633 INFO L225 Difference]: With dead ends: 76 [2018-11-18 21:08:38,633 INFO L226 Difference]: Without dead ends: 49 [2018-11-18 21:08:38,634 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=19, Invalid=23, Unknown=0, NotChecked=0, Total=42 [2018-11-18 21:08:38,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-11-18 21:08:38,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 49. [2018-11-18 21:08:38,662 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:08:38,662 INFO L82 GeneralOperation]: Start isEquivalent. First operand 49 states. Second operand 49 states. [2018-11-18 21:08:38,662 INFO L74 IsIncluded]: Start isIncluded. First operand 49 states. Second operand 49 states. [2018-11-18 21:08:38,662 INFO L87 Difference]: Start difference. First operand 49 states. Second operand 49 states. [2018-11-18 21:08:38,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:38,665 INFO L93 Difference]: Finished difference Result 49 states and 56 transitions. [2018-11-18 21:08:38,665 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 56 transitions. [2018-11-18 21:08:38,666 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:08:38,666 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:08:38,667 INFO L74 IsIncluded]: Start isIncluded. First operand 49 states. Second operand 49 states. [2018-11-18 21:08:38,667 INFO L87 Difference]: Start difference. First operand 49 states. Second operand 49 states. [2018-11-18 21:08:38,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:38,670 INFO L93 Difference]: Finished difference Result 49 states and 56 transitions. [2018-11-18 21:08:38,670 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 56 transitions. [2018-11-18 21:08:38,671 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:08:38,671 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:08:38,671 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:08:38,671 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:08:38,671 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2018-11-18 21:08:38,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 56 transitions. [2018-11-18 21:08:38,674 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 56 transitions. Word has length 27 [2018-11-18 21:08:38,674 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:08:38,675 INFO L480 AbstractCegarLoop]: Abstraction has 49 states and 56 transitions. [2018-11-18 21:08:38,675 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 21:08:38,675 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 56 transitions. [2018-11-18 21:08:38,676 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-11-18 21:08:38,676 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:08:38,676 INFO L375 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:08:38,677 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:08:38,677 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:08:38,677 INFO L82 PathProgramCache]: Analyzing trace with hash 1020204105, now seen corresponding path program 2 times [2018-11-18 21:08:38,678 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:08:38,678 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:08:38,709 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-18 21:08:38,960 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 21:08:38,960 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 21:08:39,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:08:39,002 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:08:39,121 INFO L256 TraceCheckUtils]: 0: Hoare triple {1450#true} call ULTIMATE.init(); {1450#true} is VALID [2018-11-18 21:08:39,122 INFO L273 TraceCheckUtils]: 1: Hoare triple {1450#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1450#true} is VALID [2018-11-18 21:08:39,122 INFO L273 TraceCheckUtils]: 2: Hoare triple {1450#true} assume true; {1450#true} is VALID [2018-11-18 21:08:39,122 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1450#true} {1450#true} #86#return; {1450#true} is VALID [2018-11-18 21:08:39,123 INFO L256 TraceCheckUtils]: 4: Hoare triple {1450#true} call #t~ret8 := main(); {1450#true} is VALID [2018-11-18 21:08:39,123 INFO L273 TraceCheckUtils]: 5: Hoare triple {1450#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1450#true} is VALID [2018-11-18 21:08:39,123 INFO L273 TraceCheckUtils]: 6: Hoare triple {1450#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1450#true} is VALID [2018-11-18 21:08:39,123 INFO L273 TraceCheckUtils]: 7: Hoare triple {1450#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1450#true} is VALID [2018-11-18 21:08:39,124 INFO L273 TraceCheckUtils]: 8: Hoare triple {1450#true} assume true; {1450#true} is VALID [2018-11-18 21:08:39,124 INFO L273 TraceCheckUtils]: 9: Hoare triple {1450#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {1482#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:39,125 INFO L273 TraceCheckUtils]: 10: Hoare triple {1482#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} assume true; {1482#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:39,125 INFO L273 TraceCheckUtils]: 11: Hoare triple {1482#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {1482#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:39,126 INFO L273 TraceCheckUtils]: 12: Hoare triple {1482#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1482#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:39,126 INFO L273 TraceCheckUtils]: 13: Hoare triple {1482#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1495#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:39,127 INFO L273 TraceCheckUtils]: 14: Hoare triple {1495#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} assume true; {1495#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:39,127 INFO L273 TraceCheckUtils]: 15: Hoare triple {1495#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {1495#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:39,128 INFO L273 TraceCheckUtils]: 16: Hoare triple {1495#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1495#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:39,129 INFO L273 TraceCheckUtils]: 17: Hoare triple {1495#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1508#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:39,134 INFO L273 TraceCheckUtils]: 18: Hoare triple {1508#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} assume true; {1508#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:39,134 INFO L273 TraceCheckUtils]: 19: Hoare triple {1508#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {1508#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:39,135 INFO L273 TraceCheckUtils]: 20: Hoare triple {1508#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1508#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:39,136 INFO L273 TraceCheckUtils]: 21: Hoare triple {1508#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1521#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:39,136 INFO L273 TraceCheckUtils]: 22: Hoare triple {1521#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} assume true; {1521#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:39,137 INFO L273 TraceCheckUtils]: 23: Hoare triple {1521#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {1521#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:39,137 INFO L273 TraceCheckUtils]: 24: Hoare triple {1521#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1521#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:39,138 INFO L273 TraceCheckUtils]: 25: Hoare triple {1521#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1534#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:39,138 INFO L273 TraceCheckUtils]: 26: Hoare triple {1534#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} assume true; {1534#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:39,139 INFO L273 TraceCheckUtils]: 27: Hoare triple {1534#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} assume !~bvsge32(~j~0, 1bv32); {1451#false} is VALID [2018-11-18 21:08:39,140 INFO L273 TraceCheckUtils]: 28: Hoare triple {1451#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1451#false} is VALID [2018-11-18 21:08:39,140 INFO L273 TraceCheckUtils]: 29: Hoare triple {1451#false} assume true; {1451#false} is VALID [2018-11-18 21:08:39,140 INFO L273 TraceCheckUtils]: 30: Hoare triple {1451#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {1451#false} is VALID [2018-11-18 21:08:39,141 INFO L273 TraceCheckUtils]: 31: Hoare triple {1451#false} ~i~0 := 0bv32; {1451#false} is VALID [2018-11-18 21:08:39,141 INFO L273 TraceCheckUtils]: 32: Hoare triple {1451#false} assume true; {1451#false} is VALID [2018-11-18 21:08:39,141 INFO L273 TraceCheckUtils]: 33: Hoare triple {1451#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1451#false} is VALID [2018-11-18 21:08:39,142 INFO L273 TraceCheckUtils]: 34: Hoare triple {1451#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1451#false} is VALID [2018-11-18 21:08:39,142 INFO L256 TraceCheckUtils]: 35: Hoare triple {1451#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1451#false} is VALID [2018-11-18 21:08:39,142 INFO L273 TraceCheckUtils]: 36: Hoare triple {1451#false} ~cond := #in~cond; {1451#false} is VALID [2018-11-18 21:08:39,142 INFO L273 TraceCheckUtils]: 37: Hoare triple {1451#false} assume 0bv32 == ~cond; {1451#false} is VALID [2018-11-18 21:08:39,143 INFO L273 TraceCheckUtils]: 38: Hoare triple {1451#false} assume !false; {1451#false} is VALID [2018-11-18 21:08:39,146 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 2 proven. 32 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:08:39,147 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 21:08:39,416 INFO L273 TraceCheckUtils]: 38: Hoare triple {1451#false} assume !false; {1451#false} is VALID [2018-11-18 21:08:39,417 INFO L273 TraceCheckUtils]: 37: Hoare triple {1451#false} assume 0bv32 == ~cond; {1451#false} is VALID [2018-11-18 21:08:39,417 INFO L273 TraceCheckUtils]: 36: Hoare triple {1451#false} ~cond := #in~cond; {1451#false} is VALID [2018-11-18 21:08:39,417 INFO L256 TraceCheckUtils]: 35: Hoare triple {1451#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1451#false} is VALID [2018-11-18 21:08:39,417 INFO L273 TraceCheckUtils]: 34: Hoare triple {1451#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1451#false} is VALID [2018-11-18 21:08:39,418 INFO L273 TraceCheckUtils]: 33: Hoare triple {1451#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1451#false} is VALID [2018-11-18 21:08:39,418 INFO L273 TraceCheckUtils]: 32: Hoare triple {1451#false} assume true; {1451#false} is VALID [2018-11-18 21:08:39,418 INFO L273 TraceCheckUtils]: 31: Hoare triple {1451#false} ~i~0 := 0bv32; {1451#false} is VALID [2018-11-18 21:08:39,419 INFO L273 TraceCheckUtils]: 30: Hoare triple {1451#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {1451#false} is VALID [2018-11-18 21:08:39,419 INFO L273 TraceCheckUtils]: 29: Hoare triple {1451#false} assume true; {1451#false} is VALID [2018-11-18 21:08:39,419 INFO L273 TraceCheckUtils]: 28: Hoare triple {1451#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1451#false} is VALID [2018-11-18 21:08:39,420 INFO L273 TraceCheckUtils]: 27: Hoare triple {1607#(bvsge main_~j~0 (_ bv1 32))} assume !~bvsge32(~j~0, 1bv32); {1451#false} is VALID [2018-11-18 21:08:39,420 INFO L273 TraceCheckUtils]: 26: Hoare triple {1607#(bvsge main_~j~0 (_ bv1 32))} assume true; {1607#(bvsge main_~j~0 (_ bv1 32))} is VALID [2018-11-18 21:08:39,422 INFO L273 TraceCheckUtils]: 25: Hoare triple {1614#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1607#(bvsge main_~j~0 (_ bv1 32))} is VALID [2018-11-18 21:08:39,423 INFO L273 TraceCheckUtils]: 24: Hoare triple {1614#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1614#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-18 21:08:39,423 INFO L273 TraceCheckUtils]: 23: Hoare triple {1614#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} assume !!~bvsge32(~j~0, 1bv32); {1614#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-18 21:08:39,423 INFO L273 TraceCheckUtils]: 22: Hoare triple {1614#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} assume true; {1614#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-18 21:08:39,428 INFO L273 TraceCheckUtils]: 21: Hoare triple {1627#(bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1614#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-18 21:08:39,429 INFO L273 TraceCheckUtils]: 20: Hoare triple {1627#(bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1627#(bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32))} is VALID [2018-11-18 21:08:39,429 INFO L273 TraceCheckUtils]: 19: Hoare triple {1627#(bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32))} assume !!~bvsge32(~j~0, 1bv32); {1627#(bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32))} is VALID [2018-11-18 21:08:39,431 INFO L273 TraceCheckUtils]: 18: Hoare triple {1627#(bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32))} assume true; {1627#(bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32))} is VALID [2018-11-18 21:08:39,435 INFO L273 TraceCheckUtils]: 17: Hoare triple {1640#(bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1627#(bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32))} is VALID [2018-11-18 21:08:39,435 INFO L273 TraceCheckUtils]: 16: Hoare triple {1640#(bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1640#(bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32))} is VALID [2018-11-18 21:08:39,440 INFO L273 TraceCheckUtils]: 15: Hoare triple {1640#(bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32))} assume !!~bvsge32(~j~0, 1bv32); {1640#(bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32))} is VALID [2018-11-18 21:08:39,440 INFO L273 TraceCheckUtils]: 14: Hoare triple {1640#(bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32))} assume true; {1640#(bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32))} is VALID [2018-11-18 21:08:39,444 INFO L273 TraceCheckUtils]: 13: Hoare triple {1653#(bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1640#(bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32))} is VALID [2018-11-18 21:08:39,445 INFO L273 TraceCheckUtils]: 12: Hoare triple {1653#(bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {1653#(bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32))} is VALID [2018-11-18 21:08:39,446 INFO L273 TraceCheckUtils]: 11: Hoare triple {1653#(bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32))} assume !!~bvsge32(~j~0, 1bv32); {1653#(bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32))} is VALID [2018-11-18 21:08:39,446 INFO L273 TraceCheckUtils]: 10: Hoare triple {1653#(bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32))} assume true; {1653#(bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32))} is VALID [2018-11-18 21:08:39,447 INFO L273 TraceCheckUtils]: 9: Hoare triple {1450#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {1653#(bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32))} is VALID [2018-11-18 21:08:39,447 INFO L273 TraceCheckUtils]: 8: Hoare triple {1450#true} assume true; {1450#true} is VALID [2018-11-18 21:08:39,447 INFO L273 TraceCheckUtils]: 7: Hoare triple {1450#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1450#true} is VALID [2018-11-18 21:08:39,448 INFO L273 TraceCheckUtils]: 6: Hoare triple {1450#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1450#true} is VALID [2018-11-18 21:08:39,448 INFO L273 TraceCheckUtils]: 5: Hoare triple {1450#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1450#true} is VALID [2018-11-18 21:08:39,448 INFO L256 TraceCheckUtils]: 4: Hoare triple {1450#true} call #t~ret8 := main(); {1450#true} is VALID [2018-11-18 21:08:39,448 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1450#true} {1450#true} #86#return; {1450#true} is VALID [2018-11-18 21:08:39,448 INFO L273 TraceCheckUtils]: 2: Hoare triple {1450#true} assume true; {1450#true} is VALID [2018-11-18 21:08:39,449 INFO L273 TraceCheckUtils]: 1: Hoare triple {1450#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1450#true} is VALID [2018-11-18 21:08:39,449 INFO L256 TraceCheckUtils]: 0: Hoare triple {1450#true} call ULTIMATE.init(); {1450#true} is VALID [2018-11-18 21:08:39,453 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 2 proven. 32 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:08:39,462 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 21:08:39,462 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 12 [2018-11-18 21:08:39,463 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 39 [2018-11-18 21:08:39,463 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:08:39,464 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 12 states. [2018-11-18 21:08:39,632 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 58 edges. 58 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:08:39,632 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-18 21:08:39,632 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-18 21:08:39,633 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2018-11-18 21:08:39,633 INFO L87 Difference]: Start difference. First operand 49 states and 56 transitions. Second operand 12 states. [2018-11-18 21:08:41,340 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:41,340 INFO L93 Difference]: Finished difference Result 94 states and 111 transitions. [2018-11-18 21:08:41,341 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-18 21:08:41,341 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 39 [2018-11-18 21:08:41,341 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:08:41,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2018-11-18 21:08:41,344 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 82 transitions. [2018-11-18 21:08:41,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2018-11-18 21:08:41,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 82 transitions. [2018-11-18 21:08:41,348 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 8 states and 82 transitions. [2018-11-18 21:08:41,623 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 82 edges. 82 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:08:41,625 INFO L225 Difference]: With dead ends: 94 [2018-11-18 21:08:41,626 INFO L226 Difference]: Without dead ends: 55 [2018-11-18 21:08:41,627 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 77 GetRequests, 67 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2018-11-18 21:08:41,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states. [2018-11-18 21:08:41,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 53. [2018-11-18 21:08:41,672 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:08:41,672 INFO L82 GeneralOperation]: Start isEquivalent. First operand 55 states. Second operand 53 states. [2018-11-18 21:08:41,672 INFO L74 IsIncluded]: Start isIncluded. First operand 55 states. Second operand 53 states. [2018-11-18 21:08:41,672 INFO L87 Difference]: Start difference. First operand 55 states. Second operand 53 states. [2018-11-18 21:08:41,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:41,676 INFO L93 Difference]: Finished difference Result 55 states and 64 transitions. [2018-11-18 21:08:41,676 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 64 transitions. [2018-11-18 21:08:41,677 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:08:41,677 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:08:41,677 INFO L74 IsIncluded]: Start isIncluded. First operand 53 states. Second operand 55 states. [2018-11-18 21:08:41,677 INFO L87 Difference]: Start difference. First operand 53 states. Second operand 55 states. [2018-11-18 21:08:41,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:41,680 INFO L93 Difference]: Finished difference Result 55 states and 64 transitions. [2018-11-18 21:08:41,680 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 64 transitions. [2018-11-18 21:08:41,681 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:08:41,681 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:08:41,681 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:08:41,681 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:08:41,682 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53 states. [2018-11-18 21:08:41,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 61 transitions. [2018-11-18 21:08:41,684 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 61 transitions. Word has length 39 [2018-11-18 21:08:41,685 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:08:41,685 INFO L480 AbstractCegarLoop]: Abstraction has 53 states and 61 transitions. [2018-11-18 21:08:41,685 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-18 21:08:41,685 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 61 transitions. [2018-11-18 21:08:41,686 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-11-18 21:08:41,686 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:08:41,686 INFO L375 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:08:41,687 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:08:41,687 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:08:41,687 INFO L82 PathProgramCache]: Analyzing trace with hash -1462962464, now seen corresponding path program 3 times [2018-11-18 21:08:41,687 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:08:41,688 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:08:41,715 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2018-11-18 21:08:42,142 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-11-18 21:08:42,142 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 21:08:42,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:08:42,205 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:08:42,353 INFO L256 TraceCheckUtils]: 0: Hoare triple {1997#true} call ULTIMATE.init(); {1997#true} is VALID [2018-11-18 21:08:42,354 INFO L273 TraceCheckUtils]: 1: Hoare triple {1997#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1997#true} is VALID [2018-11-18 21:08:42,354 INFO L273 TraceCheckUtils]: 2: Hoare triple {1997#true} assume true; {1997#true} is VALID [2018-11-18 21:08:42,355 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1997#true} {1997#true} #86#return; {1997#true} is VALID [2018-11-18 21:08:42,355 INFO L256 TraceCheckUtils]: 4: Hoare triple {1997#true} call #t~ret8 := main(); {1997#true} is VALID [2018-11-18 21:08:42,355 INFO L273 TraceCheckUtils]: 5: Hoare triple {1997#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1997#true} is VALID [2018-11-18 21:08:42,356 INFO L273 TraceCheckUtils]: 6: Hoare triple {1997#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {2020#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-18 21:08:42,357 INFO L273 TraceCheckUtils]: 7: Hoare triple {2020#(= (_ bv2 32) main_~MINVAL~0)} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {2020#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-18 21:08:42,357 INFO L273 TraceCheckUtils]: 8: Hoare triple {2020#(= (_ bv2 32) main_~MINVAL~0)} assume true; {2020#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-18 21:08:42,358 INFO L273 TraceCheckUtils]: 9: Hoare triple {2020#(= (_ bv2 32) main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {2020#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-18 21:08:42,359 INFO L273 TraceCheckUtils]: 10: Hoare triple {2020#(= (_ bv2 32) main_~MINVAL~0)} assume true; {2020#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-18 21:08:42,363 INFO L273 TraceCheckUtils]: 11: Hoare triple {2020#(= (_ bv2 32) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {2020#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-18 21:08:42,363 INFO L273 TraceCheckUtils]: 12: Hoare triple {2020#(= (_ bv2 32) main_~MINVAL~0)} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2020#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-18 21:08:42,364 INFO L273 TraceCheckUtils]: 13: Hoare triple {2020#(= (_ bv2 32) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2020#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-18 21:08:42,364 INFO L273 TraceCheckUtils]: 14: Hoare triple {2020#(= (_ bv2 32) main_~MINVAL~0)} assume true; {2020#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-18 21:08:42,365 INFO L273 TraceCheckUtils]: 15: Hoare triple {2020#(= (_ bv2 32) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {2020#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-18 21:08:42,365 INFO L273 TraceCheckUtils]: 16: Hoare triple {2020#(= (_ bv2 32) main_~MINVAL~0)} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2020#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-18 21:08:42,366 INFO L273 TraceCheckUtils]: 17: Hoare triple {2020#(= (_ bv2 32) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2020#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-18 21:08:42,368 INFO L273 TraceCheckUtils]: 18: Hoare triple {2020#(= (_ bv2 32) main_~MINVAL~0)} assume true; {2020#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-18 21:08:42,375 INFO L273 TraceCheckUtils]: 19: Hoare triple {2020#(= (_ bv2 32) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {2020#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-18 21:08:42,376 INFO L273 TraceCheckUtils]: 20: Hoare triple {2020#(= (_ bv2 32) main_~MINVAL~0)} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2020#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-18 21:08:42,376 INFO L273 TraceCheckUtils]: 21: Hoare triple {2020#(= (_ bv2 32) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2020#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-18 21:08:42,377 INFO L273 TraceCheckUtils]: 22: Hoare triple {2020#(= (_ bv2 32) main_~MINVAL~0)} assume true; {2020#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-18 21:08:42,383 INFO L273 TraceCheckUtils]: 23: Hoare triple {2020#(= (_ bv2 32) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {2020#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-18 21:08:42,383 INFO L273 TraceCheckUtils]: 24: Hoare triple {2020#(= (_ bv2 32) main_~MINVAL~0)} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2020#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-18 21:08:42,384 INFO L273 TraceCheckUtils]: 25: Hoare triple {2020#(= (_ bv2 32) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2020#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-18 21:08:42,384 INFO L273 TraceCheckUtils]: 26: Hoare triple {2020#(= (_ bv2 32) main_~MINVAL~0)} assume true; {2020#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-18 21:08:42,385 INFO L273 TraceCheckUtils]: 27: Hoare triple {2020#(= (_ bv2 32) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {2084#(and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:42,386 INFO L273 TraceCheckUtils]: 28: Hoare triple {2084#(and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2088#(bvsge main_~j~0 (_ bv2 32))} is VALID [2018-11-18 21:08:42,391 INFO L273 TraceCheckUtils]: 29: Hoare triple {2088#(bvsge main_~j~0 (_ bv2 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2092#(bvsge (bvadd main_~j~0 (_ bv1 32)) (_ bv2 32))} is VALID [2018-11-18 21:08:42,391 INFO L273 TraceCheckUtils]: 30: Hoare triple {2092#(bvsge (bvadd main_~j~0 (_ bv1 32)) (_ bv2 32))} assume true; {2092#(bvsge (bvadd main_~j~0 (_ bv1 32)) (_ bv2 32))} is VALID [2018-11-18 21:08:42,393 INFO L273 TraceCheckUtils]: 31: Hoare triple {2092#(bvsge (bvadd main_~j~0 (_ bv1 32)) (_ bv2 32))} assume !~bvsge32(~j~0, 1bv32); {1998#false} is VALID [2018-11-18 21:08:42,393 INFO L273 TraceCheckUtils]: 32: Hoare triple {1998#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1998#false} is VALID [2018-11-18 21:08:42,393 INFO L273 TraceCheckUtils]: 33: Hoare triple {1998#false} assume true; {1998#false} is VALID [2018-11-18 21:08:42,394 INFO L273 TraceCheckUtils]: 34: Hoare triple {1998#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {1998#false} is VALID [2018-11-18 21:08:42,394 INFO L273 TraceCheckUtils]: 35: Hoare triple {1998#false} ~i~0 := 0bv32; {1998#false} is VALID [2018-11-18 21:08:42,394 INFO L273 TraceCheckUtils]: 36: Hoare triple {1998#false} assume true; {1998#false} is VALID [2018-11-18 21:08:42,394 INFO L273 TraceCheckUtils]: 37: Hoare triple {1998#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1998#false} is VALID [2018-11-18 21:08:42,394 INFO L273 TraceCheckUtils]: 38: Hoare triple {1998#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1998#false} is VALID [2018-11-18 21:08:42,395 INFO L256 TraceCheckUtils]: 39: Hoare triple {1998#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1998#false} is VALID [2018-11-18 21:08:42,395 INFO L273 TraceCheckUtils]: 40: Hoare triple {1998#false} ~cond := #in~cond; {1998#false} is VALID [2018-11-18 21:08:42,395 INFO L273 TraceCheckUtils]: 41: Hoare triple {1998#false} assume 0bv32 == ~cond; {1998#false} is VALID [2018-11-18 21:08:42,395 INFO L273 TraceCheckUtils]: 42: Hoare triple {1998#false} assume !false; {1998#false} is VALID [2018-11-18 21:08:42,399 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 6 proven. 14 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-18 21:08:42,399 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 21:08:43,198 INFO L273 TraceCheckUtils]: 42: Hoare triple {1998#false} assume !false; {1998#false} is VALID [2018-11-18 21:08:43,198 INFO L273 TraceCheckUtils]: 41: Hoare triple {1998#false} assume 0bv32 == ~cond; {1998#false} is VALID [2018-11-18 21:08:43,198 INFO L273 TraceCheckUtils]: 40: Hoare triple {1998#false} ~cond := #in~cond; {1998#false} is VALID [2018-11-18 21:08:43,199 INFO L256 TraceCheckUtils]: 39: Hoare triple {1998#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1998#false} is VALID [2018-11-18 21:08:43,199 INFO L273 TraceCheckUtils]: 38: Hoare triple {1998#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1998#false} is VALID [2018-11-18 21:08:43,199 INFO L273 TraceCheckUtils]: 37: Hoare triple {1998#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1998#false} is VALID [2018-11-18 21:08:43,200 INFO L273 TraceCheckUtils]: 36: Hoare triple {1998#false} assume true; {1998#false} is VALID [2018-11-18 21:08:43,200 INFO L273 TraceCheckUtils]: 35: Hoare triple {1998#false} ~i~0 := 0bv32; {1998#false} is VALID [2018-11-18 21:08:43,200 INFO L273 TraceCheckUtils]: 34: Hoare triple {1998#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {1998#false} is VALID [2018-11-18 21:08:43,201 INFO L273 TraceCheckUtils]: 33: Hoare triple {1998#false} assume true; {1998#false} is VALID [2018-11-18 21:08:43,201 INFO L273 TraceCheckUtils]: 32: Hoare triple {1998#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1998#false} is VALID [2018-11-18 21:08:43,202 INFO L273 TraceCheckUtils]: 31: Hoare triple {2165#(bvsge main_~j~0 (_ bv1 32))} assume !~bvsge32(~j~0, 1bv32); {1998#false} is VALID [2018-11-18 21:08:43,203 INFO L273 TraceCheckUtils]: 30: Hoare triple {2165#(bvsge main_~j~0 (_ bv1 32))} assume true; {2165#(bvsge main_~j~0 (_ bv1 32))} is VALID [2018-11-18 21:08:43,204 INFO L273 TraceCheckUtils]: 29: Hoare triple {2172#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2165#(bvsge main_~j~0 (_ bv1 32))} is VALID [2018-11-18 21:08:43,206 INFO L273 TraceCheckUtils]: 28: Hoare triple {2176#(or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 main_~MINVAL~0)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2172#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-18 21:08:43,208 INFO L273 TraceCheckUtils]: 27: Hoare triple {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} assume !!~bvsge32(~j~0, 1bv32); {2176#(or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 main_~MINVAL~0)))} is VALID [2018-11-18 21:08:43,213 INFO L273 TraceCheckUtils]: 26: Hoare triple {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} assume true; {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} is VALID [2018-11-18 21:08:43,214 INFO L273 TraceCheckUtils]: 25: Hoare triple {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} is VALID [2018-11-18 21:08:43,215 INFO L273 TraceCheckUtils]: 24: Hoare triple {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} is VALID [2018-11-18 21:08:43,216 INFO L273 TraceCheckUtils]: 23: Hoare triple {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} assume !!~bvsge32(~j~0, 1bv32); {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} is VALID [2018-11-18 21:08:43,216 INFO L273 TraceCheckUtils]: 22: Hoare triple {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} assume true; {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} is VALID [2018-11-18 21:08:43,217 INFO L273 TraceCheckUtils]: 21: Hoare triple {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} is VALID [2018-11-18 21:08:43,217 INFO L273 TraceCheckUtils]: 20: Hoare triple {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} is VALID [2018-11-18 21:08:43,218 INFO L273 TraceCheckUtils]: 19: Hoare triple {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} assume !!~bvsge32(~j~0, 1bv32); {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} is VALID [2018-11-18 21:08:43,219 INFO L273 TraceCheckUtils]: 18: Hoare triple {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} assume true; {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} is VALID [2018-11-18 21:08:43,220 INFO L273 TraceCheckUtils]: 17: Hoare triple {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} is VALID [2018-11-18 21:08:43,220 INFO L273 TraceCheckUtils]: 16: Hoare triple {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} is VALID [2018-11-18 21:08:43,221 INFO L273 TraceCheckUtils]: 15: Hoare triple {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} assume !!~bvsge32(~j~0, 1bv32); {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} is VALID [2018-11-18 21:08:43,222 INFO L273 TraceCheckUtils]: 14: Hoare triple {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} assume true; {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} is VALID [2018-11-18 21:08:43,223 INFO L273 TraceCheckUtils]: 13: Hoare triple {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} is VALID [2018-11-18 21:08:43,223 INFO L273 TraceCheckUtils]: 12: Hoare triple {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} is VALID [2018-11-18 21:08:43,224 INFO L273 TraceCheckUtils]: 11: Hoare triple {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} assume !!~bvsge32(~j~0, 1bv32); {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} is VALID [2018-11-18 21:08:43,225 INFO L273 TraceCheckUtils]: 10: Hoare triple {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} assume true; {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} is VALID [2018-11-18 21:08:43,226 INFO L273 TraceCheckUtils]: 9: Hoare triple {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} is VALID [2018-11-18 21:08:43,227 INFO L273 TraceCheckUtils]: 8: Hoare triple {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} assume true; {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} is VALID [2018-11-18 21:08:43,228 INFO L273 TraceCheckUtils]: 7: Hoare triple {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} is VALID [2018-11-18 21:08:43,233 INFO L273 TraceCheckUtils]: 6: Hoare triple {1997#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {2180#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)) (not (bvsge main_~j~0 (_ bv1 32))) (not (bvsge main_~j~0 main_~MINVAL~0))))} is VALID [2018-11-18 21:08:43,234 INFO L273 TraceCheckUtils]: 5: Hoare triple {1997#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1997#true} is VALID [2018-11-18 21:08:43,235 INFO L256 TraceCheckUtils]: 4: Hoare triple {1997#true} call #t~ret8 := main(); {1997#true} is VALID [2018-11-18 21:08:43,235 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1997#true} {1997#true} #86#return; {1997#true} is VALID [2018-11-18 21:08:43,235 INFO L273 TraceCheckUtils]: 2: Hoare triple {1997#true} assume true; {1997#true} is VALID [2018-11-18 21:08:43,236 INFO L273 TraceCheckUtils]: 1: Hoare triple {1997#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1997#true} is VALID [2018-11-18 21:08:43,236 INFO L256 TraceCheckUtils]: 0: Hoare triple {1997#true} call ULTIMATE.init(); {1997#true} is VALID [2018-11-18 21:08:43,243 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 2 proven. 18 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-18 21:08:43,247 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 21:08:43,247 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 10 [2018-11-18 21:08:43,248 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 43 [2018-11-18 21:08:43,249 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:08:43,249 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 10 states. [2018-11-18 21:08:43,431 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 43 edges. 43 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:08:43,431 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-18 21:08:43,431 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-18 21:08:43,431 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=61, Unknown=0, NotChecked=0, Total=90 [2018-11-18 21:08:43,432 INFO L87 Difference]: Start difference. First operand 53 states and 61 transitions. Second operand 10 states. [2018-11-18 21:08:44,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:44,424 INFO L93 Difference]: Finished difference Result 114 states and 134 transitions. [2018-11-18 21:08:44,425 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 21:08:44,425 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 43 [2018-11-18 21:08:44,425 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:08:44,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10 states. [2018-11-18 21:08:44,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 67 transitions. [2018-11-18 21:08:44,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10 states. [2018-11-18 21:08:44,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 67 transitions. [2018-11-18 21:08:44,430 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 7 states and 67 transitions. [2018-11-18 21:08:44,813 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 67 edges. 67 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:08:44,815 INFO L225 Difference]: With dead ends: 114 [2018-11-18 21:08:44,815 INFO L226 Difference]: Without dead ends: 71 [2018-11-18 21:08:44,816 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=58, Invalid=98, Unknown=0, NotChecked=0, Total=156 [2018-11-18 21:08:44,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states. [2018-11-18 21:08:44,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 53. [2018-11-18 21:08:44,880 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:08:44,880 INFO L82 GeneralOperation]: Start isEquivalent. First operand 71 states. Second operand 53 states. [2018-11-18 21:08:44,880 INFO L74 IsIncluded]: Start isIncluded. First operand 71 states. Second operand 53 states. [2018-11-18 21:08:44,881 INFO L87 Difference]: Start difference. First operand 71 states. Second operand 53 states. [2018-11-18 21:08:44,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:44,885 INFO L93 Difference]: Finished difference Result 71 states and 81 transitions. [2018-11-18 21:08:44,885 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 81 transitions. [2018-11-18 21:08:44,885 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:08:44,885 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:08:44,886 INFO L74 IsIncluded]: Start isIncluded. First operand 53 states. Second operand 71 states. [2018-11-18 21:08:44,886 INFO L87 Difference]: Start difference. First operand 53 states. Second operand 71 states. [2018-11-18 21:08:44,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:44,888 INFO L93 Difference]: Finished difference Result 71 states and 81 transitions. [2018-11-18 21:08:44,889 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 81 transitions. [2018-11-18 21:08:44,889 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:08:44,889 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:08:44,889 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:08:44,889 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:08:44,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53 states. [2018-11-18 21:08:44,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 60 transitions. [2018-11-18 21:08:44,892 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 60 transitions. Word has length 43 [2018-11-18 21:08:44,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:08:44,892 INFO L480 AbstractCegarLoop]: Abstraction has 53 states and 60 transitions. [2018-11-18 21:08:44,892 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-18 21:08:44,892 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 60 transitions. [2018-11-18 21:08:44,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-11-18 21:08:44,893 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:08:44,893 INFO L375 BasicCegarLoop]: trace histogram [6, 5, 5, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:08:44,894 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:08:44,894 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:08:44,894 INFO L82 PathProgramCache]: Analyzing trace with hash 1552141154, now seen corresponding path program 1 times [2018-11-18 21:08:44,894 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:08:44,894 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:08:44,917 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 21:08:45,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:08:45,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:08:45,198 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:08:45,309 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 16 [2018-11-18 21:08:45,317 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 15 [2018-11-18 21:08:45,322 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:08:45,329 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:45,382 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:45,383 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:36, output treesize:32 [2018-11-18 21:08:45,531 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 34 [2018-11-18 21:08:45,570 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:45,572 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:45,574 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 75 [2018-11-18 21:08:45,576 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:08:45,590 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:45,625 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:45,625 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:55, output treesize:51 [2018-11-18 21:08:45,866 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 51 [2018-11-18 21:08:45,934 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:45,936 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:45,938 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:45,940 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:45,942 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:45,944 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:45,946 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 190 [2018-11-18 21:08:45,950 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:08:45,980 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:46,018 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:46,018 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:74, output treesize:70 [2018-11-18 21:08:46,420 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 77 treesize of output 68 [2018-11-18 21:08:46,525 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:46,529 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:46,531 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:46,533 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:46,536 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:46,538 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:46,547 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:46,550 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:46,554 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:46,556 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:46,558 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:46,563 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:46,565 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 68 treesize of output 361 [2018-11-18 21:08:46,570 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:08:46,628 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:46,678 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:46,679 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:93, output treesize:89 [2018-11-18 21:08:47,080 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 37 [2018-11-18 21:08:47,098 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:47,101 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:47,104 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:47,107 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:47,109 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:47,112 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:47,114 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:47,116 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:47,119 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:47,121 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:47,123 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:47,126 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:47,128 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:47,131 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:47,133 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:47,135 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:47,137 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:47,140 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:47,143 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:47,145 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:08:47,147 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 20 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 244 [2018-11-18 21:08:47,150 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:08:47,215 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:47,241 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:08:47,242 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:54, output treesize:50 [2018-11-18 21:08:47,687 INFO L256 TraceCheckUtils]: 0: Hoare triple {2629#true} call ULTIMATE.init(); {2629#true} is VALID [2018-11-18 21:08:47,687 INFO L273 TraceCheckUtils]: 1: Hoare triple {2629#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {2629#true} is VALID [2018-11-18 21:08:47,687 INFO L273 TraceCheckUtils]: 2: Hoare triple {2629#true} assume true; {2629#true} is VALID [2018-11-18 21:08:47,687 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2629#true} {2629#true} #86#return; {2629#true} is VALID [2018-11-18 21:08:47,688 INFO L256 TraceCheckUtils]: 4: Hoare triple {2629#true} call #t~ret8 := main(); {2629#true} is VALID [2018-11-18 21:08:47,688 INFO L273 TraceCheckUtils]: 5: Hoare triple {2629#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {2629#true} is VALID [2018-11-18 21:08:47,696 INFO L273 TraceCheckUtils]: 6: Hoare triple {2629#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {2652#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:47,697 INFO L273 TraceCheckUtils]: 7: Hoare triple {2652#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {2656#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:47,697 INFO L273 TraceCheckUtils]: 8: Hoare triple {2656#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {2656#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:47,698 INFO L273 TraceCheckUtils]: 9: Hoare triple {2656#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {2663#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:47,698 INFO L273 TraceCheckUtils]: 10: Hoare triple {2663#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {2663#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:47,699 INFO L273 TraceCheckUtils]: 11: Hoare triple {2663#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {2663#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:47,700 INFO L273 TraceCheckUtils]: 12: Hoare triple {2663#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2673#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:47,705 INFO L273 TraceCheckUtils]: 13: Hoare triple {2673#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2677#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:47,706 INFO L273 TraceCheckUtils]: 14: Hoare triple {2677#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {2677#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:47,708 INFO L273 TraceCheckUtils]: 15: Hoare triple {2677#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {2677#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:47,715 INFO L273 TraceCheckUtils]: 16: Hoare triple {2677#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2687#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:47,723 INFO L273 TraceCheckUtils]: 17: Hoare triple {2687#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2691#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:47,728 INFO L273 TraceCheckUtils]: 18: Hoare triple {2691#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {2691#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:47,731 INFO L273 TraceCheckUtils]: 19: Hoare triple {2691#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {2691#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:47,739 INFO L273 TraceCheckUtils]: 20: Hoare triple {2691#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2701#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:47,750 INFO L273 TraceCheckUtils]: 21: Hoare triple {2701#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2705#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:47,755 INFO L273 TraceCheckUtils]: 22: Hoare triple {2705#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {2705#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:47,759 INFO L273 TraceCheckUtils]: 23: Hoare triple {2705#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {2705#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:47,766 INFO L273 TraceCheckUtils]: 24: Hoare triple {2705#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2715#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:47,778 INFO L273 TraceCheckUtils]: 25: Hoare triple {2715#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2719#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:47,785 INFO L273 TraceCheckUtils]: 26: Hoare triple {2719#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {2719#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:47,791 INFO L273 TraceCheckUtils]: 27: Hoare triple {2719#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {2719#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:08:47,799 INFO L273 TraceCheckUtils]: 28: Hoare triple {2719#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2729#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:47,801 INFO L273 TraceCheckUtils]: 29: Hoare triple {2729#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2729#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:47,802 INFO L273 TraceCheckUtils]: 30: Hoare triple {2729#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume true; {2729#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:47,803 INFO L273 TraceCheckUtils]: 31: Hoare triple {2729#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsge32(~j~0, 1bv32); {2729#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:47,805 INFO L273 TraceCheckUtils]: 32: Hoare triple {2729#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {2729#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:47,806 INFO L273 TraceCheckUtils]: 33: Hoare triple {2729#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume true; {2729#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:47,821 INFO L273 TraceCheckUtils]: 34: Hoare triple {2729#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {2729#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:47,822 INFO L273 TraceCheckUtils]: 35: Hoare triple {2729#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 0bv32; {2751#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= main_~i~0 (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:47,823 INFO L273 TraceCheckUtils]: 36: Hoare triple {2751#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= main_~i~0 (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume true; {2751#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= main_~i~0 (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:08:47,825 INFO L273 TraceCheckUtils]: 37: Hoare triple {2751#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= main_~i~0 (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv5 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {2758#|main_#t~short7|} is VALID [2018-11-18 21:08:47,826 INFO L273 TraceCheckUtils]: 38: Hoare triple {2758#|main_#t~short7|} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {2630#false} is VALID [2018-11-18 21:08:47,826 INFO L256 TraceCheckUtils]: 39: Hoare triple {2630#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {2630#false} is VALID [2018-11-18 21:08:47,826 INFO L273 TraceCheckUtils]: 40: Hoare triple {2630#false} ~cond := #in~cond; {2630#false} is VALID [2018-11-18 21:08:47,827 INFO L273 TraceCheckUtils]: 41: Hoare triple {2630#false} assume 0bv32 == ~cond; {2630#false} is VALID [2018-11-18 21:08:47,827 INFO L273 TraceCheckUtils]: 42: Hoare triple {2630#false} assume !false; {2630#false} is VALID [2018-11-18 21:08:47,840 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 0 proven. 52 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:08:47,840 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 21:08:49,399 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 76 treesize of output 74 [2018-11-18 21:08:49,413 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 74 treesize of output 78 [2018-11-18 21:08:49,433 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:49,434 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:49,437 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 78 treesize of output 117 [2018-11-18 21:08:49,481 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:49,483 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:49,484 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:49,484 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:49,487 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 96 treesize of output 196 [2018-11-18 21:08:49,661 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:49,662 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:49,663 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:49,663 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:49,665 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:49,666 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:49,669 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 131 treesize of output 315 [2018-11-18 21:08:50,107 WARN L180 SmtUtils]: Spent 376.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 52 [2018-11-18 21:08:50,248 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,249 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,250 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,250 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,251 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,251 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,253 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,254 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,255 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,257 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,258 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,266 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,270 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 12 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 82 treesize of output 182 [2018-11-18 21:08:50,273 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-11-18 21:08:50,420 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,429 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,498 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,514 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,558 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,593 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,632 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,645 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,685 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,698 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,712 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,717 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:08:50,723 INFO L303 Elim1Store]: Index analysis took 339 ms [2018-11-18 21:08:50,821 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 12 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 4 case distinctions, treesize of input 74 treesize of output 248 [2018-11-18 21:08:50,841 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 5 xjuncts. [2018-11-18 21:08:51,565 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 11 xjuncts. [2018-11-18 21:08:52,110 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 7 xjuncts. [2018-11-18 21:08:52,570 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 7 xjuncts. [2018-11-18 21:08:53,022 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 7 xjuncts. [2018-11-18 21:08:53,472 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 7 xjuncts. [2018-11-18 21:08:53,975 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 7 xjuncts. [2018-11-18 21:08:53,976 INFO L202 ElimStorePlain]: Needed 8 recursive calls to eliminate 2 variables, input treesize:76, output treesize:361 [2018-11-18 21:08:54,023 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-18 21:08:55,554 WARN L180 SmtUtils]: Spent 1.18 s on a formula simplification. DAG size of input: 55 DAG size of output: 51 [2018-11-18 21:08:56,131 WARN L180 SmtUtils]: Spent 227.00 ms on a formula simplification. DAG size of input: 40 DAG size of output: 39 [2018-11-18 21:08:56,328 INFO L273 TraceCheckUtils]: 42: Hoare triple {2630#false} assume !false; {2630#false} is VALID [2018-11-18 21:08:56,329 INFO L273 TraceCheckUtils]: 41: Hoare triple {2630#false} assume 0bv32 == ~cond; {2630#false} is VALID [2018-11-18 21:08:56,329 INFO L273 TraceCheckUtils]: 40: Hoare triple {2630#false} ~cond := #in~cond; {2630#false} is VALID [2018-11-18 21:08:56,329 INFO L256 TraceCheckUtils]: 39: Hoare triple {2630#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {2630#false} is VALID [2018-11-18 21:08:56,330 INFO L273 TraceCheckUtils]: 38: Hoare triple {2758#|main_#t~short7|} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {2630#false} is VALID [2018-11-18 21:08:56,332 INFO L273 TraceCheckUtils]: 37: Hoare triple {2789#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {2758#|main_#t~short7|} is VALID [2018-11-18 21:08:56,332 INFO L273 TraceCheckUtils]: 36: Hoare triple {2789#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume true; {2789#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:56,333 INFO L273 TraceCheckUtils]: 35: Hoare triple {2796#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} ~i~0 := 0bv32; {2789#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is VALID [2018-11-18 21:08:56,334 INFO L273 TraceCheckUtils]: 34: Hoare triple {2796#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {2796#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:08:56,335 INFO L273 TraceCheckUtils]: 33: Hoare triple {2796#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume true; {2796#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:08:56,335 INFO L273 TraceCheckUtils]: 32: Hoare triple {2796#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {2796#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:08:56,336 INFO L273 TraceCheckUtils]: 31: Hoare triple {2796#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsge32(~j~0, 1bv32); {2796#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:08:56,336 INFO L273 TraceCheckUtils]: 30: Hoare triple {2796#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume true; {2796#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:08:56,337 INFO L273 TraceCheckUtils]: 29: Hoare triple {2796#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2796#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:08:57,336 INFO L273 TraceCheckUtils]: 28: Hoare triple {2818#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2796#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:08:57,337 INFO L273 TraceCheckUtils]: 27: Hoare triple {2818#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {2818#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:08:57,337 INFO L273 TraceCheckUtils]: 26: Hoare triple {2818#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume true; {2818#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:08:57,563 INFO L273 TraceCheckUtils]: 25: Hoare triple {2828#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2818#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:08:58,138 INFO L273 TraceCheckUtils]: 24: Hoare triple {2832#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2828#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:08:58,139 INFO L273 TraceCheckUtils]: 23: Hoare triple {2832#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {2832#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:08:58,140 INFO L273 TraceCheckUtils]: 22: Hoare triple {2832#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume true; {2832#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:08:58,907 INFO L273 TraceCheckUtils]: 21: Hoare triple {2842#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2832#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:08:59,771 INFO L273 TraceCheckUtils]: 20: Hoare triple {2846#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2842#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:08:59,772 INFO L273 TraceCheckUtils]: 19: Hoare triple {2846#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {2846#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:08:59,772 INFO L273 TraceCheckUtils]: 18: Hoare triple {2846#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume true; {2846#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:09:01,365 INFO L273 TraceCheckUtils]: 17: Hoare triple {2856#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2846#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:09:02,262 INFO L273 TraceCheckUtils]: 16: Hoare triple {2860#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2856#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:09:02,263 INFO L273 TraceCheckUtils]: 15: Hoare triple {2860#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {2860#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:09:02,263 INFO L273 TraceCheckUtils]: 14: Hoare triple {2860#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume true; {2860#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:09:04,270 INFO L273 TraceCheckUtils]: 13: Hoare triple {2870#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967293 32))) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2860#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is UNKNOWN [2018-11-18 21:09:05,534 INFO L273 TraceCheckUtils]: 12: Hoare triple {2874#(and (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) main_~MINVAL~0)) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (forall ((v_arrayElimCell_7 (_ BitVec 32))) (bvsge v_arrayElimCell_7 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32))) (or (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) main_~MINVAL~0)) (or (bvsge (_ bv0 32) main_~MINVAL~0) (not (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))))))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {2870#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967293 32))) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:09:05,536 INFO L273 TraceCheckUtils]: 11: Hoare triple {2874#(and (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) main_~MINVAL~0)) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (forall ((v_arrayElimCell_7 (_ BitVec 32))) (bvsge v_arrayElimCell_7 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32))) (or (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) main_~MINVAL~0)) (or (bvsge (_ bv0 32) main_~MINVAL~0) (not (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))))))} assume !!~bvsge32(~j~0, 1bv32); {2874#(and (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) main_~MINVAL~0)) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (forall ((v_arrayElimCell_7 (_ BitVec 32))) (bvsge v_arrayElimCell_7 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32))) (or (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) main_~MINVAL~0)) (or (bvsge (_ bv0 32) main_~MINVAL~0) (not (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))))))} is VALID [2018-11-18 21:09:05,537 INFO L273 TraceCheckUtils]: 10: Hoare triple {2874#(and (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) main_~MINVAL~0)) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (forall ((v_arrayElimCell_7 (_ BitVec 32))) (bvsge v_arrayElimCell_7 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32))) (or (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) main_~MINVAL~0)) (or (bvsge (_ bv0 32) main_~MINVAL~0) (not (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))))))} assume true; {2874#(and (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) main_~MINVAL~0)) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (forall ((v_arrayElimCell_7 (_ BitVec 32))) (bvsge v_arrayElimCell_7 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32))) (or (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) main_~MINVAL~0)) (or (bvsge (_ bv0 32) main_~MINVAL~0) (not (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))))))} is VALID [2018-11-18 21:09:05,583 INFO L273 TraceCheckUtils]: 9: Hoare triple {2884#(and (or (not (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32))) (bvsge (_ bv0 32) main_~MINVAL~0)) (or (forall ((v_arrayElimCell_7 (_ BitVec 32))) (bvsge v_arrayElimCell_7 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32))) (bvsge (_ bv5 32) main_~MINVAL~0) (or (bvsge (_ bv3 32) main_~MINVAL~0) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32))) (or (bvsge (_ bv4 32) main_~MINVAL~0) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32)) (bvsge (_ bv2 32) main_~MINVAL~0)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {2874#(and (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) main_~MINVAL~0)) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (forall ((v_arrayElimCell_7 (_ BitVec 32))) (bvsge v_arrayElimCell_7 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32))) (or (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv20 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv20 32) main_~i~0)) (_ bv0 32)) (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) main_~MINVAL~0)) (or (bvsge (_ bv0 32) main_~MINVAL~0) (not (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) (bvmul (_ bv20 32) main_~i~0))))))} is VALID [2018-11-18 21:09:05,585 INFO L273 TraceCheckUtils]: 8: Hoare triple {2884#(and (or (not (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32))) (bvsge (_ bv0 32) main_~MINVAL~0)) (or (forall ((v_arrayElimCell_7 (_ BitVec 32))) (bvsge v_arrayElimCell_7 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32))) (bvsge (_ bv5 32) main_~MINVAL~0) (or (bvsge (_ bv3 32) main_~MINVAL~0) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32))) (or (bvsge (_ bv4 32) main_~MINVAL~0) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32)) (bvsge (_ bv2 32) main_~MINVAL~0)))} assume true; {2884#(and (or (not (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32))) (bvsge (_ bv0 32) main_~MINVAL~0)) (or (forall ((v_arrayElimCell_7 (_ BitVec 32))) (bvsge v_arrayElimCell_7 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32))) (bvsge (_ bv5 32) main_~MINVAL~0) (or (bvsge (_ bv3 32) main_~MINVAL~0) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32))) (or (bvsge (_ bv4 32) main_~MINVAL~0) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32)) (bvsge (_ bv2 32) main_~MINVAL~0)))} is VALID [2018-11-18 21:09:05,585 INFO L273 TraceCheckUtils]: 7: Hoare triple {2891#(bvsge (_ bv5 32) main_~MINVAL~0)} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {2884#(and (or (not (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32))) (bvsge (_ bv0 32) main_~MINVAL~0)) (or (forall ((v_arrayElimCell_7 (_ BitVec 32))) (bvsge v_arrayElimCell_7 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32))) (bvsge (_ bv5 32) main_~MINVAL~0) (or (bvsge (_ bv3 32) main_~MINVAL~0) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32))) (or (bvsge (_ bv4 32) main_~MINVAL~0) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32))) (or (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32)) (_ bv0 32)) (bvsge (_ bv2 32) main_~MINVAL~0)))} is VALID [2018-11-18 21:09:05,586 INFO L273 TraceCheckUtils]: 6: Hoare triple {2629#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {2891#(bvsge (_ bv5 32) main_~MINVAL~0)} is VALID [2018-11-18 21:09:05,586 INFO L273 TraceCheckUtils]: 5: Hoare triple {2629#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {2629#true} is VALID [2018-11-18 21:09:05,586 INFO L256 TraceCheckUtils]: 4: Hoare triple {2629#true} call #t~ret8 := main(); {2629#true} is VALID [2018-11-18 21:09:05,587 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2629#true} {2629#true} #86#return; {2629#true} is VALID [2018-11-18 21:09:05,587 INFO L273 TraceCheckUtils]: 2: Hoare triple {2629#true} assume true; {2629#true} is VALID [2018-11-18 21:09:05,587 INFO L273 TraceCheckUtils]: 1: Hoare triple {2629#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {2629#true} is VALID [2018-11-18 21:09:05,587 INFO L256 TraceCheckUtils]: 0: Hoare triple {2629#true} call ULTIMATE.init(); {2629#true} is VALID [2018-11-18 21:09:05,597 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 0 proven. 52 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:09:05,601 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 21:09:05,601 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 29 [2018-11-18 21:09:05,602 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 43 [2018-11-18 21:09:05,602 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:09:05,602 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 29 states. [2018-11-18 21:09:14,102 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 75 edges. 74 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2018-11-18 21:09:14,102 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-11-18 21:09:14,103 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-11-18 21:09:14,103 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=622, Unknown=0, NotChecked=0, Total=812 [2018-11-18 21:09:14,103 INFO L87 Difference]: Start difference. First operand 53 states and 60 transitions. Second operand 29 states. [2018-11-18 21:09:18,546 WARN L180 SmtUtils]: Spent 103.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 44 [2018-11-18 21:09:19,243 WARN L180 SmtUtils]: Spent 374.00 ms on a formula simplification. DAG size of input: 98 DAG size of output: 84 [2018-11-18 21:09:21,698 WARN L180 SmtUtils]: Spent 266.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 68 [2018-11-18 21:09:22,835 WARN L180 SmtUtils]: Spent 259.00 ms on a formula simplification. DAG size of input: 76 DAG size of output: 64 [2018-11-18 21:09:23,534 WARN L180 SmtUtils]: Spent 232.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 55 [2018-11-18 21:09:24,144 WARN L180 SmtUtils]: Spent 213.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 51 [2018-11-18 21:09:28,582 WARN L180 SmtUtils]: Spent 184.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 45 [2018-11-18 21:09:29,034 WARN L180 SmtUtils]: Spent 148.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 41 [2018-11-18 21:09:31,337 WARN L180 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 36 [2018-11-18 21:09:38,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:38,226 INFO L93 Difference]: Finished difference Result 272 states and 333 transitions. [2018-11-18 21:09:38,226 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-11-18 21:09:38,226 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 43 [2018-11-18 21:09:38,227 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:09:38,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2018-11-18 21:09:38,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 235 transitions. [2018-11-18 21:09:38,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2018-11-18 21:09:38,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 235 transitions. [2018-11-18 21:09:38,248 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 40 states and 235 transitions. [2018-11-18 21:09:39,449 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 235 edges. 235 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:09:39,455 INFO L225 Difference]: With dead ends: 272 [2018-11-18 21:09:39,455 INFO L226 Difference]: Without dead ends: 229 [2018-11-18 21:09:39,457 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 110 GetRequests, 58 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 780 ImplicationChecksByTransitivity, 10.9s TimeCoverageRelationStatistics Valid=684, Invalid=2178, Unknown=0, NotChecked=0, Total=2862 [2018-11-18 21:09:39,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 229 states. [2018-11-18 21:09:39,812 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 229 to 130. [2018-11-18 21:09:39,812 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:09:39,812 INFO L82 GeneralOperation]: Start isEquivalent. First operand 229 states. Second operand 130 states. [2018-11-18 21:09:39,812 INFO L74 IsIncluded]: Start isIncluded. First operand 229 states. Second operand 130 states. [2018-11-18 21:09:39,812 INFO L87 Difference]: Start difference. First operand 229 states. Second operand 130 states. [2018-11-18 21:09:39,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:39,824 INFO L93 Difference]: Finished difference Result 229 states and 275 transitions. [2018-11-18 21:09:39,824 INFO L276 IsEmpty]: Start isEmpty. Operand 229 states and 275 transitions. [2018-11-18 21:09:39,825 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:09:39,825 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:09:39,825 INFO L74 IsIncluded]: Start isIncluded. First operand 130 states. Second operand 229 states. [2018-11-18 21:09:39,826 INFO L87 Difference]: Start difference. First operand 130 states. Second operand 229 states. [2018-11-18 21:09:39,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:39,836 INFO L93 Difference]: Finished difference Result 229 states and 275 transitions. [2018-11-18 21:09:39,836 INFO L276 IsEmpty]: Start isEmpty. Operand 229 states and 275 transitions. [2018-11-18 21:09:39,837 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:09:39,837 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:09:39,837 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:09:39,837 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:09:39,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 130 states. [2018-11-18 21:09:39,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 130 states to 130 states and 152 transitions. [2018-11-18 21:09:39,843 INFO L78 Accepts]: Start accepts. Automaton has 130 states and 152 transitions. Word has length 43 [2018-11-18 21:09:39,843 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:09:39,843 INFO L480 AbstractCegarLoop]: Abstraction has 130 states and 152 transitions. [2018-11-18 21:09:39,843 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-11-18 21:09:39,843 INFO L276 IsEmpty]: Start isEmpty. Operand 130 states and 152 transitions. [2018-11-18 21:09:39,844 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-11-18 21:09:39,844 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:09:39,844 INFO L375 BasicCegarLoop]: trace histogram [7, 6, 6, 4, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:09:39,845 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:09:39,845 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:09:39,845 INFO L82 PathProgramCache]: Analyzing trace with hash -5432474, now seen corresponding path program 1 times [2018-11-18 21:09:39,845 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:09:39,846 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:09:39,889 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:09:39,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:09:40,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:09:40,037 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:09:40,126 INFO L256 TraceCheckUtils]: 0: Hoare triple {3941#true} call ULTIMATE.init(); {3941#true} is VALID [2018-11-18 21:09:40,126 INFO L273 TraceCheckUtils]: 1: Hoare triple {3941#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {3941#true} is VALID [2018-11-18 21:09:40,127 INFO L273 TraceCheckUtils]: 2: Hoare triple {3941#true} assume true; {3941#true} is VALID [2018-11-18 21:09:40,127 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {3941#true} {3941#true} #86#return; {3941#true} is VALID [2018-11-18 21:09:40,127 INFO L256 TraceCheckUtils]: 4: Hoare triple {3941#true} call #t~ret8 := main(); {3941#true} is VALID [2018-11-18 21:09:40,127 INFO L273 TraceCheckUtils]: 5: Hoare triple {3941#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {3941#true} is VALID [2018-11-18 21:09:40,127 INFO L273 TraceCheckUtils]: 6: Hoare triple {3941#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {3941#true} is VALID [2018-11-18 21:09:40,128 INFO L273 TraceCheckUtils]: 7: Hoare triple {3941#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {3941#true} is VALID [2018-11-18 21:09:40,128 INFO L273 TraceCheckUtils]: 8: Hoare triple {3941#true} assume true; {3941#true} is VALID [2018-11-18 21:09:40,133 INFO L273 TraceCheckUtils]: 9: Hoare triple {3941#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {3973#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:40,134 INFO L273 TraceCheckUtils]: 10: Hoare triple {3973#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} assume true; {3973#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:40,134 INFO L273 TraceCheckUtils]: 11: Hoare triple {3973#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {3973#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:40,137 INFO L273 TraceCheckUtils]: 12: Hoare triple {3973#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {3973#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:40,137 INFO L273 TraceCheckUtils]: 13: Hoare triple {3973#(= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3986#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:40,140 INFO L273 TraceCheckUtils]: 14: Hoare triple {3986#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} assume true; {3986#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:40,140 INFO L273 TraceCheckUtils]: 15: Hoare triple {3986#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {3986#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:40,142 INFO L273 TraceCheckUtils]: 16: Hoare triple {3986#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {3986#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:40,142 INFO L273 TraceCheckUtils]: 17: Hoare triple {3986#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3999#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:40,143 INFO L273 TraceCheckUtils]: 18: Hoare triple {3999#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} assume true; {3999#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:40,143 INFO L273 TraceCheckUtils]: 19: Hoare triple {3999#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {3999#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:40,143 INFO L273 TraceCheckUtils]: 20: Hoare triple {3999#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {3999#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:40,144 INFO L273 TraceCheckUtils]: 21: Hoare triple {3999#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4012#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:40,144 INFO L273 TraceCheckUtils]: 22: Hoare triple {4012#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} assume true; {4012#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:40,144 INFO L273 TraceCheckUtils]: 23: Hoare triple {4012#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {4012#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:40,145 INFO L273 TraceCheckUtils]: 24: Hoare triple {4012#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {4012#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:40,146 INFO L273 TraceCheckUtils]: 25: Hoare triple {4012#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4025#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:40,146 INFO L273 TraceCheckUtils]: 26: Hoare triple {4025#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} assume true; {4025#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:40,147 INFO L273 TraceCheckUtils]: 27: Hoare triple {4025#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {4025#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:40,147 INFO L273 TraceCheckUtils]: 28: Hoare triple {4025#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {4025#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:40,148 INFO L273 TraceCheckUtils]: 29: Hoare triple {4025#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4038#(= main_~j~0 (_ bv0 32))} is VALID [2018-11-18 21:09:40,149 INFO L273 TraceCheckUtils]: 30: Hoare triple {4038#(= main_~j~0 (_ bv0 32))} assume true; {4038#(= main_~j~0 (_ bv0 32))} is VALID [2018-11-18 21:09:40,149 INFO L273 TraceCheckUtils]: 31: Hoare triple {4038#(= main_~j~0 (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {3942#false} is VALID [2018-11-18 21:09:40,150 INFO L273 TraceCheckUtils]: 32: Hoare triple {3942#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {3942#false} is VALID [2018-11-18 21:09:40,150 INFO L273 TraceCheckUtils]: 33: Hoare triple {3942#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3942#false} is VALID [2018-11-18 21:09:40,150 INFO L273 TraceCheckUtils]: 34: Hoare triple {3942#false} assume true; {3942#false} is VALID [2018-11-18 21:09:40,150 INFO L273 TraceCheckUtils]: 35: Hoare triple {3942#false} assume !~bvsge32(~j~0, 1bv32); {3942#false} is VALID [2018-11-18 21:09:40,151 INFO L273 TraceCheckUtils]: 36: Hoare triple {3942#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3942#false} is VALID [2018-11-18 21:09:40,151 INFO L273 TraceCheckUtils]: 37: Hoare triple {3942#false} assume true; {3942#false} is VALID [2018-11-18 21:09:40,151 INFO L273 TraceCheckUtils]: 38: Hoare triple {3942#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {3942#false} is VALID [2018-11-18 21:09:40,151 INFO L273 TraceCheckUtils]: 39: Hoare triple {3942#false} ~i~0 := 0bv32; {3942#false} is VALID [2018-11-18 21:09:40,151 INFO L273 TraceCheckUtils]: 40: Hoare triple {3942#false} assume true; {3942#false} is VALID [2018-11-18 21:09:40,152 INFO L273 TraceCheckUtils]: 41: Hoare triple {3942#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {3942#false} is VALID [2018-11-18 21:09:40,152 INFO L273 TraceCheckUtils]: 42: Hoare triple {3942#false} assume #t~short7; {3942#false} is VALID [2018-11-18 21:09:40,152 INFO L256 TraceCheckUtils]: 43: Hoare triple {3942#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {3942#false} is VALID [2018-11-18 21:09:40,152 INFO L273 TraceCheckUtils]: 44: Hoare triple {3942#false} ~cond := #in~cond; {3942#false} is VALID [2018-11-18 21:09:40,152 INFO L273 TraceCheckUtils]: 45: Hoare triple {3942#false} assume !(0bv32 == ~cond); {3942#false} is VALID [2018-11-18 21:09:40,152 INFO L273 TraceCheckUtils]: 46: Hoare triple {3942#false} assume true; {3942#false} is VALID [2018-11-18 21:09:40,153 INFO L268 TraceCheckUtils]: 47: Hoare quadruple {3942#false} {3942#false} #90#return; {3942#false} is VALID [2018-11-18 21:09:40,153 INFO L273 TraceCheckUtils]: 48: Hoare triple {3942#false} havoc #t~mem5;havoc #t~mem6;havoc #t~short7; {3942#false} is VALID [2018-11-18 21:09:40,153 INFO L273 TraceCheckUtils]: 49: Hoare triple {3942#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3942#false} is VALID [2018-11-18 21:09:40,153 INFO L273 TraceCheckUtils]: 50: Hoare triple {3942#false} assume true; {3942#false} is VALID [2018-11-18 21:09:40,153 INFO L273 TraceCheckUtils]: 51: Hoare triple {3942#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {3942#false} is VALID [2018-11-18 21:09:40,153 INFO L273 TraceCheckUtils]: 52: Hoare triple {3942#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {3942#false} is VALID [2018-11-18 21:09:40,153 INFO L256 TraceCheckUtils]: 53: Hoare triple {3942#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {3942#false} is VALID [2018-11-18 21:09:40,154 INFO L273 TraceCheckUtils]: 54: Hoare triple {3942#false} ~cond := #in~cond; {3942#false} is VALID [2018-11-18 21:09:40,154 INFO L273 TraceCheckUtils]: 55: Hoare triple {3942#false} assume 0bv32 == ~cond; {3942#false} is VALID [2018-11-18 21:09:40,154 INFO L273 TraceCheckUtils]: 56: Hoare triple {3942#false} assume !false; {3942#false} is VALID [2018-11-18 21:09:40,156 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 24 proven. 50 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-18 21:09:40,157 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 21:09:40,452 INFO L273 TraceCheckUtils]: 56: Hoare triple {3942#false} assume !false; {3942#false} is VALID [2018-11-18 21:09:40,452 INFO L273 TraceCheckUtils]: 55: Hoare triple {3942#false} assume 0bv32 == ~cond; {3942#false} is VALID [2018-11-18 21:09:40,453 INFO L273 TraceCheckUtils]: 54: Hoare triple {3942#false} ~cond := #in~cond; {3942#false} is VALID [2018-11-18 21:09:40,453 INFO L256 TraceCheckUtils]: 53: Hoare triple {3942#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {3942#false} is VALID [2018-11-18 21:09:40,453 INFO L273 TraceCheckUtils]: 52: Hoare triple {3942#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {3942#false} is VALID [2018-11-18 21:09:40,453 INFO L273 TraceCheckUtils]: 51: Hoare triple {3942#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {3942#false} is VALID [2018-11-18 21:09:40,454 INFO L273 TraceCheckUtils]: 50: Hoare triple {3942#false} assume true; {3942#false} is VALID [2018-11-18 21:09:40,454 INFO L273 TraceCheckUtils]: 49: Hoare triple {3942#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3942#false} is VALID [2018-11-18 21:09:40,454 INFO L273 TraceCheckUtils]: 48: Hoare triple {3942#false} havoc #t~mem5;havoc #t~mem6;havoc #t~short7; {3942#false} is VALID [2018-11-18 21:09:40,454 INFO L268 TraceCheckUtils]: 47: Hoare quadruple {3941#true} {3942#false} #90#return; {3942#false} is VALID [2018-11-18 21:09:40,454 INFO L273 TraceCheckUtils]: 46: Hoare triple {3941#true} assume true; {3941#true} is VALID [2018-11-18 21:09:40,455 INFO L273 TraceCheckUtils]: 45: Hoare triple {3941#true} assume !(0bv32 == ~cond); {3941#true} is VALID [2018-11-18 21:09:40,455 INFO L273 TraceCheckUtils]: 44: Hoare triple {3941#true} ~cond := #in~cond; {3941#true} is VALID [2018-11-18 21:09:40,455 INFO L256 TraceCheckUtils]: 43: Hoare triple {3942#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {3941#true} is VALID [2018-11-18 21:09:40,455 INFO L273 TraceCheckUtils]: 42: Hoare triple {3942#false} assume #t~short7; {3942#false} is VALID [2018-11-18 21:09:40,455 INFO L273 TraceCheckUtils]: 41: Hoare triple {3942#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {3942#false} is VALID [2018-11-18 21:09:40,456 INFO L273 TraceCheckUtils]: 40: Hoare triple {3942#false} assume true; {3942#false} is VALID [2018-11-18 21:09:40,456 INFO L273 TraceCheckUtils]: 39: Hoare triple {3942#false} ~i~0 := 0bv32; {3942#false} is VALID [2018-11-18 21:09:40,456 INFO L273 TraceCheckUtils]: 38: Hoare triple {3942#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {3942#false} is VALID [2018-11-18 21:09:40,456 INFO L273 TraceCheckUtils]: 37: Hoare triple {3942#false} assume true; {3942#false} is VALID [2018-11-18 21:09:40,456 INFO L273 TraceCheckUtils]: 36: Hoare triple {3942#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3942#false} is VALID [2018-11-18 21:09:40,456 INFO L273 TraceCheckUtils]: 35: Hoare triple {3942#false} assume !~bvsge32(~j~0, 1bv32); {3942#false} is VALID [2018-11-18 21:09:40,456 INFO L273 TraceCheckUtils]: 34: Hoare triple {3942#false} assume true; {3942#false} is VALID [2018-11-18 21:09:40,457 INFO L273 TraceCheckUtils]: 33: Hoare triple {3942#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3942#false} is VALID [2018-11-18 21:09:40,457 INFO L273 TraceCheckUtils]: 32: Hoare triple {3942#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {3942#false} is VALID [2018-11-18 21:09:40,460 INFO L273 TraceCheckUtils]: 31: Hoare triple {4195#(not (bvsge main_~j~0 (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {3942#false} is VALID [2018-11-18 21:09:40,460 INFO L273 TraceCheckUtils]: 30: Hoare triple {4195#(not (bvsge main_~j~0 (_ bv1 32)))} assume true; {4195#(not (bvsge main_~j~0 (_ bv1 32)))} is VALID [2018-11-18 21:09:40,461 INFO L273 TraceCheckUtils]: 29: Hoare triple {4202#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4195#(not (bvsge main_~j~0 (_ bv1 32)))} is VALID [2018-11-18 21:09:40,462 INFO L273 TraceCheckUtils]: 28: Hoare triple {4202#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {4202#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} is VALID [2018-11-18 21:09:40,462 INFO L273 TraceCheckUtils]: 27: Hoare triple {4202#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {4202#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} is VALID [2018-11-18 21:09:40,463 INFO L273 TraceCheckUtils]: 26: Hoare triple {4202#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} assume true; {4202#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} is VALID [2018-11-18 21:09:40,467 INFO L273 TraceCheckUtils]: 25: Hoare triple {4215#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4202#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} is VALID [2018-11-18 21:09:40,468 INFO L273 TraceCheckUtils]: 24: Hoare triple {4215#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {4215#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} is VALID [2018-11-18 21:09:40,468 INFO L273 TraceCheckUtils]: 23: Hoare triple {4215#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {4215#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} is VALID [2018-11-18 21:09:40,469 INFO L273 TraceCheckUtils]: 22: Hoare triple {4215#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} assume true; {4215#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} is VALID [2018-11-18 21:09:40,473 INFO L273 TraceCheckUtils]: 21: Hoare triple {4228#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4215#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} is VALID [2018-11-18 21:09:40,474 INFO L273 TraceCheckUtils]: 20: Hoare triple {4228#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {4228#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} is VALID [2018-11-18 21:09:40,474 INFO L273 TraceCheckUtils]: 19: Hoare triple {4228#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {4228#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} is VALID [2018-11-18 21:09:40,475 INFO L273 TraceCheckUtils]: 18: Hoare triple {4228#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} assume true; {4228#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} is VALID [2018-11-18 21:09:40,478 INFO L273 TraceCheckUtils]: 17: Hoare triple {4241#(not (bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4228#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} is VALID [2018-11-18 21:09:40,479 INFO L273 TraceCheckUtils]: 16: Hoare triple {4241#(not (bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {4241#(not (bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32)))} is VALID [2018-11-18 21:09:40,479 INFO L273 TraceCheckUtils]: 15: Hoare triple {4241#(not (bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {4241#(not (bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32)))} is VALID [2018-11-18 21:09:40,479 INFO L273 TraceCheckUtils]: 14: Hoare triple {4241#(not (bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32)))} assume true; {4241#(not (bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32)))} is VALID [2018-11-18 21:09:40,483 INFO L273 TraceCheckUtils]: 13: Hoare triple {4254#(not (bvsge (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv1 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4241#(not (bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32)))} is VALID [2018-11-18 21:09:40,484 INFO L273 TraceCheckUtils]: 12: Hoare triple {4254#(not (bvsge (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv1 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {4254#(not (bvsge (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv1 32)))} is VALID [2018-11-18 21:09:40,484 INFO L273 TraceCheckUtils]: 11: Hoare triple {4254#(not (bvsge (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {4254#(not (bvsge (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv1 32)))} is VALID [2018-11-18 21:09:40,485 INFO L273 TraceCheckUtils]: 10: Hoare triple {4254#(not (bvsge (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv1 32)))} assume true; {4254#(not (bvsge (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv1 32)))} is VALID [2018-11-18 21:09:40,485 INFO L273 TraceCheckUtils]: 9: Hoare triple {3941#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {4254#(not (bvsge (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv1 32)))} is VALID [2018-11-18 21:09:40,485 INFO L273 TraceCheckUtils]: 8: Hoare triple {3941#true} assume true; {3941#true} is VALID [2018-11-18 21:09:40,485 INFO L273 TraceCheckUtils]: 7: Hoare triple {3941#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {3941#true} is VALID [2018-11-18 21:09:40,485 INFO L273 TraceCheckUtils]: 6: Hoare triple {3941#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {3941#true} is VALID [2018-11-18 21:09:40,486 INFO L273 TraceCheckUtils]: 5: Hoare triple {3941#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {3941#true} is VALID [2018-11-18 21:09:40,486 INFO L256 TraceCheckUtils]: 4: Hoare triple {3941#true} call #t~ret8 := main(); {3941#true} is VALID [2018-11-18 21:09:40,486 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {3941#true} {3941#true} #86#return; {3941#true} is VALID [2018-11-18 21:09:40,486 INFO L273 TraceCheckUtils]: 2: Hoare triple {3941#true} assume true; {3941#true} is VALID [2018-11-18 21:09:40,486 INFO L273 TraceCheckUtils]: 1: Hoare triple {3941#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {3941#true} is VALID [2018-11-18 21:09:40,487 INFO L256 TraceCheckUtils]: 0: Hoare triple {3941#true} call ULTIMATE.init(); {3941#true} is VALID [2018-11-18 21:09:40,491 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 26 proven. 50 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-18 21:09:40,495 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 21:09:40,495 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 14 [2018-11-18 21:09:40,495 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 57 [2018-11-18 21:09:40,496 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:09:40,496 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 14 states. [2018-11-18 21:09:40,675 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 81 edges. 81 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:09:40,675 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-18 21:09:40,675 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-18 21:09:40,676 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=136, Unknown=0, NotChecked=0, Total=182 [2018-11-18 21:09:40,676 INFO L87 Difference]: Start difference. First operand 130 states and 152 transitions. Second operand 14 states. [2018-11-18 21:09:42,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:42,482 INFO L93 Difference]: Finished difference Result 179 states and 208 transitions. [2018-11-18 21:09:42,483 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-18 21:09:42,483 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 57 [2018-11-18 21:09:42,483 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:09:42,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2018-11-18 21:09:42,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 79 transitions. [2018-11-18 21:09:42,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2018-11-18 21:09:42,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 79 transitions. [2018-11-18 21:09:42,487 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 8 states and 79 transitions. [2018-11-18 21:09:42,703 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 79 edges. 79 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:09:42,705 INFO L225 Difference]: With dead ends: 179 [2018-11-18 21:09:42,705 INFO L226 Difference]: Without dead ends: 94 [2018-11-18 21:09:42,706 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 113 GetRequests, 101 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=46, Invalid=136, Unknown=0, NotChecked=0, Total=182 [2018-11-18 21:09:42,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-11-18 21:09:42,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 94. [2018-11-18 21:09:42,883 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:09:42,883 INFO L82 GeneralOperation]: Start isEquivalent. First operand 94 states. Second operand 94 states. [2018-11-18 21:09:42,884 INFO L74 IsIncluded]: Start isIncluded. First operand 94 states. Second operand 94 states. [2018-11-18 21:09:42,884 INFO L87 Difference]: Start difference. First operand 94 states. Second operand 94 states. [2018-11-18 21:09:42,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:42,888 INFO L93 Difference]: Finished difference Result 94 states and 102 transitions. [2018-11-18 21:09:42,888 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 102 transitions. [2018-11-18 21:09:42,888 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:09:42,889 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:09:42,889 INFO L74 IsIncluded]: Start isIncluded. First operand 94 states. Second operand 94 states. [2018-11-18 21:09:42,889 INFO L87 Difference]: Start difference. First operand 94 states. Second operand 94 states. [2018-11-18 21:09:42,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:42,893 INFO L93 Difference]: Finished difference Result 94 states and 102 transitions. [2018-11-18 21:09:42,893 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 102 transitions. [2018-11-18 21:09:42,893 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:09:42,893 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:09:42,894 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:09:42,894 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:09:42,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2018-11-18 21:09:42,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 102 transitions. [2018-11-18 21:09:42,897 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 102 transitions. Word has length 57 [2018-11-18 21:09:42,898 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:09:42,898 INFO L480 AbstractCegarLoop]: Abstraction has 94 states and 102 transitions. [2018-11-18 21:09:42,898 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-18 21:09:42,898 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 102 transitions. [2018-11-18 21:09:42,899 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-11-18 21:09:42,899 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:09:42,899 INFO L375 BasicCegarLoop]: trace histogram [12, 10, 10, 8, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:09:42,899 INFO L423 AbstractCegarLoop]: === Iteration 10 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:09:42,899 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:09:42,900 INFO L82 PathProgramCache]: Analyzing trace with hash -1704609870, now seen corresponding path program 2 times [2018-11-18 21:09:42,900 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:09:42,900 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:09:42,921 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-18 21:09:43,425 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 21:09:43,425 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 21:09:43,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:09:43,587 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:09:43,677 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 16 [2018-11-18 21:09:43,683 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 15 [2018-11-18 21:09:43,685 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:09:43,692 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:43,711 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:43,712 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:36, output treesize:32 [2018-11-18 21:09:43,850 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 34 [2018-11-18 21:09:43,896 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:43,897 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:43,899 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 75 [2018-11-18 21:09:43,901 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:09:43,914 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:43,952 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:43,952 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:55, output treesize:51 [2018-11-18 21:09:44,169 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 51 [2018-11-18 21:09:44,231 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:44,233 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:44,237 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:44,239 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:44,241 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:44,243 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:44,244 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 190 [2018-11-18 21:09:44,247 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:09:44,275 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:44,315 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:44,316 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:74, output treesize:70 [2018-11-18 21:09:44,558 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 77 treesize of output 68 [2018-11-18 21:09:44,672 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:44,675 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:44,679 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:44,682 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:44,684 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:44,688 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:44,694 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:44,696 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:44,698 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:44,700 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:44,707 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:44,709 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:44,711 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 68 treesize of output 361 [2018-11-18 21:09:44,715 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:09:44,778 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:44,828 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:44,829 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:93, output treesize:89 [2018-11-18 21:09:45,200 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 54 [2018-11-18 21:09:45,219 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:45,220 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:45,222 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:45,223 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:45,226 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:45,227 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:45,229 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:45,230 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:45,231 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:45,233 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:45,235 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:45,236 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:45,238 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:45,239 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:45,241 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:45,242 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:45,244 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:45,246 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:45,249 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:45,251 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:45,253 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 20 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 54 treesize of output 385 [2018-11-18 21:09:45,257 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:09:45,318 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:45,356 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:45,356 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:76, output treesize:72 [2018-11-18 21:09:46,138 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 84 treesize of output 71 [2018-11-18 21:09:46,152 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,154 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,155 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,157 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,158 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,160 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,161 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,163 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,164 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,166 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,169 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,170 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,171 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,172 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,174 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,177 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,179 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,180 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,182 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,184 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,185 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,187 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,188 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,190 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,192 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,194 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 25 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 525 [2018-11-18 21:09:46,200 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:09:46,298 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:46,349 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:46,349 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:98, output treesize:94 [2018-11-18 21:09:46,703 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 103 treesize of output 88 [2018-11-18 21:09:46,758 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,759 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,760 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,762 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,764 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,765 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,767 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,769 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,771 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,773 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,774 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,780 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,781 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,782 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,783 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,785 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,787 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,788 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,790 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,792 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,794 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,797 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,800 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,803 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,806 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,809 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,812 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,814 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,817 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,820 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,821 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:46,824 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,826 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,828 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:46,833 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 31 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 88 treesize of output 741 [2018-11-18 21:09:46,846 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:09:46,986 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:47,050 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:47,051 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:117, output treesize:113 [2018-11-18 21:09:47,485 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 122 treesize of output 105 [2018-11-18 21:09:47,568 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,569 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,570 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,571 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,573 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,574 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,576 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,577 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,579 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,580 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,582 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,583 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,585 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,586 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,607 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,609 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,610 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,611 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,612 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,614 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,615 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,616 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,617 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,619 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,620 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,622 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,623 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,625 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,627 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,628 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,630 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,632 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,633 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,635 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,636 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,638 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,655 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:47,656 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,657 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,658 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:47,659 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,660 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,661 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:47,664 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 38 disjoint index pairs (out of 21 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 105 treesize of output 964 [2018-11-18 21:09:47,672 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:09:47,856 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:47,943 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:47,944 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:136, output treesize:156 [2018-11-18 21:09:48,504 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 165 treesize of output 142 [2018-11-18 21:09:48,631 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,636 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,641 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,646 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,652 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,657 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,662 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,668 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,673 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,678 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,685 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,688 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,693 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,697 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,702 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,719 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,725 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,731 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,736 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,741 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,774 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,797 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,817 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,823 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,827 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,832 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,837 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,842 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,845 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,851 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,855 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,860 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,866 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,872 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,876 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,881 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,887 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,893 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,897 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,902 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,907 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,913 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,920 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,927 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,934 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,939 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,944 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,948 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,954 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:48,954 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:48,956 INFO L303 Elim1Store]: Index analysis took 339 ms [2018-11-18 21:09:48,958 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 46 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 142 treesize of output 1166 [2018-11-18 21:09:48,974 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:09:49,195 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:49,315 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:49,316 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:179, output treesize:175 [2018-11-18 21:09:49,622 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification that was a NOOP. DAG size: 64 [2018-11-18 21:09:49,919 WARN L180 SmtUtils]: Spent 111.00 ms on a formula simplification that was a NOOP. DAG size: 65 [2018-11-18 21:09:50,060 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 105 treesize of output 80 [2018-11-18 21:09:50,102 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,104 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,107 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,110 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,113 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,116 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,119 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,122 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,125 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,127 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,130 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,132 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,134 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,137 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,140 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,143 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,145 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,147 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,150 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,153 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,156 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,159 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,161 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,164 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,167 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,194 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,196 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,197 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,198 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,199 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,200 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,201 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,215 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,216 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,217 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,217 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,218 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,219 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,220 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,221 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,223 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,224 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,225 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,227 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,228 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,230 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,231 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,233 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,234 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,236 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,237 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,239 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,240 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,242 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,243 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:50,244 INFO L303 Elim1Store]: Index analysis took 149 ms [2018-11-18 21:09:50,247 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 55 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 80 treesize of output 603 [2018-11-18 21:09:50,255 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:09:50,483 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:50,539 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:50,540 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:111, output treesize:107 [2018-11-18 21:09:50,996 INFO L256 TraceCheckUtils]: 0: Hoare triple {4839#true} call ULTIMATE.init(); {4839#true} is VALID [2018-11-18 21:09:50,996 INFO L273 TraceCheckUtils]: 1: Hoare triple {4839#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {4839#true} is VALID [2018-11-18 21:09:50,996 INFO L273 TraceCheckUtils]: 2: Hoare triple {4839#true} assume true; {4839#true} is VALID [2018-11-18 21:09:50,997 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {4839#true} {4839#true} #86#return; {4839#true} is VALID [2018-11-18 21:09:50,997 INFO L256 TraceCheckUtils]: 4: Hoare triple {4839#true} call #t~ret8 := main(); {4839#true} is VALID [2018-11-18 21:09:50,997 INFO L273 TraceCheckUtils]: 5: Hoare triple {4839#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {4839#true} is VALID [2018-11-18 21:09:50,998 INFO L273 TraceCheckUtils]: 6: Hoare triple {4839#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {4862#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:50,998 INFO L273 TraceCheckUtils]: 7: Hoare triple {4862#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 5bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 5bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {4866#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:50,999 INFO L273 TraceCheckUtils]: 8: Hoare triple {4866#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {4866#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:50,999 INFO L273 TraceCheckUtils]: 9: Hoare triple {4866#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {4873#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,000 INFO L273 TraceCheckUtils]: 10: Hoare triple {4873#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {4873#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,000 INFO L273 TraceCheckUtils]: 11: Hoare triple {4873#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {4873#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,002 INFO L273 TraceCheckUtils]: 12: Hoare triple {4873#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {4883#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,007 INFO L273 TraceCheckUtils]: 13: Hoare triple {4883#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4887#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,008 INFO L273 TraceCheckUtils]: 14: Hoare triple {4887#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {4887#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,009 INFO L273 TraceCheckUtils]: 15: Hoare triple {4887#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {4887#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,014 INFO L273 TraceCheckUtils]: 16: Hoare triple {4887#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {4897#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,022 INFO L273 TraceCheckUtils]: 17: Hoare triple {4897#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4901#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,039 INFO L273 TraceCheckUtils]: 18: Hoare triple {4901#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {4901#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,043 INFO L273 TraceCheckUtils]: 19: Hoare triple {4901#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {4901#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,051 INFO L273 TraceCheckUtils]: 20: Hoare triple {4901#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {4911#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,062 INFO L273 TraceCheckUtils]: 21: Hoare triple {4911#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4915#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,067 INFO L273 TraceCheckUtils]: 22: Hoare triple {4915#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {4915#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,073 INFO L273 TraceCheckUtils]: 23: Hoare triple {4915#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {4915#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,080 INFO L273 TraceCheckUtils]: 24: Hoare triple {4915#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {4925#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,093 INFO L273 TraceCheckUtils]: 25: Hoare triple {4925#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4929#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,098 INFO L273 TraceCheckUtils]: 26: Hoare triple {4929#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {4929#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,104 INFO L273 TraceCheckUtils]: 27: Hoare triple {4929#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {4929#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,116 INFO L273 TraceCheckUtils]: 28: Hoare triple {4929#(and (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {4939#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967288 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,121 INFO L273 TraceCheckUtils]: 29: Hoare triple {4939#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967288 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4939#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967288 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,124 INFO L273 TraceCheckUtils]: 30: Hoare triple {4939#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967288 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {4939#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967288 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,129 INFO L273 TraceCheckUtils]: 31: Hoare triple {4939#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967288 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~j~0, 1bv32); {4939#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967288 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,135 INFO L273 TraceCheckUtils]: 32: Hoare triple {4939#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967276 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967288 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967280 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {4952#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,136 INFO L273 TraceCheckUtils]: 33: Hoare triple {4952#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} assume true; {4952#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,155 INFO L273 TraceCheckUtils]: 34: Hoare triple {4952#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32));~j~0 := 5bv32; {4959#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,159 INFO L273 TraceCheckUtils]: 35: Hoare triple {4959#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} assume true; {4959#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,164 INFO L273 TraceCheckUtils]: 36: Hoare triple {4959#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {4959#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,171 INFO L273 TraceCheckUtils]: 37: Hoare triple {4959#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {4969#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,180 INFO L273 TraceCheckUtils]: 38: Hoare triple {4969#(and (= (bvadd main_~j~0 (_ bv4294967291 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4973#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,185 INFO L273 TraceCheckUtils]: 39: Hoare triple {4973#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} assume true; {4973#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,190 INFO L273 TraceCheckUtils]: 40: Hoare triple {4973#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {4973#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,198 INFO L273 TraceCheckUtils]: 41: Hoare triple {4973#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {4983#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,210 INFO L273 TraceCheckUtils]: 42: Hoare triple {4983#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4987#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,216 INFO L273 TraceCheckUtils]: 43: Hoare triple {4987#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} assume true; {4987#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,222 INFO L273 TraceCheckUtils]: 44: Hoare triple {4987#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {4987#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,235 INFO L273 TraceCheckUtils]: 45: Hoare triple {4987#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {4997#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,247 INFO L273 TraceCheckUtils]: 46: Hoare triple {4997#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {5001#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,254 INFO L273 TraceCheckUtils]: 47: Hoare triple {5001#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} assume true; {5001#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,262 INFO L273 TraceCheckUtils]: 48: Hoare triple {5001#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {5001#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,275 INFO L273 TraceCheckUtils]: 49: Hoare triple {5001#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {5011#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-18 21:09:51,291 INFO L273 TraceCheckUtils]: 50: Hoare triple {5011#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= (_ bv2 32) main_~i~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {5015#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-18 21:09:51,294 INFO L273 TraceCheckUtils]: 51: Hoare triple {5015#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume true; {5015#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-18 21:09:51,296 INFO L273 TraceCheckUtils]: 52: Hoare triple {5015#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume !!~bvsge32(~j~0, 1bv32); {5015#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-18 21:09:51,306 INFO L273 TraceCheckUtils]: 53: Hoare triple {5015#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967260 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967264 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv3 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967268 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967256 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv4 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0) (_ bv4294967272 32)))) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(5bv32, ~i~0), ~j~0))), 4bv32); {5025#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv36 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,308 INFO L273 TraceCheckUtils]: 54: Hoare triple {5025#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv36 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {5025#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv36 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,310 INFO L273 TraceCheckUtils]: 55: Hoare triple {5025#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv36 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume true; {5025#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv36 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,313 INFO L273 TraceCheckUtils]: 56: Hoare triple {5025#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv36 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsge32(~j~0, 1bv32); {5025#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv36 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,316 INFO L273 TraceCheckUtils]: 57: Hoare triple {5025#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv36 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {5025#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv36 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,318 INFO L273 TraceCheckUtils]: 58: Hoare triple {5025#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv36 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume true; {5025#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv36 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,336 INFO L273 TraceCheckUtils]: 59: Hoare triple {5025#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv36 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 5bv32)); {5025#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv36 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-18 21:09:51,339 INFO L273 TraceCheckUtils]: 60: Hoare triple {5025#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv36 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 0bv32; {5047#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv36 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967292 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,343 INFO L273 TraceCheckUtils]: 61: Hoare triple {5047#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv36 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967292 32)) (_ bv0 32)))} assume true; {5047#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv36 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967292 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:51,346 INFO L273 TraceCheckUtils]: 62: Hoare triple {5047#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv36 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967291 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967292 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {5054#|main_#t~short7|} is VALID [2018-11-18 21:09:51,347 INFO L273 TraceCheckUtils]: 63: Hoare triple {5054#|main_#t~short7|} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {4840#false} is VALID [2018-11-18 21:09:51,347 INFO L256 TraceCheckUtils]: 64: Hoare triple {4840#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {4840#false} is VALID [2018-11-18 21:09:51,348 INFO L273 TraceCheckUtils]: 65: Hoare triple {4840#false} ~cond := #in~cond; {4840#false} is VALID [2018-11-18 21:09:51,348 INFO L273 TraceCheckUtils]: 66: Hoare triple {4840#false} assume 0bv32 == ~cond; {4840#false} is VALID [2018-11-18 21:09:51,348 INFO L273 TraceCheckUtils]: 67: Hoare triple {4840#false} assume !false; {4840#false} is VALID [2018-11-18 21:09:51,402 INFO L134 CoverageAnalysis]: Checked inductivity of 229 backedges. 0 proven. 229 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:09:51,402 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 21:09:58,062 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 115 treesize of output 113 [2018-11-18 21:09:58,077 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 113 treesize of output 117 [2018-11-18 21:09:58,105 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:58,106 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:58,109 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 117 treesize of output 156 [2018-11-18 21:09:58,197 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:58,198 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:58,199 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:58,199 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:58,203 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 135 treesize of output 235 [2018-11-18 21:09:58,327 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:58,328 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:58,328 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:58,329 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:58,330 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:58,331 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:58,334 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 170 treesize of output 354 [2018-11-18 21:09:58,559 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:58,560 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:58,561 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:58,564 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:58,592 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 16 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 222 treesize of output 447 [2018-11-18 21:09:58,891 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:58,898 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:58,905 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:58,905 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:58,960 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:58,975 INFO L303 Elim1Store]: Index analysis took 108 ms [2018-11-18 21:09:59,198 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 17 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 10 case distinctions, treesize of input 225 treesize of output 483 [2018-11-18 21:09:59,326 WARN L307 Elim1Store]: Array PQE input equivalent to true [2018-11-18 21:09:59,327 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 1 xjuncts. [2018-11-18 21:10:06,330 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:06,331 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:06,331 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:08,342 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) |main_~#volArray~0.offset| .cse0) (bvadd |main_~#volArray~0.offset| .cse0))) [2018-11-18 21:10:08,354 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:10,361 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0 (_ bv4 32)) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) |main_~#volArray~0.offset| .cse0))) [2018-11-18 21:10:10,366 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:10,367 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:12,380 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0 (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd |main_~#volArray~0.offset| .cse0))) [2018-11-18 21:10:12,393 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:14,395 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0 (_ bv4 32)) (bvadd |main_~#volArray~0.offset| .cse0 (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))) [2018-11-18 21:10:14,402 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:16,404 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) |main_~#volArray~0.offset| .cse0) (bvadd |main_~#volArray~0.offset| .cse0))) [2018-11-18 21:10:16,412 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:18,423 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0 (_ bv4 32)) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) |main_~#volArray~0.offset| .cse0))) [2018-11-18 21:10:20,436 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) .cse0) (bvadd |main_~#volArray~0.offset| .cse0))) [2018-11-18 21:10:20,441 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:22,450 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0 (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) .cse0))) [2018-11-18 21:10:24,459 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0))) [2018-11-18 21:10:24,463 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:24,468 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:26,478 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (select v_prenex_9 (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) |main_~#volArray~0.offset| .cse0)) (select v_prenex_9 (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) |main_~#volArray~0.offset| .cse0)))) [2018-11-18 21:10:26,489 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:26,494 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:28,509 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (select v_prenex_9 (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) |main_~#volArray~0.offset| .cse0)) (select v_prenex_9 (bvadd |main_~#volArray~0.offset| .cse0 (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))))) [2018-11-18 21:10:28,518 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:28,530 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,545 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (select v_prenex_9 (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) |main_~#volArray~0.offset| .cse0)) (select v_prenex_9 (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) .cse0)))) [2018-11-18 21:10:30,550 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:32,555 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (select v_prenex_9 (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) |main_~#volArray~0.offset| .cse0)) (select v_prenex_9 (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0)))) [2018-11-18 21:10:32,561 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:32,567 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:32,579 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:34,589 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (= (_ bv4 32) (select v_prenex_9 (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) [2018-11-18 21:10:34,594 INFO L303 Elim1Store]: Index analysis took 28289 ms [2018-11-18 21:10:55,108 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 20 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 14 case distinctions, treesize of input 132 treesize of output 529 [2018-11-18 21:10:55,209 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:55,210 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:55,210 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:55,210 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:55,211 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:55,211 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:57,215 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0 (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd |main_~#volArray~0.offset| .cse0 (_ bv8 32)))) [2018-11-18 21:10:57,220 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:57,220 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:57,221 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:57,221 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:57,222 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:57,222 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:57,223 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:57,223 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:57,224 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:57,225 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:57,226 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:57,226 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:59,237 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0 (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) .cse0))) [2018-11-18 21:11:01,249 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) .cse0) (bvadd |main_~#volArray~0.offset| .cse0 (_ bv8 32)))) [2018-11-18 21:11:03,262 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0))) [2018-11-18 21:11:03,270 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:05,276 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0 (_ bv4 32)) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0))) [2018-11-18 21:11:05,291 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:05,292 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:05,293 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:05,293 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:05,301 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:05,312 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:05,313 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:05,319 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:05,331 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,342 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (select v_arrayElimArr_11 (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) |main_~#volArray~0.offset| .cse0)) (select v_arrayElimArr_11 (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0)))) [2018-11-18 21:11:07,348 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,348 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,354 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,361 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,366 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,367 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,368 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,368 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,370 INFO L303 Elim1Store]: Index analysis took 12176 ms [2018-11-18 21:11:07,593 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 40 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 8 case distinctions, treesize of input 491 treesize of output 827 [2018-11-18 21:11:07,823 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,823 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,824 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,824 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,825 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,825 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,826 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,826 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,827 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,827 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,828 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,829 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,830 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,834 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:11:07,835 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,836 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,836 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,837 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:07,838 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:09,851 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (select v_arrayElimArr_12 (bvadd |main_~#volArray~0.offset| .cse0 (_ bv8 32))) (select v_arrayElimArr_12 (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) |main_~#volArray~0.offset| .cse0)))) [2018-11-18 21:11:11,866 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (select v_arrayElimArr_12 (bvadd |main_~#volArray~0.offset| .cse0)) (select v_arrayElimArr_12 (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) |main_~#volArray~0.offset| .cse0)))) [2018-11-18 21:11:13,883 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (select v_arrayElimArr_12 (bvadd |main_~#volArray~0.offset| .cse0 (_ bv4 32))) (select v_arrayElimArr_12 (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) |main_~#volArray~0.offset| .cse0)))) [2018-11-18 21:11:15,900 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (= (_ bv2 32) (select v_arrayElimArr_12 (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) |main_~#volArray~0.offset| (bvmul (_ bv20 32) main_~i~0)))) [2018-11-18 21:11:15,905 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:15,905 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:15,906 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:15,906 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:15,907 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:15,908 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:15,908 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:15,909 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:15,912 INFO L303 Elim1Store]: Index analysis took 8103 ms [2018-11-18 21:11:15,914 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 47 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 812 treesize of output 1148 [2018-11-18 21:11:16,810 WARN L180 SmtUtils]: Spent 748.00 ms on a formula simplification. DAG size of input: 146 DAG size of output: 72 [2018-11-18 21:11:16,908 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,909 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,911 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,912 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,913 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,913 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,916 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,917 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,918 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,918 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,920 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,920 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,923 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,923 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,925 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,925 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,927 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,927 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,929 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,931 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,931 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,934 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,934 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,937 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,937 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,939 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,939 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,941 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,941 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,943 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,944 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,945 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,945 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,948 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,949 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,950 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,950 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,952 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,955 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,956 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,957 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,957 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:16,961 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 7 select indices, 7 select index equivalence classes, 42 disjoint index pairs (out of 21 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 111 treesize of output 451 [2018-11-18 21:11:16,966 INFO L267 ElimStorePlain]: Start of recursive call 13: End of recursive call: and 1 xjuncts. [2018-11-18 21:11:17,068 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,069 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,069 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,085 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,085 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,087 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,087 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,089 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,099 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,100 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,101 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,102 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,112 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,112 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,114 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,127 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,127 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,129 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,143 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,145 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,145 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,147 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,148 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,149 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,156 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,156 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,158 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,158 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,159 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,166 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,166 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,168 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,169 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,177 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,179 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,180 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,186 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,186 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,188 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,201 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,202 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,202 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:17,204 INFO L303 Elim1Store]: Index analysis took 150 ms [2018-11-18 21:11:17,392 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 42 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 7 case distinctions, treesize of input 110 treesize of output 562 [2018-11-18 21:11:17,393 WARN L138 XnfTransformerHelper]: expecting exponential blowup for input size 7 [2018-11-18 21:11:17,980 INFO L267 ElimStorePlain]: Start of recursive call 14: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 20 xjuncts. [2018-11-18 21:11:19,703 INFO L267 ElimStorePlain]: Start of recursive call 12: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 14 xjuncts. [2018-11-18 21:11:31,449 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:31,450 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:31,450 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:33,460 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0 (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd |main_~#volArray~0.offset| .cse0 (_ bv8 32)))) [2018-11-18 21:11:33,466 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:33,467 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:33,467 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:33,468 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:33,468 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:33,469 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:33,469 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:33,470 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:33,470 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:33,470 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:35,475 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) |main_~#volArray~0.offset| .cse0) (bvadd |main_~#volArray~0.offset| .cse0 (_ bv12 32)))) [2018-11-18 21:11:35,478 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:35,478 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:35,479 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:35,479 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:35,480 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:35,480 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:35,481 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:35,481 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:35,482 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:37,489 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0 (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) .cse0))) [2018-11-18 21:11:39,513 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) .cse0) (bvadd |main_~#volArray~0.offset| .cse0 (_ bv12 32)))) [2018-11-18 21:11:39,523 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:41,538 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0 (_ bv8 32)) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0))) [2018-11-18 21:11:41,559 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:41,559 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:43,564 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0))) [2018-11-18 21:11:43,568 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:43,569 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:43,569 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:43,578 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:43,579 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:43,581 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:43,582 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:43,594 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:43,603 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:43,604 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:43,606 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:43,619 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:43,632 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:43,633 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:43,633 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:45,638 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv20 32) main_~i~0))) (= (select v_prenex_36 (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967292 32)))) |main_~#volArray~0.offset| .cse0)) (select v_prenex_36 (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0)))) [2018-11-18 21:11:45,646 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:45,646 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:45,648 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:45,654 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:45,662 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:45,663 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:45,664 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:45,664 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:45,665 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:45,672 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:45,672 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:45,673 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:45,674 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:45,674 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:45,676 INFO L303 Elim1Store]: Index analysis took 14248 ms [2018-11-18 21:11:48,458 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 54 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 9 case distinctions, treesize of input 223 treesize of output 1040