java -ea -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf -i ../../../trunk/examples/svcomp/array-tiling/pr3_true-unreach-call.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-18e5b2d-m [2018-11-18 21:08:54,829 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 21:08:54,832 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 21:08:54,847 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 21:08:54,847 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 21:08:54,848 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 21:08:54,850 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 21:08:54,852 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 21:08:54,853 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 21:08:54,854 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 21:08:54,855 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 21:08:54,856 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 21:08:54,857 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 21:08:54,858 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 21:08:54,859 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 21:08:54,860 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 21:08:54,861 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 21:08:54,862 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 21:08:54,864 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 21:08:54,866 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 21:08:54,867 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 21:08:54,871 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 21:08:54,876 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 21:08:54,877 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 21:08:54,877 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 21:08:54,878 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 21:08:54,881 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 21:08:54,882 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 21:08:54,883 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 21:08:54,887 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 21:08:54,888 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 21:08:54,888 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 21:08:54,891 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 21:08:54,891 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 21:08:54,892 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 21:08:54,893 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 21:08:54,893 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf [2018-11-18 21:08:54,926 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 21:08:54,926 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 21:08:54,927 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-18 21:08:54,927 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-11-18 21:08:54,929 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 21:08:54,930 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 21:08:54,930 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 21:08:54,930 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 21:08:54,930 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 21:08:54,931 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 21:08:54,932 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 21:08:54,932 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-18 21:08:54,932 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-18 21:08:54,932 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-18 21:08:54,932 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-18 21:08:54,933 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-18 21:08:54,933 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 21:08:54,933 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 21:08:54,933 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 21:08:54,933 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-18 21:08:54,934 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 21:08:54,934 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 21:08:54,934 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-18 21:08:54,934 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-18 21:08:54,934 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 21:08:54,935 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 21:08:54,935 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-18 21:08:54,935 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-18 21:08:54,935 INFO L133 SettingsManager]: * Trace refinement strategy=WOLF [2018-11-18 21:08:54,936 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-18 21:08:54,936 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-11-18 21:08:54,936 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-11-18 21:08:54,936 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-18 21:08:54,983 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 21:08:55,004 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 21:08:55,009 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 21:08:55,011 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 21:08:55,011 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 21:08:55,012 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-tiling/pr3_true-unreach-call.i [2018-11-18 21:08:55,084 INFO L221 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/06eaf07f9/d0c364c8604a44a78ffa3632307bbc82/FLAGf72610d15 [2018-11-18 21:08:55,568 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 21:08:55,569 INFO L161 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-tiling/pr3_true-unreach-call.i [2018-11-18 21:08:55,577 INFO L355 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/06eaf07f9/d0c364c8604a44a78ffa3632307bbc82/FLAGf72610d15 [2018-11-18 21:08:55,918 INFO L363 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/06eaf07f9/d0c364c8604a44a78ffa3632307bbc82 [2018-11-18 21:08:55,933 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 21:08:55,936 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-11-18 21:08:55,937 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 21:08:55,937 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 21:08:55,941 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 21:08:55,943 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 09:08:55" (1/1) ... [2018-11-18 21:08:55,946 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1527bbd9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:08:55, skipping insertion in model container [2018-11-18 21:08:55,946 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 09:08:55" (1/1) ... [2018-11-18 21:08:55,954 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 21:08:55,978 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 21:08:56,204 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 21:08:56,213 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 21:08:56,249 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 21:08:56,274 INFO L195 MainTranslator]: Completed translation [2018-11-18 21:08:56,275 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:08:56 WrapperNode [2018-11-18 21:08:56,275 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 21:08:56,276 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 21:08:56,276 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 21:08:56,276 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 21:08:56,291 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:08:56" (1/1) ... [2018-11-18 21:08:56,292 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:08:56" (1/1) ... [2018-11-18 21:08:56,302 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:08:56" (1/1) ... [2018-11-18 21:08:56,303 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:08:56" (1/1) ... [2018-11-18 21:08:56,318 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:08:56" (1/1) ... [2018-11-18 21:08:56,330 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:08:56" (1/1) ... [2018-11-18 21:08:56,332 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:08:56" (1/1) ... [2018-11-18 21:08:56,338 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 21:08:56,338 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 21:08:56,340 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 21:08:56,340 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 21:08:56,341 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:08:56" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 21:08:56,468 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-18 21:08:56,468 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 21:08:56,468 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-11-18 21:08:56,468 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-18 21:08:56,469 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-11-18 21:08:56,469 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assume [2018-11-18 21:08:56,469 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-11-18 21:08:56,469 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-11-18 21:08:56,469 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-18 21:08:56,469 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-18 21:08:56,470 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-18 21:08:56,470 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE4 [2018-11-18 21:08:56,470 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE4 [2018-11-18 21:08:56,470 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-18 21:08:56,470 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 21:08:56,470 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~intINTTYPE4 [2018-11-18 21:08:57,230 INFO L280 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 21:08:57,231 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 09:08:57 BoogieIcfgContainer [2018-11-18 21:08:57,231 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 21:08:57,232 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-18 21:08:57,232 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-18 21:08:57,236 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-18 21:08:57,236 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 18.11 09:08:55" (1/3) ... [2018-11-18 21:08:57,237 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@71fdacc8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 09:08:57, skipping insertion in model container [2018-11-18 21:08:57,237 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:08:56" (2/3) ... [2018-11-18 21:08:57,238 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@71fdacc8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 09:08:57, skipping insertion in model container [2018-11-18 21:08:57,238 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 09:08:57" (3/3) ... [2018-11-18 21:08:57,240 INFO L112 eAbstractionObserver]: Analyzing ICFG pr3_true-unreach-call.i [2018-11-18 21:08:57,250 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-18 21:08:57,258 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-18 21:08:57,272 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-18 21:08:57,308 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 21:08:57,309 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-18 21:08:57,309 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-18 21:08:57,309 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-18 21:08:57,310 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 21:08:57,310 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 21:08:57,310 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-18 21:08:57,310 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 21:08:57,310 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-18 21:08:57,329 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states. [2018-11-18 21:08:57,336 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-18 21:08:57,336 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:08:57,338 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:08:57,340 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:08:57,347 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:08:57,347 INFO L82 PathProgramCache]: Analyzing trace with hash 1823049264, now seen corresponding path program 1 times [2018-11-18 21:08:57,351 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:08:57,352 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:08:57,369 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:08:57,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:08:57,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:08:57,461 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:08:57,684 INFO L256 TraceCheckUtils]: 0: Hoare triple {36#true} call ULTIMATE.init(); {36#true} is VALID [2018-11-18 21:08:57,687 INFO L273 TraceCheckUtils]: 1: Hoare triple {36#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {36#true} is VALID [2018-11-18 21:08:57,688 INFO L273 TraceCheckUtils]: 2: Hoare triple {36#true} assume true; {36#true} is VALID [2018-11-18 21:08:57,688 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {36#true} {36#true} #85#return; {36#true} is VALID [2018-11-18 21:08:57,689 INFO L256 TraceCheckUtils]: 4: Hoare triple {36#true} call #t~ret7 := main(); {36#true} is VALID [2018-11-18 21:08:57,689 INFO L273 TraceCheckUtils]: 5: Hoare triple {36#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {36#true} is VALID [2018-11-18 21:08:57,689 INFO L273 TraceCheckUtils]: 6: Hoare triple {36#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {36#true} is VALID [2018-11-18 21:08:57,689 INFO L273 TraceCheckUtils]: 7: Hoare triple {36#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {36#true} is VALID [2018-11-18 21:08:57,691 INFO L273 TraceCheckUtils]: 8: Hoare triple {36#true} assume !true; {37#false} is VALID [2018-11-18 21:08:57,691 INFO L273 TraceCheckUtils]: 9: Hoare triple {37#false} ~i~0 := 0bv32; {37#false} is VALID [2018-11-18 21:08:57,691 INFO L273 TraceCheckUtils]: 10: Hoare triple {37#false} assume true; {37#false} is VALID [2018-11-18 21:08:57,691 INFO L273 TraceCheckUtils]: 11: Hoare triple {37#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {37#false} is VALID [2018-11-18 21:08:57,692 INFO L273 TraceCheckUtils]: 12: Hoare triple {37#false} assume #t~short6; {37#false} is VALID [2018-11-18 21:08:57,692 INFO L256 TraceCheckUtils]: 13: Hoare triple {37#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {37#false} is VALID [2018-11-18 21:08:57,692 INFO L273 TraceCheckUtils]: 14: Hoare triple {37#false} ~cond := #in~cond; {37#false} is VALID [2018-11-18 21:08:57,692 INFO L273 TraceCheckUtils]: 15: Hoare triple {37#false} assume 0bv32 == ~cond; {37#false} is VALID [2018-11-18 21:08:57,693 INFO L273 TraceCheckUtils]: 16: Hoare triple {37#false} assume !false; {37#false} is VALID [2018-11-18 21:08:57,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:08:57,698 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-18 21:08:57,707 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 21:08:57,707 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 21:08:57,713 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 17 [2018-11-18 21:08:57,720 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:08:57,725 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 2 states. [2018-11-18 21:08:57,846 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 17 edges. 17 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:08:57,847 INFO L459 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-11-18 21:08:57,856 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-11-18 21:08:57,857 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-18 21:08:57,860 INFO L87 Difference]: Start difference. First operand 33 states. Second operand 2 states. [2018-11-18 21:08:58,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:58,078 INFO L93 Difference]: Finished difference Result 52 states and 66 transitions. [2018-11-18 21:08:58,078 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-11-18 21:08:58,079 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 17 [2018-11-18 21:08:58,079 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:08:58,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2018-11-18 21:08:58,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 66 transitions. [2018-11-18 21:08:58,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2018-11-18 21:08:58,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 66 transitions. [2018-11-18 21:08:58,096 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 2 states and 66 transitions. [2018-11-18 21:08:58,424 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 66 edges. 66 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:08:58,440 INFO L225 Difference]: With dead ends: 52 [2018-11-18 21:08:58,440 INFO L226 Difference]: Without dead ends: 27 [2018-11-18 21:08:58,444 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 16 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-18 21:08:58,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states. [2018-11-18 21:08:58,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 27. [2018-11-18 21:08:58,489 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:08:58,489 INFO L82 GeneralOperation]: Start isEquivalent. First operand 27 states. Second operand 27 states. [2018-11-18 21:08:58,490 INFO L74 IsIncluded]: Start isIncluded. First operand 27 states. Second operand 27 states. [2018-11-18 21:08:58,490 INFO L87 Difference]: Start difference. First operand 27 states. Second operand 27 states. [2018-11-18 21:08:58,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:58,495 INFO L93 Difference]: Finished difference Result 27 states and 32 transitions. [2018-11-18 21:08:58,495 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 32 transitions. [2018-11-18 21:08:58,496 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:08:58,496 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:08:58,496 INFO L74 IsIncluded]: Start isIncluded. First operand 27 states. Second operand 27 states. [2018-11-18 21:08:58,497 INFO L87 Difference]: Start difference. First operand 27 states. Second operand 27 states. [2018-11-18 21:08:58,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:58,501 INFO L93 Difference]: Finished difference Result 27 states and 32 transitions. [2018-11-18 21:08:58,501 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 32 transitions. [2018-11-18 21:08:58,502 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:08:58,502 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:08:58,502 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:08:58,503 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:08:58,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27 states. [2018-11-18 21:08:58,506 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 32 transitions. [2018-11-18 21:08:58,508 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 32 transitions. Word has length 17 [2018-11-18 21:08:58,508 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:08:58,508 INFO L480 AbstractCegarLoop]: Abstraction has 27 states and 32 transitions. [2018-11-18 21:08:58,508 INFO L481 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-11-18 21:08:58,509 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 32 transitions. [2018-11-18 21:08:58,509 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-11-18 21:08:58,509 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:08:58,510 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:08:58,510 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:08:58,510 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:08:58,511 INFO L82 PathProgramCache]: Analyzing trace with hash 797203505, now seen corresponding path program 1 times [2018-11-18 21:08:58,511 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:08:58,511 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:08:58,537 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:08:58,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:08:58,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:08:58,578 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:08:58,777 INFO L256 TraceCheckUtils]: 0: Hoare triple {240#true} call ULTIMATE.init(); {240#true} is VALID [2018-11-18 21:08:58,778 INFO L273 TraceCheckUtils]: 1: Hoare triple {240#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {240#true} is VALID [2018-11-18 21:08:58,778 INFO L273 TraceCheckUtils]: 2: Hoare triple {240#true} assume true; {240#true} is VALID [2018-11-18 21:08:58,778 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {240#true} {240#true} #85#return; {240#true} is VALID [2018-11-18 21:08:58,779 INFO L256 TraceCheckUtils]: 4: Hoare triple {240#true} call #t~ret7 := main(); {240#true} is VALID [2018-11-18 21:08:58,779 INFO L273 TraceCheckUtils]: 5: Hoare triple {240#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {240#true} is VALID [2018-11-18 21:08:58,779 INFO L273 TraceCheckUtils]: 6: Hoare triple {240#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {240#true} is VALID [2018-11-18 21:08:58,780 INFO L273 TraceCheckUtils]: 7: Hoare triple {240#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {240#true} is VALID [2018-11-18 21:08:58,780 INFO L273 TraceCheckUtils]: 8: Hoare triple {240#true} assume true; {240#true} is VALID [2018-11-18 21:08:58,780 INFO L273 TraceCheckUtils]: 9: Hoare triple {240#true} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {240#true} is VALID [2018-11-18 21:08:58,781 INFO L273 TraceCheckUtils]: 10: Hoare triple {240#true} ~i~0 := 0bv32; {240#true} is VALID [2018-11-18 21:08:58,781 INFO L273 TraceCheckUtils]: 11: Hoare triple {240#true} assume true; {240#true} is VALID [2018-11-18 21:08:58,781 INFO L273 TraceCheckUtils]: 12: Hoare triple {240#true} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {240#true} is VALID [2018-11-18 21:08:58,794 INFO L273 TraceCheckUtils]: 13: Hoare triple {240#true} assume #t~short6; {284#|main_#t~short6|} is VALID [2018-11-18 21:08:58,808 INFO L256 TraceCheckUtils]: 14: Hoare triple {284#|main_#t~short6|} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {288#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:58,820 INFO L273 TraceCheckUtils]: 15: Hoare triple {288#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {292#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-18 21:08:58,833 INFO L273 TraceCheckUtils]: 16: Hoare triple {292#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 == ~cond; {241#false} is VALID [2018-11-18 21:08:58,834 INFO L273 TraceCheckUtils]: 17: Hoare triple {241#false} assume !false; {241#false} is VALID [2018-11-18 21:08:58,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:08:58,836 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-18 21:08:58,842 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 21:08:58,842 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 21:08:58,844 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 18 [2018-11-18 21:08:58,844 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:08:58,844 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states. [2018-11-18 21:08:59,050 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 18 edges. 18 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:08:59,050 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 21:08:59,051 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 21:08:59,051 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 21:08:59,051 INFO L87 Difference]: Start difference. First operand 27 states and 32 transitions. Second operand 5 states. [2018-11-18 21:08:59,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:08:59,873 INFO L93 Difference]: Finished difference Result 35 states and 40 transitions. [2018-11-18 21:08:59,873 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 21:08:59,874 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 18 [2018-11-18 21:08:59,874 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:08:59,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-18 21:08:59,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 40 transitions. [2018-11-18 21:08:59,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-18 21:08:59,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 40 transitions. [2018-11-18 21:08:59,880 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states and 40 transitions. [2018-11-18 21:08:59,990 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 40 edges. 40 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:08:59,993 INFO L225 Difference]: With dead ends: 35 [2018-11-18 21:08:59,993 INFO L226 Difference]: Without dead ends: 33 [2018-11-18 21:08:59,994 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 14 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 21:08:59,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33 states. [2018-11-18 21:09:00,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33 to 32. [2018-11-18 21:09:00,015 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:09:00,015 INFO L82 GeneralOperation]: Start isEquivalent. First operand 33 states. Second operand 32 states. [2018-11-18 21:09:00,016 INFO L74 IsIncluded]: Start isIncluded. First operand 33 states. Second operand 32 states. [2018-11-18 21:09:00,016 INFO L87 Difference]: Start difference. First operand 33 states. Second operand 32 states. [2018-11-18 21:09:00,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:00,019 INFO L93 Difference]: Finished difference Result 33 states and 38 transitions. [2018-11-18 21:09:00,019 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 38 transitions. [2018-11-18 21:09:00,020 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:09:00,020 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:09:00,020 INFO L74 IsIncluded]: Start isIncluded. First operand 32 states. Second operand 33 states. [2018-11-18 21:09:00,021 INFO L87 Difference]: Start difference. First operand 32 states. Second operand 33 states. [2018-11-18 21:09:00,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:00,024 INFO L93 Difference]: Finished difference Result 33 states and 38 transitions. [2018-11-18 21:09:00,024 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 38 transitions. [2018-11-18 21:09:00,025 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:09:00,025 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:09:00,025 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:09:00,025 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:09:00,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32 states. [2018-11-18 21:09:00,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 37 transitions. [2018-11-18 21:09:00,028 INFO L78 Accepts]: Start accepts. Automaton has 32 states and 37 transitions. Word has length 18 [2018-11-18 21:09:00,029 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:09:00,029 INFO L480 AbstractCegarLoop]: Abstraction has 32 states and 37 transitions. [2018-11-18 21:09:00,029 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 21:09:00,029 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 37 transitions. [2018-11-18 21:09:00,030 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-11-18 21:09:00,030 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:09:00,030 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:09:00,031 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:09:00,031 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:09:00,031 INFO L82 PathProgramCache]: Analyzing trace with hash 799050547, now seen corresponding path program 1 times [2018-11-18 21:09:00,032 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:09:00,032 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:09:00,052 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:09:00,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:09:00,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:09:00,279 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:09:00,516 WARN L180 SmtUtils]: Spent 138.00 ms on a formula simplification that was a NOOP. DAG size: 12 [2018-11-18 21:09:00,572 INFO L256 TraceCheckUtils]: 0: Hoare triple {453#true} call ULTIMATE.init(); {453#true} is VALID [2018-11-18 21:09:00,572 INFO L273 TraceCheckUtils]: 1: Hoare triple {453#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {453#true} is VALID [2018-11-18 21:09:00,573 INFO L273 TraceCheckUtils]: 2: Hoare triple {453#true} assume true; {453#true} is VALID [2018-11-18 21:09:00,573 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {453#true} {453#true} #85#return; {453#true} is VALID [2018-11-18 21:09:00,574 INFO L256 TraceCheckUtils]: 4: Hoare triple {453#true} call #t~ret7 := main(); {453#true} is VALID [2018-11-18 21:09:00,574 INFO L273 TraceCheckUtils]: 5: Hoare triple {453#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {453#true} is VALID [2018-11-18 21:09:00,575 INFO L273 TraceCheckUtils]: 6: Hoare triple {453#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {476#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} is VALID [2018-11-18 21:09:00,576 INFO L273 TraceCheckUtils]: 7: Hoare triple {476#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {480#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv3 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:00,577 INFO L273 TraceCheckUtils]: 8: Hoare triple {480#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv3 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {480#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv3 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:00,596 INFO L273 TraceCheckUtils]: 9: Hoare triple {480#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv3 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {454#false} is VALID [2018-11-18 21:09:00,597 INFO L273 TraceCheckUtils]: 10: Hoare triple {454#false} ~i~0 := 0bv32; {454#false} is VALID [2018-11-18 21:09:00,597 INFO L273 TraceCheckUtils]: 11: Hoare triple {454#false} assume true; {454#false} is VALID [2018-11-18 21:09:00,598 INFO L273 TraceCheckUtils]: 12: Hoare triple {454#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {454#false} is VALID [2018-11-18 21:09:00,598 INFO L273 TraceCheckUtils]: 13: Hoare triple {454#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := 0bv32 == #t~mem5; {454#false} is VALID [2018-11-18 21:09:00,598 INFO L256 TraceCheckUtils]: 14: Hoare triple {454#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {454#false} is VALID [2018-11-18 21:09:00,599 INFO L273 TraceCheckUtils]: 15: Hoare triple {454#false} ~cond := #in~cond; {454#false} is VALID [2018-11-18 21:09:00,599 INFO L273 TraceCheckUtils]: 16: Hoare triple {454#false} assume 0bv32 == ~cond; {454#false} is VALID [2018-11-18 21:09:00,599 INFO L273 TraceCheckUtils]: 17: Hoare triple {454#false} assume !false; {454#false} is VALID [2018-11-18 21:09:00,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:09:00,601 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-18 21:09:00,604 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 21:09:00,604 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 21:09:00,605 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 18 [2018-11-18 21:09:00,605 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:09:00,605 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states. [2018-11-18 21:09:00,679 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 18 edges. 18 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:09:00,679 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 21:09:00,680 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 21:09:00,680 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-18 21:09:00,680 INFO L87 Difference]: Start difference. First operand 32 states and 37 transitions. Second operand 4 states. [2018-11-18 21:09:02,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:02,280 INFO L93 Difference]: Finished difference Result 56 states and 66 transitions. [2018-11-18 21:09:02,280 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 21:09:02,280 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 18 [2018-11-18 21:09:02,281 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:09:02,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-18 21:09:02,284 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 56 transitions. [2018-11-18 21:09:02,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-18 21:09:02,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 56 transitions. [2018-11-18 21:09:02,287 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states and 56 transitions. [2018-11-18 21:09:02,564 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 56 edges. 56 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:09:02,567 INFO L225 Difference]: With dead ends: 56 [2018-11-18 21:09:02,568 INFO L226 Difference]: Without dead ends: 38 [2018-11-18 21:09:02,568 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 15 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-18 21:09:02,569 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states. [2018-11-18 21:09:02,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 34. [2018-11-18 21:09:02,603 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:09:02,603 INFO L82 GeneralOperation]: Start isEquivalent. First operand 38 states. Second operand 34 states. [2018-11-18 21:09:02,604 INFO L74 IsIncluded]: Start isIncluded. First operand 38 states. Second operand 34 states. [2018-11-18 21:09:02,604 INFO L87 Difference]: Start difference. First operand 38 states. Second operand 34 states. [2018-11-18 21:09:02,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:02,607 INFO L93 Difference]: Finished difference Result 38 states and 46 transitions. [2018-11-18 21:09:02,608 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 46 transitions. [2018-11-18 21:09:02,608 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:09:02,608 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:09:02,609 INFO L74 IsIncluded]: Start isIncluded. First operand 34 states. Second operand 38 states. [2018-11-18 21:09:02,609 INFO L87 Difference]: Start difference. First operand 34 states. Second operand 38 states. [2018-11-18 21:09:02,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:02,612 INFO L93 Difference]: Finished difference Result 38 states and 46 transitions. [2018-11-18 21:09:02,612 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 46 transitions. [2018-11-18 21:09:02,613 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:09:02,613 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:09:02,613 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:09:02,614 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:09:02,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34 states. [2018-11-18 21:09:02,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 39 transitions. [2018-11-18 21:09:02,616 INFO L78 Accepts]: Start accepts. Automaton has 34 states and 39 transitions. Word has length 18 [2018-11-18 21:09:02,616 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:09:02,617 INFO L480 AbstractCegarLoop]: Abstraction has 34 states and 39 transitions. [2018-11-18 21:09:02,617 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 21:09:02,617 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 39 transitions. [2018-11-18 21:09:02,618 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-11-18 21:09:02,618 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:09:02,618 INFO L375 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:09:02,618 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:09:02,619 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:09:02,619 INFO L82 PathProgramCache]: Analyzing trace with hash -493897724, now seen corresponding path program 1 times [2018-11-18 21:09:02,619 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:09:02,619 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:09:02,638 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:09:02,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:09:02,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:09:02,770 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:09:03,059 INFO L256 TraceCheckUtils]: 0: Hoare triple {703#true} call ULTIMATE.init(); {703#true} is VALID [2018-11-18 21:09:03,060 INFO L273 TraceCheckUtils]: 1: Hoare triple {703#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {703#true} is VALID [2018-11-18 21:09:03,060 INFO L273 TraceCheckUtils]: 2: Hoare triple {703#true} assume true; {703#true} is VALID [2018-11-18 21:09:03,060 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {703#true} {703#true} #85#return; {703#true} is VALID [2018-11-18 21:09:03,060 INFO L256 TraceCheckUtils]: 4: Hoare triple {703#true} call #t~ret7 := main(); {703#true} is VALID [2018-11-18 21:09:03,061 INFO L273 TraceCheckUtils]: 5: Hoare triple {703#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {703#true} is VALID [2018-11-18 21:09:03,062 INFO L273 TraceCheckUtils]: 6: Hoare triple {703#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {726#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0))} is VALID [2018-11-18 21:09:03,062 INFO L273 TraceCheckUtils]: 7: Hoare triple {726#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {726#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0))} is VALID [2018-11-18 21:09:03,063 INFO L273 TraceCheckUtils]: 8: Hoare triple {726#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0))} assume true; {726#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0))} is VALID [2018-11-18 21:09:03,066 INFO L273 TraceCheckUtils]: 9: Hoare triple {726#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {726#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0))} is VALID [2018-11-18 21:09:03,067 INFO L273 TraceCheckUtils]: 10: Hoare triple {726#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 3bv32))), 4bv32); {739#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0))} is VALID [2018-11-18 21:09:03,068 INFO L273 TraceCheckUtils]: 11: Hoare triple {739#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (_ bv1 32) main_~CCCELVOL1~0))} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 2bv32))), 4bv32); {743#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv1 32) main_~CCCELVOL1~0) (not (bvsge (_ bv3 32) main_~MINVAL~0)))} is VALID [2018-11-18 21:09:03,072 INFO L273 TraceCheckUtils]: 12: Hoare triple {743#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv1 32) main_~CCCELVOL1~0) (not (bvsge (_ bv3 32) main_~MINVAL~0)))} assume ~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL1~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 1bv32))), 4bv32); {704#false} is VALID [2018-11-18 21:09:03,073 INFO L273 TraceCheckUtils]: 13: Hoare triple {704#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {704#false} is VALID [2018-11-18 21:09:03,073 INFO L273 TraceCheckUtils]: 14: Hoare triple {704#false} assume true; {704#false} is VALID [2018-11-18 21:09:03,073 INFO L273 TraceCheckUtils]: 15: Hoare triple {704#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {704#false} is VALID [2018-11-18 21:09:03,073 INFO L273 TraceCheckUtils]: 16: Hoare triple {704#false} ~i~0 := 0bv32; {704#false} is VALID [2018-11-18 21:09:03,073 INFO L273 TraceCheckUtils]: 17: Hoare triple {704#false} assume true; {704#false} is VALID [2018-11-18 21:09:03,074 INFO L273 TraceCheckUtils]: 18: Hoare triple {704#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {704#false} is VALID [2018-11-18 21:09:03,074 INFO L273 TraceCheckUtils]: 19: Hoare triple {704#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := 0bv32 == #t~mem5; {704#false} is VALID [2018-11-18 21:09:03,074 INFO L256 TraceCheckUtils]: 20: Hoare triple {704#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {704#false} is VALID [2018-11-18 21:09:03,074 INFO L273 TraceCheckUtils]: 21: Hoare triple {704#false} ~cond := #in~cond; {704#false} is VALID [2018-11-18 21:09:03,075 INFO L273 TraceCheckUtils]: 22: Hoare triple {704#false} assume 0bv32 == ~cond; {704#false} is VALID [2018-11-18 21:09:03,075 INFO L273 TraceCheckUtils]: 23: Hoare triple {704#false} assume !false; {704#false} is VALID [2018-11-18 21:09:03,077 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:09:03,077 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-18 21:09:03,078 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 21:09:03,079 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 21:09:03,080 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 24 [2018-11-18 21:09:03,080 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:09:03,080 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states. [2018-11-18 21:09:03,158 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 24 edges. 24 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:09:03,159 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 21:09:03,159 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 21:09:03,159 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 21:09:03,160 INFO L87 Difference]: Start difference. First operand 34 states and 39 transitions. Second operand 5 states. [2018-11-18 21:09:04,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:04,106 INFO L93 Difference]: Finished difference Result 86 states and 110 transitions. [2018-11-18 21:09:04,106 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 21:09:04,107 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 24 [2018-11-18 21:09:04,107 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:09:04,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-18 21:09:04,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 94 transitions. [2018-11-18 21:09:04,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-18 21:09:04,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 94 transitions. [2018-11-18 21:09:04,116 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states and 94 transitions. [2018-11-18 21:09:04,469 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 94 edges. 94 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:09:04,474 INFO L225 Difference]: With dead ends: 86 [2018-11-18 21:09:04,474 INFO L226 Difference]: Without dead ends: 62 [2018-11-18 21:09:04,475 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 20 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-11-18 21:09:04,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2018-11-18 21:09:04,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 46. [2018-11-18 21:09:04,634 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:09:04,634 INFO L82 GeneralOperation]: Start isEquivalent. First operand 62 states. Second operand 46 states. [2018-11-18 21:09:04,634 INFO L74 IsIncluded]: Start isIncluded. First operand 62 states. Second operand 46 states. [2018-11-18 21:09:04,634 INFO L87 Difference]: Start difference. First operand 62 states. Second operand 46 states. [2018-11-18 21:09:04,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:04,643 INFO L93 Difference]: Finished difference Result 62 states and 77 transitions. [2018-11-18 21:09:04,643 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 77 transitions. [2018-11-18 21:09:04,645 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:09:04,646 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:09:04,646 INFO L74 IsIncluded]: Start isIncluded. First operand 46 states. Second operand 62 states. [2018-11-18 21:09:04,646 INFO L87 Difference]: Start difference. First operand 46 states. Second operand 62 states. [2018-11-18 21:09:04,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:04,652 INFO L93 Difference]: Finished difference Result 62 states and 77 transitions. [2018-11-18 21:09:04,652 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 77 transitions. [2018-11-18 21:09:04,653 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:09:04,653 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:09:04,654 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:09:04,654 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:09:04,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-11-18 21:09:04,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 55 transitions. [2018-11-18 21:09:04,657 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 55 transitions. Word has length 24 [2018-11-18 21:09:04,657 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:09:04,657 INFO L480 AbstractCegarLoop]: Abstraction has 46 states and 55 transitions. [2018-11-18 21:09:04,657 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 21:09:04,658 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 55 transitions. [2018-11-18 21:09:04,659 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-11-18 21:09:04,659 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:09:04,659 INFO L375 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:09:04,659 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:09:04,660 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:09:04,660 INFO L82 PathProgramCache]: Analyzing trace with hash -235732286, now seen corresponding path program 1 times [2018-11-18 21:09:04,660 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:09:04,660 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:09:04,689 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:09:04,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:09:04,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:09:04,903 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:09:05,079 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-18 21:09:05,122 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-18 21:09:05,148 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:09:05,186 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:05,271 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:05,271 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:31, output treesize:27 [2018-11-18 21:09:05,369 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 26 [2018-11-18 21:09:05,379 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:05,381 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:05,383 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 54 [2018-11-18 21:09:05,389 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:09:05,404 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:05,576 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:05,576 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:46, output treesize:42 [2018-11-18 21:09:05,666 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 23 [2018-11-18 21:09:05,678 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:05,680 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:05,683 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:05,686 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:05,687 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 4 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 60 [2018-11-18 21:09:05,691 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:09:05,711 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:05,732 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:05,733 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:40, output treesize:36 [2018-11-18 21:09:05,950 INFO L256 TraceCheckUtils]: 0: Hoare triple {1077#true} call ULTIMATE.init(); {1077#true} is VALID [2018-11-18 21:09:05,950 INFO L273 TraceCheckUtils]: 1: Hoare triple {1077#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1077#true} is VALID [2018-11-18 21:09:05,950 INFO L273 TraceCheckUtils]: 2: Hoare triple {1077#true} assume true; {1077#true} is VALID [2018-11-18 21:09:05,951 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1077#true} {1077#true} #85#return; {1077#true} is VALID [2018-11-18 21:09:05,951 INFO L256 TraceCheckUtils]: 4: Hoare triple {1077#true} call #t~ret7 := main(); {1077#true} is VALID [2018-11-18 21:09:05,951 INFO L273 TraceCheckUtils]: 5: Hoare triple {1077#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1077#true} is VALID [2018-11-18 21:09:05,953 INFO L273 TraceCheckUtils]: 6: Hoare triple {1077#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {1100#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-18 21:09:05,957 INFO L273 TraceCheckUtils]: 7: Hoare triple {1100#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1104#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:05,957 INFO L273 TraceCheckUtils]: 8: Hoare triple {1104#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {1104#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:05,958 INFO L273 TraceCheckUtils]: 9: Hoare triple {1104#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {1104#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:05,959 INFO L273 TraceCheckUtils]: 10: Hoare triple {1104#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 3bv32))), 4bv32); {1114#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) (_ bv4294967289 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:05,965 INFO L273 TraceCheckUtils]: 11: Hoare triple {1114#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) (_ bv4294967289 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 2bv32))), 4bv32); {1118#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:05,970 INFO L273 TraceCheckUtils]: 12: Hoare triple {1118#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 1bv32))), 4bv32); {1122#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:09:05,972 INFO L273 TraceCheckUtils]: 13: Hoare triple {1122#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1122#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:09:05,973 INFO L273 TraceCheckUtils]: 14: Hoare triple {1122#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume true; {1122#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:09:05,990 INFO L273 TraceCheckUtils]: 15: Hoare triple {1122#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {1122#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:09:05,992 INFO L273 TraceCheckUtils]: 16: Hoare triple {1122#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} ~i~0 := 0bv32; {1135#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:09:05,993 INFO L273 TraceCheckUtils]: 17: Hoare triple {1135#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume true; {1135#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:09:05,995 INFO L273 TraceCheckUtils]: 18: Hoare triple {1135#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {1142#|main_#t~short6|} is VALID [2018-11-18 21:09:05,996 INFO L273 TraceCheckUtils]: 19: Hoare triple {1142#|main_#t~short6|} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := 0bv32 == #t~mem5; {1078#false} is VALID [2018-11-18 21:09:05,997 INFO L256 TraceCheckUtils]: 20: Hoare triple {1078#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {1078#false} is VALID [2018-11-18 21:09:05,997 INFO L273 TraceCheckUtils]: 21: Hoare triple {1078#false} ~cond := #in~cond; {1078#false} is VALID [2018-11-18 21:09:05,997 INFO L273 TraceCheckUtils]: 22: Hoare triple {1078#false} assume 0bv32 == ~cond; {1078#false} is VALID [2018-11-18 21:09:05,997 INFO L273 TraceCheckUtils]: 23: Hoare triple {1078#false} assume !false; {1078#false} is VALID [2018-11-18 21:09:06,002 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:09:06,003 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 21:09:06,332 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 29 [2018-11-18 21:09:06,343 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 33 [2018-11-18 21:09:06,355 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:06,361 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 49 [2018-11-18 21:09:06,495 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:06,496 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:06,498 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 25 [2018-11-18 21:09:06,501 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-18 21:09:06,516 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:08,562 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (= |main_~#volArray~0.offset| (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) [2018-11-18 21:09:08,587 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:08,588 INFO L303 Elim1Store]: Index analysis took 2080 ms [2018-11-18 21:09:08,598 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 2 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 41 [2018-11-18 21:09:08,606 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 21:09:08,684 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 4 xjuncts. [2018-11-18 21:09:08,759 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 21:09:08,798 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 21:09:08,858 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 3 dim-0 vars, and 2 xjuncts. [2018-11-18 21:09:08,859 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 3 variables, input treesize:39, output treesize:54 [2018-11-18 21:09:08,869 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-18 21:09:09,219 INFO L273 TraceCheckUtils]: 23: Hoare triple {1078#false} assume !false; {1078#false} is VALID [2018-11-18 21:09:09,219 INFO L273 TraceCheckUtils]: 22: Hoare triple {1078#false} assume 0bv32 == ~cond; {1078#false} is VALID [2018-11-18 21:09:09,219 INFO L273 TraceCheckUtils]: 21: Hoare triple {1078#false} ~cond := #in~cond; {1078#false} is VALID [2018-11-18 21:09:09,220 INFO L256 TraceCheckUtils]: 20: Hoare triple {1078#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {1078#false} is VALID [2018-11-18 21:09:09,221 INFO L273 TraceCheckUtils]: 19: Hoare triple {1142#|main_#t~short6|} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := 0bv32 == #t~mem5; {1078#false} is VALID [2018-11-18 21:09:09,227 INFO L273 TraceCheckUtils]: 18: Hoare triple {1173#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {1142#|main_#t~short6|} is VALID [2018-11-18 21:09:09,229 INFO L273 TraceCheckUtils]: 17: Hoare triple {1173#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume true; {1173#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is VALID [2018-11-18 21:09:09,230 INFO L273 TraceCheckUtils]: 16: Hoare triple {1180#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} ~i~0 := 0bv32; {1173#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is VALID [2018-11-18 21:09:09,231 INFO L273 TraceCheckUtils]: 15: Hoare triple {1180#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {1180#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:09:09,231 INFO L273 TraceCheckUtils]: 14: Hoare triple {1180#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume true; {1180#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:09:09,233 INFO L273 TraceCheckUtils]: 13: Hoare triple {1180#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1180#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:09:09,262 INFO L273 TraceCheckUtils]: 12: Hoare triple {1193#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 1bv32))), 4bv32); {1180#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:09:09,300 INFO L273 TraceCheckUtils]: 11: Hoare triple {1197#(or (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 2bv32))), 4bv32); {1193#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:09:09,392 INFO L273 TraceCheckUtils]: 10: Hoare triple {1201#(and (or (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL3~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (bvsge (_ bv0 32) main_~MINVAL~0)))) (or (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((v_prenex_2 (_ BitVec 32)) (v_prenex_1 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL3~0 v_prenex_2)) (bvsge v_prenex_1 v_prenex_2) (bvsge main_~CCCELVOL2~0 v_prenex_2))) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv8 32) (bvmul (_ bv12 32) main_~i~0))))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 3bv32))), 4bv32); {1197#(or (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} is VALID [2018-11-18 21:09:09,393 INFO L273 TraceCheckUtils]: 9: Hoare triple {1201#(and (or (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL3~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (bvsge (_ bv0 32) main_~MINVAL~0)))) (or (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((v_prenex_2 (_ BitVec 32)) (v_prenex_1 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL3~0 v_prenex_2)) (bvsge v_prenex_1 v_prenex_2) (bvsge main_~CCCELVOL2~0 v_prenex_2))) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv8 32) (bvmul (_ bv12 32) main_~i~0))))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {1201#(and (or (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL3~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (bvsge (_ bv0 32) main_~MINVAL~0)))) (or (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((v_prenex_2 (_ BitVec 32)) (v_prenex_1 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL3~0 v_prenex_2)) (bvsge v_prenex_1 v_prenex_2) (bvsge main_~CCCELVOL2~0 v_prenex_2))) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv8 32) (bvmul (_ bv12 32) main_~i~0))))} is VALID [2018-11-18 21:09:09,394 INFO L273 TraceCheckUtils]: 8: Hoare triple {1201#(and (or (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL3~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (bvsge (_ bv0 32) main_~MINVAL~0)))) (or (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((v_prenex_2 (_ BitVec 32)) (v_prenex_1 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL3~0 v_prenex_2)) (bvsge v_prenex_1 v_prenex_2) (bvsge main_~CCCELVOL2~0 v_prenex_2))) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv8 32) (bvmul (_ bv12 32) main_~i~0))))} assume true; {1201#(and (or (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL3~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (bvsge (_ bv0 32) main_~MINVAL~0)))) (or (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((v_prenex_2 (_ BitVec 32)) (v_prenex_1 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL3~0 v_prenex_2)) (bvsge v_prenex_1 v_prenex_2) (bvsge main_~CCCELVOL2~0 v_prenex_2))) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv8 32) (bvmul (_ bv12 32) main_~i~0))))} is VALID [2018-11-18 21:09:09,395 INFO L273 TraceCheckUtils]: 7: Hoare triple {1077#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1201#(and (or (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL3~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (bvsge (_ bv0 32) main_~MINVAL~0)))) (or (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((v_prenex_2 (_ BitVec 32)) (v_prenex_1 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL3~0 v_prenex_2)) (bvsge v_prenex_1 v_prenex_2) (bvsge main_~CCCELVOL2~0 v_prenex_2))) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv8 32) (bvmul (_ bv12 32) main_~i~0))))} is VALID [2018-11-18 21:09:09,396 INFO L273 TraceCheckUtils]: 6: Hoare triple {1077#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {1077#true} is VALID [2018-11-18 21:09:09,396 INFO L273 TraceCheckUtils]: 5: Hoare triple {1077#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1077#true} is VALID [2018-11-18 21:09:09,396 INFO L256 TraceCheckUtils]: 4: Hoare triple {1077#true} call #t~ret7 := main(); {1077#true} is VALID [2018-11-18 21:09:09,397 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1077#true} {1077#true} #85#return; {1077#true} is VALID [2018-11-18 21:09:09,397 INFO L273 TraceCheckUtils]: 2: Hoare triple {1077#true} assume true; {1077#true} is VALID [2018-11-18 21:09:09,398 INFO L273 TraceCheckUtils]: 1: Hoare triple {1077#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1077#true} is VALID [2018-11-18 21:09:09,398 INFO L256 TraceCheckUtils]: 0: Hoare triple {1077#true} call ULTIMATE.init(); {1077#true} is VALID [2018-11-18 21:09:09,400 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:09:09,410 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 21:09:09,410 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8] total 14 [2018-11-18 21:09:09,411 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 24 [2018-11-18 21:09:09,411 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:09:09,411 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 14 states. [2018-11-18 21:09:09,766 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 37 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:09:09,766 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-18 21:09:09,767 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-18 21:09:09,767 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=141, Unknown=0, NotChecked=0, Total=182 [2018-11-18 21:09:09,767 INFO L87 Difference]: Start difference. First operand 46 states and 55 transitions. Second operand 14 states. [2018-11-18 21:09:11,794 WARN L180 SmtUtils]: Spent 112.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 37 [2018-11-18 21:09:14,037 WARN L180 SmtUtils]: Spent 134.00 ms on a formula simplification that was a NOOP. DAG size: 37 [2018-11-18 21:09:18,449 WARN L180 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 38 [2018-11-18 21:09:19,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:19,085 INFO L93 Difference]: Finished difference Result 158 states and 203 transitions. [2018-11-18 21:09:19,085 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-18 21:09:19,086 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 24 [2018-11-18 21:09:19,086 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:09:19,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2018-11-18 21:09:19,094 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 170 transitions. [2018-11-18 21:09:19,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2018-11-18 21:09:19,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 170 transitions. [2018-11-18 21:09:19,101 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 25 states and 170 transitions. [2018-11-18 21:09:22,624 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 170 edges. 169 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2018-11-18 21:09:22,633 INFO L225 Difference]: With dead ends: 158 [2018-11-18 21:09:22,633 INFO L226 Difference]: Without dead ends: 141 [2018-11-18 21:09:22,634 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 35 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 239 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=294, Invalid=896, Unknown=0, NotChecked=0, Total=1190 [2018-11-18 21:09:22,635 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2018-11-18 21:09:22,732 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 82. [2018-11-18 21:09:22,732 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:09:22,733 INFO L82 GeneralOperation]: Start isEquivalent. First operand 141 states. Second operand 82 states. [2018-11-18 21:09:22,733 INFO L74 IsIncluded]: Start isIncluded. First operand 141 states. Second operand 82 states. [2018-11-18 21:09:22,733 INFO L87 Difference]: Start difference. First operand 141 states. Second operand 82 states. [2018-11-18 21:09:22,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:22,742 INFO L93 Difference]: Finished difference Result 141 states and 183 transitions. [2018-11-18 21:09:22,742 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 183 transitions. [2018-11-18 21:09:22,743 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:09:22,743 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:09:22,743 INFO L74 IsIncluded]: Start isIncluded. First operand 82 states. Second operand 141 states. [2018-11-18 21:09:22,744 INFO L87 Difference]: Start difference. First operand 82 states. Second operand 141 states. [2018-11-18 21:09:22,752 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:22,752 INFO L93 Difference]: Finished difference Result 141 states and 183 transitions. [2018-11-18 21:09:22,752 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 183 transitions. [2018-11-18 21:09:22,753 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:09:22,753 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:09:22,754 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:09:22,754 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:09:22,754 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-11-18 21:09:22,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 106 transitions. [2018-11-18 21:09:22,758 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 106 transitions. Word has length 24 [2018-11-18 21:09:22,758 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:09:22,758 INFO L480 AbstractCegarLoop]: Abstraction has 82 states and 106 transitions. [2018-11-18 21:09:22,758 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-18 21:09:22,758 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 106 transitions. [2018-11-18 21:09:22,759 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-11-18 21:09:22,759 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:09:22,759 INFO L375 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:09:22,760 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:09:22,760 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:09:22,760 INFO L82 PathProgramCache]: Analyzing trace with hash -1505014974, now seen corresponding path program 1 times [2018-11-18 21:09:22,761 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:09:22,761 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:09:22,785 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:09:22,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:09:22,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:09:22,901 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:09:23,023 INFO L256 TraceCheckUtils]: 0: Hoare triple {1859#true} call ULTIMATE.init(); {1859#true} is VALID [2018-11-18 21:09:23,024 INFO L273 TraceCheckUtils]: 1: Hoare triple {1859#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1859#true} is VALID [2018-11-18 21:09:23,024 INFO L273 TraceCheckUtils]: 2: Hoare triple {1859#true} assume true; {1859#true} is VALID [2018-11-18 21:09:23,024 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1859#true} {1859#true} #85#return; {1859#true} is VALID [2018-11-18 21:09:23,025 INFO L256 TraceCheckUtils]: 4: Hoare triple {1859#true} call #t~ret7 := main(); {1859#true} is VALID [2018-11-18 21:09:23,025 INFO L273 TraceCheckUtils]: 5: Hoare triple {1859#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1859#true} is VALID [2018-11-18 21:09:23,029 INFO L273 TraceCheckUtils]: 6: Hoare triple {1859#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {1882#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv1 32) main_~CCCELVOL1~0))} is VALID [2018-11-18 21:09:23,029 INFO L273 TraceCheckUtils]: 7: Hoare triple {1882#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv1 32) main_~CCCELVOL1~0))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1882#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv1 32) main_~CCCELVOL1~0))} is VALID [2018-11-18 21:09:23,031 INFO L273 TraceCheckUtils]: 8: Hoare triple {1882#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv1 32) main_~CCCELVOL1~0))} assume true; {1882#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv1 32) main_~CCCELVOL1~0))} is VALID [2018-11-18 21:09:23,031 INFO L273 TraceCheckUtils]: 9: Hoare triple {1882#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv1 32) main_~CCCELVOL1~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {1882#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv1 32) main_~CCCELVOL1~0))} is VALID [2018-11-18 21:09:23,033 INFO L273 TraceCheckUtils]: 10: Hoare triple {1882#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv1 32) main_~CCCELVOL1~0))} assume !~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 3bv32))), 4bv32); {1895#(and (= (_ bv1 32) main_~CCCELVOL1~0) (not (bvsge (_ bv7 32) main_~MINVAL~0)))} is VALID [2018-11-18 21:09:23,034 INFO L273 TraceCheckUtils]: 11: Hoare triple {1895#(and (= (_ bv1 32) main_~CCCELVOL1~0) (not (bvsge (_ bv7 32) main_~MINVAL~0)))} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 2bv32))), 4bv32); {1895#(and (= (_ bv1 32) main_~CCCELVOL1~0) (not (bvsge (_ bv7 32) main_~MINVAL~0)))} is VALID [2018-11-18 21:09:23,036 INFO L273 TraceCheckUtils]: 12: Hoare triple {1895#(and (= (_ bv1 32) main_~CCCELVOL1~0) (not (bvsge (_ bv7 32) main_~MINVAL~0)))} assume ~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL1~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 1bv32))), 4bv32); {1860#false} is VALID [2018-11-18 21:09:23,036 INFO L273 TraceCheckUtils]: 13: Hoare triple {1860#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1860#false} is VALID [2018-11-18 21:09:23,037 INFO L273 TraceCheckUtils]: 14: Hoare triple {1860#false} assume true; {1860#false} is VALID [2018-11-18 21:09:23,037 INFO L273 TraceCheckUtils]: 15: Hoare triple {1860#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {1860#false} is VALID [2018-11-18 21:09:23,037 INFO L273 TraceCheckUtils]: 16: Hoare triple {1860#false} ~i~0 := 0bv32; {1860#false} is VALID [2018-11-18 21:09:23,037 INFO L273 TraceCheckUtils]: 17: Hoare triple {1860#false} assume true; {1860#false} is VALID [2018-11-18 21:09:23,037 INFO L273 TraceCheckUtils]: 18: Hoare triple {1860#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {1860#false} is VALID [2018-11-18 21:09:23,037 INFO L273 TraceCheckUtils]: 19: Hoare triple {1860#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := 0bv32 == #t~mem5; {1860#false} is VALID [2018-11-18 21:09:23,038 INFO L256 TraceCheckUtils]: 20: Hoare triple {1860#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {1860#false} is VALID [2018-11-18 21:09:23,038 INFO L273 TraceCheckUtils]: 21: Hoare triple {1860#false} ~cond := #in~cond; {1860#false} is VALID [2018-11-18 21:09:23,038 INFO L273 TraceCheckUtils]: 22: Hoare triple {1860#false} assume 0bv32 == ~cond; {1860#false} is VALID [2018-11-18 21:09:23,038 INFO L273 TraceCheckUtils]: 23: Hoare triple {1860#false} assume !false; {1860#false} is VALID [2018-11-18 21:09:23,039 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:09:23,039 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-18 21:09:23,041 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 21:09:23,041 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 21:09:23,041 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 24 [2018-11-18 21:09:23,042 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:09:23,042 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states. [2018-11-18 21:09:23,151 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 24 edges. 24 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:09:23,152 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 21:09:23,152 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 21:09:23,152 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 21:09:23,152 INFO L87 Difference]: Start difference. First operand 82 states and 106 transitions. Second operand 4 states. [2018-11-18 21:09:23,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:23,730 INFO L93 Difference]: Finished difference Result 137 states and 173 transitions. [2018-11-18 21:09:23,731 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 21:09:23,731 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 24 [2018-11-18 21:09:23,731 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:09:23,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-18 21:09:23,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 74 transitions. [2018-11-18 21:09:23,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-18 21:09:23,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 74 transitions. [2018-11-18 21:09:23,738 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states and 74 transitions. [2018-11-18 21:09:23,961 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 74 edges. 74 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:09:23,963 INFO L225 Difference]: With dead ends: 137 [2018-11-18 21:09:23,963 INFO L226 Difference]: Without dead ends: 92 [2018-11-18 21:09:23,964 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 21 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-18 21:09:23,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92 states. [2018-11-18 21:09:24,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92 to 79. [2018-11-18 21:09:24,032 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:09:24,033 INFO L82 GeneralOperation]: Start isEquivalent. First operand 92 states. Second operand 79 states. [2018-11-18 21:09:24,033 INFO L74 IsIncluded]: Start isIncluded. First operand 92 states. Second operand 79 states. [2018-11-18 21:09:24,033 INFO L87 Difference]: Start difference. First operand 92 states. Second operand 79 states. [2018-11-18 21:09:24,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:24,038 INFO L93 Difference]: Finished difference Result 92 states and 114 transitions. [2018-11-18 21:09:24,038 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 114 transitions. [2018-11-18 21:09:24,038 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:09:24,039 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:09:24,039 INFO L74 IsIncluded]: Start isIncluded. First operand 79 states. Second operand 92 states. [2018-11-18 21:09:24,039 INFO L87 Difference]: Start difference. First operand 79 states. Second operand 92 states. [2018-11-18 21:09:24,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:24,044 INFO L93 Difference]: Finished difference Result 92 states and 114 transitions. [2018-11-18 21:09:24,044 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 114 transitions. [2018-11-18 21:09:24,044 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:09:24,044 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:09:24,045 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:09:24,045 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:09:24,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79 states. [2018-11-18 21:09:24,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 97 transitions. [2018-11-18 21:09:24,050 INFO L78 Accepts]: Start accepts. Automaton has 79 states and 97 transitions. Word has length 24 [2018-11-18 21:09:24,050 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:09:24,050 INFO L480 AbstractCegarLoop]: Abstraction has 79 states and 97 transitions. [2018-11-18 21:09:24,050 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 21:09:24,050 INFO L276 IsEmpty]: Start isEmpty. Operand 79 states and 97 transitions. [2018-11-18 21:09:24,051 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-11-18 21:09:24,051 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:09:24,051 INFO L375 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:09:24,051 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:09:24,051 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:09:24,052 INFO L82 PathProgramCache]: Analyzing trace with hash -1246849536, now seen corresponding path program 1 times [2018-11-18 21:09:24,052 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:09:24,052 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:09:24,078 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:09:24,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:09:24,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:09:24,309 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:09:24,375 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-18 21:09:24,382 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-18 21:09:24,386 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:09:24,389 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:24,411 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:24,411 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:25, output treesize:21 [2018-11-18 21:09:24,475 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 24 [2018-11-18 21:09:24,482 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:24,483 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 39 [2018-11-18 21:09:24,485 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:09:24,496 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:24,515 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:24,515 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:37, output treesize:33 [2018-11-18 21:09:24,587 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 23 [2018-11-18 21:09:24,598 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:24,606 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:24,608 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:24,609 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 46 [2018-11-18 21:09:24,613 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:09:24,625 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:24,638 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:24,639 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:33, output treesize:29 [2018-11-18 21:09:24,783 INFO L256 TraceCheckUtils]: 0: Hoare triple {2388#true} call ULTIMATE.init(); {2388#true} is VALID [2018-11-18 21:09:24,784 INFO L273 TraceCheckUtils]: 1: Hoare triple {2388#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {2388#true} is VALID [2018-11-18 21:09:24,784 INFO L273 TraceCheckUtils]: 2: Hoare triple {2388#true} assume true; {2388#true} is VALID [2018-11-18 21:09:24,784 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2388#true} {2388#true} #85#return; {2388#true} is VALID [2018-11-18 21:09:24,784 INFO L256 TraceCheckUtils]: 4: Hoare triple {2388#true} call #t~ret7 := main(); {2388#true} is VALID [2018-11-18 21:09:24,784 INFO L273 TraceCheckUtils]: 5: Hoare triple {2388#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {2388#true} is VALID [2018-11-18 21:09:24,785 INFO L273 TraceCheckUtils]: 6: Hoare triple {2388#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {2411#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:09:24,786 INFO L273 TraceCheckUtils]: 7: Hoare triple {2411#(= |main_~#volArray~0.offset| (_ bv0 32))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {2415#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:24,787 INFO L273 TraceCheckUtils]: 8: Hoare triple {2415#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {2415#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:24,787 INFO L273 TraceCheckUtils]: 9: Hoare triple {2415#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {2415#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:24,788 INFO L273 TraceCheckUtils]: 10: Hoare triple {2415#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 3bv32))), 4bv32); {2425#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:24,793 INFO L273 TraceCheckUtils]: 11: Hoare triple {2425#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 2bv32))), 4bv32); {2429#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:24,797 INFO L273 TraceCheckUtils]: 12: Hoare triple {2429#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 1bv32))), 4bv32); {2433#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:09:24,798 INFO L273 TraceCheckUtils]: 13: Hoare triple {2433#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {2433#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:09:24,799 INFO L273 TraceCheckUtils]: 14: Hoare triple {2433#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume true; {2433#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:09:24,799 INFO L273 TraceCheckUtils]: 15: Hoare triple {2433#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {2433#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:09:24,800 INFO L273 TraceCheckUtils]: 16: Hoare triple {2433#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} ~i~0 := 0bv32; {2446#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:09:24,800 INFO L273 TraceCheckUtils]: 17: Hoare triple {2446#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume true; {2446#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:09:24,802 INFO L273 TraceCheckUtils]: 18: Hoare triple {2446#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {2446#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:09:24,803 INFO L273 TraceCheckUtils]: 19: Hoare triple {2446#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := 0bv32 == #t~mem5; {2456#|main_#t~short6|} is VALID [2018-11-18 21:09:24,804 INFO L256 TraceCheckUtils]: 20: Hoare triple {2456#|main_#t~short6|} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {2460#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:24,805 INFO L273 TraceCheckUtils]: 21: Hoare triple {2460#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {2464#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:24,806 INFO L273 TraceCheckUtils]: 22: Hoare triple {2464#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 == ~cond; {2389#false} is VALID [2018-11-18 21:09:24,806 INFO L273 TraceCheckUtils]: 23: Hoare triple {2389#false} assume !false; {2389#false} is VALID [2018-11-18 21:09:24,809 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:09:24,809 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 21:09:25,062 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 29 [2018-11-18 21:09:25,069 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 33 [2018-11-18 21:09:25,118 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:25,119 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 49 [2018-11-18 21:09:25,246 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:09:25,248 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 33 [2018-11-18 21:09:25,251 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-18 21:09:25,263 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:25,275 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:25,284 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:25,297 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:25,297 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 2 variables, input treesize:31, output treesize:24 [2018-11-18 21:09:25,302 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-18 21:09:25,366 INFO L273 TraceCheckUtils]: 23: Hoare triple {2389#false} assume !false; {2389#false} is VALID [2018-11-18 21:09:25,367 INFO L273 TraceCheckUtils]: 22: Hoare triple {2474#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} assume 0bv32 == ~cond; {2389#false} is VALID [2018-11-18 21:09:25,368 INFO L273 TraceCheckUtils]: 21: Hoare triple {2478#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} ~cond := #in~cond; {2474#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} is VALID [2018-11-18 21:09:25,369 INFO L256 TraceCheckUtils]: 20: Hoare triple {2456#|main_#t~short6|} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {2478#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-18 21:09:25,370 INFO L273 TraceCheckUtils]: 19: Hoare triple {2485#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := 0bv32 == #t~mem5; {2456#|main_#t~short6|} is VALID [2018-11-18 21:09:25,370 INFO L273 TraceCheckUtils]: 18: Hoare triple {2485#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {2485#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-18 21:09:25,371 INFO L273 TraceCheckUtils]: 17: Hoare triple {2485#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume true; {2485#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-18 21:09:25,372 INFO L273 TraceCheckUtils]: 16: Hoare triple {2495#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|))} ~i~0 := 0bv32; {2485#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-18 21:09:25,372 INFO L273 TraceCheckUtils]: 15: Hoare triple {2495#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {2495#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|))} is VALID [2018-11-18 21:09:25,373 INFO L273 TraceCheckUtils]: 14: Hoare triple {2495#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|))} assume true; {2495#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|))} is VALID [2018-11-18 21:09:25,374 INFO L273 TraceCheckUtils]: 13: Hoare triple {2495#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {2495#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|))} is VALID [2018-11-18 21:09:25,386 INFO L273 TraceCheckUtils]: 12: Hoare triple {2508#(= (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) |main_~#volArray~0.offset|) (_ bv0 32))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 1bv32))), 4bv32); {2495#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|))} is VALID [2018-11-18 21:09:25,397 INFO L273 TraceCheckUtils]: 11: Hoare triple {2512#(= (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) |main_~#volArray~0.offset|) (_ bv0 32))} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 2bv32))), 4bv32); {2508#(= (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) |main_~#volArray~0.offset|) (_ bv0 32))} is VALID [2018-11-18 21:09:25,406 INFO L273 TraceCheckUtils]: 10: Hoare triple {2516#(or (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv8 32) (bvmul (_ bv12 32) main_~i~0)))} assume !~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 3bv32))), 4bv32); {2512#(= (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) |main_~#volArray~0.offset|) (_ bv0 32))} is VALID [2018-11-18 21:09:25,407 INFO L273 TraceCheckUtils]: 9: Hoare triple {2516#(or (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv8 32) (bvmul (_ bv12 32) main_~i~0)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {2516#(or (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv8 32) (bvmul (_ bv12 32) main_~i~0)))} is VALID [2018-11-18 21:09:25,408 INFO L273 TraceCheckUtils]: 8: Hoare triple {2516#(or (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv8 32) (bvmul (_ bv12 32) main_~i~0)))} assume true; {2516#(or (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv8 32) (bvmul (_ bv12 32) main_~i~0)))} is VALID [2018-11-18 21:09:25,409 INFO L273 TraceCheckUtils]: 7: Hoare triple {2388#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {2516#(or (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv8 32) (bvmul (_ bv12 32) main_~i~0)))} is VALID [2018-11-18 21:09:25,409 INFO L273 TraceCheckUtils]: 6: Hoare triple {2388#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {2388#true} is VALID [2018-11-18 21:09:25,409 INFO L273 TraceCheckUtils]: 5: Hoare triple {2388#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {2388#true} is VALID [2018-11-18 21:09:25,409 INFO L256 TraceCheckUtils]: 4: Hoare triple {2388#true} call #t~ret7 := main(); {2388#true} is VALID [2018-11-18 21:09:25,410 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2388#true} {2388#true} #85#return; {2388#true} is VALID [2018-11-18 21:09:25,410 INFO L273 TraceCheckUtils]: 2: Hoare triple {2388#true} assume true; {2388#true} is VALID [2018-11-18 21:09:25,410 INFO L273 TraceCheckUtils]: 1: Hoare triple {2388#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {2388#true} is VALID [2018-11-18 21:09:25,411 INFO L256 TraceCheckUtils]: 0: Hoare triple {2388#true} call ULTIMATE.init(); {2388#true} is VALID [2018-11-18 21:09:25,412 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:09:25,414 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 21:09:25,414 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10] total 18 [2018-11-18 21:09:25,414 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 24 [2018-11-18 21:09:25,415 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:09:25,415 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 18 states. [2018-11-18 21:09:25,588 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 41 edges. 41 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:09:25,588 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-18 21:09:25,588 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-18 21:09:25,589 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=242, Unknown=0, NotChecked=0, Total=306 [2018-11-18 21:09:25,589 INFO L87 Difference]: Start difference. First operand 79 states and 97 transitions. Second operand 18 states. [2018-11-18 21:09:31,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:31,782 INFO L93 Difference]: Finished difference Result 146 states and 184 transitions. [2018-11-18 21:09:31,782 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-11-18 21:09:31,782 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 24 [2018-11-18 21:09:31,782 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:09:31,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2018-11-18 21:09:31,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 133 transitions. [2018-11-18 21:09:31,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2018-11-18 21:09:31,789 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 133 transitions. [2018-11-18 21:09:31,790 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 24 states and 133 transitions. [2018-11-18 21:09:40,197 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 133 edges. 129 inductive. 0 not inductive. 4 times theorem prover too weak to decide inductivity. [2018-11-18 21:09:40,200 INFO L225 Difference]: With dead ends: 146 [2018-11-18 21:09:40,200 INFO L226 Difference]: Without dead ends: 144 [2018-11-18 21:09:40,201 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 31 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 184 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=235, Invalid=757, Unknown=0, NotChecked=0, Total=992 [2018-11-18 21:09:40,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-11-18 21:09:40,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 101. [2018-11-18 21:09:40,317 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:09:40,317 INFO L82 GeneralOperation]: Start isEquivalent. First operand 144 states. Second operand 101 states. [2018-11-18 21:09:40,318 INFO L74 IsIncluded]: Start isIncluded. First operand 144 states. Second operand 101 states. [2018-11-18 21:09:40,318 INFO L87 Difference]: Start difference. First operand 144 states. Second operand 101 states. [2018-11-18 21:09:40,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:40,325 INFO L93 Difference]: Finished difference Result 144 states and 182 transitions. [2018-11-18 21:09:40,325 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 182 transitions. [2018-11-18 21:09:40,325 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:09:40,326 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:09:40,326 INFO L74 IsIncluded]: Start isIncluded. First operand 101 states. Second operand 144 states. [2018-11-18 21:09:40,326 INFO L87 Difference]: Start difference. First operand 101 states. Second operand 144 states. [2018-11-18 21:09:40,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:40,332 INFO L93 Difference]: Finished difference Result 144 states and 182 transitions. [2018-11-18 21:09:40,332 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 182 transitions. [2018-11-18 21:09:40,333 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:09:40,333 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:09:40,333 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:09:40,333 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:09:40,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 101 states. [2018-11-18 21:09:40,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 125 transitions. [2018-11-18 21:09:40,337 INFO L78 Accepts]: Start accepts. Automaton has 101 states and 125 transitions. Word has length 24 [2018-11-18 21:09:40,337 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:09:40,337 INFO L480 AbstractCegarLoop]: Abstraction has 101 states and 125 transitions. [2018-11-18 21:09:40,338 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-18 21:09:40,338 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 125 transitions. [2018-11-18 21:09:40,338 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-11-18 21:09:40,338 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:09:40,339 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:09:40,339 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:09:40,339 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:09:40,339 INFO L82 PathProgramCache]: Analyzing trace with hash 1994688011, now seen corresponding path program 1 times [2018-11-18 21:09:40,339 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:09:40,340 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:09:40,363 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:09:40,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:09:40,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:09:40,414 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:09:40,468 INFO L256 TraceCheckUtils]: 0: Hoare triple {3177#true} call ULTIMATE.init(); {3177#true} is VALID [2018-11-18 21:09:40,469 INFO L273 TraceCheckUtils]: 1: Hoare triple {3177#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {3177#true} is VALID [2018-11-18 21:09:40,469 INFO L273 TraceCheckUtils]: 2: Hoare triple {3177#true} assume true; {3177#true} is VALID [2018-11-18 21:09:40,469 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {3177#true} {3177#true} #85#return; {3177#true} is VALID [2018-11-18 21:09:40,469 INFO L256 TraceCheckUtils]: 4: Hoare triple {3177#true} call #t~ret7 := main(); {3177#true} is VALID [2018-11-18 21:09:40,469 INFO L273 TraceCheckUtils]: 5: Hoare triple {3177#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {3177#true} is VALID [2018-11-18 21:09:40,470 INFO L273 TraceCheckUtils]: 6: Hoare triple {3177#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {3177#true} is VALID [2018-11-18 21:09:40,470 INFO L273 TraceCheckUtils]: 7: Hoare triple {3177#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {3177#true} is VALID [2018-11-18 21:09:40,470 INFO L273 TraceCheckUtils]: 8: Hoare triple {3177#true} assume true; {3177#true} is VALID [2018-11-18 21:09:40,470 INFO L273 TraceCheckUtils]: 9: Hoare triple {3177#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {3177#true} is VALID [2018-11-18 21:09:40,471 INFO L273 TraceCheckUtils]: 10: Hoare triple {3177#true} assume !~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 3bv32))), 4bv32); {3177#true} is VALID [2018-11-18 21:09:40,476 INFO L273 TraceCheckUtils]: 11: Hoare triple {3177#true} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 2bv32))), 4bv32); {3215#(not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} is VALID [2018-11-18 21:09:40,477 INFO L273 TraceCheckUtils]: 12: Hoare triple {3215#(not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 1bv32))), 4bv32); {3215#(not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} is VALID [2018-11-18 21:09:40,477 INFO L273 TraceCheckUtils]: 13: Hoare triple {3215#(not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3215#(not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} is VALID [2018-11-18 21:09:40,480 INFO L273 TraceCheckUtils]: 14: Hoare triple {3215#(not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} assume true; {3215#(not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} is VALID [2018-11-18 21:09:40,480 INFO L273 TraceCheckUtils]: 15: Hoare triple {3215#(not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {3215#(not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} is VALID [2018-11-18 21:09:40,480 INFO L273 TraceCheckUtils]: 16: Hoare triple {3215#(not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} assume !~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 3bv32))), 4bv32); {3215#(not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} is VALID [2018-11-18 21:09:40,481 INFO L273 TraceCheckUtils]: 17: Hoare triple {3215#(not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 2bv32))), 4bv32); {3178#false} is VALID [2018-11-18 21:09:40,481 INFO L273 TraceCheckUtils]: 18: Hoare triple {3178#false} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 1bv32))), 4bv32); {3178#false} is VALID [2018-11-18 21:09:40,481 INFO L273 TraceCheckUtils]: 19: Hoare triple {3178#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3178#false} is VALID [2018-11-18 21:09:40,481 INFO L273 TraceCheckUtils]: 20: Hoare triple {3178#false} assume true; {3178#false} is VALID [2018-11-18 21:09:40,482 INFO L273 TraceCheckUtils]: 21: Hoare triple {3178#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {3178#false} is VALID [2018-11-18 21:09:40,482 INFO L273 TraceCheckUtils]: 22: Hoare triple {3178#false} ~i~0 := 0bv32; {3178#false} is VALID [2018-11-18 21:09:40,482 INFO L273 TraceCheckUtils]: 23: Hoare triple {3178#false} assume true; {3178#false} is VALID [2018-11-18 21:09:40,482 INFO L273 TraceCheckUtils]: 24: Hoare triple {3178#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3178#false} is VALID [2018-11-18 21:09:40,482 INFO L273 TraceCheckUtils]: 25: Hoare triple {3178#false} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := 0bv32 == #t~mem5; {3178#false} is VALID [2018-11-18 21:09:40,482 INFO L256 TraceCheckUtils]: 26: Hoare triple {3178#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3178#false} is VALID [2018-11-18 21:09:40,482 INFO L273 TraceCheckUtils]: 27: Hoare triple {3178#false} ~cond := #in~cond; {3178#false} is VALID [2018-11-18 21:09:40,483 INFO L273 TraceCheckUtils]: 28: Hoare triple {3178#false} assume 0bv32 == ~cond; {3178#false} is VALID [2018-11-18 21:09:40,483 INFO L273 TraceCheckUtils]: 29: Hoare triple {3178#false} assume !false; {3178#false} is VALID [2018-11-18 21:09:40,484 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:09:40,484 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-18 21:09:40,485 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 21:09:40,485 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 21:09:40,486 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 30 [2018-11-18 21:09:40,486 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:09:40,486 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2018-11-18 21:09:40,580 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 30 edges. 30 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:09:40,581 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 21:09:40,581 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 21:09:40,581 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 21:09:40,581 INFO L87 Difference]: Start difference. First operand 101 states and 125 transitions. Second operand 3 states. [2018-11-18 21:09:41,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:41,071 INFO L93 Difference]: Finished difference Result 134 states and 163 transitions. [2018-11-18 21:09:41,071 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 21:09:41,072 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 30 [2018-11-18 21:09:41,072 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:09:41,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-18 21:09:41,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 68 transitions. [2018-11-18 21:09:41,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-18 21:09:41,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 68 transitions. [2018-11-18 21:09:41,074 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states and 68 transitions. [2018-11-18 21:09:41,246 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 68 edges. 68 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:09:41,249 INFO L225 Difference]: With dead ends: 134 [2018-11-18 21:09:41,249 INFO L226 Difference]: Without dead ends: 112 [2018-11-18 21:09:41,249 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 28 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 21:09:41,249 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-11-18 21:09:41,466 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 97. [2018-11-18 21:09:41,467 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:09:41,467 INFO L82 GeneralOperation]: Start isEquivalent. First operand 112 states. Second operand 97 states. [2018-11-18 21:09:41,467 INFO L74 IsIncluded]: Start isIncluded. First operand 112 states. Second operand 97 states. [2018-11-18 21:09:41,467 INFO L87 Difference]: Start difference. First operand 112 states. Second operand 97 states. [2018-11-18 21:09:41,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:41,472 INFO L93 Difference]: Finished difference Result 112 states and 139 transitions. [2018-11-18 21:09:41,472 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 139 transitions. [2018-11-18 21:09:41,472 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:09:41,472 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:09:41,473 INFO L74 IsIncluded]: Start isIncluded. First operand 97 states. Second operand 112 states. [2018-11-18 21:09:41,473 INFO L87 Difference]: Start difference. First operand 97 states. Second operand 112 states. [2018-11-18 21:09:41,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:41,477 INFO L93 Difference]: Finished difference Result 112 states and 139 transitions. [2018-11-18 21:09:41,477 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 139 transitions. [2018-11-18 21:09:41,478 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:09:41,478 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:09:41,478 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:09:41,478 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:09:41,478 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-11-18 21:09:41,481 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 120 transitions. [2018-11-18 21:09:41,482 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 120 transitions. Word has length 30 [2018-11-18 21:09:41,482 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:09:41,482 INFO L480 AbstractCegarLoop]: Abstraction has 97 states and 120 transitions. [2018-11-18 21:09:41,482 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 21:09:41,482 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 120 transitions. [2018-11-18 21:09:41,483 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-11-18 21:09:41,483 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:09:41,483 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:09:41,484 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:09:41,484 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:09:41,484 INFO L82 PathProgramCache]: Analyzing trace with hash 1935151821, now seen corresponding path program 1 times [2018-11-18 21:09:41,484 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:09:41,484 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:09:41,513 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:09:41,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:09:41,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:09:41,851 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:09:42,082 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-18 21:09:42,087 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-18 21:09:42,091 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:09:42,094 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:42,109 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:42,109 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:25, output treesize:21 [2018-11-18 21:09:42,172 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 18 [2018-11-18 21:09:42,178 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:42,179 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 27 [2018-11-18 21:09:42,188 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:09:42,195 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:42,208 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:42,208 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:26, output treesize:22 [2018-11-18 21:09:42,658 INFO L256 TraceCheckUtils]: 0: Hoare triple {3783#true} call ULTIMATE.init(); {3783#true} is VALID [2018-11-18 21:09:42,658 INFO L273 TraceCheckUtils]: 1: Hoare triple {3783#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {3783#true} is VALID [2018-11-18 21:09:42,659 INFO L273 TraceCheckUtils]: 2: Hoare triple {3783#true} assume true; {3783#true} is VALID [2018-11-18 21:09:42,659 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {3783#true} {3783#true} #85#return; {3783#true} is VALID [2018-11-18 21:09:42,659 INFO L256 TraceCheckUtils]: 4: Hoare triple {3783#true} call #t~ret7 := main(); {3783#true} is VALID [2018-11-18 21:09:42,660 INFO L273 TraceCheckUtils]: 5: Hoare triple {3783#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {3783#true} is VALID [2018-11-18 21:09:42,660 INFO L273 TraceCheckUtils]: 6: Hoare triple {3783#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {3806#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:09:42,661 INFO L273 TraceCheckUtils]: 7: Hoare triple {3806#(= |main_~#volArray~0.offset| (_ bv0 32))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {3810#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:42,662 INFO L273 TraceCheckUtils]: 8: Hoare triple {3810#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {3810#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:42,662 INFO L273 TraceCheckUtils]: 9: Hoare triple {3810#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {3810#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:42,663 INFO L273 TraceCheckUtils]: 10: Hoare triple {3810#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 3bv32))), 4bv32); {3810#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:42,664 INFO L273 TraceCheckUtils]: 11: Hoare triple {3810#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 2bv32))), 4bv32); {3823#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:42,668 INFO L273 TraceCheckUtils]: 12: Hoare triple {3823#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 1bv32))), 4bv32); {3827#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:09:42,669 INFO L273 TraceCheckUtils]: 13: Hoare triple {3827#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3827#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:09:42,670 INFO L273 TraceCheckUtils]: 14: Hoare triple {3827#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume true; {3827#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:09:42,671 INFO L273 TraceCheckUtils]: 15: Hoare triple {3827#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {3827#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:09:42,671 INFO L273 TraceCheckUtils]: 16: Hoare triple {3827#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} ~i~0 := 0bv32; {3840#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:09:42,672 INFO L273 TraceCheckUtils]: 17: Hoare triple {3840#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume true; {3840#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:09:42,675 INFO L273 TraceCheckUtils]: 18: Hoare triple {3840#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3840#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:09:42,678 INFO L273 TraceCheckUtils]: 19: Hoare triple {3840#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume #t~short6; {3840#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:09:42,680 INFO L256 TraceCheckUtils]: 20: Hoare triple {3840#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3853#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32)))))} is VALID [2018-11-18 21:09:42,680 INFO L273 TraceCheckUtils]: 21: Hoare triple {3853#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32)))))} ~cond := #in~cond; {3853#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32)))))} is VALID [2018-11-18 21:09:42,681 INFO L273 TraceCheckUtils]: 22: Hoare triple {3853#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32)))))} assume !(0bv32 == ~cond); {3853#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32)))))} is VALID [2018-11-18 21:09:42,681 INFO L273 TraceCheckUtils]: 23: Hoare triple {3853#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32)))))} assume true; {3853#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32)))))} is VALID [2018-11-18 21:09:42,682 INFO L268 TraceCheckUtils]: 24: Hoare quadruple {3853#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32)))))} {3840#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #89#return; {3840#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:09:42,683 INFO L273 TraceCheckUtils]: 25: Hoare triple {3840#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} havoc #t~mem5;havoc #t~mem4;havoc #t~short6; {3840#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:09:42,686 INFO L273 TraceCheckUtils]: 26: Hoare triple {3840#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {3872#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:42,689 INFO L273 TraceCheckUtils]: 27: Hoare triple {3872#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {3872#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:42,694 INFO L273 TraceCheckUtils]: 28: Hoare triple {3872#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3872#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:42,696 INFO L273 TraceCheckUtils]: 29: Hoare triple {3872#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := 0bv32 == #t~mem5; {3882#|main_#t~short6|} is VALID [2018-11-18 21:09:42,697 INFO L256 TraceCheckUtils]: 30: Hoare triple {3882#|main_#t~short6|} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3886#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:42,697 INFO L273 TraceCheckUtils]: 31: Hoare triple {3886#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {3890#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-18 21:09:42,698 INFO L273 TraceCheckUtils]: 32: Hoare triple {3890#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 == ~cond; {3784#false} is VALID [2018-11-18 21:09:42,698 INFO L273 TraceCheckUtils]: 33: Hoare triple {3784#false} assume !false; {3784#false} is VALID [2018-11-18 21:09:42,703 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:09:42,703 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 21:09:42,981 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 23 [2018-11-18 21:09:42,990 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 27 [2018-11-18 21:09:43,066 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 14 [2018-11-18 21:09:43,069 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-18 21:09:43,078 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:43,088 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:43,097 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:43,097 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 2 variables, input treesize:25, output treesize:18 [2018-11-18 21:09:43,104 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-18 21:09:43,181 INFO L273 TraceCheckUtils]: 33: Hoare triple {3784#false} assume !false; {3784#false} is VALID [2018-11-18 21:09:43,182 INFO L273 TraceCheckUtils]: 32: Hoare triple {3900#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} assume 0bv32 == ~cond; {3784#false} is VALID [2018-11-18 21:09:43,182 INFO L273 TraceCheckUtils]: 31: Hoare triple {3904#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} ~cond := #in~cond; {3900#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} is VALID [2018-11-18 21:09:43,183 INFO L256 TraceCheckUtils]: 30: Hoare triple {3882#|main_#t~short6|} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3904#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-18 21:09:43,183 INFO L273 TraceCheckUtils]: 29: Hoare triple {3911#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := 0bv32 == #t~mem5; {3882#|main_#t~short6|} is VALID [2018-11-18 21:09:43,184 INFO L273 TraceCheckUtils]: 28: Hoare triple {3911#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3911#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-18 21:09:43,184 INFO L273 TraceCheckUtils]: 27: Hoare triple {3911#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume true; {3911#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-18 21:09:43,400 INFO L273 TraceCheckUtils]: 26: Hoare triple {3921#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {3911#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-18 21:09:43,400 INFO L273 TraceCheckUtils]: 25: Hoare triple {3921#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} havoc #t~mem5;havoc #t~mem4;havoc #t~short6; {3921#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-18 21:09:43,401 INFO L268 TraceCheckUtils]: 24: Hoare quadruple {3783#true} {3921#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} #89#return; {3921#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-18 21:09:43,401 INFO L273 TraceCheckUtils]: 23: Hoare triple {3783#true} assume true; {3783#true} is VALID [2018-11-18 21:09:43,402 INFO L273 TraceCheckUtils]: 22: Hoare triple {3783#true} assume !(0bv32 == ~cond); {3783#true} is VALID [2018-11-18 21:09:43,402 INFO L273 TraceCheckUtils]: 21: Hoare triple {3783#true} ~cond := #in~cond; {3783#true} is VALID [2018-11-18 21:09:43,402 INFO L256 TraceCheckUtils]: 20: Hoare triple {3921#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {3783#true} is VALID [2018-11-18 21:09:43,408 INFO L273 TraceCheckUtils]: 19: Hoare triple {3921#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} assume #t~short6; {3921#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-18 21:09:43,409 INFO L273 TraceCheckUtils]: 18: Hoare triple {3921#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {3921#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-18 21:09:43,409 INFO L273 TraceCheckUtils]: 17: Hoare triple {3921#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} assume true; {3921#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-18 21:09:43,411 INFO L273 TraceCheckUtils]: 16: Hoare triple {3952#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} ~i~0 := 0bv32; {3921#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-18 21:09:43,411 INFO L273 TraceCheckUtils]: 15: Hoare triple {3952#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {3952#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-18 21:09:43,411 INFO L273 TraceCheckUtils]: 14: Hoare triple {3952#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} assume true; {3952#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-18 21:09:43,435 INFO L273 TraceCheckUtils]: 13: Hoare triple {3952#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3952#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-18 21:09:43,458 INFO L273 TraceCheckUtils]: 12: Hoare triple {3965#(= (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 1bv32))), 4bv32); {3952#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-18 21:09:43,474 INFO L273 TraceCheckUtils]: 11: Hoare triple {3969#(or (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)))} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 2bv32))), 4bv32); {3965#(= (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-18 21:09:43,475 INFO L273 TraceCheckUtils]: 10: Hoare triple {3969#(or (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 3bv32))), 4bv32); {3969#(or (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)))} is VALID [2018-11-18 21:09:43,475 INFO L273 TraceCheckUtils]: 9: Hoare triple {3969#(or (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {3969#(or (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)))} is VALID [2018-11-18 21:09:43,476 INFO L273 TraceCheckUtils]: 8: Hoare triple {3969#(or (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)))} assume true; {3969#(or (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)))} is VALID [2018-11-18 21:09:43,476 INFO L273 TraceCheckUtils]: 7: Hoare triple {3783#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {3969#(or (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)))} is VALID [2018-11-18 21:09:43,477 INFO L273 TraceCheckUtils]: 6: Hoare triple {3783#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {3783#true} is VALID [2018-11-18 21:09:43,477 INFO L273 TraceCheckUtils]: 5: Hoare triple {3783#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {3783#true} is VALID [2018-11-18 21:09:43,477 INFO L256 TraceCheckUtils]: 4: Hoare triple {3783#true} call #t~ret7 := main(); {3783#true} is VALID [2018-11-18 21:09:43,477 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {3783#true} {3783#true} #85#return; {3783#true} is VALID [2018-11-18 21:09:43,477 INFO L273 TraceCheckUtils]: 2: Hoare triple {3783#true} assume true; {3783#true} is VALID [2018-11-18 21:09:43,478 INFO L273 TraceCheckUtils]: 1: Hoare triple {3783#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {3783#true} is VALID [2018-11-18 21:09:43,478 INFO L256 TraceCheckUtils]: 0: Hoare triple {3783#true} call ULTIMATE.init(); {3783#true} is VALID [2018-11-18 21:09:43,481 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:09:43,483 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 21:09:43,483 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 10] total 19 [2018-11-18 21:09:43,484 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 34 [2018-11-18 21:09:43,484 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:09:43,484 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 19 states. [2018-11-18 21:09:43,914 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 61 edges. 61 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:09:43,914 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-11-18 21:09:43,914 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-11-18 21:09:43,915 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=276, Unknown=0, NotChecked=0, Total=342 [2018-11-18 21:09:43,915 INFO L87 Difference]: Start difference. First operand 97 states and 120 transitions. Second operand 19 states. [2018-11-18 21:09:52,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:52,760 INFO L93 Difference]: Finished difference Result 174 states and 208 transitions. [2018-11-18 21:09:52,760 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-11-18 21:09:52,760 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 34 [2018-11-18 21:09:52,760 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:09:52,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19 states. [2018-11-18 21:09:52,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 123 transitions. [2018-11-18 21:09:52,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19 states. [2018-11-18 21:09:52,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 123 transitions. [2018-11-18 21:09:52,767 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 23 states and 123 transitions. [2018-11-18 21:09:57,313 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 123 edges. 121 inductive. 0 not inductive. 2 times theorem prover too weak to decide inductivity. [2018-11-18 21:09:57,318 INFO L225 Difference]: With dead ends: 174 [2018-11-18 21:09:57,318 INFO L226 Difference]: Without dead ends: 172 [2018-11-18 21:09:57,319 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 80 GetRequests, 50 SyntacticMatches, 1 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 187 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=172, Invalid=758, Unknown=0, NotChecked=0, Total=930 [2018-11-18 21:09:57,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states. [2018-11-18 21:09:57,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 142. [2018-11-18 21:09:57,645 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:09:57,645 INFO L82 GeneralOperation]: Start isEquivalent. First operand 172 states. Second operand 142 states. [2018-11-18 21:09:57,645 INFO L74 IsIncluded]: Start isIncluded. First operand 172 states. Second operand 142 states. [2018-11-18 21:09:57,645 INFO L87 Difference]: Start difference. First operand 172 states. Second operand 142 states. [2018-11-18 21:09:57,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:57,653 INFO L93 Difference]: Finished difference Result 172 states and 206 transitions. [2018-11-18 21:09:57,653 INFO L276 IsEmpty]: Start isEmpty. Operand 172 states and 206 transitions. [2018-11-18 21:09:57,654 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:09:57,654 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:09:57,654 INFO L74 IsIncluded]: Start isIncluded. First operand 142 states. Second operand 172 states. [2018-11-18 21:09:57,654 INFO L87 Difference]: Start difference. First operand 142 states. Second operand 172 states. [2018-11-18 21:09:57,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:09:57,660 INFO L93 Difference]: Finished difference Result 172 states and 206 transitions. [2018-11-18 21:09:57,660 INFO L276 IsEmpty]: Start isEmpty. Operand 172 states and 206 transitions. [2018-11-18 21:09:57,661 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:09:57,661 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:09:57,661 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:09:57,661 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:09:57,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-11-18 21:09:57,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 173 transitions. [2018-11-18 21:09:57,666 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 173 transitions. Word has length 34 [2018-11-18 21:09:57,666 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:09:57,666 INFO L480 AbstractCegarLoop]: Abstraction has 142 states and 173 transitions. [2018-11-18 21:09:57,666 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-11-18 21:09:57,666 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 173 transitions. [2018-11-18 21:09:57,667 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-11-18 21:09:57,668 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:09:57,668 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:09:57,668 INFO L423 AbstractCegarLoop]: === Iteration 10 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:09:57,668 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:09:57,668 INFO L82 PathProgramCache]: Analyzing trace with hash -773231859, now seen corresponding path program 1 times [2018-11-18 21:09:57,669 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:09:57,669 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:09:57,705 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 21:09:57,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:09:58,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:09:58,073 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:09:58,256 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-18 21:09:58,260 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-18 21:09:58,264 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:09:58,267 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:58,287 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:58,287 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:31, output treesize:24 [2018-11-18 21:09:58,357 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 18 [2018-11-18 21:09:58,366 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:09:58,369 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 27 [2018-11-18 21:09:58,377 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:09:58,388 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:58,406 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:09:58,406 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:29, output treesize:16 [2018-11-18 21:09:58,417 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-18 21:09:58,593 INFO L256 TraceCheckUtils]: 0: Hoare triple {4775#true} call ULTIMATE.init(); {4775#true} is VALID [2018-11-18 21:09:58,594 INFO L273 TraceCheckUtils]: 1: Hoare triple {4775#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {4775#true} is VALID [2018-11-18 21:09:58,594 INFO L273 TraceCheckUtils]: 2: Hoare triple {4775#true} assume true; {4775#true} is VALID [2018-11-18 21:09:58,594 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {4775#true} {4775#true} #85#return; {4775#true} is VALID [2018-11-18 21:09:58,594 INFO L256 TraceCheckUtils]: 4: Hoare triple {4775#true} call #t~ret7 := main(); {4775#true} is VALID [2018-11-18 21:09:58,594 INFO L273 TraceCheckUtils]: 5: Hoare triple {4775#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {4775#true} is VALID [2018-11-18 21:09:58,595 INFO L273 TraceCheckUtils]: 6: Hoare triple {4775#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {4798#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-18 21:09:58,596 INFO L273 TraceCheckUtils]: 7: Hoare triple {4798#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {4802#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:58,597 INFO L273 TraceCheckUtils]: 8: Hoare triple {4802#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {4802#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:58,597 INFO L273 TraceCheckUtils]: 9: Hoare triple {4802#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {4802#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:58,598 INFO L273 TraceCheckUtils]: 10: Hoare triple {4802#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 3bv32))), 4bv32); {4812#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:58,599 INFO L273 TraceCheckUtils]: 11: Hoare triple {4812#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 2bv32))), 4bv32); {4816#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:58,601 INFO L273 TraceCheckUtils]: 12: Hoare triple {4816#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL1~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 1bv32))), 4bv32); {4820#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:58,602 INFO L273 TraceCheckUtils]: 13: Hoare triple {4820#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {4820#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:58,603 INFO L273 TraceCheckUtils]: 14: Hoare triple {4820#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))} assume true; {4820#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:58,604 INFO L273 TraceCheckUtils]: 15: Hoare triple {4820#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {4820#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:58,606 INFO L273 TraceCheckUtils]: 16: Hoare triple {4820#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))} ~i~0 := 0bv32; {4833#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:58,606 INFO L273 TraceCheckUtils]: 17: Hoare triple {4833#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))} assume true; {4833#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:58,607 INFO L273 TraceCheckUtils]: 18: Hoare triple {4833#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {4833#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:58,607 INFO L273 TraceCheckUtils]: 19: Hoare triple {4833#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))} assume #t~short6; {4833#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:58,609 INFO L256 TraceCheckUtils]: 20: Hoare triple {4833#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {4846#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))))} is VALID [2018-11-18 21:09:58,610 INFO L273 TraceCheckUtils]: 21: Hoare triple {4846#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))))} ~cond := #in~cond; {4846#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))))} is VALID [2018-11-18 21:09:58,610 INFO L273 TraceCheckUtils]: 22: Hoare triple {4846#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))))} assume !(0bv32 == ~cond); {4846#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))))} is VALID [2018-11-18 21:09:58,611 INFO L273 TraceCheckUtils]: 23: Hoare triple {4846#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))))} assume true; {4846#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))))} is VALID [2018-11-18 21:09:58,612 INFO L268 TraceCheckUtils]: 24: Hoare quadruple {4846#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))))} {4833#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))} #89#return; {4833#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:58,613 INFO L273 TraceCheckUtils]: 25: Hoare triple {4833#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))} havoc #t~mem5;havoc #t~mem4;havoc #t~short6; {4833#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:58,614 INFO L273 TraceCheckUtils]: 26: Hoare triple {4833#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {4816#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:58,615 INFO L273 TraceCheckUtils]: 27: Hoare triple {4816#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {4816#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:09:58,616 INFO L273 TraceCheckUtils]: 28: Hoare triple {4816#(and (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {4871#|main_#t~short6|} is VALID [2018-11-18 21:09:58,616 INFO L273 TraceCheckUtils]: 29: Hoare triple {4871#|main_#t~short6|} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := 0bv32 == #t~mem5; {4776#false} is VALID [2018-11-18 21:09:58,617 INFO L256 TraceCheckUtils]: 30: Hoare triple {4776#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {4776#false} is VALID [2018-11-18 21:09:58,617 INFO L273 TraceCheckUtils]: 31: Hoare triple {4776#false} ~cond := #in~cond; {4776#false} is VALID [2018-11-18 21:09:58,617 INFO L273 TraceCheckUtils]: 32: Hoare triple {4776#false} assume 0bv32 == ~cond; {4776#false} is VALID [2018-11-18 21:09:58,617 INFO L273 TraceCheckUtils]: 33: Hoare triple {4776#false} assume !false; {4776#false} is VALID [2018-11-18 21:09:58,621 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:09:58,621 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 21:10:00,943 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 23 [2018-11-18 21:10:00,951 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 27 [2018-11-18 21:10:01,042 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 8 [2018-11-18 21:10:01,044 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-18 21:10:03,111 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (= (bvadd |main_~#volArray~0.offset| (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32))) [2018-11-18 21:10:03,119 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:03,120 INFO L303 Elim1Store]: Index analysis took 2072 ms [2018-11-18 21:10:03,121 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 17 [2018-11-18 21:10:03,124 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-18 21:10:03,174 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 3 xjuncts. [2018-11-18 21:10:03,226 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 3 xjuncts. [2018-11-18 21:10:03,303 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 4 dim-0 vars, and 3 xjuncts. [2018-11-18 21:10:03,303 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:30, output treesize:63 [2018-11-18 21:10:03,359 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-18 21:10:03,598 WARN L180 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 29 DAG size of output: 12 [2018-11-18 21:10:03,718 INFO L273 TraceCheckUtils]: 33: Hoare triple {4776#false} assume !false; {4776#false} is VALID [2018-11-18 21:10:03,718 INFO L273 TraceCheckUtils]: 32: Hoare triple {4776#false} assume 0bv32 == ~cond; {4776#false} is VALID [2018-11-18 21:10:03,718 INFO L273 TraceCheckUtils]: 31: Hoare triple {4776#false} ~cond := #in~cond; {4776#false} is VALID [2018-11-18 21:10:03,719 INFO L256 TraceCheckUtils]: 30: Hoare triple {4776#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {4776#false} is VALID [2018-11-18 21:10:03,719 INFO L273 TraceCheckUtils]: 29: Hoare triple {4871#|main_#t~short6|} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := 0bv32 == #t~mem5; {4776#false} is VALID [2018-11-18 21:10:03,721 INFO L273 TraceCheckUtils]: 28: Hoare triple {4902#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {4871#|main_#t~short6|} is VALID [2018-11-18 21:10:03,722 INFO L273 TraceCheckUtils]: 27: Hoare triple {4902#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume true; {4902#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is VALID [2018-11-18 21:10:05,746 INFO L273 TraceCheckUtils]: 26: Hoare triple {4909#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {4902#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is UNKNOWN [2018-11-18 21:10:05,749 INFO L273 TraceCheckUtils]: 25: Hoare triple {4909#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} havoc #t~mem5;havoc #t~mem4;havoc #t~short6; {4909#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:10:05,750 INFO L268 TraceCheckUtils]: 24: Hoare quadruple {4775#true} {4909#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} #89#return; {4909#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:10:05,750 INFO L273 TraceCheckUtils]: 23: Hoare triple {4775#true} assume true; {4775#true} is VALID [2018-11-18 21:10:05,750 INFO L273 TraceCheckUtils]: 22: Hoare triple {4775#true} assume !(0bv32 == ~cond); {4775#true} is VALID [2018-11-18 21:10:05,750 INFO L273 TraceCheckUtils]: 21: Hoare triple {4775#true} ~cond := #in~cond; {4775#true} is VALID [2018-11-18 21:10:05,750 INFO L256 TraceCheckUtils]: 20: Hoare triple {4909#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {4775#true} is VALID [2018-11-18 21:10:05,751 INFO L273 TraceCheckUtils]: 19: Hoare triple {4909#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} assume #t~short6; {4909#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:10:05,752 INFO L273 TraceCheckUtils]: 18: Hoare triple {4909#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {4909#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:10:05,752 INFO L273 TraceCheckUtils]: 17: Hoare triple {4909#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} assume true; {4909#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:10:05,753 INFO L273 TraceCheckUtils]: 16: Hoare triple {4940#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} ~i~0 := 0bv32; {4909#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:10:05,753 INFO L273 TraceCheckUtils]: 15: Hoare triple {4940#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {4940#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:10:05,753 INFO L273 TraceCheckUtils]: 14: Hoare triple {4940#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume true; {4940#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:10:05,754 INFO L273 TraceCheckUtils]: 13: Hoare triple {4940#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {4940#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:10:05,795 INFO L273 TraceCheckUtils]: 12: Hoare triple {4953#(forall ((main_~CCCELVOL1~0 (_ BitVec 32))) (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} assume ~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL1~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 1bv32))), 4bv32); {4940#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-18 21:10:05,835 INFO L273 TraceCheckUtils]: 11: Hoare triple {4957#(or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((v_prenex_3 (_ BitVec 32))) (bvsge v_prenex_3 main_~MINVAL~0)))} assume ~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL2~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 2bv32))), 4bv32); {4953#(forall ((main_~CCCELVOL1~0 (_ BitVec 32))) (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) main_~CCCELVOL1~0) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-18 21:10:05,855 INFO L273 TraceCheckUtils]: 10: Hoare triple {4961#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_prenex_3 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL3~0 main_~MINVAL~0)) (bvsge v_prenex_3 main_~MINVAL~0))) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 3bv32))), 4bv32); {4957#(or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((v_prenex_3 (_ BitVec 32))) (bvsge v_prenex_3 main_~MINVAL~0)))} is VALID [2018-11-18 21:10:05,855 INFO L273 TraceCheckUtils]: 9: Hoare triple {4961#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_prenex_3 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL3~0 main_~MINVAL~0)) (bvsge v_prenex_3 main_~MINVAL~0))) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {4961#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_prenex_3 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL3~0 main_~MINVAL~0)) (bvsge v_prenex_3 main_~MINVAL~0))) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)))} is VALID [2018-11-18 21:10:05,856 INFO L273 TraceCheckUtils]: 8: Hoare triple {4961#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_prenex_3 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL3~0 main_~MINVAL~0)) (bvsge v_prenex_3 main_~MINVAL~0))) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)))} assume true; {4961#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_prenex_3 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL3~0 main_~MINVAL~0)) (bvsge v_prenex_3 main_~MINVAL~0))) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)))} is VALID [2018-11-18 21:10:05,856 INFO L273 TraceCheckUtils]: 7: Hoare triple {4775#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {4961#(or (forall ((main_~MINVAL~0 (_ BitVec 32)) (v_prenex_3 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL2~0 main_~MINVAL~0)) (not (bvsge main_~CCCELVOL3~0 main_~MINVAL~0)) (bvsge v_prenex_3 main_~MINVAL~0))) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)))} is VALID [2018-11-18 21:10:05,856 INFO L273 TraceCheckUtils]: 6: Hoare triple {4775#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {4775#true} is VALID [2018-11-18 21:10:05,857 INFO L273 TraceCheckUtils]: 5: Hoare triple {4775#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {4775#true} is VALID [2018-11-18 21:10:05,857 INFO L256 TraceCheckUtils]: 4: Hoare triple {4775#true} call #t~ret7 := main(); {4775#true} is VALID [2018-11-18 21:10:05,857 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {4775#true} {4775#true} #85#return; {4775#true} is VALID [2018-11-18 21:10:05,857 INFO L273 TraceCheckUtils]: 2: Hoare triple {4775#true} assume true; {4775#true} is VALID [2018-11-18 21:10:05,857 INFO L273 TraceCheckUtils]: 1: Hoare triple {4775#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {4775#true} is VALID [2018-11-18 21:10:05,857 INFO L256 TraceCheckUtils]: 0: Hoare triple {4775#true} call ULTIMATE.init(); {4775#true} is VALID [2018-11-18 21:10:05,860 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:10:05,862 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 21:10:05,863 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 16 [2018-11-18 21:10:05,863 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 34 [2018-11-18 21:10:05,863 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:10:05,864 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 16 states. [2018-11-18 21:10:08,207 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 57 edges. 56 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2018-11-18 21:10:08,207 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-11-18 21:10:08,208 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-11-18 21:10:08,208 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=191, Unknown=0, NotChecked=0, Total=240 [2018-11-18 21:10:08,208 INFO L87 Difference]: Start difference. First operand 142 states and 173 transitions. Second operand 16 states. [2018-11-18 21:10:16,788 WARN L180 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 32 DAG size of output: 31 [2018-11-18 21:10:17,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:10:17,973 INFO L93 Difference]: Finished difference Result 239 states and 290 transitions. [2018-11-18 21:10:17,973 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-11-18 21:10:17,973 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 34 [2018-11-18 21:10:17,973 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:10:17,973 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2018-11-18 21:10:17,976 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 169 transitions. [2018-11-18 21:10:17,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2018-11-18 21:10:17,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 169 transitions. [2018-11-18 21:10:17,979 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 26 states and 169 transitions. [2018-11-18 21:10:23,234 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 169 edges. 167 inductive. 0 not inductive. 2 times theorem prover too weak to decide inductivity. [2018-11-18 21:10:23,241 INFO L225 Difference]: With dead ends: 239 [2018-11-18 21:10:23,241 INFO L226 Difference]: Without dead ends: 222 [2018-11-18 21:10:23,242 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 51 SyntacticMatches, 2 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 264 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=296, Invalid=1036, Unknown=0, NotChecked=0, Total=1332 [2018-11-18 21:10:23,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 222 states. [2018-11-18 21:10:23,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 222 to 149. [2018-11-18 21:10:23,526 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:10:23,526 INFO L82 GeneralOperation]: Start isEquivalent. First operand 222 states. Second operand 149 states. [2018-11-18 21:10:23,526 INFO L74 IsIncluded]: Start isIncluded. First operand 222 states. Second operand 149 states. [2018-11-18 21:10:23,526 INFO L87 Difference]: Start difference. First operand 222 states. Second operand 149 states. [2018-11-18 21:10:23,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:10:23,533 INFO L93 Difference]: Finished difference Result 222 states and 270 transitions. [2018-11-18 21:10:23,534 INFO L276 IsEmpty]: Start isEmpty. Operand 222 states and 270 transitions. [2018-11-18 21:10:23,535 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:10:23,535 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:10:23,535 INFO L74 IsIncluded]: Start isIncluded. First operand 149 states. Second operand 222 states. [2018-11-18 21:10:23,535 INFO L87 Difference]: Start difference. First operand 149 states. Second operand 222 states. [2018-11-18 21:10:23,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:10:23,542 INFO L93 Difference]: Finished difference Result 222 states and 270 transitions. [2018-11-18 21:10:23,542 INFO L276 IsEmpty]: Start isEmpty. Operand 222 states and 270 transitions. [2018-11-18 21:10:23,543 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:10:23,543 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:10:23,543 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:10:23,543 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:10:23,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-11-18 21:10:23,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 181 transitions. [2018-11-18 21:10:23,547 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 181 transitions. Word has length 34 [2018-11-18 21:10:23,547 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:10:23,547 INFO L480 AbstractCegarLoop]: Abstraction has 149 states and 181 transitions. [2018-11-18 21:10:23,547 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-11-18 21:10:23,547 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 181 transitions. [2018-11-18 21:10:23,548 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-11-18 21:10:23,548 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:10:23,548 INFO L375 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:10:23,549 INFO L423 AbstractCegarLoop]: === Iteration 11 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:10:23,549 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:10:23,549 INFO L82 PathProgramCache]: Analyzing trace with hash -1150030816, now seen corresponding path program 2 times [2018-11-18 21:10:23,549 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:10:23,550 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:10:23,579 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-18 21:10:23,990 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 21:10:23,990 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 21:10:24,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:10:24,064 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:10:24,140 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-18 21:10:24,146 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-18 21:10:24,149 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:10:24,152 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:10:24,176 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:10:24,176 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:34, output treesize:30 [2018-11-18 21:10:24,244 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 24 [2018-11-18 21:10:24,253 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,255 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,256 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 52 [2018-11-18 21:10:24,259 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:10:24,272 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:10:24,302 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:10:24,302 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:47, output treesize:43 [2018-11-18 21:10:24,400 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 34 [2018-11-18 21:10:24,414 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,416 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,419 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,421 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,422 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 4 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 101 [2018-11-18 21:10:24,430 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:10:24,451 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:10:24,489 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:10:24,489 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:59, output treesize:55 [2018-11-18 21:10:24,691 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 44 [2018-11-18 21:10:24,712 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,714 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,716 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,717 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,720 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,722 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,725 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,727 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 7 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 155 [2018-11-18 21:10:24,730 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:10:24,761 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:10:24,803 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:10:24,803 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:69, output treesize:65 [2018-11-18 21:10:24,943 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 54 [2018-11-18 21:10:24,960 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,965 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,968 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,971 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,975 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,977 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,980 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,984 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,986 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,989 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,993 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:24,994 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 11 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 54 treesize of output 223 [2018-11-18 21:10:24,998 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:10:25,040 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:10:25,092 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:10:25,092 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:81, output treesize:77 [2018-11-18 21:10:25,244 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 77 treesize of output 64 [2018-11-18 21:10:25,265 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,269 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,272 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,274 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,277 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,281 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,284 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,287 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,291 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,294 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,297 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,301 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,305 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,308 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,312 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,316 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,318 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 16 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 64 treesize of output 305 [2018-11-18 21:10:25,332 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:10:25,391 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:10:25,447 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:10:25,448 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:93, output treesize:89 [2018-11-18 21:10:25,882 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 89 treesize of output 74 [2018-11-18 21:10:25,898 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,900 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,902 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,904 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,906 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,908 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,910 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,912 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,914 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,916 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,918 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,920 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,922 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,924 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,926 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,928 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,930 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,932 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,934 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,936 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,938 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,942 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:25,946 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 22 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 74 treesize of output 401 [2018-11-18 21:10:25,951 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:10:26,055 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:10:26,134 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:10:26,135 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:104, output treesize:100 [2018-11-18 21:10:26,349 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 105 treesize of output 88 [2018-11-18 21:10:26,374 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,378 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,382 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,386 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,390 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,395 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,399 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,403 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,408 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,411 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,414 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,418 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,423 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,427 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,430 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,432 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,436 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,442 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,446 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,450 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,455 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,458 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,461 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,465 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,469 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,472 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,476 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,478 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,483 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,485 INFO L303 Elim1Store]: Index analysis took 124 ms [2018-11-18 21:10:26,487 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 29 disjoint index pairs (out of 21 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 88 treesize of output 515 [2018-11-18 21:10:26,491 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:10:26,620 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:10:26,710 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:10:26,711 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:120, output treesize:116 [2018-11-18 21:10:26,946 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 86 treesize of output 67 [2018-11-18 21:10:26,968 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,973 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,978 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,984 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,989 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:26,995 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,001 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,007 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,013 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,018 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,024 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,028 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,033 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,037 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,042 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,045 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,053 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,059 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,065 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,070 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,075 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,081 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,086 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,091 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,097 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,102 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,111 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,116 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,121 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,126 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,137 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,143 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,149 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,154 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,161 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,167 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,174 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:10:27,174 INFO L303 Elim1Store]: Index analysis took 219 ms [2018-11-18 21:10:27,176 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 37 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 67 treesize of output 370 [2018-11-18 21:10:27,181 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:10:27,327 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:10:27,378 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:10:27,379 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:96, output treesize:92 [2018-11-18 21:10:28,129 INFO L256 TraceCheckUtils]: 0: Hoare triple {5978#true} call ULTIMATE.init(); {5978#true} is VALID [2018-11-18 21:10:28,129 INFO L273 TraceCheckUtils]: 1: Hoare triple {5978#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {5978#true} is VALID [2018-11-18 21:10:28,129 INFO L273 TraceCheckUtils]: 2: Hoare triple {5978#true} assume true; {5978#true} is VALID [2018-11-18 21:10:28,129 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {5978#true} {5978#true} #85#return; {5978#true} is VALID [2018-11-18 21:10:28,130 INFO L256 TraceCheckUtils]: 4: Hoare triple {5978#true} call #t~ret7 := main(); {5978#true} is VALID [2018-11-18 21:10:28,130 INFO L273 TraceCheckUtils]: 5: Hoare triple {5978#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {5978#true} is VALID [2018-11-18 21:10:28,130 INFO L273 TraceCheckUtils]: 6: Hoare triple {5978#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {6001#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-18 21:10:28,131 INFO L273 TraceCheckUtils]: 7: Hoare triple {6001#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {6005#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:10:28,131 INFO L273 TraceCheckUtils]: 8: Hoare triple {6005#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {6005#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:10:28,132 INFO L273 TraceCheckUtils]: 9: Hoare triple {6005#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {6005#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:10:28,135 INFO L273 TraceCheckUtils]: 10: Hoare triple {6005#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 3bv32))), 4bv32); {6015#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) main_~CCCELVOL3~0) (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:10:28,139 INFO L273 TraceCheckUtils]: 11: Hoare triple {6015#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) main_~CCCELVOL3~0) (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv3 32) main_~CCCELVOL2~0) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 2bv32))), 4bv32); {6019#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) main_~CCCELVOL3~0) (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:10:28,144 INFO L273 TraceCheckUtils]: 12: Hoare triple {6019#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) main_~CCCELVOL3~0) (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 1bv32))), 4bv32); {6023#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) main_~CCCELVOL3~0) (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)))) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:10:28,148 INFO L273 TraceCheckUtils]: 13: Hoare triple {6023#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) main_~CCCELVOL3~0) (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)))) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {6027#(and (= (_ bv7 32) main_~CCCELVOL3~0) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-18 21:10:28,152 INFO L273 TraceCheckUtils]: 14: Hoare triple {6027#(and (= (_ bv7 32) main_~CCCELVOL3~0) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume true; {6027#(and (= (_ bv7 32) main_~CCCELVOL3~0) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-18 21:10:28,170 INFO L273 TraceCheckUtils]: 15: Hoare triple {6027#(and (= (_ bv7 32) main_~CCCELVOL3~0) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {6027#(and (= (_ bv7 32) main_~CCCELVOL3~0) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-18 21:10:28,175 INFO L273 TraceCheckUtils]: 16: Hoare triple {6027#(and (= (_ bv7 32) main_~CCCELVOL3~0) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 3bv32))), 4bv32); {6037#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) main_~CCCELVOL3~0) (= (_ bv7 32) main_~CCCELVOL3~0) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-18 21:10:28,182 INFO L273 TraceCheckUtils]: 17: Hoare triple {6037#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) main_~CCCELVOL3~0) (= (_ bv7 32) main_~CCCELVOL3~0) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 2bv32))), 4bv32); {6041#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) main_~CCCELVOL3~0) (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-18 21:10:28,192 INFO L273 TraceCheckUtils]: 18: Hoare triple {6041#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) main_~CCCELVOL3~0) (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 1bv32))), 4bv32); {6045#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) main_~CCCELVOL3~0) (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)))) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-18 21:10:28,201 INFO L273 TraceCheckUtils]: 19: Hoare triple {6045#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) main_~CCCELVOL3~0) (= (_ bv7 32) main_~CCCELVOL3~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)))) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {6049#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967264 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967268 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967260 32))) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-18 21:10:28,203 INFO L273 TraceCheckUtils]: 20: Hoare triple {6049#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967264 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967268 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967260 32))) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume true; {6049#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967264 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967268 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967260 32))) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-18 21:10:28,209 INFO L273 TraceCheckUtils]: 21: Hoare triple {6049#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967264 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967268 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967260 32))) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {6049#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967264 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967268 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967260 32))) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-18 21:10:28,218 INFO L273 TraceCheckUtils]: 22: Hoare triple {6049#(and (= (_ bv7 32) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967264 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (bvsge main_~CCCELVOL3~0 main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) main_~CCCELVOL3~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967268 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967260 32))) main_~CCCELVOL3~0) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 3bv32))), 4bv32); {6059#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967260 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967264 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967268 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-18 21:10:28,227 INFO L273 TraceCheckUtils]: 23: Hoare triple {6059#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967260 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967264 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967268 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 2bv32))), 4bv32); {6063#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967260 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967264 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967268 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32)))))} is VALID [2018-11-18 21:10:28,239 INFO L273 TraceCheckUtils]: 24: Hoare triple {6063#(and (bvsge (_ bv7 32) main_~MINVAL~0) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967260 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967264 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967268 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32)))))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 1bv32))), 4bv32); {6067#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (bvsge (_ bv7 32) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:10:28,242 INFO L273 TraceCheckUtils]: 25: Hoare triple {6067#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (bvsge (_ bv7 32) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {6067#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (bvsge (_ bv7 32) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:10:28,244 INFO L273 TraceCheckUtils]: 26: Hoare triple {6067#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (bvsge (_ bv7 32) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume true; {6067#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (bvsge (_ bv7 32) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:10:28,261 INFO L273 TraceCheckUtils]: 27: Hoare triple {6067#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (bvsge (_ bv7 32) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {6067#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (bvsge (_ bv7 32) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:10:28,263 INFO L273 TraceCheckUtils]: 28: Hoare triple {6067#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (bvsge (_ bv7 32) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} ~i~0 := 0bv32; {6080#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))) (_ bv4294967289 32)) (_ bv0 32)) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (bvsge (_ bv7 32) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:10:28,265 INFO L273 TraceCheckUtils]: 29: Hoare triple {6080#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))) (_ bv4294967289 32)) (_ bv0 32)) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (bvsge (_ bv7 32) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume true; {6080#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))) (_ bv4294967289 32)) (_ bv0 32)) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (bvsge (_ bv7 32) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:10:28,268 INFO L273 TraceCheckUtils]: 30: Hoare triple {6080#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))) (_ bv4294967289 32)) (_ bv0 32)) (not (bvsge (_ bv3 32) main_~MINVAL~0)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (bvsge (_ bv7 32) main_~MINVAL~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967289 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv32 32)))) (= (_ bv7 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {6087#|main_#t~short6|} is VALID [2018-11-18 21:10:28,269 INFO L273 TraceCheckUtils]: 31: Hoare triple {6087#|main_#t~short6|} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := 0bv32 == #t~mem5; {5979#false} is VALID [2018-11-18 21:10:28,269 INFO L256 TraceCheckUtils]: 32: Hoare triple {5979#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {5979#false} is VALID [2018-11-18 21:10:28,269 INFO L273 TraceCheckUtils]: 33: Hoare triple {5979#false} ~cond := #in~cond; {5979#false} is VALID [2018-11-18 21:10:28,269 INFO L273 TraceCheckUtils]: 34: Hoare triple {5979#false} assume 0bv32 == ~cond; {5979#false} is VALID [2018-11-18 21:10:28,270 INFO L273 TraceCheckUtils]: 35: Hoare triple {5979#false} assume !false; {5979#false} is VALID [2018-11-18 21:10:28,281 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:10:28,282 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 21:10:29,929 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 78 treesize of output 76 [2018-11-18 21:10:29,941 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 76 treesize of output 80 [2018-11-18 21:10:29,955 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:29,961 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 80 treesize of output 96 [2018-11-18 21:10:29,982 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:29,982 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:29,982 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:29,994 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 83 treesize of output 125 [2018-11-18 21:10:30,013 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,013 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,014 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,014 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,014 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,015 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,036 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 86 treesize of output 164 [2018-11-18 21:10:30,070 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,070 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,071 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,071 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,071 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,072 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,072 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,073 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,074 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,074 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,104 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 10 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 89 treesize of output 218 [2018-11-18 21:10:30,135 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,135 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,136 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,136 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,137 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,137 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,137 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,138 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,138 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,139 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,140 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,140 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,141 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,142 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,142 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,181 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 15 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 92 treesize of output 285 [2018-11-18 21:10:30,219 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,219 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,220 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,220 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,220 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,221 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,221 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,222 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,222 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,223 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,224 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,224 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,225 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,226 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,226 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,227 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,228 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,228 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,229 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,230 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,230 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,293 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 21 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 95 treesize of output 365 [2018-11-18 21:10:30,387 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,388 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,388 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,391 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,391 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,392 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,393 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,393 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,394 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,394 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,395 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,395 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,395 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,412 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,414 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,414 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,415 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,415 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,416 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,416 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,416 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,417 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,417 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,418 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,419 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,420 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,420 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,421 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,485 INFO L303 Elim1Store]: Index analysis took 112 ms [2018-11-18 21:10:30,488 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 28 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 98 treesize of output 458 [2018-11-18 21:10:30,669 WARN L180 SmtUtils]: Spent 125.00 ms on a formula simplification that was a NOOP. DAG size: 55 [2018-11-18 21:10:30,697 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,697 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,698 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,698 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,699 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,699 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,700 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,700 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,701 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,702 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,702 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,703 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,704 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,704 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,705 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,706 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,706 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,707 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,708 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,708 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,709 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,710 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,710 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,711 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,712 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,712 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,713 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,714 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,715 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,720 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 29 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 94 treesize of output 367 [2018-11-18 21:10:30,724 INFO L267 ElimStorePlain]: Start of recursive call 11: End of recursive call: and 1 xjuncts. [2018-11-18 21:10:30,761 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,761 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,762 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,763 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,774 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,775 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:30,775 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:32,909 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (= |main_~#volArray~0.offset| (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) [2018-11-18 21:10:34,974 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (= |main_~#volArray~0.offset| (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv12 32))) [2018-11-18 21:10:37,094 WARN L669 Elim1Store]: solver failed to check if following equality is implied: (= |main_~#volArray~0.offset| (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) [2018-11-18 21:10:37,096 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:37,097 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:37,098 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:37,098 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:37,099 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:37,100 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:37,100 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:37,101 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:37,104 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:37,105 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:37,106 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:37,106 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:37,106 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:37,107 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:37,107 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:37,108 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:37,108 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:37,109 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:37,110 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:37,110 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:37,111 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:37,149 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:10:37,214 INFO L303 Elim1Store]: Index analysis took 6479 ms [2018-11-18 21:10:37,274 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 9 select indices, 9 select index equivalence classes, 29 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 5 case distinctions, treesize of input 93 treesize of output 452 [2018-11-18 21:10:37,287 INFO L267 ElimStorePlain]: Start of recursive call 12: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 21:10:37,662 INFO L267 ElimStorePlain]: Start of recursive call 10: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 4 xjuncts. [2018-11-18 21:10:37,877 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 21:10:38,020 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 21:10:38,138 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 21:10:38,246 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 21:10:38,334 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 21:10:38,416 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 21:10:38,493 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 21:10:38,574 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 21:10:38,673 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 3 dim-0 vars, and 2 xjuncts. [2018-11-18 21:10:38,673 INFO L202 ElimStorePlain]: Needed 12 recursive calls to eliminate 3 variables, input treesize:86, output treesize:114 [2018-11-18 21:10:38,687 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-18 21:10:39,061 WARN L180 SmtUtils]: Spent 127.00 ms on a formula simplification that was a NOOP. DAG size: 41 [2018-11-18 21:10:39,164 INFO L273 TraceCheckUtils]: 35: Hoare triple {5979#false} assume !false; {5979#false} is VALID [2018-11-18 21:10:39,164 INFO L273 TraceCheckUtils]: 34: Hoare triple {5979#false} assume 0bv32 == ~cond; {5979#false} is VALID [2018-11-18 21:10:39,164 INFO L273 TraceCheckUtils]: 33: Hoare triple {5979#false} ~cond := #in~cond; {5979#false} is VALID [2018-11-18 21:10:39,165 INFO L256 TraceCheckUtils]: 32: Hoare triple {5979#false} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {5979#false} is VALID [2018-11-18 21:10:39,165 INFO L273 TraceCheckUtils]: 31: Hoare triple {6087#|main_#t~short6|} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := 0bv32 == #t~mem5; {5979#false} is VALID [2018-11-18 21:10:39,167 INFO L273 TraceCheckUtils]: 30: Hoare triple {6118#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {6087#|main_#t~short6|} is VALID [2018-11-18 21:10:39,167 INFO L273 TraceCheckUtils]: 29: Hoare triple {6118#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume true; {6118#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is VALID [2018-11-18 21:10:39,169 INFO L273 TraceCheckUtils]: 28: Hoare triple {6125#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} ~i~0 := 0bv32; {6118#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is VALID [2018-11-18 21:10:39,169 INFO L273 TraceCheckUtils]: 27: Hoare triple {6125#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {6125#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:10:39,170 INFO L273 TraceCheckUtils]: 26: Hoare triple {6125#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume true; {6125#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:10:39,170 INFO L273 TraceCheckUtils]: 25: Hoare triple {6125#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {6125#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:10:39,203 INFO L273 TraceCheckUtils]: 24: Hoare triple {6138#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 1bv32))), 4bv32); {6125#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:10:39,249 INFO L273 TraceCheckUtils]: 23: Hoare triple {6142#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 2bv32))), 4bv32); {6138#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:10:39,296 INFO L273 TraceCheckUtils]: 22: Hoare triple {6146#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 3bv32))), 4bv32); {6142#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:10:39,297 INFO L273 TraceCheckUtils]: 21: Hoare triple {6146#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {6146#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:10:39,297 INFO L273 TraceCheckUtils]: 20: Hoare triple {6146#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume true; {6146#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:10:39,316 INFO L273 TraceCheckUtils]: 19: Hoare triple {6156#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {6146#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:10:39,355 INFO L273 TraceCheckUtils]: 18: Hoare triple {6160#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 1bv32))), 4bv32); {6156#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:10:39,410 INFO L273 TraceCheckUtils]: 17: Hoare triple {6164#(bvsge (select (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 2bv32))), 4bv32); {6160#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:10:39,445 INFO L273 TraceCheckUtils]: 16: Hoare triple {6168#(bvsge (select (store (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 3bv32))), 4bv32); {6164#(bvsge (select (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:10:39,446 INFO L273 TraceCheckUtils]: 15: Hoare triple {6168#(bvsge (select (store (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {6168#(bvsge (select (store (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:10:39,447 INFO L273 TraceCheckUtils]: 14: Hoare triple {6168#(bvsge (select (store (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume true; {6168#(bvsge (select (store (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:10:39,495 INFO L273 TraceCheckUtils]: 13: Hoare triple {6178#(bvsge (select (store (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv12 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv16 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv20 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {6168#(bvsge (select (store (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:10:39,537 INFO L273 TraceCheckUtils]: 12: Hoare triple {6182#(bvsge (select (store (store (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv12 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv16 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv20 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 1bv32))), 4bv32); {6178#(bvsge (select (store (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv12 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv16 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv20 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:10:39,596 INFO L273 TraceCheckUtils]: 11: Hoare triple {6186#(or (bvsge (select (store (store (store (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv12 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv16 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv20 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 2bv32))), 4bv32); {6182#(bvsge (select (store (store (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv12 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv16 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv20 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-18 21:10:39,665 INFO L273 TraceCheckUtils]: 10: Hoare triple {6190#(and (or (= (_ bv0 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967284 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL3~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (bvsge (_ bv0 32) main_~MINVAL~0)))) (or (= (_ bv0 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967292 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967288 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((v_prenex_6 (_ BitVec 32)) (v_arrayElimCell_29 (_ BitVec 32))) (or (bvsge v_arrayElimCell_29 v_prenex_6) (bvsge main_~CCCELVOL2~0 v_prenex_6) (not (bvsge main_~CCCELVOL3~0 v_prenex_6)))) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv16 32)) (_ bv0 32)) (= (_ bv4294967276 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967284 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv8 32) (bvmul (_ bv12 32) main_~i~0))))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 3bv32))), 4bv32); {6186#(or (bvsge (select (store (store (store (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv12 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv16 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv20 32)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0))} is VALID [2018-11-18 21:10:39,667 INFO L273 TraceCheckUtils]: 9: Hoare triple {6190#(and (or (= (_ bv0 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967284 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL3~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (bvsge (_ bv0 32) main_~MINVAL~0)))) (or (= (_ bv0 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967292 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967288 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((v_prenex_6 (_ BitVec 32)) (v_arrayElimCell_29 (_ BitVec 32))) (or (bvsge v_arrayElimCell_29 v_prenex_6) (bvsge main_~CCCELVOL2~0 v_prenex_6) (not (bvsge main_~CCCELVOL3~0 v_prenex_6)))) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv16 32)) (_ bv0 32)) (= (_ bv4294967276 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967284 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv8 32) (bvmul (_ bv12 32) main_~i~0))))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {6190#(and (or (= (_ bv0 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967284 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL3~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (bvsge (_ bv0 32) main_~MINVAL~0)))) (or (= (_ bv0 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967292 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967288 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((v_prenex_6 (_ BitVec 32)) (v_arrayElimCell_29 (_ BitVec 32))) (or (bvsge v_arrayElimCell_29 v_prenex_6) (bvsge main_~CCCELVOL2~0 v_prenex_6) (not (bvsge main_~CCCELVOL3~0 v_prenex_6)))) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv16 32)) (_ bv0 32)) (= (_ bv4294967276 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967284 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv8 32) (bvmul (_ bv12 32) main_~i~0))))} is VALID [2018-11-18 21:10:39,667 INFO L273 TraceCheckUtils]: 8: Hoare triple {6190#(and (or (= (_ bv0 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967284 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL3~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (bvsge (_ bv0 32) main_~MINVAL~0)))) (or (= (_ bv0 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967292 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967288 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((v_prenex_6 (_ BitVec 32)) (v_arrayElimCell_29 (_ BitVec 32))) (or (bvsge v_arrayElimCell_29 v_prenex_6) (bvsge main_~CCCELVOL2~0 v_prenex_6) (not (bvsge main_~CCCELVOL3~0 v_prenex_6)))) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv16 32)) (_ bv0 32)) (= (_ bv4294967276 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967284 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv8 32) (bvmul (_ bv12 32) main_~i~0))))} assume true; {6190#(and (or (= (_ bv0 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967284 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL3~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (bvsge (_ bv0 32) main_~MINVAL~0)))) (or (= (_ bv0 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967292 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967288 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((v_prenex_6 (_ BitVec 32)) (v_arrayElimCell_29 (_ BitVec 32))) (or (bvsge v_arrayElimCell_29 v_prenex_6) (bvsge main_~CCCELVOL2~0 v_prenex_6) (not (bvsge main_~CCCELVOL3~0 v_prenex_6)))) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv16 32)) (_ bv0 32)) (= (_ bv4294967276 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967284 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv8 32) (bvmul (_ bv12 32) main_~i~0))))} is VALID [2018-11-18 21:10:39,668 INFO L273 TraceCheckUtils]: 7: Hoare triple {5978#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {6190#(and (or (= (_ bv0 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967284 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((main_~MINVAL~0 (_ BitVec 32))) (or (not (bvsge main_~CCCELVOL3~0 main_~MINVAL~0)) (bvsge main_~CCCELVOL2~0 main_~MINVAL~0) (bvsge (_ bv0 32) main_~MINVAL~0)))) (or (= (_ bv0 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967292 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967288 32) (bvmul (_ bv12 32) main_~i~0)) (forall ((v_prenex_6 (_ BitVec 32)) (v_arrayElimCell_29 (_ BitVec 32))) (or (bvsge v_arrayElimCell_29 v_prenex_6) (bvsge main_~CCCELVOL2~0 v_prenex_6) (not (bvsge main_~CCCELVOL3~0 v_prenex_6)))) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv16 32)) (_ bv0 32)) (= (_ bv4294967276 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967284 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv8 32) (bvmul (_ bv12 32) main_~i~0))))} is VALID [2018-11-18 21:10:39,669 INFO L273 TraceCheckUtils]: 6: Hoare triple {5978#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {5978#true} is VALID [2018-11-18 21:10:39,669 INFO L273 TraceCheckUtils]: 5: Hoare triple {5978#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {5978#true} is VALID [2018-11-18 21:10:39,669 INFO L256 TraceCheckUtils]: 4: Hoare triple {5978#true} call #t~ret7 := main(); {5978#true} is VALID [2018-11-18 21:10:39,670 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {5978#true} {5978#true} #85#return; {5978#true} is VALID [2018-11-18 21:10:39,670 INFO L273 TraceCheckUtils]: 2: Hoare triple {5978#true} assume true; {5978#true} is VALID [2018-11-18 21:10:39,670 INFO L273 TraceCheckUtils]: 1: Hoare triple {5978#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {5978#true} is VALID [2018-11-18 21:10:39,670 INFO L256 TraceCheckUtils]: 0: Hoare triple {5978#true} call ULTIMATE.init(); {5978#true} is VALID [2018-11-18 21:10:39,677 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:10:39,679 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 21:10:39,680 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 16] total 30 [2018-11-18 21:10:39,680 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 36 [2018-11-18 21:10:39,680 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:10:39,681 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 30 states. [2018-11-18 21:10:40,866 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 61 edges. 61 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:10:40,866 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-11-18 21:10:40,867 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-11-18 21:10:40,867 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=193, Invalid=677, Unknown=0, NotChecked=0, Total=870 [2018-11-18 21:10:40,867 INFO L87 Difference]: Start difference. First operand 149 states and 181 transitions. Second operand 30 states. [2018-11-18 21:10:45,887 WARN L180 SmtUtils]: Spent 541.00 ms on a formula simplification. DAG size of input: 84 DAG size of output: 52 [2018-11-18 21:10:51,026 WARN L180 SmtUtils]: Spent 1.04 s on a formula simplification. DAG size of input: 115 DAG size of output: 59 [2018-11-18 21:10:52,177 WARN L180 SmtUtils]: Spent 304.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 40 [2018-11-18 21:10:56,262 WARN L180 SmtUtils]: Spent 1.03 s on a formula simplification. DAG size of input: 116 DAG size of output: 60 [2018-11-18 21:10:57,546 WARN L180 SmtUtils]: Spent 292.00 ms on a formula simplification. DAG size of input: 73 DAG size of output: 41 [2018-11-18 21:11:00,688 WARN L180 SmtUtils]: Spent 298.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 38 [2018-11-18 21:11:04,397 WARN L180 SmtUtils]: Spent 362.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 53 [2018-11-18 21:11:05,272 WARN L180 SmtUtils]: Spent 214.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 55 [2018-11-18 21:11:06,743 WARN L180 SmtUtils]: Spent 400.00 ms on a formula simplification. DAG size of input: 74 DAG size of output: 55 [2018-11-18 21:11:08,269 WARN L180 SmtUtils]: Spent 296.00 ms on a formula simplification. DAG size of input: 95 DAG size of output: 61 [2018-11-18 21:11:11,185 WARN L180 SmtUtils]: Spent 367.00 ms on a formula simplification. DAG size of input: 117 DAG size of output: 75 [2018-11-18 21:11:11,912 WARN L180 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 37 DAG size of output: 30 [2018-11-18 21:11:16,593 WARN L180 SmtUtils]: Spent 232.00 ms on a formula simplification. DAG size of input: 112 DAG size of output: 67 [2018-11-18 21:11:18,629 WARN L180 SmtUtils]: Spent 614.00 ms on a formula simplification. DAG size of input: 85 DAG size of output: 53 [2018-11-18 21:11:19,432 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 31 DAG size of output: 28 [2018-11-18 21:11:20,370 WARN L180 SmtUtils]: Spent 184.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 52 [2018-11-18 21:11:20,768 WARN L180 SmtUtils]: Spent 235.00 ms on a formula simplification. DAG size of input: 113 DAG size of output: 68 [2018-11-18 21:11:25,508 WARN L180 SmtUtils]: Spent 297.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 39 [2018-11-18 21:11:28,265 WARN L180 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 38 DAG size of output: 31 [2018-11-18 21:11:29,864 WARN L180 SmtUtils]: Spent 211.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 58 [2018-11-18 21:11:30,292 WARN L180 SmtUtils]: Spent 185.00 ms on a formula simplification. DAG size of input: 73 DAG size of output: 59 [2018-11-18 21:11:32,116 WARN L180 SmtUtils]: Spent 198.00 ms on a formula simplification. DAG size of input: 83 DAG size of output: 61 [2018-11-18 21:11:32,674 WARN L180 SmtUtils]: Spent 232.00 ms on a formula simplification. DAG size of input: 84 DAG size of output: 62 [2018-11-18 21:11:34,764 WARN L180 SmtUtils]: Spent 312.00 ms on a formula simplification. DAG size of input: 96 DAG size of output: 62 [2018-11-18 21:11:36,277 WARN L180 SmtUtils]: Spent 332.00 ms on a formula simplification. DAG size of input: 118 DAG size of output: 76 [2018-11-18 21:11:37,267 WARN L180 SmtUtils]: Spent 356.00 ms on a formula simplification. DAG size of input: 97 DAG size of output: 69 [2018-11-18 21:11:37,917 WARN L180 SmtUtils]: Spent 296.00 ms on a formula simplification. DAG size of input: 98 DAG size of output: 70 [2018-11-18 21:11:39,150 WARN L180 SmtUtils]: Spent 221.00 ms on a formula simplification. DAG size of input: 74 DAG size of output: 66 [2018-11-18 21:11:39,718 WARN L180 SmtUtils]: Spent 243.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 67 [2018-11-18 21:11:41,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:11:41,986 INFO L93 Difference]: Finished difference Result 388 states and 492 transitions. [2018-11-18 21:11:41,986 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-11-18 21:11:41,986 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 36 [2018-11-18 21:11:41,986 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:11:41,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-11-18 21:11:41,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 292 transitions. [2018-11-18 21:11:41,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-11-18 21:11:41,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 292 transitions. [2018-11-18 21:11:42,000 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 53 states and 292 transitions. [2018-11-18 21:11:46,141 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 292 edges. 292 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:11:46,152 INFO L225 Difference]: With dead ends: 388 [2018-11-18 21:11:46,153 INFO L226 Difference]: Without dead ends: 371 [2018-11-18 21:11:46,155 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 119 GetRequests, 43 SyntacticMatches, 0 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1717 ImplicationChecksByTransitivity, 22.6s TimeCoverageRelationStatistics Valid=1276, Invalid=4730, Unknown=0, NotChecked=0, Total=6006 [2018-11-18 21:11:46,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 371 states. [2018-11-18 21:11:46,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 371 to 215. [2018-11-18 21:11:46,824 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-18 21:11:46,824 INFO L82 GeneralOperation]: Start isEquivalent. First operand 371 states. Second operand 215 states. [2018-11-18 21:11:46,824 INFO L74 IsIncluded]: Start isIncluded. First operand 371 states. Second operand 215 states. [2018-11-18 21:11:46,825 INFO L87 Difference]: Start difference. First operand 371 states. Second operand 215 states. [2018-11-18 21:11:46,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:11:46,842 INFO L93 Difference]: Finished difference Result 371 states and 471 transitions. [2018-11-18 21:11:46,842 INFO L276 IsEmpty]: Start isEmpty. Operand 371 states and 471 transitions. [2018-11-18 21:11:46,848 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:11:46,848 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:11:46,848 INFO L74 IsIncluded]: Start isIncluded. First operand 215 states. Second operand 371 states. [2018-11-18 21:11:46,848 INFO L87 Difference]: Start difference. First operand 215 states. Second operand 371 states. [2018-11-18 21:11:46,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:11:46,865 INFO L93 Difference]: Finished difference Result 371 states and 471 transitions. [2018-11-18 21:11:46,865 INFO L276 IsEmpty]: Start isEmpty. Operand 371 states and 471 transitions. [2018-11-18 21:11:46,868 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 21:11:46,868 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-18 21:11:46,868 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-18 21:11:46,868 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-18 21:11:46,869 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 215 states. [2018-11-18 21:11:46,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 215 states to 215 states and 269 transitions. [2018-11-18 21:11:46,875 INFO L78 Accepts]: Start accepts. Automaton has 215 states and 269 transitions. Word has length 36 [2018-11-18 21:11:46,875 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 21:11:46,875 INFO L480 AbstractCegarLoop]: Abstraction has 215 states and 269 transitions. [2018-11-18 21:11:46,875 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-11-18 21:11:46,875 INFO L276 IsEmpty]: Start isEmpty. Operand 215 states and 269 transitions. [2018-11-18 21:11:46,876 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-11-18 21:11:46,876 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 21:11:46,876 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 21:11:46,878 INFO L423 AbstractCegarLoop]: === Iteration 12 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 21:11:46,878 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 21:11:46,878 INFO L82 PathProgramCache]: Analyzing trace with hash 1455393884, now seen corresponding path program 2 times [2018-11-18 21:11:46,878 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-18 21:11:46,879 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-18 21:11:46,951 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 21:11:47,427 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 21:11:47,427 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 21:11:47,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 21:11:47,482 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 21:11:47,531 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-18 21:11:47,535 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-18 21:11:47,537 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:11:47,541 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:11:47,562 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:11:47,562 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:25, output treesize:21 [2018-11-18 21:11:47,644 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 24 [2018-11-18 21:11:47,654 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:11:47,655 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 39 [2018-11-18 21:11:47,657 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:11:47,669 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:11:47,688 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:11:47,688 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:37, output treesize:33 [2018-11-18 21:11:47,845 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 34 [2018-11-18 21:11:47,857 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:11:47,861 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:11:47,863 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:11:47,870 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 79 [2018-11-18 21:11:47,877 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:11:47,916 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:11:47,959 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:11:47,959 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:47, output treesize:31 [2018-11-18 21:11:47,982 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-18 21:11:48,003 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 34 [2018-11-18 21:11:48,014 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:11:48,015 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:11:48,017 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:11:48,018 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 79 [2018-11-18 21:11:48,021 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:11:48,038 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:11:48,061 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:11:48,062 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:47, output treesize:43 [2018-11-18 21:11:48,132 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 32 [2018-11-18 21:11:48,142 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:11:48,144 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:11:48,146 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:11:48,148 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:11:48,150 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:11:48,152 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 21:11:48,153 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 85 [2018-11-18 21:11:48,155 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 21:11:48,176 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:11:48,198 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-18 21:11:48,198 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:44, output treesize:40 [2018-11-18 21:11:48,564 INFO L256 TraceCheckUtils]: 0: Hoare triple {7834#true} call ULTIMATE.init(); {7834#true} is VALID [2018-11-18 21:11:48,565 INFO L273 TraceCheckUtils]: 1: Hoare triple {7834#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {7834#true} is VALID [2018-11-18 21:11:48,565 INFO L273 TraceCheckUtils]: 2: Hoare triple {7834#true} assume true; {7834#true} is VALID [2018-11-18 21:11:48,565 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {7834#true} {7834#true} #85#return; {7834#true} is VALID [2018-11-18 21:11:48,565 INFO L256 TraceCheckUtils]: 4: Hoare triple {7834#true} call #t~ret7 := main(); {7834#true} is VALID [2018-11-18 21:11:48,566 INFO L273 TraceCheckUtils]: 5: Hoare triple {7834#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {7834#true} is VALID [2018-11-18 21:11:48,566 INFO L273 TraceCheckUtils]: 6: Hoare triple {7834#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {7857#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-18 21:11:48,567 INFO L273 TraceCheckUtils]: 7: Hoare triple {7857#(= |main_~#volArray~0.offset| (_ bv0 32))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {7861#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:11:48,567 INFO L273 TraceCheckUtils]: 8: Hoare triple {7861#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {7861#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:11:48,568 INFO L273 TraceCheckUtils]: 9: Hoare triple {7861#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {7861#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:11:48,568 INFO L273 TraceCheckUtils]: 10: Hoare triple {7861#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 3bv32))), 4bv32); {7861#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:11:48,570 INFO L273 TraceCheckUtils]: 11: Hoare triple {7861#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 2bv32))), 4bv32); {7874#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:11:48,574 INFO L273 TraceCheckUtils]: 12: Hoare triple {7874#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 1bv32))), 4bv32); {7878#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:11:48,577 INFO L273 TraceCheckUtils]: 13: Hoare triple {7878#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {7882#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-18 21:11:48,580 INFO L273 TraceCheckUtils]: 14: Hoare triple {7882#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume true; {7882#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-18 21:11:48,599 INFO L273 TraceCheckUtils]: 15: Hoare triple {7882#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {7882#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-18 21:11:48,604 INFO L273 TraceCheckUtils]: 16: Hoare triple {7882#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 3bv32))), 4bv32); {7882#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-18 21:11:48,609 INFO L273 TraceCheckUtils]: 17: Hoare triple {7882#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 2bv32))), 4bv32); {7895#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-18 21:11:48,614 INFO L273 TraceCheckUtils]: 18: Hoare triple {7895#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 1bv32))), 4bv32); {7899#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:11:48,615 INFO L273 TraceCheckUtils]: 19: Hoare triple {7899#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {7899#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:11:48,615 INFO L273 TraceCheckUtils]: 20: Hoare triple {7899#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume true; {7899#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:11:48,616 INFO L273 TraceCheckUtils]: 21: Hoare triple {7899#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {7899#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:11:48,618 INFO L273 TraceCheckUtils]: 22: Hoare triple {7899#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} ~i~0 := 0bv32; {7912#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:11:48,619 INFO L273 TraceCheckUtils]: 23: Hoare triple {7912#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume true; {7912#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:11:48,620 INFO L273 TraceCheckUtils]: 24: Hoare triple {7912#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {7912#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:11:48,621 INFO L273 TraceCheckUtils]: 25: Hoare triple {7912#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume #t~short6; {7912#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:11:48,623 INFO L256 TraceCheckUtils]: 26: Hoare triple {7912#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {7925#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv16 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv4 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv20 32)))))} is VALID [2018-11-18 21:11:48,624 INFO L273 TraceCheckUtils]: 27: Hoare triple {7925#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv16 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv4 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv20 32)))))} ~cond := #in~cond; {7925#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv16 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv4 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv20 32)))))} is VALID [2018-11-18 21:11:48,625 INFO L273 TraceCheckUtils]: 28: Hoare triple {7925#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv16 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv4 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv20 32)))))} assume !(0bv32 == ~cond); {7925#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv16 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv4 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv20 32)))))} is VALID [2018-11-18 21:11:48,625 INFO L273 TraceCheckUtils]: 29: Hoare triple {7925#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv16 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv4 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv20 32)))))} assume true; {7925#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv16 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv4 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv20 32)))))} is VALID [2018-11-18 21:11:48,626 INFO L268 TraceCheckUtils]: 30: Hoare quadruple {7925#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv16 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv4 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv20 32)))))} {7912#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #89#return; {7912#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:11:48,627 INFO L273 TraceCheckUtils]: 31: Hoare triple {7912#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} havoc #t~mem5;havoc #t~mem4;havoc #t~short6; {7912#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:11:48,629 INFO L273 TraceCheckUtils]: 32: Hoare triple {7912#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {7944#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:11:48,632 INFO L273 TraceCheckUtils]: 33: Hoare triple {7944#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume true; {7944#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:11:48,635 INFO L273 TraceCheckUtils]: 34: Hoare triple {7944#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {7944#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-18 21:11:48,636 INFO L273 TraceCheckUtils]: 35: Hoare triple {7944#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := 0bv32 == #t~mem5; {7954#|main_#t~short6|} is VALID [2018-11-18 21:11:48,637 INFO L256 TraceCheckUtils]: 36: Hoare triple {7954#|main_#t~short6|} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {7958#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-18 21:11:48,638 INFO L273 TraceCheckUtils]: 37: Hoare triple {7958#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {7962#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-18 21:11:48,638 INFO L273 TraceCheckUtils]: 38: Hoare triple {7962#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 == ~cond; {7835#false} is VALID [2018-11-18 21:11:48,638 INFO L273 TraceCheckUtils]: 39: Hoare triple {7835#false} assume !false; {7835#false} is VALID [2018-11-18 21:11:48,646 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:11:48,646 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 21:11:49,267 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 46 [2018-11-18 21:11:49,274 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 50 [2018-11-18 21:11:49,282 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:49,284 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 50 treesize of output 66 [2018-11-18 21:11:49,296 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:49,297 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:49,297 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:49,304 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 93 [2018-11-18 21:11:49,318 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:49,319 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:49,319 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:49,320 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:49,320 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:49,320 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:49,329 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 134 [2018-11-18 21:11:49,473 WARN L180 SmtUtils]: Spent 120.00 ms on a formula simplification. DAG size of input: 33 DAG size of output: 31 [2018-11-18 21:11:49,489 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:49,489 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:49,490 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:49,490 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:49,491 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:49,491 INFO L682 Elim1Store]: detected equality via solver [2018-11-18 21:11:49,520 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 10 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 51 treesize of output 123 [2018-11-18 21:11:49,532 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 2 xjuncts. [2018-11-18 21:11:49,609 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 21:11:49,663 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 21:11:49,716 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 21:11:49,759 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 21:11:49,802 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 21:11:49,847 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 2 xjuncts. [2018-11-18 21:11:49,848 INFO L202 ElimStorePlain]: Needed 7 recursive calls to eliminate 3 variables, input treesize:48, output treesize:82 [2018-11-18 21:11:49,859 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-18 21:11:49,978 INFO L273 TraceCheckUtils]: 39: Hoare triple {7835#false} assume !false; {7835#false} is VALID [2018-11-18 21:11:49,979 INFO L273 TraceCheckUtils]: 38: Hoare triple {7972#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} assume 0bv32 == ~cond; {7835#false} is VALID [2018-11-18 21:11:49,979 INFO L273 TraceCheckUtils]: 37: Hoare triple {7976#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} ~cond := #in~cond; {7972#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} is VALID [2018-11-18 21:11:49,980 INFO L256 TraceCheckUtils]: 36: Hoare triple {7954#|main_#t~short6|} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {7976#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-18 21:11:49,980 INFO L273 TraceCheckUtils]: 35: Hoare triple {7983#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume !#t~short6;call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := 0bv32 == #t~mem5; {7954#|main_#t~short6|} is VALID [2018-11-18 21:11:49,981 INFO L273 TraceCheckUtils]: 34: Hoare triple {7983#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {7983#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-18 21:11:49,981 INFO L273 TraceCheckUtils]: 33: Hoare triple {7983#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume true; {7983#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-18 21:11:50,245 INFO L273 TraceCheckUtils]: 32: Hoare triple {7993#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} #t~post3 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post3);havoc #t~post3; {7983#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-18 21:11:50,246 INFO L273 TraceCheckUtils]: 31: Hoare triple {7993#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} havoc #t~mem5;havoc #t~mem4;havoc #t~short6; {7993#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-18 21:11:50,247 INFO L268 TraceCheckUtils]: 30: Hoare quadruple {7834#true} {7993#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} #89#return; {7993#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-18 21:11:50,247 INFO L273 TraceCheckUtils]: 29: Hoare triple {7834#true} assume true; {7834#true} is VALID [2018-11-18 21:11:50,247 INFO L273 TraceCheckUtils]: 28: Hoare triple {7834#true} assume !(0bv32 == ~cond); {7834#true} is VALID [2018-11-18 21:11:50,247 INFO L273 TraceCheckUtils]: 27: Hoare triple {7834#true} ~cond := #in~cond; {7834#true} is VALID [2018-11-18 21:11:50,247 INFO L256 TraceCheckUtils]: 26: Hoare triple {7993#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} call __VERIFIER_assert((if #t~short6 then 1bv32 else 0bv32)); {7834#true} is VALID [2018-11-18 21:11:50,247 INFO L273 TraceCheckUtils]: 25: Hoare triple {7993#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} assume #t~short6; {7993#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-18 21:11:50,248 INFO L273 TraceCheckUtils]: 24: Hoare triple {7993#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem4 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short6 := ~bvsge32(#t~mem4, ~MINVAL~0); {7993#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-18 21:11:50,249 INFO L273 TraceCheckUtils]: 23: Hoare triple {7993#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} assume true; {7993#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-18 21:11:50,250 INFO L273 TraceCheckUtils]: 22: Hoare triple {8024#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} ~i~0 := 0bv32; {7993#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-18 21:11:50,251 INFO L273 TraceCheckUtils]: 21: Hoare triple {8024#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {8024#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-18 21:11:50,251 INFO L273 TraceCheckUtils]: 20: Hoare triple {8024#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} assume true; {8024#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-18 21:11:50,252 INFO L273 TraceCheckUtils]: 19: Hoare triple {8024#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {8024#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-18 21:11:50,271 INFO L273 TraceCheckUtils]: 18: Hoare triple {8037#(= (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 1bv32))), 4bv32); {8024#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-18 21:11:50,290 INFO L273 TraceCheckUtils]: 17: Hoare triple {8041#(= (_ bv0 32) (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))))} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 2bv32))), 4bv32); {8037#(= (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-18 21:11:50,327 INFO L273 TraceCheckUtils]: 16: Hoare triple {8045#(forall ((main_~CCCELVOL3~0 (_ BitVec 32))) (= (_ bv0 32) (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 3bv32))), 4bv32); {8041#(= (_ bv0 32) (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))))} is VALID [2018-11-18 21:11:50,328 INFO L273 TraceCheckUtils]: 15: Hoare triple {8045#(forall ((main_~CCCELVOL3~0 (_ BitVec 32))) (= (_ bv0 32) (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {8045#(forall ((main_~CCCELVOL3~0 (_ BitVec 32))) (= (_ bv0 32) (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))))} is VALID [2018-11-18 21:11:50,328 INFO L273 TraceCheckUtils]: 14: Hoare triple {8045#(forall ((main_~CCCELVOL3~0 (_ BitVec 32))) (= (_ bv0 32) (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))))} assume true; {8045#(forall ((main_~CCCELVOL3~0 (_ BitVec 32))) (= (_ bv0 32) (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))))} is VALID [2018-11-18 21:11:50,338 INFO L273 TraceCheckUtils]: 13: Hoare triple {8055#(forall ((main_~CCCELVOL3~0 (_ BitVec 32))) (= (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {8045#(forall ((main_~CCCELVOL3~0 (_ BitVec 32))) (= (_ bv0 32) (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))))} is VALID [2018-11-18 21:11:50,360 INFO L273 TraceCheckUtils]: 12: Hoare triple {8059#(forall ((main_~CCCELVOL3~0 (_ BitVec 32))) (= (_ bv0 32) (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))))} assume !~bvsge32(~CCCELVOL1~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 1bv32))), 4bv32); {8055#(forall ((main_~CCCELVOL3~0 (_ BitVec 32))) (= (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-18 21:11:50,380 INFO L273 TraceCheckUtils]: 11: Hoare triple {8063#(or (= (_ bv0 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967292 32) (bvmul (_ bv12 32) main_~i~0)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)))} assume !~bvsge32(~CCCELVOL2~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 2bv32))), 4bv32); {8059#(forall ((main_~CCCELVOL3~0 (_ BitVec 32))) (= (_ bv0 32) (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~CCCELVOL3~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))))} is VALID [2018-11-18 21:11:50,381 INFO L273 TraceCheckUtils]: 10: Hoare triple {8063#(or (= (_ bv0 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967292 32) (bvmul (_ bv12 32) main_~i~0)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)))} assume ~bvsge32(~CCCELVOL3~0, ~MINVAL~0);call write~intINTTYPE4(~CCCELVOL3~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), 3bv32))), 4bv32); {8063#(or (= (_ bv0 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967292 32) (bvmul (_ bv12 32) main_~i~0)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)))} is VALID [2018-11-18 21:11:50,381 INFO L273 TraceCheckUtils]: 9: Hoare triple {8063#(or (= (_ bv0 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967292 32) (bvmul (_ bv12 32) main_~i~0)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {8063#(or (= (_ bv0 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967292 32) (bvmul (_ bv12 32) main_~i~0)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)))} is VALID [2018-11-18 21:11:50,381 INFO L273 TraceCheckUtils]: 8: Hoare triple {8063#(or (= (_ bv0 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967292 32) (bvmul (_ bv12 32) main_~i~0)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)))} assume true; {8063#(or (= (_ bv0 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967292 32) (bvmul (_ bv12 32) main_~i~0)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)))} is VALID [2018-11-18 21:11:50,382 INFO L273 TraceCheckUtils]: 7: Hoare triple {7834#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {8063#(or (= (_ bv0 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4294967292 32) (bvmul (_ bv12 32) main_~i~0)) (= (bvadd (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)))} is VALID [2018-11-18 21:11:50,382 INFO L273 TraceCheckUtils]: 6: Hoare triple {7834#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);havoc ~MINVAL~0;havoc ~i~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0));~CCCELVOL3~0 := 7bv32;~CCCELVOL2~0 := 3bv32;~CCCELVOL1~0 := 1bv32; {7834#true} is VALID [2018-11-18 21:11:50,382 INFO L273 TraceCheckUtils]: 5: Hoare triple {7834#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {7834#true} is VALID [2018-11-18 21:11:50,382 INFO L256 TraceCheckUtils]: 4: Hoare triple {7834#true} call #t~ret7 := main(); {7834#true} is VALID [2018-11-18 21:11:50,382 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {7834#true} {7834#true} #85#return; {7834#true} is VALID [2018-11-18 21:11:50,383 INFO L273 TraceCheckUtils]: 2: Hoare triple {7834#true} assume true; {7834#true} is VALID [2018-11-18 21:11:50,383 INFO L273 TraceCheckUtils]: 1: Hoare triple {7834#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {7834#true} is VALID [2018-11-18 21:11:50,383 INFO L256 TraceCheckUtils]: 0: Hoare triple {7834#true} call ULTIMATE.init(); {7834#true} is VALID [2018-11-18 21:11:50,389 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 2 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 21:11:50,391 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 21:11:50,391 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 14] total 26 [2018-11-18 21:11:50,392 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 40 [2018-11-18 21:11:50,392 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-18 21:11:50,392 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 26 states. [2018-11-18 21:11:50,980 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 73 edges. 73 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-18 21:11:50,980 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-11-18 21:11:50,981 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-11-18 21:11:50,981 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=130, Invalid=520, Unknown=0, NotChecked=0, Total=650 [2018-11-18 21:11:50,981 INFO L87 Difference]: Start difference. First operand 215 states and 269 transitions. Second operand 26 states. [2018-11-18 21:11:57,306 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 26 [2018-11-18 21:11:58,239 WARN L180 SmtUtils]: Spent 193.00 ms on a formula simplification that was a NOOP. DAG size: 31 [2018-11-18 21:11:59,818 WARN L180 SmtUtils]: Spent 167.00 ms on a formula simplification that was a NOOP. DAG size: 25 [2018-11-18 21:12:02,880 WARN L180 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 27 [2018-11-18 21:12:03,192 WARN L180 SmtUtils]: Spent 143.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 50 [2018-11-18 21:12:03,827 WARN L180 SmtUtils]: Spent 152.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 53 [2018-11-18 21:12:21,181 WARN L180 SmtUtils]: Spent 133.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 51 [2018-11-18 21:12:24,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 21:12:24,196 INFO L93 Difference]: Finished difference Result 452 states and 556 transitions. [2018-11-18 21:12:24,197 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-11-18 21:12:24,197 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 40 [2018-11-18 21:12:24,197 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 21:12:24,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2018-11-18 21:12:24,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 246 transitions. [2018-11-18 21:12:24,204 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2018-11-18 21:12:24,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 246 transitions. [2018-11-18 21:12:24,209 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 48 states and 246 transitions.