java -ea -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc ../../../trunk/examples/toolchains/AutomizerCInline_WitnessPrinter.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf -i ../../../trunk/examples/svcomp/array-tiling/nr2_true-unreach-call.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-61f4311 [2018-11-23 10:27:51,357 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 10:27:51,362 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 10:27:51,378 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 10:27:51,379 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 10:27:51,380 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 10:27:51,381 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 10:27:51,383 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 10:27:51,385 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 10:27:51,385 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 10:27:51,386 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 10:27:51,387 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 10:27:51,388 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 10:27:51,389 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 10:27:51,390 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 10:27:51,391 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 10:27:51,392 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 10:27:51,393 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 10:27:51,395 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 10:27:51,397 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 10:27:51,398 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 10:27:51,399 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 10:27:51,402 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 10:27:51,402 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 10:27:51,402 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 10:27:51,403 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 10:27:51,404 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 10:27:51,405 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 10:27:51,406 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 10:27:51,407 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 10:27:51,407 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 10:27:51,408 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 10:27:51,408 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 10:27:51,408 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 10:27:51,409 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 10:27:51,410 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 10:27:51,411 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf [2018-11-23 10:27:51,437 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 10:27:51,437 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 10:27:51,438 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 10:27:51,438 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 10:27:51,439 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 10:27:51,439 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 10:27:51,439 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 10:27:51,440 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 10:27:51,440 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 10:27:51,440 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 10:27:51,440 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 10:27:51,440 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 10:27:51,441 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 10:27:51,443 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 10:27:51,444 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-23 10:27:51,444 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-23 10:27:51,444 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 10:27:51,444 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 10:27:51,444 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 10:27:51,445 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 10:27:51,445 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 10:27:51,445 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 10:27:51,445 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 10:27:51,446 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 10:27:51,447 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 10:27:51,447 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 10:27:51,448 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 10:27:51,448 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 10:27:51,448 INFO L133 SettingsManager]: * Trace refinement strategy=WOLF [2018-11-23 10:27:51,448 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 10:27:51,448 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-11-23 10:27:51,448 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-11-23 10:27:51,449 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-23 10:27:51,494 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 10:27:51,507 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 10:27:51,511 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 10:27:51,513 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 10:27:51,514 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 10:27:51,514 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-tiling/nr2_true-unreach-call.i [2018-11-23 10:27:51,576 INFO L221 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/46d1aee7b/d1a6372739044bff9e8ac1db744e258a/FLAG135874d6e [2018-11-23 10:27:52,022 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 10:27:52,023 INFO L161 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-tiling/nr2_true-unreach-call.i [2018-11-23 10:27:52,030 INFO L355 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/46d1aee7b/d1a6372739044bff9e8ac1db744e258a/FLAG135874d6e [2018-11-23 10:27:52,376 INFO L363 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/46d1aee7b/d1a6372739044bff9e8ac1db744e258a [2018-11-23 10:27:52,388 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 10:27:52,390 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 10:27:52,390 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 10:27:52,391 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 10:27:52,395 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 10:27:52,397 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 10:27:52" (1/1) ... [2018-11-23 10:27:52,400 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@45a45193 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:27:52, skipping insertion in model container [2018-11-23 10:27:52,400 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 10:27:52" (1/1) ... [2018-11-23 10:27:52,411 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 10:27:52,437 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 10:27:52,705 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 10:27:52,711 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 10:27:52,741 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 10:27:52,767 INFO L195 MainTranslator]: Completed translation [2018-11-23 10:27:52,768 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:27:52 WrapperNode [2018-11-23 10:27:52,768 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 10:27:52,769 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 10:27:52,769 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 10:27:52,769 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 10:27:52,779 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:27:52" (1/1) ... [2018-11-23 10:27:52,789 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:27:52" (1/1) ... [2018-11-23 10:27:52,798 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 10:27:52,798 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 10:27:52,798 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 10:27:52,798 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 10:27:52,809 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:27:52" (1/1) ... [2018-11-23 10:27:52,809 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:27:52" (1/1) ... [2018-11-23 10:27:52,812 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:27:52" (1/1) ... [2018-11-23 10:27:52,812 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:27:52" (1/1) ... [2018-11-23 10:27:52,826 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:27:52" (1/1) ... [2018-11-23 10:27:52,834 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:27:52" (1/1) ... [2018-11-23 10:27:52,836 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:27:52" (1/1) ... [2018-11-23 10:27:52,839 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 10:27:52,839 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 10:27:52,840 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 10:27:52,840 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 10:27:52,841 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:27:52" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 10:27:52,974 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-23 10:27:52,974 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-23 10:27:52,974 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-23 10:27:52,974 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE4 [2018-11-23 10:27:52,974 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 10:27:52,974 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 10:27:52,975 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-23 10:27:52,975 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-23 10:27:52,975 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-11-23 10:27:52,975 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-11-23 10:27:52,975 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE4 [2018-11-23 10:27:52,976 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-23 10:27:53,663 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 10:27:53,664 INFO L280 CfgBuilder]: Removed 3 assue(true) statements. [2018-11-23 10:27:53,664 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 10:27:53 BoogieIcfgContainer [2018-11-23 10:27:53,664 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 10:27:53,665 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 10:27:53,666 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 10:27:53,669 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 10:27:53,670 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 10:27:52" (1/3) ... [2018-11-23 10:27:53,671 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@71322c39 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 10:27:53, skipping insertion in model container [2018-11-23 10:27:53,671 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:27:52" (2/3) ... [2018-11-23 10:27:53,671 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@71322c39 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 10:27:53, skipping insertion in model container [2018-11-23 10:27:53,672 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 10:27:53" (3/3) ... [2018-11-23 10:27:53,674 INFO L112 eAbstractionObserver]: Analyzing ICFG nr2_true-unreach-call.i [2018-11-23 10:27:53,684 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 10:27:53,692 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-23 10:27:53,712 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-23 10:27:53,745 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 10:27:53,746 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 10:27:53,746 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 10:27:53,746 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 10:27:53,747 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 10:27:53,747 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 10:27:53,747 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 10:27:53,747 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 10:27:53,747 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 10:27:53,765 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states. [2018-11-23 10:27:53,772 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-11-23 10:27:53,772 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:27:53,773 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:27:53,775 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:27:53,782 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:27:53,782 INFO L82 PathProgramCache]: Analyzing trace with hash 1453831941, now seen corresponding path program 1 times [2018-11-23 10:27:53,786 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:27:53,786 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:27:53,804 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:27:53,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:27:53,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:27:53,887 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:27:54,425 INFO L256 TraceCheckUtils]: 0: Hoare triple {34#true} call ULTIMATE.init(); {34#true} is VALID [2018-11-23 10:27:54,429 INFO L273 TraceCheckUtils]: 1: Hoare triple {34#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {34#true} is VALID [2018-11-23 10:27:54,430 INFO L273 TraceCheckUtils]: 2: Hoare triple {34#true} assume true; {34#true} is VALID [2018-11-23 10:27:54,431 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {34#true} {34#true} #83#return; {34#true} is VALID [2018-11-23 10:27:54,431 INFO L256 TraceCheckUtils]: 4: Hoare triple {34#true} call #t~ret8 := main(); {34#true} is VALID [2018-11-23 10:27:54,431 INFO L273 TraceCheckUtils]: 5: Hoare triple {34#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {34#true} is VALID [2018-11-23 10:27:54,432 INFO L273 TraceCheckUtils]: 6: Hoare triple {34#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {34#true} is VALID [2018-11-23 10:27:54,432 INFO L273 TraceCheckUtils]: 7: Hoare triple {34#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 2bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 2bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {34#true} is VALID [2018-11-23 10:27:54,433 INFO L273 TraceCheckUtils]: 8: Hoare triple {34#true} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {34#true} is VALID [2018-11-23 10:27:54,433 INFO L273 TraceCheckUtils]: 9: Hoare triple {34#true} ~i~0 := 0bv32; {34#true} is VALID [2018-11-23 10:27:54,434 INFO L273 TraceCheckUtils]: 10: Hoare triple {34#true} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {34#true} is VALID [2018-11-23 10:27:54,434 INFO L273 TraceCheckUtils]: 11: Hoare triple {34#true} assume #t~short7; {72#|main_#t~short7|} is VALID [2018-11-23 10:27:54,436 INFO L256 TraceCheckUtils]: 12: Hoare triple {72#|main_#t~short7|} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {76#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:27:54,436 INFO L273 TraceCheckUtils]: 13: Hoare triple {76#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {80#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:27:54,438 INFO L273 TraceCheckUtils]: 14: Hoare triple {80#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 == ~cond; {35#false} is VALID [2018-11-23 10:27:54,439 INFO L273 TraceCheckUtils]: 15: Hoare triple {35#false} assume !false; {35#false} is VALID [2018-11-23 10:27:54,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:27:54,442 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:27:54,447 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:27:54,447 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 10:27:54,452 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 16 [2018-11-23 10:27:54,455 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:27:54,459 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states. [2018-11-23 10:27:54,547 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 16 edges. 16 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:27:54,547 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 10:27:54,555 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 10:27:54,556 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 10:27:54,558 INFO L87 Difference]: Start difference. First operand 31 states. Second operand 5 states. [2018-11-23 10:27:55,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:27:55,270 INFO L93 Difference]: Finished difference Result 60 states and 81 transitions. [2018-11-23 10:27:55,270 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 10:27:55,270 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 16 [2018-11-23 10:27:55,271 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:27:55,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-23 10:27:55,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 81 transitions. [2018-11-23 10:27:55,283 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-23 10:27:55,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 81 transitions. [2018-11-23 10:27:55,288 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states and 81 transitions. [2018-11-23 10:27:55,854 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 81 edges. 81 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:27:55,868 INFO L225 Difference]: With dead ends: 60 [2018-11-23 10:27:55,868 INFO L226 Difference]: Without dead ends: 31 [2018-11-23 10:27:55,872 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 10:27:55,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2018-11-23 10:27:56,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 30. [2018-11-23 10:27:56,058 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:27:56,058 INFO L82 GeneralOperation]: Start isEquivalent. First operand 31 states. Second operand 30 states. [2018-11-23 10:27:56,059 INFO L74 IsIncluded]: Start isIncluded. First operand 31 states. Second operand 30 states. [2018-11-23 10:27:56,059 INFO L87 Difference]: Start difference. First operand 31 states. Second operand 30 states. [2018-11-23 10:27:56,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:27:56,064 INFO L93 Difference]: Finished difference Result 31 states and 35 transitions. [2018-11-23 10:27:56,065 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 35 transitions. [2018-11-23 10:27:56,065 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:27:56,066 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:27:56,066 INFO L74 IsIncluded]: Start isIncluded. First operand 30 states. Second operand 31 states. [2018-11-23 10:27:56,066 INFO L87 Difference]: Start difference. First operand 30 states. Second operand 31 states. [2018-11-23 10:27:56,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:27:56,071 INFO L93 Difference]: Finished difference Result 31 states and 35 transitions. [2018-11-23 10:27:56,071 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 35 transitions. [2018-11-23 10:27:56,072 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:27:56,072 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:27:56,072 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:27:56,072 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:27:56,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-11-23 10:27:56,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 34 transitions. [2018-11-23 10:27:56,078 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 34 transitions. Word has length 16 [2018-11-23 10:27:56,078 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:27:56,078 INFO L480 AbstractCegarLoop]: Abstraction has 30 states and 34 transitions. [2018-11-23 10:27:56,079 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 10:27:56,079 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 34 transitions. [2018-11-23 10:27:56,080 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-11-23 10:27:56,080 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:27:56,080 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:27:56,080 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:27:56,081 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:27:56,081 INFO L82 PathProgramCache]: Analyzing trace with hash 1455678983, now seen corresponding path program 1 times [2018-11-23 10:27:56,082 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:27:56,082 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:27:56,110 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:27:56,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:27:56,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:27:56,205 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:27:56,447 INFO L256 TraceCheckUtils]: 0: Hoare triple {267#true} call ULTIMATE.init(); {267#true} is VALID [2018-11-23 10:27:56,447 INFO L273 TraceCheckUtils]: 1: Hoare triple {267#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {267#true} is VALID [2018-11-23 10:27:56,448 INFO L273 TraceCheckUtils]: 2: Hoare triple {267#true} assume true; {267#true} is VALID [2018-11-23 10:27:56,448 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {267#true} {267#true} #83#return; {267#true} is VALID [2018-11-23 10:27:56,449 INFO L256 TraceCheckUtils]: 4: Hoare triple {267#true} call #t~ret8 := main(); {267#true} is VALID [2018-11-23 10:27:56,449 INFO L273 TraceCheckUtils]: 5: Hoare triple {267#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {267#true} is VALID [2018-11-23 10:27:56,466 INFO L273 TraceCheckUtils]: 6: Hoare triple {267#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {290#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} is VALID [2018-11-23 10:27:56,480 INFO L273 TraceCheckUtils]: 7: Hoare triple {290#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 2bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 2bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {294#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:27:56,495 INFO L273 TraceCheckUtils]: 8: Hoare triple {294#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {268#false} is VALID [2018-11-23 10:27:56,496 INFO L273 TraceCheckUtils]: 9: Hoare triple {268#false} ~i~0 := 0bv32; {268#false} is VALID [2018-11-23 10:27:56,496 INFO L273 TraceCheckUtils]: 10: Hoare triple {268#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {268#false} is VALID [2018-11-23 10:27:56,497 INFO L273 TraceCheckUtils]: 11: Hoare triple {268#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {268#false} is VALID [2018-11-23 10:27:56,497 INFO L256 TraceCheckUtils]: 12: Hoare triple {268#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {268#false} is VALID [2018-11-23 10:27:56,497 INFO L273 TraceCheckUtils]: 13: Hoare triple {268#false} ~cond := #in~cond; {268#false} is VALID [2018-11-23 10:27:56,498 INFO L273 TraceCheckUtils]: 14: Hoare triple {268#false} assume 0bv32 == ~cond; {268#false} is VALID [2018-11-23 10:27:56,498 INFO L273 TraceCheckUtils]: 15: Hoare triple {268#false} assume !false; {268#false} is VALID [2018-11-23 10:27:56,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:27:56,500 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:27:56,507 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:27:56,507 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 10:27:56,509 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2018-11-23 10:27:56,510 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:27:56,511 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states. [2018-11-23 10:27:56,564 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 16 edges. 16 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:27:56,564 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 10:27:56,565 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 10:27:56,565 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 10:27:56,565 INFO L87 Difference]: Start difference. First operand 30 states and 34 transitions. Second operand 4 states. [2018-11-23 10:27:56,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:27:56,977 INFO L93 Difference]: Finished difference Result 52 states and 60 transitions. [2018-11-23 10:27:56,977 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 10:27:56,978 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2018-11-23 10:27:56,978 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:27:56,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-23 10:27:56,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 50 transitions. [2018-11-23 10:27:56,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-23 10:27:56,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 50 transitions. [2018-11-23 10:27:56,984 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states and 50 transitions. [2018-11-23 10:27:57,207 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 50 edges. 50 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:27:57,210 INFO L225 Difference]: With dead ends: 52 [2018-11-23 10:27:57,210 INFO L226 Difference]: Without dead ends: 35 [2018-11-23 10:27:57,212 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 13 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 10:27:57,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states. [2018-11-23 10:27:57,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 31. [2018-11-23 10:27:57,246 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:27:57,246 INFO L82 GeneralOperation]: Start isEquivalent. First operand 35 states. Second operand 31 states. [2018-11-23 10:27:57,246 INFO L74 IsIncluded]: Start isIncluded. First operand 35 states. Second operand 31 states. [2018-11-23 10:27:57,246 INFO L87 Difference]: Start difference. First operand 35 states. Second operand 31 states. [2018-11-23 10:27:57,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:27:57,250 INFO L93 Difference]: Finished difference Result 35 states and 41 transitions. [2018-11-23 10:27:57,250 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 41 transitions. [2018-11-23 10:27:57,251 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:27:57,251 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:27:57,251 INFO L74 IsIncluded]: Start isIncluded. First operand 31 states. Second operand 35 states. [2018-11-23 10:27:57,251 INFO L87 Difference]: Start difference. First operand 31 states. Second operand 35 states. [2018-11-23 10:27:57,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:27:57,255 INFO L93 Difference]: Finished difference Result 35 states and 41 transitions. [2018-11-23 10:27:57,255 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 41 transitions. [2018-11-23 10:27:57,256 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:27:57,256 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:27:57,256 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:27:57,256 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:27:57,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2018-11-23 10:27:57,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 35 transitions. [2018-11-23 10:27:57,259 INFO L78 Accepts]: Start accepts. Automaton has 31 states and 35 transitions. Word has length 16 [2018-11-23 10:27:57,259 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:27:57,260 INFO L480 AbstractCegarLoop]: Abstraction has 31 states and 35 transitions. [2018-11-23 10:27:57,260 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 10:27:57,260 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 35 transitions. [2018-11-23 10:27:57,261 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-11-23 10:27:57,261 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:27:57,261 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:27:57,261 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:27:57,262 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:27:57,262 INFO L82 PathProgramCache]: Analyzing trace with hash -2089835012, now seen corresponding path program 1 times [2018-11-23 10:27:57,262 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:27:57,263 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:27:57,280 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:27:57,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:27:57,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:27:57,349 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:27:57,445 INFO L256 TraceCheckUtils]: 0: Hoare triple {501#true} call ULTIMATE.init(); {501#true} is VALID [2018-11-23 10:27:57,446 INFO L273 TraceCheckUtils]: 1: Hoare triple {501#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {501#true} is VALID [2018-11-23 10:27:57,447 INFO L273 TraceCheckUtils]: 2: Hoare triple {501#true} assume true; {501#true} is VALID [2018-11-23 10:27:57,447 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {501#true} {501#true} #83#return; {501#true} is VALID [2018-11-23 10:27:57,447 INFO L256 TraceCheckUtils]: 4: Hoare triple {501#true} call #t~ret8 := main(); {501#true} is VALID [2018-11-23 10:27:57,448 INFO L273 TraceCheckUtils]: 5: Hoare triple {501#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {501#true} is VALID [2018-11-23 10:27:57,448 INFO L273 TraceCheckUtils]: 6: Hoare triple {501#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {501#true} is VALID [2018-11-23 10:27:57,449 INFO L273 TraceCheckUtils]: 7: Hoare triple {501#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 2bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 2bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {501#true} is VALID [2018-11-23 10:27:57,449 INFO L273 TraceCheckUtils]: 8: Hoare triple {501#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {530#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:27:57,450 INFO L273 TraceCheckUtils]: 9: Hoare triple {530#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} assume !~bvsge32(~j~0, 1bv32); {502#false} is VALID [2018-11-23 10:27:57,450 INFO L273 TraceCheckUtils]: 10: Hoare triple {502#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {502#false} is VALID [2018-11-23 10:27:57,450 INFO L273 TraceCheckUtils]: 11: Hoare triple {502#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {502#false} is VALID [2018-11-23 10:27:57,451 INFO L273 TraceCheckUtils]: 12: Hoare triple {502#false} ~i~0 := 0bv32; {502#false} is VALID [2018-11-23 10:27:57,451 INFO L273 TraceCheckUtils]: 13: Hoare triple {502#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {502#false} is VALID [2018-11-23 10:27:57,451 INFO L273 TraceCheckUtils]: 14: Hoare triple {502#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {502#false} is VALID [2018-11-23 10:27:57,452 INFO L256 TraceCheckUtils]: 15: Hoare triple {502#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {502#false} is VALID [2018-11-23 10:27:57,452 INFO L273 TraceCheckUtils]: 16: Hoare triple {502#false} ~cond := #in~cond; {502#false} is VALID [2018-11-23 10:27:57,452 INFO L273 TraceCheckUtils]: 17: Hoare triple {502#false} assume 0bv32 == ~cond; {502#false} is VALID [2018-11-23 10:27:57,453 INFO L273 TraceCheckUtils]: 18: Hoare triple {502#false} assume !false; {502#false} is VALID [2018-11-23 10:27:57,454 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:27:57,454 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:27:57,458 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:27:57,458 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 10:27:57,458 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 19 [2018-11-23 10:27:57,458 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:27:57,459 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2018-11-23 10:27:57,512 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 19 edges. 19 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:27:57,512 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 10:27:57,513 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 10:27:57,513 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 10:27:57,514 INFO L87 Difference]: Start difference. First operand 31 states and 35 transitions. Second operand 3 states. [2018-11-23 10:27:57,714 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:27:57,715 INFO L93 Difference]: Finished difference Result 56 states and 66 transitions. [2018-11-23 10:27:57,715 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 10:27:57,715 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 19 [2018-11-23 10:27:57,716 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:27:57,716 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 10:27:57,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 55 transitions. [2018-11-23 10:27:57,719 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 10:27:57,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 55 transitions. [2018-11-23 10:27:57,724 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states and 55 transitions. [2018-11-23 10:27:57,899 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 55 edges. 55 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:27:57,903 INFO L225 Difference]: With dead ends: 56 [2018-11-23 10:27:57,903 INFO L226 Difference]: Without dead ends: 34 [2018-11-23 10:27:57,904 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 17 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 10:27:57,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-11-23 10:27:57,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 32. [2018-11-23 10:27:57,930 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:27:57,930 INFO L82 GeneralOperation]: Start isEquivalent. First operand 34 states. Second operand 32 states. [2018-11-23 10:27:57,931 INFO L74 IsIncluded]: Start isIncluded. First operand 34 states. Second operand 32 states. [2018-11-23 10:27:57,931 INFO L87 Difference]: Start difference. First operand 34 states. Second operand 32 states. [2018-11-23 10:27:57,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:27:57,934 INFO L93 Difference]: Finished difference Result 34 states and 39 transitions. [2018-11-23 10:27:57,934 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 39 transitions. [2018-11-23 10:27:57,935 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:27:57,935 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:27:57,935 INFO L74 IsIncluded]: Start isIncluded. First operand 32 states. Second operand 34 states. [2018-11-23 10:27:57,935 INFO L87 Difference]: Start difference. First operand 32 states. Second operand 34 states. [2018-11-23 10:27:57,938 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:27:57,938 INFO L93 Difference]: Finished difference Result 34 states and 39 transitions. [2018-11-23 10:27:57,939 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 39 transitions. [2018-11-23 10:27:57,939 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:27:57,939 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:27:57,940 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:27:57,940 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:27:57,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32 states. [2018-11-23 10:27:57,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 36 transitions. [2018-11-23 10:27:57,943 INFO L78 Accepts]: Start accepts. Automaton has 32 states and 36 transitions. Word has length 19 [2018-11-23 10:27:57,943 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:27:57,943 INFO L480 AbstractCegarLoop]: Abstraction has 32 states and 36 transitions. [2018-11-23 10:27:57,943 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 10:27:57,943 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 36 transitions. [2018-11-23 10:27:57,944 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-11-23 10:27:57,944 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:27:57,944 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:27:57,945 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:27:57,945 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:27:57,945 INFO L82 PathProgramCache]: Analyzing trace with hash 1382648830, now seen corresponding path program 1 times [2018-11-23 10:27:57,946 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:27:57,946 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:27:57,980 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:27:58,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:27:58,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:27:58,056 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:27:58,269 INFO L256 TraceCheckUtils]: 0: Hoare triple {749#true} call ULTIMATE.init(); {749#true} is VALID [2018-11-23 10:27:58,269 INFO L273 TraceCheckUtils]: 1: Hoare triple {749#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {749#true} is VALID [2018-11-23 10:27:58,270 INFO L273 TraceCheckUtils]: 2: Hoare triple {749#true} assume true; {749#true} is VALID [2018-11-23 10:27:58,270 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {749#true} {749#true} #83#return; {749#true} is VALID [2018-11-23 10:27:58,270 INFO L256 TraceCheckUtils]: 4: Hoare triple {749#true} call #t~ret8 := main(); {749#true} is VALID [2018-11-23 10:27:58,270 INFO L273 TraceCheckUtils]: 5: Hoare triple {749#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {749#true} is VALID [2018-11-23 10:27:58,272 INFO L273 TraceCheckUtils]: 6: Hoare triple {749#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {772#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:27:58,272 INFO L273 TraceCheckUtils]: 7: Hoare triple {772#(= (_ bv2 32) main_~MINVAL~0)} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 2bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 2bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {772#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:27:58,274 INFO L273 TraceCheckUtils]: 8: Hoare triple {772#(= (_ bv2 32) main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {779#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:27:58,275 INFO L273 TraceCheckUtils]: 9: Hoare triple {779#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {779#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:27:58,276 INFO L273 TraceCheckUtils]: 10: Hoare triple {779#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {750#false} is VALID [2018-11-23 10:27:58,276 INFO L273 TraceCheckUtils]: 11: Hoare triple {750#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {750#false} is VALID [2018-11-23 10:27:58,277 INFO L273 TraceCheckUtils]: 12: Hoare triple {750#false} assume !~bvsge32(~j~0, 1bv32); {750#false} is VALID [2018-11-23 10:27:58,277 INFO L273 TraceCheckUtils]: 13: Hoare triple {750#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {750#false} is VALID [2018-11-23 10:27:58,278 INFO L273 TraceCheckUtils]: 14: Hoare triple {750#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {750#false} is VALID [2018-11-23 10:27:58,278 INFO L273 TraceCheckUtils]: 15: Hoare triple {750#false} ~i~0 := 0bv32; {750#false} is VALID [2018-11-23 10:27:58,279 INFO L273 TraceCheckUtils]: 16: Hoare triple {750#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {750#false} is VALID [2018-11-23 10:27:58,279 INFO L273 TraceCheckUtils]: 17: Hoare triple {750#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {750#false} is VALID [2018-11-23 10:27:58,280 INFO L256 TraceCheckUtils]: 18: Hoare triple {750#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {750#false} is VALID [2018-11-23 10:27:58,280 INFO L273 TraceCheckUtils]: 19: Hoare triple {750#false} ~cond := #in~cond; {750#false} is VALID [2018-11-23 10:27:58,280 INFO L273 TraceCheckUtils]: 20: Hoare triple {750#false} assume 0bv32 == ~cond; {750#false} is VALID [2018-11-23 10:27:58,281 INFO L273 TraceCheckUtils]: 21: Hoare triple {750#false} assume !false; {750#false} is VALID [2018-11-23 10:27:58,282 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:27:58,282 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:27:58,285 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:27:58,285 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 10:27:58,286 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 22 [2018-11-23 10:27:58,286 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:27:58,286 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states. [2018-11-23 10:27:58,349 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 22 edges. 22 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:27:58,350 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 10:27:58,350 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 10:27:58,350 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 10:27:58,350 INFO L87 Difference]: Start difference. First operand 32 states and 36 transitions. Second operand 4 states. [2018-11-23 10:27:58,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:27:58,721 INFO L93 Difference]: Finished difference Result 57 states and 66 transitions. [2018-11-23 10:27:58,721 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 10:27:58,722 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 22 [2018-11-23 10:27:58,722 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:27:58,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-23 10:27:58,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 54 transitions. [2018-11-23 10:27:58,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-23 10:27:58,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 54 transitions. [2018-11-23 10:27:58,727 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states and 54 transitions. [2018-11-23 10:27:58,899 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 54 edges. 54 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:27:58,901 INFO L225 Difference]: With dead ends: 57 [2018-11-23 10:27:58,902 INFO L226 Difference]: Without dead ends: 34 [2018-11-23 10:27:58,902 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 19 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 10:27:58,903 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-11-23 10:27:58,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 33. [2018-11-23 10:27:58,935 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:27:58,935 INFO L82 GeneralOperation]: Start isEquivalent. First operand 34 states. Second operand 33 states. [2018-11-23 10:27:58,936 INFO L74 IsIncluded]: Start isIncluded. First operand 34 states. Second operand 33 states. [2018-11-23 10:27:58,936 INFO L87 Difference]: Start difference. First operand 34 states. Second operand 33 states. [2018-11-23 10:27:58,938 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:27:58,938 INFO L93 Difference]: Finished difference Result 34 states and 38 transitions. [2018-11-23 10:27:58,938 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 38 transitions. [2018-11-23 10:27:58,939 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:27:58,939 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:27:58,939 INFO L74 IsIncluded]: Start isIncluded. First operand 33 states. Second operand 34 states. [2018-11-23 10:27:58,939 INFO L87 Difference]: Start difference. First operand 33 states. Second operand 34 states. [2018-11-23 10:27:58,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:27:58,942 INFO L93 Difference]: Finished difference Result 34 states and 38 transitions. [2018-11-23 10:27:58,942 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 38 transitions. [2018-11-23 10:27:58,943 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:27:58,943 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:27:58,943 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:27:58,944 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:27:58,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33 states. [2018-11-23 10:27:58,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 37 transitions. [2018-11-23 10:27:58,946 INFO L78 Accepts]: Start accepts. Automaton has 33 states and 37 transitions. Word has length 22 [2018-11-23 10:27:58,946 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:27:58,946 INFO L480 AbstractCegarLoop]: Abstraction has 33 states and 37 transitions. [2018-11-23 10:27:58,946 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 10:27:58,947 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 37 transitions. [2018-11-23 10:27:58,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-11-23 10:27:58,947 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:27:58,948 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:27:58,948 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:27:58,948 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:27:58,948 INFO L82 PathProgramCache]: Analyzing trace with hash 1124483392, now seen corresponding path program 1 times [2018-11-23 10:27:58,949 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:27:58,949 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:27:58,966 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:27:59,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:27:59,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:27:59,021 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:27:59,070 INFO L256 TraceCheckUtils]: 0: Hoare triple {1010#true} call ULTIMATE.init(); {1010#true} is VALID [2018-11-23 10:27:59,071 INFO L273 TraceCheckUtils]: 1: Hoare triple {1010#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1010#true} is VALID [2018-11-23 10:27:59,071 INFO L273 TraceCheckUtils]: 2: Hoare triple {1010#true} assume true; {1010#true} is VALID [2018-11-23 10:27:59,072 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1010#true} {1010#true} #83#return; {1010#true} is VALID [2018-11-23 10:27:59,072 INFO L256 TraceCheckUtils]: 4: Hoare triple {1010#true} call #t~ret8 := main(); {1010#true} is VALID [2018-11-23 10:27:59,072 INFO L273 TraceCheckUtils]: 5: Hoare triple {1010#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1010#true} is VALID [2018-11-23 10:27:59,073 INFO L273 TraceCheckUtils]: 6: Hoare triple {1010#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1010#true} is VALID [2018-11-23 10:27:59,073 INFO L273 TraceCheckUtils]: 7: Hoare triple {1010#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 2bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 2bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1010#true} is VALID [2018-11-23 10:27:59,075 INFO L273 TraceCheckUtils]: 8: Hoare triple {1010#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {1039#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:27:59,077 INFO L273 TraceCheckUtils]: 9: Hoare triple {1039#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {1039#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:27:59,078 INFO L273 TraceCheckUtils]: 10: Hoare triple {1039#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {1039#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:27:59,080 INFO L273 TraceCheckUtils]: 11: Hoare triple {1039#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1049#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:27:59,083 INFO L273 TraceCheckUtils]: 12: Hoare triple {1049#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} assume !~bvsge32(~j~0, 1bv32); {1011#false} is VALID [2018-11-23 10:27:59,084 INFO L273 TraceCheckUtils]: 13: Hoare triple {1011#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1011#false} is VALID [2018-11-23 10:27:59,084 INFO L273 TraceCheckUtils]: 14: Hoare triple {1011#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {1011#false} is VALID [2018-11-23 10:27:59,084 INFO L273 TraceCheckUtils]: 15: Hoare triple {1011#false} ~i~0 := 0bv32; {1011#false} is VALID [2018-11-23 10:27:59,085 INFO L273 TraceCheckUtils]: 16: Hoare triple {1011#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1011#false} is VALID [2018-11-23 10:27:59,085 INFO L273 TraceCheckUtils]: 17: Hoare triple {1011#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1011#false} is VALID [2018-11-23 10:27:59,085 INFO L256 TraceCheckUtils]: 18: Hoare triple {1011#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1011#false} is VALID [2018-11-23 10:27:59,085 INFO L273 TraceCheckUtils]: 19: Hoare triple {1011#false} ~cond := #in~cond; {1011#false} is VALID [2018-11-23 10:27:59,086 INFO L273 TraceCheckUtils]: 20: Hoare triple {1011#false} assume 0bv32 == ~cond; {1011#false} is VALID [2018-11-23 10:27:59,086 INFO L273 TraceCheckUtils]: 21: Hoare triple {1011#false} assume !false; {1011#false} is VALID [2018-11-23 10:27:59,087 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:27:59,087 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:27:59,186 INFO L273 TraceCheckUtils]: 21: Hoare triple {1011#false} assume !false; {1011#false} is VALID [2018-11-23 10:27:59,187 INFO L273 TraceCheckUtils]: 20: Hoare triple {1011#false} assume 0bv32 == ~cond; {1011#false} is VALID [2018-11-23 10:27:59,187 INFO L273 TraceCheckUtils]: 19: Hoare triple {1011#false} ~cond := #in~cond; {1011#false} is VALID [2018-11-23 10:27:59,188 INFO L256 TraceCheckUtils]: 18: Hoare triple {1011#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1011#false} is VALID [2018-11-23 10:27:59,188 INFO L273 TraceCheckUtils]: 17: Hoare triple {1011#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1011#false} is VALID [2018-11-23 10:27:59,189 INFO L273 TraceCheckUtils]: 16: Hoare triple {1011#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1011#false} is VALID [2018-11-23 10:27:59,189 INFO L273 TraceCheckUtils]: 15: Hoare triple {1011#false} ~i~0 := 0bv32; {1011#false} is VALID [2018-11-23 10:27:59,190 INFO L273 TraceCheckUtils]: 14: Hoare triple {1011#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {1011#false} is VALID [2018-11-23 10:27:59,190 INFO L273 TraceCheckUtils]: 13: Hoare triple {1011#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1011#false} is VALID [2018-11-23 10:27:59,190 INFO L273 TraceCheckUtils]: 12: Hoare triple {1107#(bvsge main_~j~0 (_ bv1 32))} assume !~bvsge32(~j~0, 1bv32); {1011#false} is VALID [2018-11-23 10:27:59,192 INFO L273 TraceCheckUtils]: 11: Hoare triple {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1107#(bvsge main_~j~0 (_ bv1 32))} is VALID [2018-11-23 10:27:59,196 INFO L273 TraceCheckUtils]: 10: Hoare triple {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-23 10:27:59,198 INFO L273 TraceCheckUtils]: 9: Hoare triple {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} assume !!~bvsge32(~j~0, 1bv32); {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-23 10:27:59,198 INFO L273 TraceCheckUtils]: 8: Hoare triple {1010#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-23 10:27:59,199 INFO L273 TraceCheckUtils]: 7: Hoare triple {1010#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 2bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 2bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1010#true} is VALID [2018-11-23 10:27:59,199 INFO L273 TraceCheckUtils]: 6: Hoare triple {1010#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1010#true} is VALID [2018-11-23 10:27:59,199 INFO L273 TraceCheckUtils]: 5: Hoare triple {1010#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1010#true} is VALID [2018-11-23 10:27:59,199 INFO L256 TraceCheckUtils]: 4: Hoare triple {1010#true} call #t~ret8 := main(); {1010#true} is VALID [2018-11-23 10:27:59,200 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1010#true} {1010#true} #83#return; {1010#true} is VALID [2018-11-23 10:27:59,200 INFO L273 TraceCheckUtils]: 2: Hoare triple {1010#true} assume true; {1010#true} is VALID [2018-11-23 10:27:59,200 INFO L273 TraceCheckUtils]: 1: Hoare triple {1010#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1010#true} is VALID [2018-11-23 10:27:59,200 INFO L256 TraceCheckUtils]: 0: Hoare triple {1010#true} call ULTIMATE.init(); {1010#true} is VALID [2018-11-23 10:27:59,201 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:27:59,205 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:27:59,205 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 6 [2018-11-23 10:27:59,205 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 22 [2018-11-23 10:27:59,206 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:27:59,206 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 6 states. [2018-11-23 10:27:59,281 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 27 edges. 27 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:27:59,281 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 10:27:59,282 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 10:27:59,282 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 10:27:59,282 INFO L87 Difference]: Start difference. First operand 33 states and 37 transitions. Second operand 6 states. [2018-11-23 10:27:59,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:27:59,775 INFO L93 Difference]: Finished difference Result 61 states and 71 transitions. [2018-11-23 10:27:59,775 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 10:27:59,775 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 22 [2018-11-23 10:27:59,776 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:27:59,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6 states. [2018-11-23 10:27:59,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 58 transitions. [2018-11-23 10:27:59,778 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6 states. [2018-11-23 10:27:59,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 58 transitions. [2018-11-23 10:27:59,780 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states and 58 transitions. [2018-11-23 10:27:59,990 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 58 edges. 58 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:27:59,992 INFO L225 Difference]: With dead ends: 61 [2018-11-23 10:27:59,992 INFO L226 Difference]: Without dead ends: 37 [2018-11-23 10:27:59,992 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 10:27:59,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2018-11-23 10:28:00,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 35. [2018-11-23 10:28:00,034 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:28:00,034 INFO L82 GeneralOperation]: Start isEquivalent. First operand 37 states. Second operand 35 states. [2018-11-23 10:28:00,034 INFO L74 IsIncluded]: Start isIncluded. First operand 37 states. Second operand 35 states. [2018-11-23 10:28:00,035 INFO L87 Difference]: Start difference. First operand 37 states. Second operand 35 states. [2018-11-23 10:28:00,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:00,036 INFO L93 Difference]: Finished difference Result 37 states and 42 transitions. [2018-11-23 10:28:00,037 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 42 transitions. [2018-11-23 10:28:00,037 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:00,037 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:00,038 INFO L74 IsIncluded]: Start isIncluded. First operand 35 states. Second operand 37 states. [2018-11-23 10:28:00,038 INFO L87 Difference]: Start difference. First operand 35 states. Second operand 37 states. [2018-11-23 10:28:00,040 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:00,040 INFO L93 Difference]: Finished difference Result 37 states and 42 transitions. [2018-11-23 10:28:00,040 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 42 transitions. [2018-11-23 10:28:00,041 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:00,041 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:00,041 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:28:00,041 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:28:00,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35 states. [2018-11-23 10:28:00,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 39 transitions. [2018-11-23 10:28:00,043 INFO L78 Accepts]: Start accepts. Automaton has 35 states and 39 transitions. Word has length 22 [2018-11-23 10:28:00,044 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:28:00,044 INFO L480 AbstractCegarLoop]: Abstraction has 35 states and 39 transitions. [2018-11-23 10:28:00,044 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 10:28:00,044 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 39 transitions. [2018-11-23 10:28:00,045 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-11-23 10:28:00,045 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:00,045 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:00,045 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:00,046 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:00,046 INFO L82 PathProgramCache]: Analyzing trace with hash -1448609222, now seen corresponding path program 1 times [2018-11-23 10:28:00,046 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:00,047 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:00,068 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:28:00,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:00,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:00,168 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:00,339 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 16 [2018-11-23 10:28:00,347 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 15 [2018-11-23 10:28:00,356 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:28:00,362 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:00,383 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:00,384 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:36, output treesize:32 [2018-11-23 10:28:00,542 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-11-23 10:28:00,550 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:00,552 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:00,554 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 31 [2018-11-23 10:28:00,556 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:28:00,567 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:00,580 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:00,581 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:27, output treesize:23 [2018-11-23 10:28:00,716 INFO L256 TraceCheckUtils]: 0: Hoare triple {1353#true} call ULTIMATE.init(); {1353#true} is VALID [2018-11-23 10:28:00,716 INFO L273 TraceCheckUtils]: 1: Hoare triple {1353#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1353#true} is VALID [2018-11-23 10:28:00,717 INFO L273 TraceCheckUtils]: 2: Hoare triple {1353#true} assume true; {1353#true} is VALID [2018-11-23 10:28:00,717 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1353#true} {1353#true} #83#return; {1353#true} is VALID [2018-11-23 10:28:00,717 INFO L256 TraceCheckUtils]: 4: Hoare triple {1353#true} call #t~ret8 := main(); {1353#true} is VALID [2018-11-23 10:28:00,718 INFO L273 TraceCheckUtils]: 5: Hoare triple {1353#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1353#true} is VALID [2018-11-23 10:28:00,734 INFO L273 TraceCheckUtils]: 6: Hoare triple {1353#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1376#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:00,737 INFO L273 TraceCheckUtils]: 7: Hoare triple {1376#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 2bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 2bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1380#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:00,738 INFO L273 TraceCheckUtils]: 8: Hoare triple {1380#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {1384#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:00,739 INFO L273 TraceCheckUtils]: 9: Hoare triple {1384#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {1384#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:00,741 INFO L273 TraceCheckUtils]: 10: Hoare triple {1384#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {1391#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:00,747 INFO L273 TraceCheckUtils]: 11: Hoare triple {1391#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1395#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:00,749 INFO L273 TraceCheckUtils]: 12: Hoare triple {1395#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {1395#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:00,750 INFO L273 TraceCheckUtils]: 13: Hoare triple {1395#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {1402#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:00,754 INFO L273 TraceCheckUtils]: 14: Hoare triple {1402#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1402#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:00,756 INFO L273 TraceCheckUtils]: 15: Hoare triple {1402#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsge32(~j~0, 1bv32); {1402#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:00,759 INFO L273 TraceCheckUtils]: 16: Hoare triple {1402#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1402#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:00,773 INFO L273 TraceCheckUtils]: 17: Hoare triple {1402#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {1402#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:00,774 INFO L273 TraceCheckUtils]: 18: Hoare triple {1402#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 0bv32; {1418#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:00,776 INFO L273 TraceCheckUtils]: 19: Hoare triple {1418#(and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1422#|main_#t~short7|} is VALID [2018-11-23 10:28:00,776 INFO L273 TraceCheckUtils]: 20: Hoare triple {1422#|main_#t~short7|} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1354#false} is VALID [2018-11-23 10:28:00,777 INFO L256 TraceCheckUtils]: 21: Hoare triple {1354#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1354#false} is VALID [2018-11-23 10:28:00,777 INFO L273 TraceCheckUtils]: 22: Hoare triple {1354#false} ~cond := #in~cond; {1354#false} is VALID [2018-11-23 10:28:00,777 INFO L273 TraceCheckUtils]: 23: Hoare triple {1354#false} assume 0bv32 == ~cond; {1354#false} is VALID [2018-11-23 10:28:00,777 INFO L273 TraceCheckUtils]: 24: Hoare triple {1354#false} assume !false; {1354#false} is VALID [2018-11-23 10:28:00,782 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:00,782 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:28:01,022 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 29 [2018-11-23 10:28:01,031 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 33 [2018-11-23 10:28:01,119 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 13 [2018-11-23 10:28:01,121 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-23 10:28:01,149 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 20 [2018-11-23 10:28:01,155 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-23 10:28:01,196 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 5 xjuncts. [2018-11-23 10:28:01,282 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 4 xjuncts. [2018-11-23 10:28:01,355 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 4 xjuncts. [2018-11-23 10:28:01,355 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 2 variables, input treesize:31, output treesize:79 [2018-11-23 10:28:01,373 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:28:01,373 WARN L384 uantifierElimination]: Input elimination task: ∀ [|#memory_int|, |main_~#volArray~0.base|]. (bvsge (select (let ((.cse0 (bvmul (_ bv8 32) main_~i~0))) (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| .cse0) (_ bv0 32))) |main_~#volArray~0.offset|) main_~MINVAL~0) [2018-11-23 10:28:01,374 WARN L385 uantifierElimination]: ElimStorePlain result: ∀ [v_prenex_1, v_arrayElimCell_4]. (let ((.cse3 (bvmul (_ bv8 32) main_~i~0))) (let ((.cse1 (bvsge (_ bv0 32) main_~MINVAL~0)) (.cse2 (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse3) |main_~#volArray~0.offset|)) (.cse0 (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) .cse3)))) (and (or (not .cse0) .cse1) (or .cse2 (bvsge v_prenex_1 main_~MINVAL~0) .cse1) (or (bvsge main_~j~0 main_~MINVAL~0) .cse0) (or .cse2 (bvsge v_arrayElimCell_4 main_~MINVAL~0) .cse0)))) [2018-11-23 10:28:01,596 WARN L180 SmtUtils]: Spent 152.00 ms on a formula simplification. DAG size of input: 31 DAG size of output: 27 [2018-11-23 10:28:01,860 INFO L273 TraceCheckUtils]: 24: Hoare triple {1354#false} assume !false; {1354#false} is VALID [2018-11-23 10:28:01,860 INFO L273 TraceCheckUtils]: 23: Hoare triple {1354#false} assume 0bv32 == ~cond; {1354#false} is VALID [2018-11-23 10:28:01,861 INFO L273 TraceCheckUtils]: 22: Hoare triple {1354#false} ~cond := #in~cond; {1354#false} is VALID [2018-11-23 10:28:01,861 INFO L256 TraceCheckUtils]: 21: Hoare triple {1354#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1354#false} is VALID [2018-11-23 10:28:01,861 INFO L273 TraceCheckUtils]: 20: Hoare triple {1422#|main_#t~short7|} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1354#false} is VALID [2018-11-23 10:28:01,863 INFO L273 TraceCheckUtils]: 19: Hoare triple {1453#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1422#|main_#t~short7|} is VALID [2018-11-23 10:28:01,864 INFO L273 TraceCheckUtils]: 18: Hoare triple {1457#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} ~i~0 := 0bv32; {1453#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is VALID [2018-11-23 10:28:01,865 INFO L273 TraceCheckUtils]: 17: Hoare triple {1457#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {1457#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:28:01,865 INFO L273 TraceCheckUtils]: 16: Hoare triple {1457#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1457#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:28:01,866 INFO L273 TraceCheckUtils]: 15: Hoare triple {1457#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsge32(~j~0, 1bv32); {1457#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:28:01,867 INFO L273 TraceCheckUtils]: 14: Hoare triple {1457#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1457#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:28:02,015 INFO L273 TraceCheckUtils]: 13: Hoare triple {1473#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {1457#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:28:02,016 INFO L273 TraceCheckUtils]: 12: Hoare triple {1473#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {1473#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:28:02,036 INFO L273 TraceCheckUtils]: 11: Hoare triple {1480#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1473#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:28:02,194 INFO L273 TraceCheckUtils]: 10: Hoare triple {1484#(and (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (forall ((v_arrayElimCell_4 (_ BitVec 32))) (bvsge v_arrayElimCell_4 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))) (or (not (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))) (bvsge (_ bv0 32) main_~MINVAL~0)) (or (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {1480#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:28:02,195 INFO L273 TraceCheckUtils]: 9: Hoare triple {1484#(and (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (forall ((v_arrayElimCell_4 (_ BitVec 32))) (bvsge v_arrayElimCell_4 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))) (or (not (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))) (bvsge (_ bv0 32) main_~MINVAL~0)) (or (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))))} assume !!~bvsge32(~j~0, 1bv32); {1484#(and (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (forall ((v_arrayElimCell_4 (_ BitVec 32))) (bvsge v_arrayElimCell_4 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))) (or (not (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))) (bvsge (_ bv0 32) main_~MINVAL~0)) (or (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))))} is VALID [2018-11-23 10:28:02,214 INFO L273 TraceCheckUtils]: 8: Hoare triple {1491#(and (or (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)) (forall ((v_arrayElimCell_4 (_ BitVec 32))) (bvsge v_arrayElimCell_4 main_~MINVAL~0))) (bvsge (_ bv2 32) main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {1484#(and (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (forall ((v_arrayElimCell_4 (_ BitVec 32))) (bvsge v_arrayElimCell_4 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))) (or (not (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))) (bvsge (_ bv0 32) main_~MINVAL~0)) (or (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))))} is VALID [2018-11-23 10:28:02,215 INFO L273 TraceCheckUtils]: 7: Hoare triple {1495#(bvsge (_ bv2 32) main_~MINVAL~0)} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 2bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 2bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1491#(and (or (= (_ bv8 32) (bvmul (_ bv8 32) main_~i~0)) (forall ((v_arrayElimCell_4 (_ BitVec 32))) (bvsge v_arrayElimCell_4 main_~MINVAL~0))) (bvsge (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:02,216 INFO L273 TraceCheckUtils]: 6: Hoare triple {1353#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1495#(bvsge (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:28:02,216 INFO L273 TraceCheckUtils]: 5: Hoare triple {1353#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1353#true} is VALID [2018-11-23 10:28:02,216 INFO L256 TraceCheckUtils]: 4: Hoare triple {1353#true} call #t~ret8 := main(); {1353#true} is VALID [2018-11-23 10:28:02,216 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1353#true} {1353#true} #83#return; {1353#true} is VALID [2018-11-23 10:28:02,216 INFO L273 TraceCheckUtils]: 2: Hoare triple {1353#true} assume true; {1353#true} is VALID [2018-11-23 10:28:02,217 INFO L273 TraceCheckUtils]: 1: Hoare triple {1353#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1353#true} is VALID [2018-11-23 10:28:02,217 INFO L256 TraceCheckUtils]: 0: Hoare triple {1353#true} call ULTIMATE.init(); {1353#true} is VALID [2018-11-23 10:28:02,221 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:02,225 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:28:02,225 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 17 [2018-11-23 10:28:02,226 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 25 [2018-11-23 10:28:02,226 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:28:02,226 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 17 states. [2018-11-23 10:28:02,672 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 39 edges. 39 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:02,672 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-11-23 10:28:02,672 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-11-23 10:28:02,673 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=208, Unknown=0, NotChecked=0, Total=272 [2018-11-23 10:28:02,673 INFO L87 Difference]: Start difference. First operand 35 states and 39 transitions. Second operand 17 states. [2018-11-23 10:28:04,369 WARN L180 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 33 DAG size of output: 31 [2018-11-23 10:28:09,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:09,201 INFO L93 Difference]: Finished difference Result 138 states and 177 transitions. [2018-11-23 10:28:09,202 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 10:28:09,202 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 25 [2018-11-23 10:28:09,202 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:28:09,202 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17 states. [2018-11-23 10:28:09,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 159 transitions. [2018-11-23 10:28:09,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17 states. [2018-11-23 10:28:09,214 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 159 transitions. [2018-11-23 10:28:09,215 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 27 states and 159 transitions. [2018-11-23 10:28:11,764 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 158 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:11,769 INFO L225 Difference]: With dead ends: 138 [2018-11-23 10:28:11,769 INFO L226 Difference]: Without dead ends: 112 [2018-11-23 10:28:11,770 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 67 GetRequests, 34 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 277 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=272, Invalid=918, Unknown=0, NotChecked=0, Total=1190 [2018-11-23 10:28:11,773 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-11-23 10:28:11,870 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 58. [2018-11-23 10:28:11,871 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:28:11,871 INFO L82 GeneralOperation]: Start isEquivalent. First operand 112 states. Second operand 58 states. [2018-11-23 10:28:11,871 INFO L74 IsIncluded]: Start isIncluded. First operand 112 states. Second operand 58 states. [2018-11-23 10:28:11,871 INFO L87 Difference]: Start difference. First operand 112 states. Second operand 58 states. [2018-11-23 10:28:11,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:11,879 INFO L93 Difference]: Finished difference Result 112 states and 144 transitions. [2018-11-23 10:28:11,879 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 144 transitions. [2018-11-23 10:28:11,880 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:11,880 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:11,880 INFO L74 IsIncluded]: Start isIncluded. First operand 58 states. Second operand 112 states. [2018-11-23 10:28:11,880 INFO L87 Difference]: Start difference. First operand 58 states. Second operand 112 states. [2018-11-23 10:28:11,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:11,886 INFO L93 Difference]: Finished difference Result 112 states and 144 transitions. [2018-11-23 10:28:11,886 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 144 transitions. [2018-11-23 10:28:11,887 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:11,887 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:11,887 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:28:11,887 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:28:11,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2018-11-23 10:28:11,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 69 transitions. [2018-11-23 10:28:11,890 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 69 transitions. Word has length 25 [2018-11-23 10:28:11,890 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:28:11,890 INFO L480 AbstractCegarLoop]: Abstraction has 58 states and 69 transitions. [2018-11-23 10:28:11,890 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-11-23 10:28:11,890 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 69 transitions. [2018-11-23 10:28:11,891 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-11-23 10:28:11,891 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:11,891 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:11,892 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:11,892 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:11,892 INFO L82 PathProgramCache]: Analyzing trace with hash -2033734151, now seen corresponding path program 1 times [2018-11-23 10:28:11,892 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:11,892 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:11,908 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:28:11,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:12,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:12,055 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:12,162 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-11-23 10:28:12,169 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-23 10:28:12,171 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:28:12,185 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:12,194 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:12,194 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:17, output treesize:13 [2018-11-23 10:28:12,602 INFO L256 TraceCheckUtils]: 0: Hoare triple {2048#true} call ULTIMATE.init(); {2048#true} is VALID [2018-11-23 10:28:12,602 INFO L273 TraceCheckUtils]: 1: Hoare triple {2048#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {2048#true} is VALID [2018-11-23 10:28:12,602 INFO L273 TraceCheckUtils]: 2: Hoare triple {2048#true} assume true; {2048#true} is VALID [2018-11-23 10:28:12,603 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2048#true} {2048#true} #83#return; {2048#true} is VALID [2018-11-23 10:28:12,603 INFO L256 TraceCheckUtils]: 4: Hoare triple {2048#true} call #t~ret8 := main(); {2048#true} is VALID [2018-11-23 10:28:12,603 INFO L273 TraceCheckUtils]: 5: Hoare triple {2048#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {2048#true} is VALID [2018-11-23 10:28:12,605 INFO L273 TraceCheckUtils]: 6: Hoare triple {2048#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {2071#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-23 10:28:12,606 INFO L273 TraceCheckUtils]: 7: Hoare triple {2071#(= |main_~#volArray~0.offset| (_ bv0 32))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 2bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 2bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {2075#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:12,606 INFO L273 TraceCheckUtils]: 8: Hoare triple {2075#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {2079#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:12,607 INFO L273 TraceCheckUtils]: 9: Hoare triple {2079#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {2079#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:12,607 INFO L273 TraceCheckUtils]: 10: Hoare triple {2079#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {2079#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:12,608 INFO L273 TraceCheckUtils]: 11: Hoare triple {2079#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2089#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:12,609 INFO L273 TraceCheckUtils]: 12: Hoare triple {2089#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {2089#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:12,610 INFO L273 TraceCheckUtils]: 13: Hoare triple {2089#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {2096#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-23 10:28:12,610 INFO L273 TraceCheckUtils]: 14: Hoare triple {2096#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2096#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-23 10:28:12,611 INFO L273 TraceCheckUtils]: 15: Hoare triple {2096#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !~bvsge32(~j~0, 1bv32); {2096#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-23 10:28:12,612 INFO L273 TraceCheckUtils]: 16: Hoare triple {2096#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {2096#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-23 10:28:12,612 INFO L273 TraceCheckUtils]: 17: Hoare triple {2096#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {2096#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-23 10:28:12,613 INFO L273 TraceCheckUtils]: 18: Hoare triple {2096#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} ~i~0 := 0bv32; {2112#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-23 10:28:12,614 INFO L273 TraceCheckUtils]: 19: Hoare triple {2112#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {2112#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-23 10:28:12,615 INFO L273 TraceCheckUtils]: 20: Hoare triple {2112#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume #t~short7; {2112#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-23 10:28:12,617 INFO L256 TraceCheckUtils]: 21: Hoare triple {2112#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {2122#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))))} is VALID [2018-11-23 10:28:12,618 INFO L273 TraceCheckUtils]: 22: Hoare triple {2122#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))))} ~cond := #in~cond; {2122#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))))} is VALID [2018-11-23 10:28:12,619 INFO L273 TraceCheckUtils]: 23: Hoare triple {2122#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))))} assume !(0bv32 == ~cond); {2122#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))))} is VALID [2018-11-23 10:28:12,619 INFO L273 TraceCheckUtils]: 24: Hoare triple {2122#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))))} assume true; {2122#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))))} is VALID [2018-11-23 10:28:12,621 INFO L268 TraceCheckUtils]: 25: Hoare quadruple {2122#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))))} {2112#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #87#return; {2112#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-23 10:28:12,622 INFO L273 TraceCheckUtils]: 26: Hoare triple {2112#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} havoc #t~mem6;havoc #t~mem5;havoc #t~short7; {2112#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-23 10:28:12,623 INFO L273 TraceCheckUtils]: 27: Hoare triple {2112#(and (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {2141#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:12,624 INFO L273 TraceCheckUtils]: 28: Hoare triple {2141#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {2141#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:12,624 INFO L273 TraceCheckUtils]: 29: Hoare triple {2141#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {2148#|main_#t~short7|} is VALID [2018-11-23 10:28:12,625 INFO L256 TraceCheckUtils]: 30: Hoare triple {2148#|main_#t~short7|} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {2152#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:12,626 INFO L273 TraceCheckUtils]: 31: Hoare triple {2152#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {2156#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:12,626 INFO L273 TraceCheckUtils]: 32: Hoare triple {2156#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 == ~cond; {2049#false} is VALID [2018-11-23 10:28:12,626 INFO L273 TraceCheckUtils]: 33: Hoare triple {2049#false} assume !false; {2049#false} is VALID [2018-11-23 10:28:12,631 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:12,631 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:28:12,855 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2018-11-23 10:28:12,905 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 3 [2018-11-23 10:28:12,908 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:28:12,911 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:12,915 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:12,916 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:20, output treesize:11 [2018-11-23 10:28:12,921 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:28:12,922 WARN L384 uantifierElimination]: Input elimination task: ∀ [|#memory_int|, |main_~#volArray~0.base|]. (= (_ bv0 32) (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) [2018-11-23 10:28:12,922 WARN L385 uantifierElimination]: ElimStorePlain result: ∀ []. (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) [2018-11-23 10:28:13,067 INFO L273 TraceCheckUtils]: 33: Hoare triple {2049#false} assume !false; {2049#false} is VALID [2018-11-23 10:28:13,069 INFO L273 TraceCheckUtils]: 32: Hoare triple {2166#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} assume 0bv32 == ~cond; {2049#false} is VALID [2018-11-23 10:28:13,075 INFO L273 TraceCheckUtils]: 31: Hoare triple {2170#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} ~cond := #in~cond; {2166#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} is VALID [2018-11-23 10:28:13,076 INFO L256 TraceCheckUtils]: 30: Hoare triple {2148#|main_#t~short7|} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {2170#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-23 10:28:13,077 INFO L273 TraceCheckUtils]: 29: Hoare triple {2177#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {2148#|main_#t~short7|} is VALID [2018-11-23 10:28:13,077 INFO L273 TraceCheckUtils]: 28: Hoare triple {2177#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {2177#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-23 10:28:13,325 INFO L273 TraceCheckUtils]: 27: Hoare triple {2184#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {2177#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-23 10:28:13,326 INFO L273 TraceCheckUtils]: 26: Hoare triple {2184#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} havoc #t~mem6;havoc #t~mem5;havoc #t~short7; {2184#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-23 10:28:13,327 INFO L268 TraceCheckUtils]: 25: Hoare quadruple {2048#true} {2184#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} #87#return; {2184#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-23 10:28:13,327 INFO L273 TraceCheckUtils]: 24: Hoare triple {2048#true} assume true; {2048#true} is VALID [2018-11-23 10:28:13,327 INFO L273 TraceCheckUtils]: 23: Hoare triple {2048#true} assume !(0bv32 == ~cond); {2048#true} is VALID [2018-11-23 10:28:13,327 INFO L273 TraceCheckUtils]: 22: Hoare triple {2048#true} ~cond := #in~cond; {2048#true} is VALID [2018-11-23 10:28:13,327 INFO L256 TraceCheckUtils]: 21: Hoare triple {2184#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {2048#true} is VALID [2018-11-23 10:28:13,328 INFO L273 TraceCheckUtils]: 20: Hoare triple {2184#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} assume #t~short7; {2184#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-23 10:28:13,329 INFO L273 TraceCheckUtils]: 19: Hoare triple {2184#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {2184#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-23 10:28:13,330 INFO L273 TraceCheckUtils]: 18: Hoare triple {2212#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} ~i~0 := 0bv32; {2184#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-23 10:28:13,330 INFO L273 TraceCheckUtils]: 17: Hoare triple {2212#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {2212#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-23 10:28:13,331 INFO L273 TraceCheckUtils]: 16: Hoare triple {2212#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {2212#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-23 10:28:13,332 INFO L273 TraceCheckUtils]: 15: Hoare triple {2212#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} assume !~bvsge32(~j~0, 1bv32); {2212#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-23 10:28:13,332 INFO L273 TraceCheckUtils]: 14: Hoare triple {2212#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2212#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-23 10:28:13,517 INFO L273 TraceCheckUtils]: 13: Hoare triple {2228#(= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {2212#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-23 10:28:13,518 INFO L273 TraceCheckUtils]: 12: Hoare triple {2228#(= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {2228#(= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:13,530 INFO L273 TraceCheckUtils]: 11: Hoare triple {2235#(= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2228#(= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:13,530 INFO L273 TraceCheckUtils]: 10: Hoare triple {2235#(= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {2235#(= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))} is VALID [2018-11-23 10:28:13,531 INFO L273 TraceCheckUtils]: 9: Hoare triple {2235#(= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))} assume !!~bvsge32(~j~0, 1bv32); {2235#(= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))} is VALID [2018-11-23 10:28:13,532 INFO L273 TraceCheckUtils]: 8: Hoare triple {2245#(= (bvadd (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {2235#(= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))} is VALID [2018-11-23 10:28:13,532 INFO L273 TraceCheckUtils]: 7: Hoare triple {2048#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 2bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 2bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {2245#(= (bvadd (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:13,533 INFO L273 TraceCheckUtils]: 6: Hoare triple {2048#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {2048#true} is VALID [2018-11-23 10:28:13,533 INFO L273 TraceCheckUtils]: 5: Hoare triple {2048#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {2048#true} is VALID [2018-11-23 10:28:13,533 INFO L256 TraceCheckUtils]: 4: Hoare triple {2048#true} call #t~ret8 := main(); {2048#true} is VALID [2018-11-23 10:28:13,533 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2048#true} {2048#true} #83#return; {2048#true} is VALID [2018-11-23 10:28:13,534 INFO L273 TraceCheckUtils]: 2: Hoare triple {2048#true} assume true; {2048#true} is VALID [2018-11-23 10:28:13,534 INFO L273 TraceCheckUtils]: 1: Hoare triple {2048#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {2048#true} is VALID [2018-11-23 10:28:13,534 INFO L256 TraceCheckUtils]: 0: Hoare triple {2048#true} call ULTIMATE.init(); {2048#true} is VALID [2018-11-23 10:28:13,537 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 2 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:13,539 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:28:13,539 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 11] total 21 [2018-11-23 10:28:13,539 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 34 [2018-11-23 10:28:13,540 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:28:13,540 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 21 states. [2018-11-23 10:28:14,131 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 61 edges. 61 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:14,132 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 10:28:14,132 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 10:28:14,132 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=354, Unknown=0, NotChecked=0, Total=420 [2018-11-23 10:28:14,133 INFO L87 Difference]: Start difference. First operand 58 states and 69 transitions. Second operand 21 states. [2018-11-23 10:28:20,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:20,707 INFO L93 Difference]: Finished difference Result 125 states and 155 transitions. [2018-11-23 10:28:20,707 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-11-23 10:28:20,707 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 34 [2018-11-23 10:28:20,708 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:28:20,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2018-11-23 10:28:20,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 96 transitions. [2018-11-23 10:28:20,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2018-11-23 10:28:20,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 96 transitions. [2018-11-23 10:28:20,714 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 21 states and 96 transitions. [2018-11-23 10:28:20,963 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 96 edges. 96 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:20,967 INFO L225 Difference]: With dead ends: 125 [2018-11-23 10:28:20,967 INFO L226 Difference]: Without dead ends: 123 [2018-11-23 10:28:20,968 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 77 GetRequests, 48 SyntacticMatches, 1 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 187 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=139, Invalid=731, Unknown=0, NotChecked=0, Total=870 [2018-11-23 10:28:20,968 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states. [2018-11-23 10:28:21,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 102. [2018-11-23 10:28:21,152 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:28:21,152 INFO L82 GeneralOperation]: Start isEquivalent. First operand 123 states. Second operand 102 states. [2018-11-23 10:28:21,152 INFO L74 IsIncluded]: Start isIncluded. First operand 123 states. Second operand 102 states. [2018-11-23 10:28:21,153 INFO L87 Difference]: Start difference. First operand 123 states. Second operand 102 states. [2018-11-23 10:28:21,158 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:21,159 INFO L93 Difference]: Finished difference Result 123 states and 153 transitions. [2018-11-23 10:28:21,159 INFO L276 IsEmpty]: Start isEmpty. Operand 123 states and 153 transitions. [2018-11-23 10:28:21,160 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:21,160 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:21,160 INFO L74 IsIncluded]: Start isIncluded. First operand 102 states. Second operand 123 states. [2018-11-23 10:28:21,160 INFO L87 Difference]: Start difference. First operand 102 states. Second operand 123 states. [2018-11-23 10:28:21,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:21,166 INFO L93 Difference]: Finished difference Result 123 states and 153 transitions. [2018-11-23 10:28:21,166 INFO L276 IsEmpty]: Start isEmpty. Operand 123 states and 153 transitions. [2018-11-23 10:28:21,167 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:21,167 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:21,167 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:28:21,167 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:28:21,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-11-23 10:28:21,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 127 transitions. [2018-11-23 10:28:21,172 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 127 transitions. Word has length 34 [2018-11-23 10:28:21,172 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:28:21,173 INFO L480 AbstractCegarLoop]: Abstraction has 102 states and 127 transitions. [2018-11-23 10:28:21,173 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 10:28:21,173 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 127 transitions. [2018-11-23 10:28:21,174 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-11-23 10:28:21,174 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:21,174 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:21,174 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:21,175 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:21,175 INFO L82 PathProgramCache]: Analyzing trace with hash 743455936, now seen corresponding path program 2 times [2018-11-23 10:28:21,175 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:21,175 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:21,199 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-23 10:28:21,275 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 10:28:21,276 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 10:28:21,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:21,299 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:21,511 INFO L256 TraceCheckUtils]: 0: Hoare triple {2849#true} call ULTIMATE.init(); {2849#true} is VALID [2018-11-23 10:28:21,511 INFO L273 TraceCheckUtils]: 1: Hoare triple {2849#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {2849#true} is VALID [2018-11-23 10:28:21,511 INFO L273 TraceCheckUtils]: 2: Hoare triple {2849#true} assume true; {2849#true} is VALID [2018-11-23 10:28:21,512 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2849#true} {2849#true} #83#return; {2849#true} is VALID [2018-11-23 10:28:21,512 INFO L256 TraceCheckUtils]: 4: Hoare triple {2849#true} call #t~ret8 := main(); {2849#true} is VALID [2018-11-23 10:28:21,512 INFO L273 TraceCheckUtils]: 5: Hoare triple {2849#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {2849#true} is VALID [2018-11-23 10:28:21,513 INFO L273 TraceCheckUtils]: 6: Hoare triple {2849#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {2849#true} is VALID [2018-11-23 10:28:21,513 INFO L273 TraceCheckUtils]: 7: Hoare triple {2849#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 2bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 2bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {2849#true} is VALID [2018-11-23 10:28:21,514 INFO L273 TraceCheckUtils]: 8: Hoare triple {2849#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {2878#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:21,514 INFO L273 TraceCheckUtils]: 9: Hoare triple {2878#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {2878#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:21,514 INFO L273 TraceCheckUtils]: 10: Hoare triple {2878#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {2878#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:21,515 INFO L273 TraceCheckUtils]: 11: Hoare triple {2878#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2888#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:21,516 INFO L273 TraceCheckUtils]: 12: Hoare triple {2888#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {2888#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:21,524 INFO L273 TraceCheckUtils]: 13: Hoare triple {2888#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {2888#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:21,539 INFO L273 TraceCheckUtils]: 14: Hoare triple {2888#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2898#(= main_~j~0 (_ bv0 32))} is VALID [2018-11-23 10:28:21,554 INFO L273 TraceCheckUtils]: 15: Hoare triple {2898#(= main_~j~0 (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {2850#false} is VALID [2018-11-23 10:28:21,554 INFO L273 TraceCheckUtils]: 16: Hoare triple {2850#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {2850#false} is VALID [2018-11-23 10:28:21,555 INFO L273 TraceCheckUtils]: 17: Hoare triple {2850#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2850#false} is VALID [2018-11-23 10:28:21,555 INFO L273 TraceCheckUtils]: 18: Hoare triple {2850#false} assume !!~bvsge32(~j~0, 1bv32); {2850#false} is VALID [2018-11-23 10:28:21,555 INFO L273 TraceCheckUtils]: 19: Hoare triple {2850#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {2850#false} is VALID [2018-11-23 10:28:21,555 INFO L273 TraceCheckUtils]: 20: Hoare triple {2850#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2850#false} is VALID [2018-11-23 10:28:21,556 INFO L273 TraceCheckUtils]: 21: Hoare triple {2850#false} assume !!~bvsge32(~j~0, 1bv32); {2850#false} is VALID [2018-11-23 10:28:21,556 INFO L273 TraceCheckUtils]: 22: Hoare triple {2850#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {2850#false} is VALID [2018-11-23 10:28:21,556 INFO L273 TraceCheckUtils]: 23: Hoare triple {2850#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2850#false} is VALID [2018-11-23 10:28:21,556 INFO L273 TraceCheckUtils]: 24: Hoare triple {2850#false} assume !~bvsge32(~j~0, 1bv32); {2850#false} is VALID [2018-11-23 10:28:21,557 INFO L273 TraceCheckUtils]: 25: Hoare triple {2850#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {2850#false} is VALID [2018-11-23 10:28:21,557 INFO L273 TraceCheckUtils]: 26: Hoare triple {2850#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {2850#false} is VALID [2018-11-23 10:28:21,557 INFO L273 TraceCheckUtils]: 27: Hoare triple {2850#false} ~i~0 := 0bv32; {2850#false} is VALID [2018-11-23 10:28:21,557 INFO L273 TraceCheckUtils]: 28: Hoare triple {2850#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {2850#false} is VALID [2018-11-23 10:28:21,558 INFO L273 TraceCheckUtils]: 29: Hoare triple {2850#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {2850#false} is VALID [2018-11-23 10:28:21,558 INFO L256 TraceCheckUtils]: 30: Hoare triple {2850#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {2850#false} is VALID [2018-11-23 10:28:21,558 INFO L273 TraceCheckUtils]: 31: Hoare triple {2850#false} ~cond := #in~cond; {2850#false} is VALID [2018-11-23 10:28:21,558 INFO L273 TraceCheckUtils]: 32: Hoare triple {2850#false} assume 0bv32 == ~cond; {2850#false} is VALID [2018-11-23 10:28:21,559 INFO L273 TraceCheckUtils]: 33: Hoare triple {2850#false} assume !false; {2850#false} is VALID [2018-11-23 10:28:21,560 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 22 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-23 10:28:21,561 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:28:21,718 INFO L273 TraceCheckUtils]: 33: Hoare triple {2850#false} assume !false; {2850#false} is VALID [2018-11-23 10:28:21,718 INFO L273 TraceCheckUtils]: 32: Hoare triple {2850#false} assume 0bv32 == ~cond; {2850#false} is VALID [2018-11-23 10:28:21,719 INFO L273 TraceCheckUtils]: 31: Hoare triple {2850#false} ~cond := #in~cond; {2850#false} is VALID [2018-11-23 10:28:21,719 INFO L256 TraceCheckUtils]: 30: Hoare triple {2850#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {2850#false} is VALID [2018-11-23 10:28:21,719 INFO L273 TraceCheckUtils]: 29: Hoare triple {2850#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {2850#false} is VALID [2018-11-23 10:28:21,719 INFO L273 TraceCheckUtils]: 28: Hoare triple {2850#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {2850#false} is VALID [2018-11-23 10:28:21,719 INFO L273 TraceCheckUtils]: 27: Hoare triple {2850#false} ~i~0 := 0bv32; {2850#false} is VALID [2018-11-23 10:28:21,719 INFO L273 TraceCheckUtils]: 26: Hoare triple {2850#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {2850#false} is VALID [2018-11-23 10:28:21,720 INFO L273 TraceCheckUtils]: 25: Hoare triple {2850#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {2850#false} is VALID [2018-11-23 10:28:21,720 INFO L273 TraceCheckUtils]: 24: Hoare triple {2850#false} assume !~bvsge32(~j~0, 1bv32); {2850#false} is VALID [2018-11-23 10:28:21,720 INFO L273 TraceCheckUtils]: 23: Hoare triple {2850#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2850#false} is VALID [2018-11-23 10:28:21,720 INFO L273 TraceCheckUtils]: 22: Hoare triple {2850#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {2850#false} is VALID [2018-11-23 10:28:21,720 INFO L273 TraceCheckUtils]: 21: Hoare triple {2850#false} assume !!~bvsge32(~j~0, 1bv32); {2850#false} is VALID [2018-11-23 10:28:21,721 INFO L273 TraceCheckUtils]: 20: Hoare triple {2850#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2850#false} is VALID [2018-11-23 10:28:21,721 INFO L273 TraceCheckUtils]: 19: Hoare triple {2850#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {2850#false} is VALID [2018-11-23 10:28:21,721 INFO L273 TraceCheckUtils]: 18: Hoare triple {2850#false} assume !!~bvsge32(~j~0, 1bv32); {2850#false} is VALID [2018-11-23 10:28:21,721 INFO L273 TraceCheckUtils]: 17: Hoare triple {2850#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2850#false} is VALID [2018-11-23 10:28:21,721 INFO L273 TraceCheckUtils]: 16: Hoare triple {2850#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {2850#false} is VALID [2018-11-23 10:28:21,722 INFO L273 TraceCheckUtils]: 15: Hoare triple {3010#(not (bvsge main_~j~0 (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {2850#false} is VALID [2018-11-23 10:28:21,730 INFO L273 TraceCheckUtils]: 14: Hoare triple {3014#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3010#(not (bvsge main_~j~0 (_ bv1 32)))} is VALID [2018-11-23 10:28:21,730 INFO L273 TraceCheckUtils]: 13: Hoare triple {3014#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {3014#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} is VALID [2018-11-23 10:28:21,731 INFO L273 TraceCheckUtils]: 12: Hoare triple {3014#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {3014#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} is VALID [2018-11-23 10:28:21,735 INFO L273 TraceCheckUtils]: 11: Hoare triple {3024#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3014#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} is VALID [2018-11-23 10:28:21,736 INFO L273 TraceCheckUtils]: 10: Hoare triple {3024#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {3024#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} is VALID [2018-11-23 10:28:21,736 INFO L273 TraceCheckUtils]: 9: Hoare triple {3024#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {3024#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} is VALID [2018-11-23 10:28:21,737 INFO L273 TraceCheckUtils]: 8: Hoare triple {2849#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {3024#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} is VALID [2018-11-23 10:28:21,737 INFO L273 TraceCheckUtils]: 7: Hoare triple {2849#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 2bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 2bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {2849#true} is VALID [2018-11-23 10:28:21,737 INFO L273 TraceCheckUtils]: 6: Hoare triple {2849#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {2849#true} is VALID [2018-11-23 10:28:21,737 INFO L273 TraceCheckUtils]: 5: Hoare triple {2849#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {2849#true} is VALID [2018-11-23 10:28:21,737 INFO L256 TraceCheckUtils]: 4: Hoare triple {2849#true} call #t~ret8 := main(); {2849#true} is VALID [2018-11-23 10:28:21,738 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2849#true} {2849#true} #83#return; {2849#true} is VALID [2018-11-23 10:28:21,738 INFO L273 TraceCheckUtils]: 2: Hoare triple {2849#true} assume true; {2849#true} is VALID [2018-11-23 10:28:21,738 INFO L273 TraceCheckUtils]: 1: Hoare triple {2849#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {2849#true} is VALID [2018-11-23 10:28:21,738 INFO L256 TraceCheckUtils]: 0: Hoare triple {2849#true} call ULTIMATE.init(); {2849#true} is VALID [2018-11-23 10:28:21,739 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 22 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-23 10:28:21,741 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:28:21,741 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 8 [2018-11-23 10:28:21,741 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 34 [2018-11-23 10:28:21,742 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:28:21,742 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 8 states. [2018-11-23 10:28:21,831 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 37 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:21,831 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 10:28:21,831 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 10:28:21,831 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 10:28:21,832 INFO L87 Difference]: Start difference. First operand 102 states and 127 transitions. Second operand 8 states. [2018-11-23 10:28:22,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:22,662 INFO L93 Difference]: Finished difference Result 159 states and 193 transitions. [2018-11-23 10:28:22,662 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 10:28:22,663 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 34 [2018-11-23 10:28:22,663 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:28:22,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8 states. [2018-11-23 10:28:22,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 55 transitions. [2018-11-23 10:28:22,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8 states. [2018-11-23 10:28:22,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 55 transitions. [2018-11-23 10:28:22,666 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states and 55 transitions. [2018-11-23 10:28:22,846 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 55 edges. 55 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:22,847 INFO L225 Difference]: With dead ends: 159 [2018-11-23 10:28:22,847 INFO L226 Difference]: Without dead ends: 73 [2018-11-23 10:28:22,850 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 67 GetRequests, 61 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 10:28:22,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2018-11-23 10:28:22,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 73. [2018-11-23 10:28:22,986 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:28:22,987 INFO L82 GeneralOperation]: Start isEquivalent. First operand 73 states. Second operand 73 states. [2018-11-23 10:28:22,987 INFO L74 IsIncluded]: Start isIncluded. First operand 73 states. Second operand 73 states. [2018-11-23 10:28:22,987 INFO L87 Difference]: Start difference. First operand 73 states. Second operand 73 states. [2018-11-23 10:28:22,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:22,990 INFO L93 Difference]: Finished difference Result 73 states and 81 transitions. [2018-11-23 10:28:22,990 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 81 transitions. [2018-11-23 10:28:22,991 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:22,991 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:22,991 INFO L74 IsIncluded]: Start isIncluded. First operand 73 states. Second operand 73 states. [2018-11-23 10:28:22,991 INFO L87 Difference]: Start difference. First operand 73 states. Second operand 73 states. [2018-11-23 10:28:22,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:22,994 INFO L93 Difference]: Finished difference Result 73 states and 81 transitions. [2018-11-23 10:28:22,994 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 81 transitions. [2018-11-23 10:28:22,994 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:22,995 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:22,995 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:28:22,995 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:28:22,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states. [2018-11-23 10:28:22,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 81 transitions. [2018-11-23 10:28:22,998 INFO L78 Accepts]: Start accepts. Automaton has 73 states and 81 transitions. Word has length 34 [2018-11-23 10:28:22,998 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:28:22,998 INFO L480 AbstractCegarLoop]: Abstraction has 73 states and 81 transitions. [2018-11-23 10:28:22,998 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 10:28:22,998 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 81 transitions. [2018-11-23 10:28:22,999 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-11-23 10:28:22,999 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:22,999 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:23,000 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:23,000 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:23,000 INFO L82 PathProgramCache]: Analyzing trace with hash -1720925926, now seen corresponding path program 2 times [2018-11-23 10:28:23,000 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:23,001 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:23,020 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-23 10:28:23,100 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 10:28:23,100 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 10:28:23,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:23,141 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:23,558 WARN L180 SmtUtils]: Spent 103.00 ms on a formula simplification that was a NOOP. DAG size: 11 [2018-11-23 10:28:24,110 WARN L180 SmtUtils]: Spent 106.00 ms on a formula simplification that was a NOOP. DAG size: 15 [2018-11-23 10:28:24,440 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification that was a NOOP. DAG size: 13 [2018-11-23 10:28:24,484 INFO L256 TraceCheckUtils]: 0: Hoare triple {3528#true} call ULTIMATE.init(); {3528#true} is VALID [2018-11-23 10:28:24,484 INFO L273 TraceCheckUtils]: 1: Hoare triple {3528#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {3528#true} is VALID [2018-11-23 10:28:24,484 INFO L273 TraceCheckUtils]: 2: Hoare triple {3528#true} assume true; {3528#true} is VALID [2018-11-23 10:28:24,484 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {3528#true} {3528#true} #83#return; {3528#true} is VALID [2018-11-23 10:28:24,485 INFO L256 TraceCheckUtils]: 4: Hoare triple {3528#true} call #t~ret8 := main(); {3528#true} is VALID [2018-11-23 10:28:24,485 INFO L273 TraceCheckUtils]: 5: Hoare triple {3528#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {3528#true} is VALID [2018-11-23 10:28:24,486 INFO L273 TraceCheckUtils]: 6: Hoare triple {3528#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {3551#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} is VALID [2018-11-23 10:28:24,487 INFO L273 TraceCheckUtils]: 7: Hoare triple {3551#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 2bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 2bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {3555#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:24,489 INFO L273 TraceCheckUtils]: 8: Hoare triple {3555#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {3555#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:24,489 INFO L273 TraceCheckUtils]: 9: Hoare triple {3555#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {3555#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:24,490 INFO L273 TraceCheckUtils]: 10: Hoare triple {3555#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {3555#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:24,490 INFO L273 TraceCheckUtils]: 11: Hoare triple {3555#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3555#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:24,491 INFO L273 TraceCheckUtils]: 12: Hoare triple {3555#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {3555#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:24,491 INFO L273 TraceCheckUtils]: 13: Hoare triple {3555#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {3555#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:24,492 INFO L273 TraceCheckUtils]: 14: Hoare triple {3555#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3555#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:24,492 INFO L273 TraceCheckUtils]: 15: Hoare triple {3555#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~j~0, 1bv32); {3555#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:24,493 INFO L273 TraceCheckUtils]: 16: Hoare triple {3555#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3583#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:28:24,494 INFO L273 TraceCheckUtils]: 17: Hoare triple {3583#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {3587#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-23 10:28:24,495 INFO L273 TraceCheckUtils]: 18: Hoare triple {3587#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} ~i~0 := 0bv32; {3591#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-23 10:28:24,496 INFO L273 TraceCheckUtils]: 19: Hoare triple {3591#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {3591#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-23 10:28:24,497 INFO L273 TraceCheckUtils]: 20: Hoare triple {3591#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} assume #t~short7; {3591#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-23 10:28:24,498 INFO L256 TraceCheckUtils]: 21: Hoare triple {3591#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {3587#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-23 10:28:24,499 INFO L273 TraceCheckUtils]: 22: Hoare triple {3587#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} ~cond := #in~cond; {3587#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-23 10:28:24,500 INFO L273 TraceCheckUtils]: 23: Hoare triple {3587#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} assume !(0bv32 == ~cond); {3587#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-23 10:28:24,500 INFO L273 TraceCheckUtils]: 24: Hoare triple {3587#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} assume true; {3587#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-23 10:28:24,501 INFO L268 TraceCheckUtils]: 25: Hoare quadruple {3587#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} {3591#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} #87#return; {3591#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-23 10:28:24,508 INFO L273 TraceCheckUtils]: 26: Hoare triple {3591#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} havoc #t~mem6;havoc #t~mem5;havoc #t~short7; {3591#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-23 10:28:24,525 INFO L273 TraceCheckUtils]: 27: Hoare triple {3591#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3619#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:24,527 INFO L273 TraceCheckUtils]: 28: Hoare triple {3619#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {3619#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:24,527 INFO L273 TraceCheckUtils]: 29: Hoare triple {3619#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume #t~short7; {3619#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:24,528 INFO L256 TraceCheckUtils]: 30: Hoare triple {3619#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {3587#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-23 10:28:24,529 INFO L273 TraceCheckUtils]: 31: Hoare triple {3587#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} ~cond := #in~cond; {3587#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-23 10:28:24,529 INFO L273 TraceCheckUtils]: 32: Hoare triple {3587#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} assume !(0bv32 == ~cond); {3587#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-23 10:28:24,530 INFO L273 TraceCheckUtils]: 33: Hoare triple {3587#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} assume true; {3587#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} is VALID [2018-11-23 10:28:24,530 INFO L268 TraceCheckUtils]: 34: Hoare quadruple {3587#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))))} {3619#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #87#return; {3619#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:24,549 INFO L273 TraceCheckUtils]: 35: Hoare triple {3619#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} havoc #t~mem6;havoc #t~mem5;havoc #t~short7; {3619#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:24,571 INFO L273 TraceCheckUtils]: 36: Hoare triple {3619#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3647#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:28:24,593 INFO L273 TraceCheckUtils]: 37: Hoare triple {3647#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv2 32)) (_ bv0 32)) (not (bvsle (_ bv2 32) (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (= (_ bv2 32) main_~i~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {3529#false} is VALID [2018-11-23 10:28:24,594 INFO L273 TraceCheckUtils]: 38: Hoare triple {3529#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {3529#false} is VALID [2018-11-23 10:28:24,594 INFO L256 TraceCheckUtils]: 39: Hoare triple {3529#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {3529#false} is VALID [2018-11-23 10:28:24,594 INFO L273 TraceCheckUtils]: 40: Hoare triple {3529#false} ~cond := #in~cond; {3529#false} is VALID [2018-11-23 10:28:24,594 INFO L273 TraceCheckUtils]: 41: Hoare triple {3529#false} assume 0bv32 == ~cond; {3529#false} is VALID [2018-11-23 10:28:24,594 INFO L273 TraceCheckUtils]: 42: Hoare triple {3529#false} assume !false; {3529#false} is VALID [2018-11-23 10:28:24,599 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 8 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-23 10:28:24,599 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:28:26,153 INFO L273 TraceCheckUtils]: 42: Hoare triple {3529#false} assume !false; {3529#false} is VALID [2018-11-23 10:28:26,153 INFO L273 TraceCheckUtils]: 41: Hoare triple {3529#false} assume 0bv32 == ~cond; {3529#false} is VALID [2018-11-23 10:28:26,154 INFO L273 TraceCheckUtils]: 40: Hoare triple {3529#false} ~cond := #in~cond; {3529#false} is VALID [2018-11-23 10:28:26,154 INFO L256 TraceCheckUtils]: 39: Hoare triple {3529#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {3529#false} is VALID [2018-11-23 10:28:26,154 INFO L273 TraceCheckUtils]: 38: Hoare triple {3529#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {3529#false} is VALID [2018-11-23 10:28:26,155 INFO L273 TraceCheckUtils]: 37: Hoare triple {3681#(not (bvslt main_~i~0 ~CELLCOUNT~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {3529#false} is VALID [2018-11-23 10:28:26,176 INFO L273 TraceCheckUtils]: 36: Hoare triple {3685#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3681#(not (bvslt main_~i~0 ~CELLCOUNT~0))} is VALID [2018-11-23 10:28:26,177 INFO L273 TraceCheckUtils]: 35: Hoare triple {3685#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} havoc #t~mem6;havoc #t~mem5;havoc #t~short7; {3685#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} is VALID [2018-11-23 10:28:26,178 INFO L268 TraceCheckUtils]: 34: Hoare quadruple {3528#true} {3685#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} #87#return; {3685#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} is VALID [2018-11-23 10:28:26,178 INFO L273 TraceCheckUtils]: 33: Hoare triple {3528#true} assume true; {3528#true} is VALID [2018-11-23 10:28:26,178 INFO L273 TraceCheckUtils]: 32: Hoare triple {3528#true} assume !(0bv32 == ~cond); {3528#true} is VALID [2018-11-23 10:28:26,178 INFO L273 TraceCheckUtils]: 31: Hoare triple {3528#true} ~cond := #in~cond; {3528#true} is VALID [2018-11-23 10:28:26,178 INFO L256 TraceCheckUtils]: 30: Hoare triple {3685#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {3528#true} is VALID [2018-11-23 10:28:26,179 INFO L273 TraceCheckUtils]: 29: Hoare triple {3685#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} assume #t~short7; {3685#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} is VALID [2018-11-23 10:28:26,179 INFO L273 TraceCheckUtils]: 28: Hoare triple {3685#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {3685#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} is VALID [2018-11-23 10:28:26,204 INFO L273 TraceCheckUtils]: 27: Hoare triple {3713#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3685#(not (bvslt (bvadd main_~i~0 (_ bv1 32)) ~CELLCOUNT~0))} is VALID [2018-11-23 10:28:26,204 INFO L273 TraceCheckUtils]: 26: Hoare triple {3713#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} havoc #t~mem6;havoc #t~mem5;havoc #t~short7; {3713#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} is VALID [2018-11-23 10:28:26,205 INFO L268 TraceCheckUtils]: 25: Hoare quadruple {3528#true} {3713#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} #87#return; {3713#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} is VALID [2018-11-23 10:28:26,205 INFO L273 TraceCheckUtils]: 24: Hoare triple {3528#true} assume true; {3528#true} is VALID [2018-11-23 10:28:26,205 INFO L273 TraceCheckUtils]: 23: Hoare triple {3528#true} assume !(0bv32 == ~cond); {3528#true} is VALID [2018-11-23 10:28:26,205 INFO L273 TraceCheckUtils]: 22: Hoare triple {3528#true} ~cond := #in~cond; {3528#true} is VALID [2018-11-23 10:28:26,206 INFO L256 TraceCheckUtils]: 21: Hoare triple {3713#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {3528#true} is VALID [2018-11-23 10:28:26,206 INFO L273 TraceCheckUtils]: 20: Hoare triple {3713#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} assume #t~short7; {3713#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} is VALID [2018-11-23 10:28:26,206 INFO L273 TraceCheckUtils]: 19: Hoare triple {3713#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {3713#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} is VALID [2018-11-23 10:28:26,207 INFO L273 TraceCheckUtils]: 18: Hoare triple {3741#(not (bvslt (_ bv2 32) ~CELLCOUNT~0))} ~i~0 := 0bv32; {3713#(not (bvslt (bvadd main_~i~0 (_ bv2 32)) ~CELLCOUNT~0))} is VALID [2018-11-23 10:28:26,207 INFO L273 TraceCheckUtils]: 17: Hoare triple {3745#(or (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {3741#(not (bvslt (_ bv2 32) ~CELLCOUNT~0))} is VALID [2018-11-23 10:28:26,224 INFO L273 TraceCheckUtils]: 16: Hoare triple {3749#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3745#(or (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} is VALID [2018-11-23 10:28:26,225 INFO L273 TraceCheckUtils]: 15: Hoare triple {3749#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} assume !~bvsge32(~j~0, 1bv32); {3749#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} is VALID [2018-11-23 10:28:26,225 INFO L273 TraceCheckUtils]: 14: Hoare triple {3749#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3749#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} is VALID [2018-11-23 10:28:26,225 INFO L273 TraceCheckUtils]: 13: Hoare triple {3749#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {3749#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} is VALID [2018-11-23 10:28:26,226 INFO L273 TraceCheckUtils]: 12: Hoare triple {3749#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} assume !!~bvsge32(~j~0, 1bv32); {3749#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} is VALID [2018-11-23 10:28:26,226 INFO L273 TraceCheckUtils]: 11: Hoare triple {3749#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3749#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} is VALID [2018-11-23 10:28:26,226 INFO L273 TraceCheckUtils]: 10: Hoare triple {3749#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {3749#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} is VALID [2018-11-23 10:28:26,229 INFO L273 TraceCheckUtils]: 9: Hoare triple {3749#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} assume !!~bvsge32(~j~0, 1bv32); {3749#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} is VALID [2018-11-23 10:28:26,230 INFO L273 TraceCheckUtils]: 8: Hoare triple {3774#(or (not (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {3749#(or (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} is VALID [2018-11-23 10:28:26,249 INFO L273 TraceCheckUtils]: 7: Hoare triple {3528#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 2bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 2bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {3774#(or (not (bvsle main_~i~0 (bvsdiv ~CELLCOUNT~0 (_ bv2 32)))) (bvsle (bvadd main_~i~0 (_ bv1 32)) (bvsdiv ~CELLCOUNT~0 (_ bv2 32))) (not (bvslt (_ bv2 32) ~CELLCOUNT~0)))} is VALID [2018-11-23 10:28:26,250 INFO L273 TraceCheckUtils]: 6: Hoare triple {3528#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {3528#true} is VALID [2018-11-23 10:28:26,250 INFO L273 TraceCheckUtils]: 5: Hoare triple {3528#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {3528#true} is VALID [2018-11-23 10:28:26,250 INFO L256 TraceCheckUtils]: 4: Hoare triple {3528#true} call #t~ret8 := main(); {3528#true} is VALID [2018-11-23 10:28:26,250 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {3528#true} {3528#true} #83#return; {3528#true} is VALID [2018-11-23 10:28:26,251 INFO L273 TraceCheckUtils]: 2: Hoare triple {3528#true} assume true; {3528#true} is VALID [2018-11-23 10:28:26,251 INFO L273 TraceCheckUtils]: 1: Hoare triple {3528#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {3528#true} is VALID [2018-11-23 10:28:26,251 INFO L256 TraceCheckUtils]: 0: Hoare triple {3528#true} call ULTIMATE.init(); {3528#true} is VALID [2018-11-23 10:28:26,254 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 8 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-23 10:28:26,257 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:28:26,257 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 16 [2018-11-23 10:28:26,258 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 43 [2018-11-23 10:28:26,258 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:28:26,258 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 16 states. [2018-11-23 10:28:26,820 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 65 edges. 65 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:26,820 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-11-23 10:28:26,820 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-11-23 10:28:26,820 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=168, Unknown=0, NotChecked=0, Total=240 [2018-11-23 10:28:26,821 INFO L87 Difference]: Start difference. First operand 73 states and 81 transitions. Second operand 16 states. [2018-11-23 10:28:31,962 WARN L180 SmtUtils]: Spent 155.00 ms on a formula simplification that was a NOOP. DAG size: 14 [2018-11-23 10:28:32,386 WARN L180 SmtUtils]: Spent 139.00 ms on a formula simplification that was a NOOP. DAG size: 11 [2018-11-23 10:28:33,174 WARN L180 SmtUtils]: Spent 144.00 ms on a formula simplification that was a NOOP. DAG size: 14 [2018-11-23 10:28:37,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:37,254 INFO L93 Difference]: Finished difference Result 100 states and 112 transitions. [2018-11-23 10:28:37,254 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-23 10:28:37,254 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 43 [2018-11-23 10:28:37,254 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:28:37,254 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2018-11-23 10:28:37,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 87 transitions. [2018-11-23 10:28:37,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2018-11-23 10:28:37,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 87 transitions. [2018-11-23 10:28:37,260 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 13 states and 87 transitions. [2018-11-23 10:28:38,140 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 87 edges. 87 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:38,142 INFO L225 Difference]: With dead ends: 100 [2018-11-23 10:28:38,142 INFO L226 Difference]: Without dead ends: 63 [2018-11-23 10:28:38,143 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 69 SyntacticMatches, 2 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 76 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=104, Invalid=238, Unknown=0, NotChecked=0, Total=342 [2018-11-23 10:28:38,143 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2018-11-23 10:28:38,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 46. [2018-11-23 10:28:38,229 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:28:38,230 INFO L82 GeneralOperation]: Start isEquivalent. First operand 63 states. Second operand 46 states. [2018-11-23 10:28:38,230 INFO L74 IsIncluded]: Start isIncluded. First operand 63 states. Second operand 46 states. [2018-11-23 10:28:38,230 INFO L87 Difference]: Start difference. First operand 63 states. Second operand 46 states. [2018-11-23 10:28:38,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:38,234 INFO L93 Difference]: Finished difference Result 63 states and 71 transitions. [2018-11-23 10:28:38,234 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 71 transitions. [2018-11-23 10:28:38,234 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:38,234 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:38,234 INFO L74 IsIncluded]: Start isIncluded. First operand 46 states. Second operand 63 states. [2018-11-23 10:28:38,235 INFO L87 Difference]: Start difference. First operand 46 states. Second operand 63 states. [2018-11-23 10:28:38,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:38,237 INFO L93 Difference]: Finished difference Result 63 states and 71 transitions. [2018-11-23 10:28:38,237 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 71 transitions. [2018-11-23 10:28:38,238 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:38,238 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:38,238 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:28:38,238 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:28:38,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-11-23 10:28:38,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 49 transitions. [2018-11-23 10:28:38,240 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 49 transitions. Word has length 43 [2018-11-23 10:28:38,240 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:28:38,240 INFO L480 AbstractCegarLoop]: Abstraction has 46 states and 49 transitions. [2018-11-23 10:28:38,240 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-11-23 10:28:38,240 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 49 transitions. [2018-11-23 10:28:38,241 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-11-23 10:28:38,241 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:38,241 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:38,242 INFO L423 AbstractCegarLoop]: === Iteration 10 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:38,242 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:38,242 INFO L82 PathProgramCache]: Analyzing trace with hash -1321190548, now seen corresponding path program 3 times [2018-11-23 10:28:38,242 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:38,242 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:38,263 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2018-11-23 10:28:38,653 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-11-23 10:28:38,653 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 10:28:38,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:38,714 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:38,832 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-23 10:28:38,836 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 12 [2018-11-23 10:28:38,838 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:28:38,842 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:38,859 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:38,859 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:28, output treesize:24 [2018-11-23 10:28:39,155 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 27 [2018-11-23 10:28:39,449 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 27 treesize of output 45 [2018-11-23 10:28:39,456 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-23 10:28:39,487 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-23 10:28:39,550 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 2 xjuncts. [2018-11-23 10:28:39,550 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:41, output treesize:79 [2018-11-23 10:28:39,570 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:28:39,571 WARN L384 uantifierElimination]: Input elimination task: ∃ [|v_#memory_int_25|]. (let ((.cse0 (select |v_#memory_int_25| |main_~#volArray~0.base|)) (.cse1 (bvmul (_ bv8 32) main_~i~0))) (and (= (store |v_#memory_int_25| |main_~#volArray~0.base| (store .cse0 (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse1) main_~j~0)) |#memory_int|) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (select .cse0 (bvadd |main_~#volArray~0.offset| .cse1 (_ bv4294967284 32))) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))) [2018-11-23 10:28:39,571 WARN L385 uantifierElimination]: ElimStorePlain result: ∃ []. (let ((.cse7 (bvmul (_ bv8 32) main_~i~0))) (let ((.cse6 (select |#memory_int| |main_~#volArray~0.base|)) (.cse0 (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse7))) (let ((.cse1 (bvadd |main_~#volArray~0.offset| .cse7 (_ bv4294967284 32))) (.cse2 (= main_~j~0 (select .cse6 .cse0))) (.cse3 (= |main_~#volArray~0.offset| (_ bv0 32))) (.cse4 (= (_ bv2 32) main_~i~0)) (.cse5 (= (_ bv2 32) main_~MINVAL~0))) (or (and (= .cse0 .cse1) .cse2 .cse3 .cse4 .cse5) (and (= (_ bv0 32) (select .cse6 .cse1)) .cse2 .cse3 .cse4 .cse5))))) [2018-11-23 10:28:40,067 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification that was a NOOP. DAG size: 32 [2018-11-23 10:28:40,119 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 54 treesize of output 47 [2018-11-23 10:28:40,131 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:40,134 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:40,136 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:40,139 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:40,142 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 4 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 106 [2018-11-23 10:28:40,145 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:28:40,206 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:40,356 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 10:28:40,357 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:108, output treesize:50 [2018-11-23 10:28:44,434 INFO L256 TraceCheckUtils]: 0: Hoare triple {4137#true} call ULTIMATE.init(); {4137#true} is VALID [2018-11-23 10:28:44,434 INFO L273 TraceCheckUtils]: 1: Hoare triple {4137#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {4137#true} is VALID [2018-11-23 10:28:44,435 INFO L273 TraceCheckUtils]: 2: Hoare triple {4137#true} assume true; {4137#true} is VALID [2018-11-23 10:28:44,435 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {4137#true} {4137#true} #83#return; {4137#true} is VALID [2018-11-23 10:28:44,435 INFO L256 TraceCheckUtils]: 4: Hoare triple {4137#true} call #t~ret8 := main(); {4137#true} is VALID [2018-11-23 10:28:44,435 INFO L273 TraceCheckUtils]: 5: Hoare triple {4137#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {4137#true} is VALID [2018-11-23 10:28:44,436 INFO L273 TraceCheckUtils]: 6: Hoare triple {4137#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {4160#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:44,437 INFO L273 TraceCheckUtils]: 7: Hoare triple {4160#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 2bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 2bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {4164#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:44,437 INFO L273 TraceCheckUtils]: 8: Hoare triple {4164#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {4168#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:44,438 INFO L273 TraceCheckUtils]: 9: Hoare triple {4168#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {4168#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:44,438 INFO L273 TraceCheckUtils]: 10: Hoare triple {4168#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {4168#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:44,439 INFO L273 TraceCheckUtils]: 11: Hoare triple {4168#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4178#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:44,439 INFO L273 TraceCheckUtils]: 12: Hoare triple {4178#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {4178#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:44,448 INFO L273 TraceCheckUtils]: 13: Hoare triple {4178#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {4185#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32))) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:44,449 INFO L273 TraceCheckUtils]: 14: Hoare triple {4185#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32))) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4185#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32))) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:44,449 INFO L273 TraceCheckUtils]: 15: Hoare triple {4185#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32))) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~j~0, 1bv32); {4185#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32))) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:44,450 INFO L273 TraceCheckUtils]: 16: Hoare triple {4185#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32))) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {4195#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:44,465 INFO L273 TraceCheckUtils]: 17: Hoare triple {4195#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {4195#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:44,467 INFO L273 TraceCheckUtils]: 18: Hoare triple {4195#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {4195#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:44,470 INFO L273 TraceCheckUtils]: 19: Hoare triple {4195#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {4205#(or (and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv12 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)))} is VALID [2018-11-23 10:28:46,474 INFO L273 TraceCheckUtils]: 20: Hoare triple {4205#(or (and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv12 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4209#(or (and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= (_ bv4294967284 32) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)))} is UNKNOWN [2018-11-23 10:28:46,476 INFO L273 TraceCheckUtils]: 21: Hoare triple {4209#(or (and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= (_ bv4294967284 32) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)))} assume !!~bvsge32(~j~0, 1bv32); {4213#(and (bvsge main_~j~0 (_ bv1 32)) (or (and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= (_ bv4294967284 32) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))))} is VALID [2018-11-23 10:28:46,495 INFO L273 TraceCheckUtils]: 22: Hoare triple {4213#(and (bvsge main_~j~0 (_ bv1 32)) (or (and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= (_ bv4294967284 32) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {4217#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-23 10:28:46,511 INFO L273 TraceCheckUtils]: 23: Hoare triple {4217#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4217#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-23 10:28:46,522 INFO L273 TraceCheckUtils]: 24: Hoare triple {4217#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !~bvsge32(~j~0, 1bv32); {4217#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-23 10:28:46,523 INFO L273 TraceCheckUtils]: 25: Hoare triple {4217#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {4217#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-23 10:28:46,524 INFO L273 TraceCheckUtils]: 26: Hoare triple {4217#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {4217#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-23 10:28:46,530 INFO L273 TraceCheckUtils]: 27: Hoare triple {4217#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} ~i~0 := 0bv32; {4233#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-23 10:28:46,531 INFO L273 TraceCheckUtils]: 28: Hoare triple {4233#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {4233#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-23 10:28:46,532 INFO L273 TraceCheckUtils]: 29: Hoare triple {4233#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} assume #t~short7; {4233#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-23 10:28:46,538 INFO L256 TraceCheckUtils]: 30: Hoare triple {4233#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {4243#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))) (not (bvsge main_~j~0 (_ bv2 32)))))} is VALID [2018-11-23 10:28:46,539 INFO L273 TraceCheckUtils]: 31: Hoare triple {4243#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))) (not (bvsge main_~j~0 (_ bv2 32)))))} ~cond := #in~cond; {4243#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))) (not (bvsge main_~j~0 (_ bv2 32)))))} is VALID [2018-11-23 10:28:46,540 INFO L273 TraceCheckUtils]: 32: Hoare triple {4243#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))) (not (bvsge main_~j~0 (_ bv2 32)))))} assume !(0bv32 == ~cond); {4243#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))) (not (bvsge main_~j~0 (_ bv2 32)))))} is VALID [2018-11-23 10:28:46,540 INFO L273 TraceCheckUtils]: 33: Hoare triple {4243#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))) (not (bvsge main_~j~0 (_ bv2 32)))))} assume true; {4243#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))) (not (bvsge main_~j~0 (_ bv2 32)))))} is VALID [2018-11-23 10:28:46,541 INFO L268 TraceCheckUtils]: 34: Hoare quadruple {4243#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (_ bv4 32))) (not (bvsge main_~j~0 (_ bv2 32)))))} {4233#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #87#return; {4233#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-23 10:28:46,543 INFO L273 TraceCheckUtils]: 35: Hoare triple {4233#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} havoc #t~mem6;havoc #t~mem5;havoc #t~short7; {4233#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} is VALID [2018-11-23 10:28:46,551 INFO L273 TraceCheckUtils]: 36: Hoare triple {4233#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)))} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {4262#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:46,559 INFO L273 TraceCheckUtils]: 37: Hoare triple {4262#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {4262#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:46,560 INFO L273 TraceCheckUtils]: 38: Hoare triple {4262#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv16 32))) (_ bv4294967295 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {4269#|main_#t~short7|} is VALID [2018-11-23 10:28:46,561 INFO L256 TraceCheckUtils]: 39: Hoare triple {4269#|main_#t~short7|} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {4273#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:46,561 INFO L273 TraceCheckUtils]: 40: Hoare triple {4273#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {4277#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:46,562 INFO L273 TraceCheckUtils]: 41: Hoare triple {4277#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 == ~cond; {4138#false} is VALID [2018-11-23 10:28:46,562 INFO L273 TraceCheckUtils]: 42: Hoare triple {4138#false} assume !false; {4138#false} is VALID [2018-11-23 10:28:46,574 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:46,574 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:28:48,138 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 44 [2018-11-23 10:28:48,151 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 48 [2018-11-23 10:28:48,178 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:54,263 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 48 treesize of output 111 [2018-11-23 10:29:06,606 WARN L180 SmtUtils]: Spent 12.30 s on a formula simplification. DAG size of input: 64 DAG size of output: 48 [2018-11-23 10:29:06,665 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:06,697 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 64 treesize of output 70 [2018-11-23 10:29:06,707 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 2 xjuncts. [2018-11-23 10:29:08,932 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv8 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0) (bvadd (bvmul (_ bv4 32) (bvneg v_subst_1)) |main_~#volArray~0.offset| .cse0 (_ bv8 32)))) [2018-11-23 10:29:08,940 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:08,942 INFO L303 Elim1Store]: Index analysis took 2036 ms [2018-11-23 10:29:08,960 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 49 treesize of output 71 [2018-11-23 10:29:08,971 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 2 xjuncts. [2018-11-23 10:29:09,068 INFO L267 ElimStorePlain]: Start of recursive call 4: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-23 10:29:09,136 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-23 10:29:09,266 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-23 10:29:09,382 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-11-23 10:29:09,382 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 3 variables, input treesize:58, output treesize:74 [2018-11-23 10:29:09,430 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:29:09,431 WARN L384 uantifierElimination]: Input elimination task: ∀ [|#memory_int|, |main_~#volArray~0.base|, v_subst_1]. (let ((.cse1 (bvadd v_subst_1 (_ bv4294967295 32)))) (or (= (_ bv0 32) (select (let ((.cse0 (bvmul (_ bv8 32) main_~i~0))) (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0) (_ bv0 32)) (bvadd (bvmul (_ bv4 32) (bvneg v_subst_1)) |main_~#volArray~0.offset| .cse0 (_ bv8 32)) v_subst_1) (bvadd (bvmul (_ bv4 32) (bvneg .cse1)) |main_~#volArray~0.offset| .cse0 (_ bv8 32)) (_ bv0 32))) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (bvsge .cse1 main_~MINVAL~0) (not (bvsge .cse1 (_ bv1 32))))) [2018-11-23 10:29:09,431 WARN L385 uantifierElimination]: ElimStorePlain result: ∀ [v_subst_1, v_prenex_6]. (let ((.cse1 (bvmul (_ bv8 32) main_~i~0)) (.cse2 (bvmul (_ bv4 32) (bvneg main_~j~0)))) (and (let ((.cse0 (bvadd v_subst_1 (_ bv4294967295 32)))) (or (not (bvsge .cse0 (_ bv1 32))) (bvsge .cse0 main_~MINVAL~0) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg .cse0)) .cse1)) (= (bvadd .cse2 |main_~#volArray~0.offset| .cse1) (bvadd |main_~#volArray~0.offset| (_ bv4 32))))) (let ((.cse3 (bvadd v_prenex_6 (_ bv4294967295 32)))) (or (bvsge .cse3 main_~MINVAL~0) (not (bvsge .cse3 (_ bv1 32))) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg .cse3)) .cse1)) (not (= (bvadd .cse2 (_ bv4294967288 32)) (bvmul (_ bv4 32) (bvneg v_prenex_6)))))))) [2018-11-23 10:29:13,325 INFO L273 TraceCheckUtils]: 42: Hoare triple {4138#false} assume !false; {4138#false} is VALID [2018-11-23 10:29:13,326 INFO L273 TraceCheckUtils]: 41: Hoare triple {4287#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} assume 0bv32 == ~cond; {4138#false} is VALID [2018-11-23 10:29:13,326 INFO L273 TraceCheckUtils]: 40: Hoare triple {4291#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} ~cond := #in~cond; {4287#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} is VALID [2018-11-23 10:29:13,327 INFO L256 TraceCheckUtils]: 39: Hoare triple {4269#|main_#t~short7|} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {4291#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-23 10:29:13,327 INFO L273 TraceCheckUtils]: 38: Hoare triple {4298#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {4269#|main_#t~short7|} is VALID [2018-11-23 10:29:13,330 INFO L273 TraceCheckUtils]: 37: Hoare triple {4298#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {4298#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-23 10:29:13,610 INFO L273 TraceCheckUtils]: 36: Hoare triple {4305#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {4298#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-23 10:29:13,611 INFO L273 TraceCheckUtils]: 35: Hoare triple {4305#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} havoc #t~mem6;havoc #t~mem5;havoc #t~short7; {4305#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-23 10:29:13,612 INFO L268 TraceCheckUtils]: 34: Hoare quadruple {4137#true} {4305#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} #87#return; {4305#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-23 10:29:13,612 INFO L273 TraceCheckUtils]: 33: Hoare triple {4137#true} assume true; {4137#true} is VALID [2018-11-23 10:29:13,612 INFO L273 TraceCheckUtils]: 32: Hoare triple {4137#true} assume !(0bv32 == ~cond); {4137#true} is VALID [2018-11-23 10:29:13,613 INFO L273 TraceCheckUtils]: 31: Hoare triple {4137#true} ~cond := #in~cond; {4137#true} is VALID [2018-11-23 10:29:13,613 INFO L256 TraceCheckUtils]: 30: Hoare triple {4305#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {4137#true} is VALID [2018-11-23 10:29:13,617 INFO L273 TraceCheckUtils]: 29: Hoare triple {4305#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} assume #t~short7; {4305#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-23 10:29:13,617 INFO L273 TraceCheckUtils]: 28: Hoare triple {4305#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {4305#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-23 10:29:13,619 INFO L273 TraceCheckUtils]: 27: Hoare triple {4333#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} ~i~0 := 0bv32; {4305#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-23 10:29:13,619 INFO L273 TraceCheckUtils]: 26: Hoare triple {4333#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {4333#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-23 10:29:13,620 INFO L273 TraceCheckUtils]: 25: Hoare triple {4333#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {4333#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-23 10:29:13,620 INFO L273 TraceCheckUtils]: 24: Hoare triple {4333#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} assume !~bvsge32(~j~0, 1bv32); {4333#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-23 10:29:13,620 INFO L273 TraceCheckUtils]: 23: Hoare triple {4333#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4333#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-23 10:29:13,858 INFO L273 TraceCheckUtils]: 22: Hoare triple {4349#(or (= (_ bv0 32) (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (bvsge main_~j~0 main_~MINVAL~0))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {4333#(= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv0 32))} is VALID [2018-11-23 10:29:13,859 INFO L273 TraceCheckUtils]: 21: Hoare triple {4353#(or (= (_ bv0 32) (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (bvsge main_~j~0 main_~MINVAL~0) (not (bvsge main_~j~0 (_ bv1 32))))} assume !!~bvsge32(~j~0, 1bv32); {4349#(or (= (_ bv0 32) (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (bvsge main_~j~0 main_~MINVAL~0))} is VALID [2018-11-23 10:29:13,881 INFO L273 TraceCheckUtils]: 20: Hoare triple {4357#(or (= (_ bv0 32) (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4353#(or (= (_ bv0 32) (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (bvsge main_~j~0 main_~MINVAL~0) (not (bvsge main_~j~0 (_ bv1 32))))} is VALID [2018-11-23 10:29:14,103 INFO L273 TraceCheckUtils]: 19: Hoare triple {4361#(forall ((main_~j~0 (_ BitVec 32))) (or (= (_ bv0 32) (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {4357#(or (= (_ bv0 32) (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))))} is VALID [2018-11-23 10:29:14,104 INFO L273 TraceCheckUtils]: 18: Hoare triple {4361#(forall ((main_~j~0 (_ BitVec 32))) (or (= (_ bv0 32) (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))))} assume !!~bvsge32(~j~0, 1bv32); {4361#(forall ((main_~j~0 (_ BitVec 32))) (or (= (_ bv0 32) (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))))} is VALID [2018-11-23 10:29:14,105 INFO L273 TraceCheckUtils]: 17: Hoare triple {4361#(forall ((main_~j~0 (_ BitVec 32))) (or (= (_ bv0 32) (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {4361#(forall ((main_~j~0 (_ BitVec 32))) (or (= (_ bv0 32) (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))))} is VALID [2018-11-23 10:29:14,254 INFO L273 TraceCheckUtils]: 16: Hoare triple {4371#(forall ((main_~j~0 (_ BitVec 32))) (or (= (_ bv0 32) (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv8 32)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {4361#(forall ((main_~j~0 (_ BitVec 32))) (or (= (_ bv0 32) (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))))} is VALID [2018-11-23 10:29:14,255 INFO L273 TraceCheckUtils]: 15: Hoare triple {4371#(forall ((main_~j~0 (_ BitVec 32))) (or (= (_ bv0 32) (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv8 32)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))))} assume !~bvsge32(~j~0, 1bv32); {4371#(forall ((main_~j~0 (_ BitVec 32))) (or (= (_ bv0 32) (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv8 32)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))))} is VALID [2018-11-23 10:29:14,255 INFO L273 TraceCheckUtils]: 14: Hoare triple {4371#(forall ((main_~j~0 (_ BitVec 32))) (or (= (_ bv0 32) (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv8 32)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4371#(forall ((main_~j~0 (_ BitVec 32))) (or (= (_ bv0 32) (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv8 32)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))))} is VALID [2018-11-23 10:29:14,628 INFO L273 TraceCheckUtils]: 13: Hoare triple {4381#(and (forall ((v_prenex_6 (_ BitVec 32))) (or (not (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) (_ bv1 32))) (not (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv4294967288 32)) (bvmul (_ bv4 32) (bvneg v_prenex_6)))) (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_prenex_6 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0))))) (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (forall ((v_subst_1 (_ BitVec 32))) (or (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) (_ bv1 32))) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_subst_1 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))))))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {4371#(forall ((main_~j~0 (_ BitVec 32))) (or (= (_ bv0 32) (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv8 32)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv8 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))))} is VALID [2018-11-23 10:29:14,629 INFO L273 TraceCheckUtils]: 12: Hoare triple {4381#(and (forall ((v_prenex_6 (_ BitVec 32))) (or (not (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) (_ bv1 32))) (not (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv4294967288 32)) (bvmul (_ bv4 32) (bvneg v_prenex_6)))) (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_prenex_6 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0))))) (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (forall ((v_subst_1 (_ BitVec 32))) (or (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) (_ bv1 32))) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_subst_1 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))))))} assume !!~bvsge32(~j~0, 1bv32); {4381#(and (forall ((v_prenex_6 (_ BitVec 32))) (or (not (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) (_ bv1 32))) (not (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv4294967288 32)) (bvmul (_ bv4 32) (bvneg v_prenex_6)))) (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_prenex_6 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0))))) (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (forall ((v_subst_1 (_ BitVec 32))) (or (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) (_ bv1 32))) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_subst_1 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))))))} is VALID [2018-11-23 10:29:14,822 INFO L273 TraceCheckUtils]: 11: Hoare triple {4388#(and (or (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0))) (forall ((v_subst_1 (_ BitVec 32))) (or (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) (_ bv1 32))) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_subst_1 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))))) (forall ((v_prenex_6 (_ BitVec 32))) (or (not (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (_ bv4294967288 32)) (bvmul (_ bv4 32) (bvneg v_prenex_6)))) (not (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) (_ bv1 32))) (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_prenex_6 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0))))))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4381#(and (forall ((v_prenex_6 (_ BitVec 32))) (or (not (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) (_ bv1 32))) (not (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv4294967288 32)) (bvmul (_ bv4 32) (bvneg v_prenex_6)))) (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_prenex_6 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0))))) (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (forall ((v_subst_1 (_ BitVec 32))) (or (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) (_ bv1 32))) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_subst_1 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))))))} is VALID [2018-11-23 10:29:14,823 INFO L273 TraceCheckUtils]: 10: Hoare triple {4388#(and (or (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0))) (forall ((v_subst_1 (_ BitVec 32))) (or (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) (_ bv1 32))) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_subst_1 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))))) (forall ((v_prenex_6 (_ BitVec 32))) (or (not (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (_ bv4294967288 32)) (bvmul (_ bv4 32) (bvneg v_prenex_6)))) (not (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) (_ bv1 32))) (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_prenex_6 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0))))))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {4388#(and (or (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0))) (forall ((v_subst_1 (_ BitVec 32))) (or (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) (_ bv1 32))) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_subst_1 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))))) (forall ((v_prenex_6 (_ BitVec 32))) (or (not (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (_ bv4294967288 32)) (bvmul (_ bv4 32) (bvneg v_prenex_6)))) (not (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) (_ bv1 32))) (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_prenex_6 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0))))))} is VALID [2018-11-23 10:29:14,824 INFO L273 TraceCheckUtils]: 9: Hoare triple {4388#(and (or (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0))) (forall ((v_subst_1 (_ BitVec 32))) (or (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) (_ bv1 32))) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_subst_1 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))))) (forall ((v_prenex_6 (_ BitVec 32))) (or (not (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (_ bv4294967288 32)) (bvmul (_ bv4 32) (bvneg v_prenex_6)))) (not (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) (_ bv1 32))) (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_prenex_6 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0))))))} assume !!~bvsge32(~j~0, 1bv32); {4388#(and (or (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0))) (forall ((v_subst_1 (_ BitVec 32))) (or (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) (_ bv1 32))) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_subst_1 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))))) (forall ((v_prenex_6 (_ BitVec 32))) (or (not (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (_ bv4294967288 32)) (bvmul (_ bv4 32) (bvneg v_prenex_6)))) (not (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) (_ bv1 32))) (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_prenex_6 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0))))))} is VALID [2018-11-23 10:29:14,846 INFO L273 TraceCheckUtils]: 8: Hoare triple {4398#(and (forall ((v_prenex_6 (_ BitVec 32))) (or (not (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) (_ bv1 32))) (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_prenex_6 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0))) (not (= (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_6)) (_ bv12 32)) (_ bv0 32))))) (or (= (bvadd (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (forall ((v_subst_1 (_ BitVec 32))) (or (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) (_ bv1 32))) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_subst_1 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))))))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {4388#(and (or (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0))) (forall ((v_subst_1 (_ BitVec 32))) (or (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) (_ bv1 32))) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_subst_1 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))))) (forall ((v_prenex_6 (_ BitVec 32))) (or (not (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (_ bv4294967288 32)) (bvmul (_ bv4 32) (bvneg v_prenex_6)))) (not (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) (_ bv1 32))) (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_prenex_6 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0))))))} is VALID [2018-11-23 10:29:14,851 INFO L273 TraceCheckUtils]: 7: Hoare triple {4402#(forall ((v_prenex_6 (_ BitVec 32))) (or (not (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) (_ bv1 32))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_prenex_6 (_ bv4294967295 32)))) (_ bv12 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) main_~MINVAL~0) (not (= (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_6)) (_ bv12 32)) (_ bv0 32)))))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 2bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 2bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {4398#(and (forall ((v_prenex_6 (_ BitVec 32))) (or (not (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) (_ bv1 32))) (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_prenex_6 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0))) (not (= (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_6)) (_ bv12 32)) (_ bv0 32))))) (or (= (bvadd (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) (_ bv0 32)) (forall ((v_subst_1 (_ BitVec 32))) (or (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (bvadd v_subst_1 (_ bv4294967295 32)) (_ bv1 32))) (= (_ bv4294967292 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_subst_1 (_ bv4294967295 32)))) (bvmul (_ bv8 32) main_~i~0)))))))} is VALID [2018-11-23 10:29:14,855 INFO L273 TraceCheckUtils]: 6: Hoare triple {4137#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {4402#(forall ((v_prenex_6 (_ BitVec 32))) (or (not (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) (_ bv1 32))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd v_prenex_6 (_ bv4294967295 32)))) (_ bv12 32)) (_ bv0 32)) (bvsge (bvadd v_prenex_6 (_ bv4294967295 32)) main_~MINVAL~0) (not (= (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_6)) (_ bv12 32)) (_ bv0 32)))))} is VALID [2018-11-23 10:29:14,856 INFO L273 TraceCheckUtils]: 5: Hoare triple {4137#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {4137#true} is VALID [2018-11-23 10:29:14,856 INFO L256 TraceCheckUtils]: 4: Hoare triple {4137#true} call #t~ret8 := main(); {4137#true} is VALID [2018-11-23 10:29:14,856 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {4137#true} {4137#true} #83#return; {4137#true} is VALID [2018-11-23 10:29:14,856 INFO L273 TraceCheckUtils]: 2: Hoare triple {4137#true} assume true; {4137#true} is VALID [2018-11-23 10:29:14,857 INFO L273 TraceCheckUtils]: 1: Hoare triple {4137#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {4137#true} is VALID [2018-11-23 10:29:14,857 INFO L256 TraceCheckUtils]: 0: Hoare triple {4137#true} call ULTIMATE.init(); {4137#true} is VALID [2018-11-23 10:29:14,868 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 32 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:29:14,871 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:29:14,871 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 17] total 32 [2018-11-23 10:29:14,871 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 43 [2018-11-23 10:29:14,872 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:29:14,872 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 32 states. [2018-11-23 10:29:18,809 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 79 edges. 78 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2018-11-23 10:29:18,809 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-11-23 10:29:18,810 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-11-23 10:29:18,810 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=146, Invalid=845, Unknown=1, NotChecked=0, Total=992 [2018-11-23 10:29:18,810 INFO L87 Difference]: Start difference. First operand 46 states and 49 transitions. Second operand 32 states. [2018-11-23 10:29:23,840 WARN L180 SmtUtils]: Spent 273.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 43 [2018-11-23 10:29:25,002 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 37 [2018-11-23 10:29:26,263 WARN L180 SmtUtils]: Spent 165.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 40 [2018-11-23 10:29:29,285 WARN L180 SmtUtils]: Spent 357.00 ms on a formula simplification. DAG size of input: 110 DAG size of output: 37 [2018-11-23 10:29:30,308 WARN L180 SmtUtils]: Spent 220.00 ms on a formula simplification. DAG size of input: 83 DAG size of output: 25 [2018-11-23 10:29:32,280 WARN L180 SmtUtils]: Spent 346.00 ms on a formula simplification. DAG size of input: 111 DAG size of output: 38 [2018-11-23 10:29:33,285 WARN L180 SmtUtils]: Spent 230.00 ms on a formula simplification. DAG size of input: 84 DAG size of output: 26 [2018-11-23 10:29:37,840 WARN L180 SmtUtils]: Spent 484.00 ms on a formula simplification. DAG size of input: 97 DAG size of output: 50 [2018-11-23 10:29:38,603 WARN L180 SmtUtils]: Spent 206.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 50 [2018-11-23 10:29:39,403 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 45 DAG size of output: 39 [2018-11-23 10:29:40,903 WARN L180 SmtUtils]: Spent 669.00 ms on a formula simplification. DAG size of input: 98 DAG size of output: 36 [2018-11-23 10:29:41,434 WARN L180 SmtUtils]: Spent 193.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 51 [2018-11-23 10:29:44,534 WARN L180 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 38 [2018-11-23 10:29:46,743 WARN L180 SmtUtils]: Spent 215.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 41 [2018-11-23 10:29:48,695 WARN L180 SmtUtils]: Spent 250.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 39 [2018-11-23 10:29:49,329 WARN L180 SmtUtils]: Spent 234.00 ms on a formula simplification. DAG size of input: 82 DAG size of output: 40 [2018-11-23 10:29:51,526 WARN L180 SmtUtils]: Spent 136.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 35 [2018-11-23 10:29:52,001 WARN L180 SmtUtils]: Spent 151.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 36 [2018-11-23 10:29:54,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:29:54,332 INFO L93 Difference]: Finished difference Result 162 states and 191 transitions. [2018-11-23 10:29:54,332 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-11-23 10:29:54,332 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 43 [2018-11-23 10:29:54,332 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:29:54,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32 states. [2018-11-23 10:29:54,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 172 transitions. [2018-11-23 10:29:54,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32 states. [2018-11-23 10:29:54,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 172 transitions. [2018-11-23 10:29:54,339 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 46 states and 172 transitions. [2018-11-23 10:30:05,402 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 172 edges. 167 inductive. 0 not inductive. 5 times theorem prover too weak to decide inductivity. [2018-11-23 10:30:05,405 INFO L225 Difference]: With dead ends: 162 [2018-11-23 10:30:05,406 INFO L226 Difference]: Without dead ends: 146 [2018-11-23 10:30:05,407 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 55 SyntacticMatches, 1 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 997 ImplicationChecksByTransitivity, 19.0s TimeCoverageRelationStatistics Valid=724, Invalid=3307, Unknown=1, NotChecked=0, Total=4032 [2018-11-23 10:30:05,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-11-23 10:30:06,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 115. [2018-11-23 10:30:06,220 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:30:06,220 INFO L82 GeneralOperation]: Start isEquivalent. First operand 146 states. Second operand 115 states. [2018-11-23 10:30:06,220 INFO L74 IsIncluded]: Start isIncluded. First operand 146 states. Second operand 115 states. [2018-11-23 10:30:06,220 INFO L87 Difference]: Start difference. First operand 146 states. Second operand 115 states. [2018-11-23 10:30:06,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:30:06,227 INFO L93 Difference]: Finished difference Result 146 states and 171 transitions. [2018-11-23 10:30:06,227 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 171 transitions. [2018-11-23 10:30:06,228 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:30:06,228 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:30:06,228 INFO L74 IsIncluded]: Start isIncluded. First operand 115 states. Second operand 146 states. [2018-11-23 10:30:06,228 INFO L87 Difference]: Start difference. First operand 115 states. Second operand 146 states. [2018-11-23 10:30:06,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:30:06,232 INFO L93 Difference]: Finished difference Result 146 states and 171 transitions. [2018-11-23 10:30:06,232 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 171 transitions. [2018-11-23 10:30:06,233 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:30:06,233 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:30:06,233 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:30:06,234 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:30:06,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-11-23 10:30:06,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 132 transitions. [2018-11-23 10:30:06,237 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 132 transitions. Word has length 43 [2018-11-23 10:30:06,237 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:30:06,237 INFO L480 AbstractCegarLoop]: Abstraction has 115 states and 132 transitions. [2018-11-23 10:30:06,237 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-11-23 10:30:06,237 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 132 transitions. [2018-11-23 10:30:06,238 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-11-23 10:30:06,238 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:30:06,238 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:30:06,238 INFO L423 AbstractCegarLoop]: === Iteration 11 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:30:06,239 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:30:06,239 INFO L82 PathProgramCache]: Analyzing trace with hash -1743892374, now seen corresponding path program 4 times [2018-11-23 10:30:06,239 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:30:06,239 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:30:06,263 INFO L101 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-23 10:30:06,332 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-23 10:30:06,332 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 10:30:06,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:30:06,371 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:30:06,869 INFO L256 TraceCheckUtils]: 0: Hoare triple {5170#true} call ULTIMATE.init(); {5170#true} is VALID [2018-11-23 10:30:06,869 INFO L273 TraceCheckUtils]: 1: Hoare triple {5170#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {5170#true} is VALID [2018-11-23 10:30:06,869 INFO L273 TraceCheckUtils]: 2: Hoare triple {5170#true} assume true; {5170#true} is VALID [2018-11-23 10:30:06,869 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {5170#true} {5170#true} #83#return; {5170#true} is VALID [2018-11-23 10:30:06,869 INFO L256 TraceCheckUtils]: 4: Hoare triple {5170#true} call #t~ret8 := main(); {5170#true} is VALID [2018-11-23 10:30:06,869 INFO L273 TraceCheckUtils]: 5: Hoare triple {5170#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {5170#true} is VALID [2018-11-23 10:30:06,870 INFO L273 TraceCheckUtils]: 6: Hoare triple {5170#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {5193#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:30:06,870 INFO L273 TraceCheckUtils]: 7: Hoare triple {5193#(= (_ bv2 32) main_~MINVAL~0)} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 2bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 2bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {5193#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:30:06,871 INFO L273 TraceCheckUtils]: 8: Hoare triple {5193#(= (_ bv2 32) main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {5193#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:30:06,871 INFO L273 TraceCheckUtils]: 9: Hoare triple {5193#(= (_ bv2 32) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {5193#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:30:06,871 INFO L273 TraceCheckUtils]: 10: Hoare triple {5193#(= (_ bv2 32) main_~MINVAL~0)} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {5193#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:30:06,872 INFO L273 TraceCheckUtils]: 11: Hoare triple {5193#(= (_ bv2 32) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {5193#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:30:06,872 INFO L273 TraceCheckUtils]: 12: Hoare triple {5193#(= (_ bv2 32) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {5193#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:30:06,872 INFO L273 TraceCheckUtils]: 13: Hoare triple {5193#(= (_ bv2 32) main_~MINVAL~0)} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {5193#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:30:06,873 INFO L273 TraceCheckUtils]: 14: Hoare triple {5193#(= (_ bv2 32) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {5193#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:30:06,873 INFO L273 TraceCheckUtils]: 15: Hoare triple {5193#(= (_ bv2 32) main_~MINVAL~0)} assume !~bvsge32(~j~0, 1bv32); {5193#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:30:06,873 INFO L273 TraceCheckUtils]: 16: Hoare triple {5193#(= (_ bv2 32) main_~MINVAL~0)} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {5193#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:30:06,874 INFO L273 TraceCheckUtils]: 17: Hoare triple {5193#(= (_ bv2 32) main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {5227#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:06,875 INFO L273 TraceCheckUtils]: 18: Hoare triple {5227#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {5227#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:06,876 INFO L273 TraceCheckUtils]: 19: Hoare triple {5227#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {5227#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:06,877 INFO L273 TraceCheckUtils]: 20: Hoare triple {5227#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {5237#(and (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:06,878 INFO L273 TraceCheckUtils]: 21: Hoare triple {5237#(and (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {5237#(and (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:06,879 INFO L273 TraceCheckUtils]: 22: Hoare triple {5237#(and (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {5171#false} is VALID [2018-11-23 10:30:06,879 INFO L273 TraceCheckUtils]: 23: Hoare triple {5171#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {5171#false} is VALID [2018-11-23 10:30:06,879 INFO L273 TraceCheckUtils]: 24: Hoare triple {5171#false} assume !~bvsge32(~j~0, 1bv32); {5171#false} is VALID [2018-11-23 10:30:06,879 INFO L273 TraceCheckUtils]: 25: Hoare triple {5171#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {5171#false} is VALID [2018-11-23 10:30:06,880 INFO L273 TraceCheckUtils]: 26: Hoare triple {5171#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {5171#false} is VALID [2018-11-23 10:30:06,880 INFO L273 TraceCheckUtils]: 27: Hoare triple {5171#false} ~i~0 := 0bv32; {5171#false} is VALID [2018-11-23 10:30:06,880 INFO L273 TraceCheckUtils]: 28: Hoare triple {5171#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {5171#false} is VALID [2018-11-23 10:30:06,880 INFO L273 TraceCheckUtils]: 29: Hoare triple {5171#false} assume #t~short7; {5171#false} is VALID [2018-11-23 10:30:06,881 INFO L256 TraceCheckUtils]: 30: Hoare triple {5171#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {5171#false} is VALID [2018-11-23 10:30:06,881 INFO L273 TraceCheckUtils]: 31: Hoare triple {5171#false} ~cond := #in~cond; {5171#false} is VALID [2018-11-23 10:30:06,881 INFO L273 TraceCheckUtils]: 32: Hoare triple {5171#false} assume !(0bv32 == ~cond); {5171#false} is VALID [2018-11-23 10:30:06,881 INFO L273 TraceCheckUtils]: 33: Hoare triple {5171#false} assume true; {5171#false} is VALID [2018-11-23 10:30:06,881 INFO L268 TraceCheckUtils]: 34: Hoare quadruple {5171#false} {5171#false} #87#return; {5171#false} is VALID [2018-11-23 10:30:06,882 INFO L273 TraceCheckUtils]: 35: Hoare triple {5171#false} havoc #t~mem6;havoc #t~mem5;havoc #t~short7; {5171#false} is VALID [2018-11-23 10:30:06,882 INFO L273 TraceCheckUtils]: 36: Hoare triple {5171#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {5171#false} is VALID [2018-11-23 10:30:06,882 INFO L273 TraceCheckUtils]: 37: Hoare triple {5171#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {5171#false} is VALID [2018-11-23 10:30:06,883 INFO L273 TraceCheckUtils]: 38: Hoare triple {5171#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {5171#false} is VALID [2018-11-23 10:30:06,883 INFO L256 TraceCheckUtils]: 39: Hoare triple {5171#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {5171#false} is VALID [2018-11-23 10:30:06,883 INFO L273 TraceCheckUtils]: 40: Hoare triple {5171#false} ~cond := #in~cond; {5171#false} is VALID [2018-11-23 10:30:06,883 INFO L273 TraceCheckUtils]: 41: Hoare triple {5171#false} assume 0bv32 == ~cond; {5171#false} is VALID [2018-11-23 10:30:06,883 INFO L273 TraceCheckUtils]: 42: Hoare triple {5171#false} assume !false; {5171#false} is VALID [2018-11-23 10:30:06,885 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 23 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-11-23 10:30:06,885 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:30:07,016 INFO L273 TraceCheckUtils]: 42: Hoare triple {5171#false} assume !false; {5171#false} is VALID [2018-11-23 10:30:07,016 INFO L273 TraceCheckUtils]: 41: Hoare triple {5171#false} assume 0bv32 == ~cond; {5171#false} is VALID [2018-11-23 10:30:07,016 INFO L273 TraceCheckUtils]: 40: Hoare triple {5171#false} ~cond := #in~cond; {5171#false} is VALID [2018-11-23 10:30:07,017 INFO L256 TraceCheckUtils]: 39: Hoare triple {5171#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {5171#false} is VALID [2018-11-23 10:30:07,017 INFO L273 TraceCheckUtils]: 38: Hoare triple {5171#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {5171#false} is VALID [2018-11-23 10:30:07,017 INFO L273 TraceCheckUtils]: 37: Hoare triple {5171#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {5171#false} is VALID [2018-11-23 10:30:07,017 INFO L273 TraceCheckUtils]: 36: Hoare triple {5171#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {5171#false} is VALID [2018-11-23 10:30:07,017 INFO L273 TraceCheckUtils]: 35: Hoare triple {5171#false} havoc #t~mem6;havoc #t~mem5;havoc #t~short7; {5171#false} is VALID [2018-11-23 10:30:07,017 INFO L268 TraceCheckUtils]: 34: Hoare quadruple {5170#true} {5171#false} #87#return; {5171#false} is VALID [2018-11-23 10:30:07,017 INFO L273 TraceCheckUtils]: 33: Hoare triple {5170#true} assume true; {5170#true} is VALID [2018-11-23 10:30:07,017 INFO L273 TraceCheckUtils]: 32: Hoare triple {5170#true} assume !(0bv32 == ~cond); {5170#true} is VALID [2018-11-23 10:30:07,018 INFO L273 TraceCheckUtils]: 31: Hoare triple {5170#true} ~cond := #in~cond; {5170#true} is VALID [2018-11-23 10:30:07,018 INFO L256 TraceCheckUtils]: 30: Hoare triple {5171#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {5170#true} is VALID [2018-11-23 10:30:07,018 INFO L273 TraceCheckUtils]: 29: Hoare triple {5171#false} assume #t~short7; {5171#false} is VALID [2018-11-23 10:30:07,018 INFO L273 TraceCheckUtils]: 28: Hoare triple {5171#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {5171#false} is VALID [2018-11-23 10:30:07,018 INFO L273 TraceCheckUtils]: 27: Hoare triple {5171#false} ~i~0 := 0bv32; {5171#false} is VALID [2018-11-23 10:30:07,018 INFO L273 TraceCheckUtils]: 26: Hoare triple {5171#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {5171#false} is VALID [2018-11-23 10:30:07,018 INFO L273 TraceCheckUtils]: 25: Hoare triple {5171#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {5171#false} is VALID [2018-11-23 10:30:07,018 INFO L273 TraceCheckUtils]: 24: Hoare triple {5171#false} assume !~bvsge32(~j~0, 1bv32); {5171#false} is VALID [2018-11-23 10:30:07,020 INFO L273 TraceCheckUtils]: 23: Hoare triple {5171#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {5171#false} is VALID [2018-11-23 10:30:07,025 INFO L273 TraceCheckUtils]: 22: Hoare triple {5364#(not (bvsge main_~j~0 main_~MINVAL~0))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {5171#false} is VALID [2018-11-23 10:30:07,027 INFO L273 TraceCheckUtils]: 21: Hoare triple {5364#(not (bvsge main_~j~0 main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {5364#(not (bvsge main_~j~0 main_~MINVAL~0))} is VALID [2018-11-23 10:30:07,027 INFO L273 TraceCheckUtils]: 20: Hoare triple {5371#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {5364#(not (bvsge main_~j~0 main_~MINVAL~0))} is VALID [2018-11-23 10:30:07,029 INFO L273 TraceCheckUtils]: 19: Hoare triple {5371#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {5371#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0))} is VALID [2018-11-23 10:30:07,029 INFO L273 TraceCheckUtils]: 18: Hoare triple {5371#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {5371#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0))} is VALID [2018-11-23 10:30:07,045 INFO L273 TraceCheckUtils]: 17: Hoare triple {5381#(not (bvsge (_ bv1 32) main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {5371#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0))} is VALID [2018-11-23 10:30:07,046 INFO L273 TraceCheckUtils]: 16: Hoare triple {5381#(not (bvsge (_ bv1 32) main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {5381#(not (bvsge (_ bv1 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:07,046 INFO L273 TraceCheckUtils]: 15: Hoare triple {5381#(not (bvsge (_ bv1 32) main_~MINVAL~0))} assume !~bvsge32(~j~0, 1bv32); {5381#(not (bvsge (_ bv1 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:07,048 INFO L273 TraceCheckUtils]: 14: Hoare triple {5381#(not (bvsge (_ bv1 32) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {5381#(not (bvsge (_ bv1 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:07,048 INFO L273 TraceCheckUtils]: 13: Hoare triple {5381#(not (bvsge (_ bv1 32) main_~MINVAL~0))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {5381#(not (bvsge (_ bv1 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:07,048 INFO L273 TraceCheckUtils]: 12: Hoare triple {5381#(not (bvsge (_ bv1 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {5381#(not (bvsge (_ bv1 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:07,050 INFO L273 TraceCheckUtils]: 11: Hoare triple {5381#(not (bvsge (_ bv1 32) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {5381#(not (bvsge (_ bv1 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:07,050 INFO L273 TraceCheckUtils]: 10: Hoare triple {5381#(not (bvsge (_ bv1 32) main_~MINVAL~0))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {5381#(not (bvsge (_ bv1 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:07,052 INFO L273 TraceCheckUtils]: 9: Hoare triple {5381#(not (bvsge (_ bv1 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {5381#(not (bvsge (_ bv1 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:07,052 INFO L273 TraceCheckUtils]: 8: Hoare triple {5381#(not (bvsge (_ bv1 32) main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {5381#(not (bvsge (_ bv1 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:07,054 INFO L273 TraceCheckUtils]: 7: Hoare triple {5381#(not (bvsge (_ bv1 32) main_~MINVAL~0))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 2bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 2bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {5381#(not (bvsge (_ bv1 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:07,054 INFO L273 TraceCheckUtils]: 6: Hoare triple {5170#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {5381#(not (bvsge (_ bv1 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:07,054 INFO L273 TraceCheckUtils]: 5: Hoare triple {5170#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {5170#true} is VALID [2018-11-23 10:30:07,054 INFO L256 TraceCheckUtils]: 4: Hoare triple {5170#true} call #t~ret8 := main(); {5170#true} is VALID [2018-11-23 10:30:07,055 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {5170#true} {5170#true} #83#return; {5170#true} is VALID [2018-11-23 10:30:07,055 INFO L273 TraceCheckUtils]: 2: Hoare triple {5170#true} assume true; {5170#true} is VALID [2018-11-23 10:30:07,055 INFO L273 TraceCheckUtils]: 1: Hoare triple {5170#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {5170#true} is VALID [2018-11-23 10:30:07,055 INFO L256 TraceCheckUtils]: 0: Hoare triple {5170#true} call ULTIMATE.init(); {5170#true} is VALID [2018-11-23 10:30:07,057 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 13 proven. 14 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-23 10:30:07,058 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:30:07,059 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 8 [2018-11-23 10:30:07,059 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 43 [2018-11-23 10:30:07,059 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:30:07,059 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 8 states. [2018-11-23 10:30:07,192 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 58 edges. 58 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:30:07,192 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 10:30:07,193 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 10:30:07,193 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-11-23 10:30:07,193 INFO L87 Difference]: Start difference. First operand 115 states and 132 transitions. Second operand 8 states. [2018-11-23 10:30:08,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:30:08,063 INFO L93 Difference]: Finished difference Result 131 states and 149 transitions. [2018-11-23 10:30:08,063 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 10:30:08,064 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 43 [2018-11-23 10:30:08,064 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:30:08,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8 states. [2018-11-23 10:30:08,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 54 transitions. [2018-11-23 10:30:08,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8 states. [2018-11-23 10:30:08,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 54 transitions. [2018-11-23 10:30:08,065 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 6 states and 54 transitions. [2018-11-23 10:30:08,235 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 54 edges. 54 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:30:08,238 INFO L225 Difference]: With dead ends: 131 [2018-11-23 10:30:08,238 INFO L226 Difference]: Without dead ends: 103 [2018-11-23 10:30:08,239 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 86 GetRequests, 79 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2018-11-23 10:30:08,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states. [2018-11-23 10:30:08,504 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 103. [2018-11-23 10:30:08,504 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:30:08,504 INFO L82 GeneralOperation]: Start isEquivalent. First operand 103 states. Second operand 103 states. [2018-11-23 10:30:08,504 INFO L74 IsIncluded]: Start isIncluded. First operand 103 states. Second operand 103 states. [2018-11-23 10:30:08,504 INFO L87 Difference]: Start difference. First operand 103 states. Second operand 103 states. [2018-11-23 10:30:08,507 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:30:08,507 INFO L93 Difference]: Finished difference Result 103 states and 116 transitions. [2018-11-23 10:30:08,507 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 116 transitions. [2018-11-23 10:30:08,508 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:30:08,508 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:30:08,508 INFO L74 IsIncluded]: Start isIncluded. First operand 103 states. Second operand 103 states. [2018-11-23 10:30:08,508 INFO L87 Difference]: Start difference. First operand 103 states. Second operand 103 states. [2018-11-23 10:30:08,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:30:08,511 INFO L93 Difference]: Finished difference Result 103 states and 116 transitions. [2018-11-23 10:30:08,511 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 116 transitions. [2018-11-23 10:30:08,511 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:30:08,511 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:30:08,511 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:30:08,511 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:30:08,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103 states. [2018-11-23 10:30:08,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 116 transitions. [2018-11-23 10:30:08,514 INFO L78 Accepts]: Start accepts. Automaton has 103 states and 116 transitions. Word has length 43 [2018-11-23 10:30:08,514 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:30:08,514 INFO L480 AbstractCegarLoop]: Abstraction has 103 states and 116 transitions. [2018-11-23 10:30:08,514 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 10:30:08,514 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 116 transitions. [2018-11-23 10:30:08,515 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-11-23 10:30:08,515 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:30:08,516 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:30:08,516 INFO L423 AbstractCegarLoop]: === Iteration 12 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:30:08,516 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:30:08,516 INFO L82 PathProgramCache]: Analyzing trace with hash -1642472518, now seen corresponding path program 5 times [2018-11-23 10:30:08,517 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:30:08,517 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:30:08,541 INFO L101 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2018-11-23 10:30:09,595 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 9 check-sat command(s) [2018-11-23 10:30:09,596 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 10:30:09,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:30:09,704 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:30:09,841 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 16 [2018-11-23 10:30:09,850 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 15 [2018-11-23 10:30:09,852 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:30:09,863 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:30:09,899 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 10:30:09,899 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:35, output treesize:31 [2018-11-23 10:30:09,919 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:30:09,919 WARN L384 uantifierElimination]: Input elimination task: ∃ [main_~j~0, |v_#memory_int_35|]. (and (bvsge main_~j~0 (_ bv1 32)) (not (bvsge main_~j~0 main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= |#memory_int| (store |v_#memory_int_35| |main_~#volArray~0.base| (store (select |v_#memory_int_35| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) [2018-11-23 10:30:09,919 WARN L385 uantifierElimination]: ElimStorePlain result: ∃ [main_~j~0]. (and (bvsge main_~j~0 (_ bv1 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0))) (_ bv0 32)) (not (bvsge main_~j~0 main_~MINVAL~0)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32))) [2018-11-23 10:30:10,184 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 31 [2018-11-23 10:30:10,197 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:10,199 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:10,201 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 70 [2018-11-23 10:30:10,203 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:30:10,225 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:30:10,290 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 10:30:10,291 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:57, output treesize:53 [2018-11-23 10:30:10,586 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 38 [2018-11-23 10:30:10,623 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:10,626 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:10,629 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:10,631 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:10,633 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 4 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 117 [2018-11-23 10:30:10,641 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:30:10,667 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:30:10,723 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 10:30:10,723 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:65, output treesize:57 [2018-11-23 10:30:11,240 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 60 treesize of output 51 [2018-11-23 10:30:11,261 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:11,266 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:11,269 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:11,271 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:11,274 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:11,277 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:11,280 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:11,282 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 7 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 183 [2018-11-23 10:30:11,288 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:30:11,335 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:30:11,423 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 10:30:11,423 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:83, output treesize:79 [2018-11-23 10:30:11,888 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 54 treesize of output 43 [2018-11-23 10:30:11,907 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:11,911 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:11,914 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:11,918 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:11,922 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:11,926 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:11,930 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:11,934 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:11,937 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:11,941 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:11,945 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:11,947 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 11 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 162 [2018-11-23 10:30:11,966 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:30:12,166 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:30:12,229 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 10:30:12,229 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:67, output treesize:63 [2018-11-23 10:30:13,545 INFO L256 TraceCheckUtils]: 0: Hoare triple {5971#true} call ULTIMATE.init(); {5971#true} is VALID [2018-11-23 10:30:13,546 INFO L273 TraceCheckUtils]: 1: Hoare triple {5971#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {5971#true} is VALID [2018-11-23 10:30:13,546 INFO L273 TraceCheckUtils]: 2: Hoare triple {5971#true} assume true; {5971#true} is VALID [2018-11-23 10:30:13,546 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {5971#true} {5971#true} #83#return; {5971#true} is VALID [2018-11-23 10:30:13,547 INFO L256 TraceCheckUtils]: 4: Hoare triple {5971#true} call #t~ret8 := main(); {5971#true} is VALID [2018-11-23 10:30:13,547 INFO L273 TraceCheckUtils]: 5: Hoare triple {5971#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {5971#true} is VALID [2018-11-23 10:30:13,547 INFO L273 TraceCheckUtils]: 6: Hoare triple {5971#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {5994#(= |main_~#volArray~0.offset| (_ bv0 32))} is VALID [2018-11-23 10:30:13,548 INFO L273 TraceCheckUtils]: 7: Hoare triple {5994#(= |main_~#volArray~0.offset| (_ bv0 32))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 2bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 2bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {5998#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:30:13,549 INFO L273 TraceCheckUtils]: 8: Hoare triple {5998#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {5998#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:30:13,549 INFO L273 TraceCheckUtils]: 9: Hoare triple {5998#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {5998#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:30:13,549 INFO L273 TraceCheckUtils]: 10: Hoare triple {5998#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {5998#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:30:13,550 INFO L273 TraceCheckUtils]: 11: Hoare triple {5998#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {5998#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:30:13,551 INFO L273 TraceCheckUtils]: 12: Hoare triple {5998#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {6014#(and (bvsge main_~j~0 (_ bv1 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:30:13,556 INFO L273 TraceCheckUtils]: 13: Hoare triple {6014#(and (bvsge main_~j~0 (_ bv1 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {6018#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0))) (_ bv0 32)) (not (bvsge main_~j~0 main_~MINVAL~0)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:30:13,556 INFO L273 TraceCheckUtils]: 14: Hoare triple {6018#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0))) (_ bv0 32)) (not (bvsge main_~j~0 main_~MINVAL~0)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {6018#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0))) (_ bv0 32)) (not (bvsge main_~j~0 main_~MINVAL~0)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:30:13,557 INFO L273 TraceCheckUtils]: 15: Hoare triple {6018#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0))) (_ bv0 32)) (not (bvsge main_~j~0 main_~MINVAL~0)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~j~0, 1bv32); {6018#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0))) (_ bv0 32)) (not (bvsge main_~j~0 main_~MINVAL~0)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:30:13,560 INFO L273 TraceCheckUtils]: 16: Hoare triple {6018#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0))) (_ bv0 32)) (not (bvsge main_~j~0 main_~MINVAL~0)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {6028#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (not (bvsge main_~j~0 main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32))) (_ bv0 32)))) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:30:13,581 INFO L273 TraceCheckUtils]: 17: Hoare triple {6028#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (not (bvsge main_~j~0 main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32))) (_ bv0 32)))) (= (_ bv2 32) main_~i~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {6032#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32))) (_ bv0 32)) (bvsge v_prenex_7 (_ bv1 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:30:13,582 INFO L273 TraceCheckUtils]: 18: Hoare triple {6032#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32))) (_ bv0 32)) (bvsge v_prenex_7 (_ bv1 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume !!~bvsge32(~j~0, 1bv32); {6032#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32))) (_ bv0 32)) (bvsge v_prenex_7 (_ bv1 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:30:13,586 INFO L273 TraceCheckUtils]: 19: Hoare triple {6032#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32))) (_ bv0 32)) (bvsge v_prenex_7 (_ bv1 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {6039#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (bvsge main_~j~0 main_~MINVAL~0) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32))) (_ bv0 32)) (bvsge v_prenex_7 (_ bv1 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:30:13,596 INFO L273 TraceCheckUtils]: 20: Hoare triple {6039#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (bvsge main_~j~0 main_~MINVAL~0) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32))) (_ bv0 32)) (bvsge v_prenex_7 (_ bv1 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {6043#(and (bvsge (bvadd main_~j~0 (_ bv1 32)) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32))) (_ bv0 32)) (bvsge v_prenex_7 (_ bv1 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:30:13,601 INFO L273 TraceCheckUtils]: 21: Hoare triple {6043#(and (bvsge (bvadd main_~j~0 (_ bv1 32)) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32))) (_ bv0 32)) (bvsge v_prenex_7 (_ bv1 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume !!~bvsge32(~j~0, 1bv32); {6043#(and (bvsge (bvadd main_~j~0 (_ bv1 32)) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32))) (_ bv0 32)) (bvsge v_prenex_7 (_ bv1 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:30:13,607 INFO L273 TraceCheckUtils]: 22: Hoare triple {6043#(and (bvsge (bvadd main_~j~0 (_ bv1 32)) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32))) (_ bv0 32)) (bvsge v_prenex_7 (_ bv1 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {6050#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32))) (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32))) (_ bv0 32)) (bvsge v_prenex_7 (_ bv1 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)))) (= (_ bv2 32) main_~i~0) (bvsge (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:13,612 INFO L273 TraceCheckUtils]: 23: Hoare triple {6050#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32))) (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32))) (_ bv0 32)) (bvsge v_prenex_7 (_ bv1 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)))) (= (_ bv2 32) main_~i~0) (bvsge (_ bv2 32) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {6050#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32))) (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32))) (_ bv0 32)) (bvsge v_prenex_7 (_ bv1 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)))) (= (_ bv2 32) main_~i~0) (bvsge (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:13,616 INFO L273 TraceCheckUtils]: 24: Hoare triple {6050#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32))) (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32))) (_ bv0 32)) (bvsge v_prenex_7 (_ bv1 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)))) (= (_ bv2 32) main_~i~0) (bvsge (_ bv2 32) main_~MINVAL~0))} assume !~bvsge32(~j~0, 1bv32); {6050#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32))) (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32))) (_ bv0 32)) (bvsge v_prenex_7 (_ bv1 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)))) (= (_ bv2 32) main_~i~0) (bvsge (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:13,622 INFO L273 TraceCheckUtils]: 25: Hoare triple {6050#(and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32))) (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32))) (_ bv0 32)) (bvsge v_prenex_7 (_ bv1 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)))) (= (_ bv2 32) main_~i~0) (bvsge (_ bv2 32) main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {6060#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (not (bvsge v_prenex_7 main_~MINVAL~0)) (bvsge v_prenex_7 (_ bv1 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (bvsge (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:13,641 INFO L273 TraceCheckUtils]: 26: Hoare triple {6060#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (not (bvsge v_prenex_7 main_~MINVAL~0)) (bvsge v_prenex_7 (_ bv1 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (bvsge (_ bv2 32) main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {6064#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (not (bvsge v_prenex_7 main_~MINVAL~0)) (bvsge v_prenex_7 (_ bv1 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (bvsge (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:13,645 INFO L273 TraceCheckUtils]: 27: Hoare triple {6064#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (not (bvsge v_prenex_7 main_~MINVAL~0)) (bvsge v_prenex_7 (_ bv1 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (bvsge (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {6064#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (not (bvsge v_prenex_7 main_~MINVAL~0)) (bvsge v_prenex_7 (_ bv1 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (bvsge (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:13,651 INFO L273 TraceCheckUtils]: 28: Hoare triple {6064#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (not (bvsge v_prenex_7 main_~MINVAL~0)) (bvsge v_prenex_7 (_ bv1 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (bvsge (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {6071#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (not (bvsge v_prenex_7 main_~MINVAL~0)) (bvsge v_prenex_7 (_ bv1 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (bvsge (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:13,658 INFO L273 TraceCheckUtils]: 29: Hoare triple {6071#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (not (bvsge v_prenex_7 main_~MINVAL~0)) (bvsge v_prenex_7 (_ bv1 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (bvsge (_ bv2 32) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {6075#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (not (bvsge v_prenex_7 main_~MINVAL~0)) (bvsge v_prenex_7 (_ bv1 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (bvsge (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:13,664 INFO L273 TraceCheckUtils]: 30: Hoare triple {6075#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (not (bvsge v_prenex_7 main_~MINVAL~0)) (bvsge v_prenex_7 (_ bv1 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (bvsge (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {6075#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (not (bvsge v_prenex_7 main_~MINVAL~0)) (bvsge v_prenex_7 (_ bv1 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (bvsge (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:13,670 INFO L273 TraceCheckUtils]: 31: Hoare triple {6075#(and (exists ((v_prenex_7 (_ BitVec 32))) (and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (not (bvsge v_prenex_7 main_~MINVAL~0)) (bvsge v_prenex_7 (_ bv1 32)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967284 32)))) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967280 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (bvsge (_ bv2 32) main_~MINVAL~0))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {6082#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (_ bv8 32)))) (bvsge v_prenex_7 (_ bv1 32)))) (bvsge (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:13,671 INFO L273 TraceCheckUtils]: 32: Hoare triple {6082#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (_ bv8 32)))) (bvsge v_prenex_7 (_ bv1 32)))) (bvsge (_ bv2 32) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {6082#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (_ bv8 32)))) (bvsge v_prenex_7 (_ bv1 32)))) (bvsge (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:13,672 INFO L273 TraceCheckUtils]: 33: Hoare triple {6082#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (_ bv8 32)))) (bvsge v_prenex_7 (_ bv1 32)))) (bvsge (_ bv2 32) main_~MINVAL~0))} assume !~bvsge32(~j~0, 1bv32); {6082#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (_ bv8 32)))) (bvsge v_prenex_7 (_ bv1 32)))) (bvsge (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:13,672 INFO L273 TraceCheckUtils]: 34: Hoare triple {6082#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (_ bv8 32)))) (bvsge v_prenex_7 (_ bv1 32)))) (bvsge (_ bv2 32) main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {6082#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (_ bv8 32)))) (bvsge v_prenex_7 (_ bv1 32)))) (bvsge (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:13,673 INFO L273 TraceCheckUtils]: 35: Hoare triple {6082#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (_ bv8 32)))) (bvsge v_prenex_7 (_ bv1 32)))) (bvsge (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {6082#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (_ bv8 32)))) (bvsge v_prenex_7 (_ bv1 32)))) (bvsge (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:13,674 INFO L273 TraceCheckUtils]: 36: Hoare triple {6082#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (_ bv8 32)))) (bvsge v_prenex_7 (_ bv1 32)))) (bvsge (_ bv2 32) main_~MINVAL~0))} ~i~0 := 0bv32; {6098#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (_ bv8 32)))) (bvsge v_prenex_7 (_ bv1 32)))) (bvsge (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:13,676 INFO L273 TraceCheckUtils]: 37: Hoare triple {6098#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (_ bv8 32)))) (bvsge v_prenex_7 (_ bv1 32)))) (bvsge (_ bv2 32) main_~MINVAL~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {6098#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (_ bv8 32)))) (bvsge v_prenex_7 (_ bv1 32)))) (bvsge (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:13,677 INFO L273 TraceCheckUtils]: 38: Hoare triple {6098#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (_ bv8 32)))) (bvsge v_prenex_7 (_ bv1 32)))) (bvsge (_ bv2 32) main_~MINVAL~0))} assume #t~short7; {6098#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (_ bv8 32)))) (bvsge v_prenex_7 (_ bv1 32)))) (bvsge (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:13,688 INFO L256 TraceCheckUtils]: 39: Hoare triple {6098#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (_ bv8 32)))) (bvsge v_prenex_7 (_ bv1 32)))) (bvsge (_ bv2 32) main_~MINVAL~0))} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {6108#(exists ((v_main_~MINVAL~0_BEFORE_CALL_1 (_ BitVec 32)) (v_prenex_7 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv12 32))) (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv16 32))) (bvsge (_ bv2 32) v_main_~MINVAL~0_BEFORE_CALL_1) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv20 32))) (bvsge v_prenex_7 (_ bv1 32)) (not (bvsge v_prenex_7 v_main_~MINVAL~0_BEFORE_CALL_1)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) (_ bv8 32))))))} is VALID [2018-11-23 10:30:13,689 INFO L273 TraceCheckUtils]: 40: Hoare triple {6108#(exists ((v_main_~MINVAL~0_BEFORE_CALL_1 (_ BitVec 32)) (v_prenex_7 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv12 32))) (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv16 32))) (bvsge (_ bv2 32) v_main_~MINVAL~0_BEFORE_CALL_1) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv20 32))) (bvsge v_prenex_7 (_ bv1 32)) (not (bvsge v_prenex_7 v_main_~MINVAL~0_BEFORE_CALL_1)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) (_ bv8 32))))))} ~cond := #in~cond; {6108#(exists ((v_main_~MINVAL~0_BEFORE_CALL_1 (_ BitVec 32)) (v_prenex_7 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv12 32))) (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv16 32))) (bvsge (_ bv2 32) v_main_~MINVAL~0_BEFORE_CALL_1) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv20 32))) (bvsge v_prenex_7 (_ bv1 32)) (not (bvsge v_prenex_7 v_main_~MINVAL~0_BEFORE_CALL_1)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) (_ bv8 32))))))} is VALID [2018-11-23 10:30:13,689 INFO L273 TraceCheckUtils]: 41: Hoare triple {6108#(exists ((v_main_~MINVAL~0_BEFORE_CALL_1 (_ BitVec 32)) (v_prenex_7 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv12 32))) (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv16 32))) (bvsge (_ bv2 32) v_main_~MINVAL~0_BEFORE_CALL_1) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv20 32))) (bvsge v_prenex_7 (_ bv1 32)) (not (bvsge v_prenex_7 v_main_~MINVAL~0_BEFORE_CALL_1)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) (_ bv8 32))))))} assume !(0bv32 == ~cond); {6108#(exists ((v_main_~MINVAL~0_BEFORE_CALL_1 (_ BitVec 32)) (v_prenex_7 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv12 32))) (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv16 32))) (bvsge (_ bv2 32) v_main_~MINVAL~0_BEFORE_CALL_1) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv20 32))) (bvsge v_prenex_7 (_ bv1 32)) (not (bvsge v_prenex_7 v_main_~MINVAL~0_BEFORE_CALL_1)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) (_ bv8 32))))))} is VALID [2018-11-23 10:30:13,690 INFO L273 TraceCheckUtils]: 42: Hoare triple {6108#(exists ((v_main_~MINVAL~0_BEFORE_CALL_1 (_ BitVec 32)) (v_prenex_7 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv12 32))) (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv16 32))) (bvsge (_ bv2 32) v_main_~MINVAL~0_BEFORE_CALL_1) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv20 32))) (bvsge v_prenex_7 (_ bv1 32)) (not (bvsge v_prenex_7 v_main_~MINVAL~0_BEFORE_CALL_1)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) (_ bv8 32))))))} assume true; {6108#(exists ((v_main_~MINVAL~0_BEFORE_CALL_1 (_ BitVec 32)) (v_prenex_7 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv12 32))) (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv16 32))) (bvsge (_ bv2 32) v_main_~MINVAL~0_BEFORE_CALL_1) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv20 32))) (bvsge v_prenex_7 (_ bv1 32)) (not (bvsge v_prenex_7 v_main_~MINVAL~0_BEFORE_CALL_1)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) (_ bv8 32))))))} is VALID [2018-11-23 10:30:13,690 INFO L268 TraceCheckUtils]: 43: Hoare quadruple {6108#(exists ((v_main_~MINVAL~0_BEFORE_CALL_1 (_ BitVec 32)) (v_prenex_7 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_5| (_ BitVec 32))) (and (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv8 32))) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv12 32))) (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv16 32))) (bvsge (_ bv2 32) v_main_~MINVAL~0_BEFORE_CALL_1) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (_ bv20 32))) (bvsge v_prenex_7 (_ bv1 32)) (not (bvsge v_prenex_7 v_main_~MINVAL~0_BEFORE_CALL_1)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_5|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) (_ bv8 32))))))} {6098#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (_ bv8 32)))) (bvsge v_prenex_7 (_ bv1 32)))) (bvsge (_ bv2 32) main_~MINVAL~0))} #87#return; {6098#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (_ bv8 32)))) (bvsge v_prenex_7 (_ bv1 32)))) (bvsge (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:13,692 INFO L273 TraceCheckUtils]: 44: Hoare triple {6098#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (_ bv8 32)))) (bvsge v_prenex_7 (_ bv1 32)))) (bvsge (_ bv2 32) main_~MINVAL~0))} havoc #t~mem6;havoc #t~mem5;havoc #t~short7; {6098#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (_ bv8 32)))) (bvsge v_prenex_7 (_ bv1 32)))) (bvsge (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:13,697 INFO L273 TraceCheckUtils]: 45: Hoare triple {6098#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (_ bv8 32)))) (bvsge v_prenex_7 (_ bv1 32)))) (bvsge (_ bv2 32) main_~MINVAL~0))} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {6127#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (_ bv8 32)))) (bvsge v_prenex_7 (_ bv1 32)))) (bvsge (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:30:13,702 INFO L273 TraceCheckUtils]: 46: Hoare triple {6127#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (exists ((v_prenex_7 (_ BitVec 32))) (and (not (bvsge v_prenex_7 main_~MINVAL~0)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg v_prenex_7)) |main_~#volArray~0.offset| (_ bv8 32)))) (bvsge v_prenex_7 (_ bv1 32)))) (bvsge (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {6131#(not |main_#t~short7|)} is VALID [2018-11-23 10:30:13,703 INFO L273 TraceCheckUtils]: 47: Hoare triple {6131#(not |main_#t~short7|)} assume #t~short7; {5972#false} is VALID [2018-11-23 10:30:13,703 INFO L256 TraceCheckUtils]: 48: Hoare triple {5972#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {5972#false} is VALID [2018-11-23 10:30:13,703 INFO L273 TraceCheckUtils]: 49: Hoare triple {5972#false} ~cond := #in~cond; {5972#false} is VALID [2018-11-23 10:30:13,703 INFO L273 TraceCheckUtils]: 50: Hoare triple {5972#false} assume !(0bv32 == ~cond); {5972#false} is VALID [2018-11-23 10:30:13,704 INFO L273 TraceCheckUtils]: 51: Hoare triple {5972#false} assume true; {5972#false} is VALID [2018-11-23 10:30:13,704 INFO L268 TraceCheckUtils]: 52: Hoare quadruple {5972#false} {5972#false} #87#return; {5972#false} is VALID [2018-11-23 10:30:13,704 INFO L273 TraceCheckUtils]: 53: Hoare triple {5972#false} havoc #t~mem6;havoc #t~mem5;havoc #t~short7; {5972#false} is VALID [2018-11-23 10:30:13,704 INFO L273 TraceCheckUtils]: 54: Hoare triple {5972#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {5972#false} is VALID [2018-11-23 10:30:13,704 INFO L273 TraceCheckUtils]: 55: Hoare triple {5972#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {5972#false} is VALID [2018-11-23 10:30:13,704 INFO L273 TraceCheckUtils]: 56: Hoare triple {5972#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {5972#false} is VALID [2018-11-23 10:30:13,704 INFO L256 TraceCheckUtils]: 57: Hoare triple {5972#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {5972#false} is VALID [2018-11-23 10:30:13,704 INFO L273 TraceCheckUtils]: 58: Hoare triple {5972#false} ~cond := #in~cond; {5972#false} is VALID [2018-11-23 10:30:13,705 INFO L273 TraceCheckUtils]: 59: Hoare triple {5972#false} assume 0bv32 == ~cond; {5972#false} is VALID [2018-11-23 10:30:13,705 INFO L273 TraceCheckUtils]: 60: Hoare triple {5972#false} assume !false; {5972#false} is VALID [2018-11-23 10:30:13,729 INFO L134 CoverageAnalysis]: Checked inductivity of 94 backedges. 18 proven. 72 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-23 10:30:13,729 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:30:16,955 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 50 [2018-11-23 10:30:16,966 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 50 treesize of output 54 [2018-11-23 10:30:16,979 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:17,025 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 54 treesize of output 74 [2018-11-23 10:30:17,038 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:17,039 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:17,040 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 59 treesize of output 83 [2018-11-23 10:30:17,054 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:17,054 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:17,056 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 4 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 95 [2018-11-23 10:30:17,213 WARN L180 SmtUtils]: Spent 126.00 ms on a formula simplification. DAG size of input: 36 DAG size of output: 35 [2018-11-23 10:30:17,228 WARN L307 Elim1Store]: Array PQE input equivalent to true [2018-11-23 10:30:17,229 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-11-23 10:30:17,244 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:19,250 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (= (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) [2018-11-23 10:30:19,252 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:19,252 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:19,253 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:19,253 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:19,257 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:19,259 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:19,261 INFO L303 Elim1Store]: Index analysis took 2027 ms [2018-11-23 10:30:19,262 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 79 [2018-11-23 10:30:19,267 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 10:30:19,289 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 10:30:19,318 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 10:30:21,413 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv8 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0) (bvadd |main_~#volArray~0.offset| .cse0))) [2018-11-23 10:30:21,419 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:21,422 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:21,423 INFO L303 Elim1Store]: Index analysis took 2033 ms [2018-11-23 10:30:21,424 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 96 [2018-11-23 10:30:21,446 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:21,450 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:21,492 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 5 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 69 treesize of output 142 [2018-11-23 10:30:25,904 WARN L180 SmtUtils]: Spent 4.36 s on a formula simplification. DAG size of input: 66 DAG size of output: 64 [2018-11-23 10:30:25,919 WARN L307 Elim1Store]: Array PQE input equivalent to true [2018-11-23 10:30:25,920 INFO L267 ElimStorePlain]: Start of recursive call 11: End of recursive call: and 1 xjuncts. [2018-11-23 10:30:25,939 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:27,942 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (= (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) [2018-11-23 10:30:29,952 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) [2018-11-23 10:30:29,966 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:29,966 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:29,967 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:29,967 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:29,972 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:31,996 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv8 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0) (bvadd |main_~#volArray~0.offset| .cse0 (_ bv8 32)))) [2018-11-23 10:30:32,004 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:32,008 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:32,010 INFO L303 Elim1Store]: Index analysis took 6084 ms [2018-11-23 10:30:32,011 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 8 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 68 treesize of output 129 [2018-11-23 10:30:32,015 INFO L267 ElimStorePlain]: Start of recursive call 12: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 10:30:32,163 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:34,168 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (= (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) [2018-11-23 10:30:34,171 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:34,172 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:34,173 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:34,173 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:34,178 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:34,182 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:34,183 INFO L303 Elim1Store]: Index analysis took 2028 ms [2018-11-23 10:30:34,184 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 88 [2018-11-23 10:30:34,193 INFO L267 ElimStorePlain]: Start of recursive call 13: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 10:30:34,258 INFO L267 ElimStorePlain]: Start of recursive call 10: 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-11-23 10:30:34,329 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-11-23 10:30:34,414 INFO L267 ElimStorePlain]: Start of recursive call 4: 2 dim-1 vars, End of recursive call: 3 dim-0 vars, and 3 xjuncts. [2018-11-23 10:30:34,501 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: 3 dim-0 vars, and 3 xjuncts. [2018-11-23 10:30:34,591 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 3 dim-0 vars, and 3 xjuncts. [2018-11-23 10:30:34,721 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 6 dim-0 vars, and 3 xjuncts. [2018-11-23 10:30:34,721 INFO L202 ElimStorePlain]: Needed 13 recursive calls to eliminate 3 variables, input treesize:63, output treesize:160 [2018-11-23 10:30:34,737 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:30:34,738 WARN L384 uantifierElimination]: Input elimination task: ∀ [|#memory_int|, |main_~#volArray~0.base|, main_~MINVAL~0]. (or (bvsge main_~j~0 main_~MINVAL~0) (not (bvsge (_ bv2 32) main_~MINVAL~0)) (bvsge (_ bv1 32) main_~MINVAL~0) (not (bvsge (select (let ((.cse0 (bvmul (_ bv8 32) main_~i~0))) (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| .cse0) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| .cse0 (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| .cse0 (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| .cse0 (_ bv12 32)) (_ bv0 32))) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))) [2018-11-23 10:30:34,738 WARN L385 uantifierElimination]: ElimStorePlain result: ∀ [v_prenex_12, v_arrayElimCell_21, v_prenex_11, v_arrayElimCell_22, main_~MINVAL~0, v_arrayElimCell_20]. (let ((.cse6 (bvmul (_ bv4 32) (bvneg main_~j~0))) (.cse2 (bvmul (_ bv8 32) main_~i~0))) (let ((.cse3 (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (.cse1 (bvadd .cse6 |main_~#volArray~0.offset| .cse2))) (let ((.cse0 (= .cse1 (bvadd |main_~#volArray~0.offset| .cse2))) (.cse4 (= (_ bv4294967288 32) .cse2)) (.cse5 (= (bvadd |main_~#volArray~0.offset| .cse2 (_ bv4 32)) .cse3))) (and (or .cse0 (bvsge main_~j~0 v_prenex_12) (= .cse1 (bvadd |main_~#volArray~0.offset| .cse2 (_ bv8 32))) (= .cse1 .cse3) (not (bvsge v_arrayElimCell_21 v_prenex_12)) (not (bvsge (_ bv2 32) v_prenex_12)) (bvsge (_ bv1 32) v_prenex_12) .cse4 .cse5) (or (bvsge main_~j~0 v_prenex_11) (not (bvsge v_arrayElimCell_22 v_prenex_11)) (not (= (bvadd .cse6 (_ bv4294967288 32)) (_ bv0 32))) (not (bvsge (_ bv2 32) v_prenex_11)) (bvsge (_ bv1 32) v_prenex_11) .cse4 .cse5) (or (bvsge main_~j~0 main_~MINVAL~0) (not .cse0) (not (bvsge v_arrayElimCell_20 main_~MINVAL~0)) (not (bvsge (_ bv2 32) main_~MINVAL~0)) (bvsge (_ bv1 32) main_~MINVAL~0) .cse4 .cse5))))) [2018-11-23 10:30:35,240 WARN L180 SmtUtils]: Spent 223.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 27 [2018-11-23 10:30:35,543 INFO L273 TraceCheckUtils]: 60: Hoare triple {5972#false} assume !false; {5972#false} is VALID [2018-11-23 10:30:35,543 INFO L273 TraceCheckUtils]: 59: Hoare triple {5972#false} assume 0bv32 == ~cond; {5972#false} is VALID [2018-11-23 10:30:35,544 INFO L273 TraceCheckUtils]: 58: Hoare triple {5972#false} ~cond := #in~cond; {5972#false} is VALID [2018-11-23 10:30:35,544 INFO L256 TraceCheckUtils]: 57: Hoare triple {5972#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {5972#false} is VALID [2018-11-23 10:30:35,544 INFO L273 TraceCheckUtils]: 56: Hoare triple {5972#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {5972#false} is VALID [2018-11-23 10:30:35,544 INFO L273 TraceCheckUtils]: 55: Hoare triple {5972#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {5972#false} is VALID [2018-11-23 10:30:35,545 INFO L273 TraceCheckUtils]: 54: Hoare triple {5972#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {5972#false} is VALID [2018-11-23 10:30:35,545 INFO L273 TraceCheckUtils]: 53: Hoare triple {5972#false} havoc #t~mem6;havoc #t~mem5;havoc #t~short7; {5972#false} is VALID [2018-11-23 10:30:35,545 INFO L268 TraceCheckUtils]: 52: Hoare quadruple {5971#true} {5972#false} #87#return; {5972#false} is VALID [2018-11-23 10:30:35,545 INFO L273 TraceCheckUtils]: 51: Hoare triple {5971#true} assume true; {5971#true} is VALID [2018-11-23 10:30:35,545 INFO L273 TraceCheckUtils]: 50: Hoare triple {5971#true} assume !(0bv32 == ~cond); {5971#true} is VALID [2018-11-23 10:30:35,546 INFO L273 TraceCheckUtils]: 49: Hoare triple {5971#true} ~cond := #in~cond; {5971#true} is VALID [2018-11-23 10:30:35,546 INFO L256 TraceCheckUtils]: 48: Hoare triple {5972#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {5971#true} is VALID [2018-11-23 10:30:35,546 INFO L273 TraceCheckUtils]: 47: Hoare triple {6131#(not |main_#t~short7|)} assume #t~short7; {5972#false} is VALID [2018-11-23 10:30:35,548 INFO L273 TraceCheckUtils]: 46: Hoare triple {6216#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {6131#(not |main_#t~short7|)} is VALID [2018-11-23 10:30:37,594 INFO L273 TraceCheckUtils]: 45: Hoare triple {6220#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {6216#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0))} is UNKNOWN [2018-11-23 10:30:37,595 INFO L273 TraceCheckUtils]: 44: Hoare triple {6220#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} havoc #t~mem6;havoc #t~mem5;havoc #t~short7; {6220#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-23 10:30:37,595 INFO L268 TraceCheckUtils]: 43: Hoare quadruple {5971#true} {6220#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} #87#return; {6220#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-23 10:30:37,595 INFO L273 TraceCheckUtils]: 42: Hoare triple {5971#true} assume true; {5971#true} is VALID [2018-11-23 10:30:37,596 INFO L273 TraceCheckUtils]: 41: Hoare triple {5971#true} assume !(0bv32 == ~cond); {5971#true} is VALID [2018-11-23 10:30:37,596 INFO L273 TraceCheckUtils]: 40: Hoare triple {5971#true} ~cond := #in~cond; {5971#true} is VALID [2018-11-23 10:30:37,596 INFO L256 TraceCheckUtils]: 39: Hoare triple {6220#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {5971#true} is VALID [2018-11-23 10:30:37,596 INFO L273 TraceCheckUtils]: 38: Hoare triple {6220#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} assume #t~short7; {6220#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-23 10:30:37,597 INFO L273 TraceCheckUtils]: 37: Hoare triple {6220#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {6220#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-23 10:30:37,598 INFO L273 TraceCheckUtils]: 36: Hoare triple {6248#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} ~i~0 := 0bv32; {6220#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-23 10:30:37,598 INFO L273 TraceCheckUtils]: 35: Hoare triple {6248#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32)); {6248#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-23 10:30:37,598 INFO L273 TraceCheckUtils]: 34: Hoare triple {6248#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {6248#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-23 10:30:37,599 INFO L273 TraceCheckUtils]: 33: Hoare triple {6248#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} assume !~bvsge32(~j~0, 1bv32); {6248#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-23 10:30:37,599 INFO L273 TraceCheckUtils]: 32: Hoare triple {6248#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {6248#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-23 10:30:37,973 INFO L273 TraceCheckUtils]: 31: Hoare triple {6264#(not (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {6248#(not (bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-23 10:30:37,974 INFO L273 TraceCheckUtils]: 30: Hoare triple {6264#(not (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {6264#(not (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-23 10:30:38,003 INFO L273 TraceCheckUtils]: 29: Hoare triple {6271#(not (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {6264#(not (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-23 10:30:38,227 INFO L273 TraceCheckUtils]: 28: Hoare triple {6275#(not (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {6271#(not (bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-23 10:30:38,228 INFO L273 TraceCheckUtils]: 27: Hoare triple {6275#(not (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {6275#(not (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-23 10:30:38,229 INFO L273 TraceCheckUtils]: 26: Hoare triple {6282#(not (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {6275#(not (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-23 10:30:38,240 INFO L273 TraceCheckUtils]: 25: Hoare triple {6286#(not (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {6282#(not (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-23 10:30:38,241 INFO L273 TraceCheckUtils]: 24: Hoare triple {6286#(not (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} assume !~bvsge32(~j~0, 1bv32); {6286#(not (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-23 10:30:38,241 INFO L273 TraceCheckUtils]: 23: Hoare triple {6286#(not (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {6286#(not (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-23 10:30:38,606 INFO L273 TraceCheckUtils]: 22: Hoare triple {6296#(or (bvsge main_~j~0 main_~MINVAL~0) (not (bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {6286#(not (bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0))} is VALID [2018-11-23 10:30:38,611 INFO L273 TraceCheckUtils]: 21: Hoare triple {6296#(or (bvsge main_~j~0 main_~MINVAL~0) (not (bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)))} assume !!~bvsge32(~j~0, 1bv32); {6296#(or (bvsge main_~j~0 main_~MINVAL~0) (not (bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)))} is VALID [2018-11-23 10:30:38,654 INFO L273 TraceCheckUtils]: 20: Hoare triple {6303#(or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {6296#(or (bvsge main_~j~0 main_~MINVAL~0) (not (bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)))} is VALID [2018-11-23 10:30:38,986 INFO L273 TraceCheckUtils]: 19: Hoare triple {6307#(or (not (bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge main_~j~0 main_~MINVAL~0)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {6303#(or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)))} is VALID [2018-11-23 10:30:38,987 INFO L273 TraceCheckUtils]: 18: Hoare triple {6307#(or (not (bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge main_~j~0 main_~MINVAL~0)))} assume !!~bvsge32(~j~0, 1bv32); {6307#(or (not (bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge main_~j~0 main_~MINVAL~0)))} is VALID [2018-11-23 10:30:39,004 INFO L273 TraceCheckUtils]: 17: Hoare triple {6314#(or (not (bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)) (not (bvsge (_ bv2 32) main_~MINVAL~0)) (bvsge (_ bv1 32) main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {6307#(or (not (bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (not (bvsge main_~j~0 main_~MINVAL~0)))} is VALID [2018-11-23 10:30:39,010 INFO L273 TraceCheckUtils]: 16: Hoare triple {6318#(or (not (bvsge (_ bv2 32) main_~MINVAL~0)) (bvsge (_ bv1 32) main_~MINVAL~0) (not (bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {6314#(or (not (bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967288 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)) (not (bvsge (_ bv2 32) main_~MINVAL~0)) (bvsge (_ bv1 32) main_~MINVAL~0))} is VALID [2018-11-23 10:30:39,010 INFO L273 TraceCheckUtils]: 15: Hoare triple {6318#(or (not (bvsge (_ bv2 32) main_~MINVAL~0)) (bvsge (_ bv1 32) main_~MINVAL~0) (not (bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)))} assume !~bvsge32(~j~0, 1bv32); {6318#(or (not (bvsge (_ bv2 32) main_~MINVAL~0)) (bvsge (_ bv1 32) main_~MINVAL~0) (not (bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)))} is VALID [2018-11-23 10:30:39,010 INFO L273 TraceCheckUtils]: 14: Hoare triple {6318#(or (not (bvsge (_ bv2 32) main_~MINVAL~0)) (bvsge (_ bv1 32) main_~MINVAL~0) (not (bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {6318#(or (not (bvsge (_ bv2 32) main_~MINVAL~0)) (bvsge (_ bv1 32) main_~MINVAL~0) (not (bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)))} is VALID [2018-11-23 10:30:39,249 INFO L273 TraceCheckUtils]: 13: Hoare triple {6328#(or (forall ((v_arrayElimCell_21 (_ BitVec 32)) (v_prenex_12 (_ BitVec 32))) (or (bvsge main_~j~0 v_prenex_12) (bvsge (_ bv1 32) v_prenex_12) (not (bvsge (_ bv2 32) v_prenex_12)) (not (bvsge v_arrayElimCell_21 v_prenex_12)))) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (bvmul (_ bv8 32) main_~i~0) (_ bv0 32)) (= (_ bv4294967288 32) (bvmul (_ bv8 32) main_~i~0)))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {6318#(or (not (bvsge (_ bv2 32) main_~MINVAL~0)) (bvsge (_ bv1 32) main_~MINVAL~0) (not (bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv4 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv8 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)))} is VALID [2018-11-23 10:30:39,255 INFO L273 TraceCheckUtils]: 12: Hoare triple {6332#(or (= (bvmul (_ bv8 32) main_~i~0) (_ bv0 32)) (= (_ bv4294967288 32) (bvmul (_ bv8 32) main_~i~0)) (forall ((v_arrayElimCell_21 (_ BitVec 32)) (main_~j~0 (_ BitVec 32)) (v_prenex_12 (_ BitVec 32))) (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32))) (bvsge main_~j~0 v_prenex_12) (bvsge (_ bv1 32) v_prenex_12) (not (bvsge (_ bv2 32) v_prenex_12)) (not (bvsge v_arrayElimCell_21 v_prenex_12)))))} assume !!~bvsge32(~j~0, 1bv32); {6328#(or (forall ((v_arrayElimCell_21 (_ BitVec 32)) (v_prenex_12 (_ BitVec 32))) (or (bvsge main_~j~0 v_prenex_12) (bvsge (_ bv1 32) v_prenex_12) (not (bvsge (_ bv2 32) v_prenex_12)) (not (bvsge v_arrayElimCell_21 v_prenex_12)))) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (= (bvmul (_ bv8 32) main_~i~0) (_ bv0 32)) (= (_ bv4294967288 32) (bvmul (_ bv8 32) main_~i~0)))} is VALID [2018-11-23 10:30:39,256 INFO L273 TraceCheckUtils]: 11: Hoare triple {6332#(or (= (bvmul (_ bv8 32) main_~i~0) (_ bv0 32)) (= (_ bv4294967288 32) (bvmul (_ bv8 32) main_~i~0)) (forall ((v_arrayElimCell_21 (_ BitVec 32)) (main_~j~0 (_ BitVec 32)) (v_prenex_12 (_ BitVec 32))) (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32))) (bvsge main_~j~0 v_prenex_12) (bvsge (_ bv1 32) v_prenex_12) (not (bvsge (_ bv2 32) v_prenex_12)) (not (bvsge v_arrayElimCell_21 v_prenex_12)))))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {6332#(or (= (bvmul (_ bv8 32) main_~i~0) (_ bv0 32)) (= (_ bv4294967288 32) (bvmul (_ bv8 32) main_~i~0)) (forall ((v_arrayElimCell_21 (_ BitVec 32)) (main_~j~0 (_ BitVec 32)) (v_prenex_12 (_ BitVec 32))) (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32))) (bvsge main_~j~0 v_prenex_12) (bvsge (_ bv1 32) v_prenex_12) (not (bvsge (_ bv2 32) v_prenex_12)) (not (bvsge v_arrayElimCell_21 v_prenex_12)))))} is VALID [2018-11-23 10:30:39,256 INFO L273 TraceCheckUtils]: 10: Hoare triple {6332#(or (= (bvmul (_ bv8 32) main_~i~0) (_ bv0 32)) (= (_ bv4294967288 32) (bvmul (_ bv8 32) main_~i~0)) (forall ((v_arrayElimCell_21 (_ BitVec 32)) (main_~j~0 (_ BitVec 32)) (v_prenex_12 (_ BitVec 32))) (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32))) (bvsge main_~j~0 v_prenex_12) (bvsge (_ bv1 32) v_prenex_12) (not (bvsge (_ bv2 32) v_prenex_12)) (not (bvsge v_arrayElimCell_21 v_prenex_12)))))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(2bv32, ~i~0), ~j~0))), 4bv32); {6332#(or (= (bvmul (_ bv8 32) main_~i~0) (_ bv0 32)) (= (_ bv4294967288 32) (bvmul (_ bv8 32) main_~i~0)) (forall ((v_arrayElimCell_21 (_ BitVec 32)) (main_~j~0 (_ BitVec 32)) (v_prenex_12 (_ BitVec 32))) (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32))) (bvsge main_~j~0 v_prenex_12) (bvsge (_ bv1 32) v_prenex_12) (not (bvsge (_ bv2 32) v_prenex_12)) (not (bvsge v_arrayElimCell_21 v_prenex_12)))))} is VALID [2018-11-23 10:30:39,257 INFO L273 TraceCheckUtils]: 9: Hoare triple {6332#(or (= (bvmul (_ bv8 32) main_~i~0) (_ bv0 32)) (= (_ bv4294967288 32) (bvmul (_ bv8 32) main_~i~0)) (forall ((v_arrayElimCell_21 (_ BitVec 32)) (main_~j~0 (_ BitVec 32)) (v_prenex_12 (_ BitVec 32))) (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32))) (bvsge main_~j~0 v_prenex_12) (bvsge (_ bv1 32) v_prenex_12) (not (bvsge (_ bv2 32) v_prenex_12)) (not (bvsge v_arrayElimCell_21 v_prenex_12)))))} assume !!~bvsge32(~j~0, 1bv32); {6332#(or (= (bvmul (_ bv8 32) main_~i~0) (_ bv0 32)) (= (_ bv4294967288 32) (bvmul (_ bv8 32) main_~i~0)) (forall ((v_arrayElimCell_21 (_ BitVec 32)) (main_~j~0 (_ BitVec 32)) (v_prenex_12 (_ BitVec 32))) (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32))) (bvsge main_~j~0 v_prenex_12) (bvsge (_ bv1 32) v_prenex_12) (not (bvsge (_ bv2 32) v_prenex_12)) (not (bvsge v_arrayElimCell_21 v_prenex_12)))))} is VALID [2018-11-23 10:30:39,257 INFO L273 TraceCheckUtils]: 8: Hoare triple {6332#(or (= (bvmul (_ bv8 32) main_~i~0) (_ bv0 32)) (= (_ bv4294967288 32) (bvmul (_ bv8 32) main_~i~0)) (forall ((v_arrayElimCell_21 (_ BitVec 32)) (main_~j~0 (_ BitVec 32)) (v_prenex_12 (_ BitVec 32))) (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32))) (bvsge main_~j~0 v_prenex_12) (bvsge (_ bv1 32) v_prenex_12) (not (bvsge (_ bv2 32) v_prenex_12)) (not (bvsge v_arrayElimCell_21 v_prenex_12)))))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 2bv32));~j~0 := 2bv32; {6332#(or (= (bvmul (_ bv8 32) main_~i~0) (_ bv0 32)) (= (_ bv4294967288 32) (bvmul (_ bv8 32) main_~i~0)) (forall ((v_arrayElimCell_21 (_ BitVec 32)) (main_~j~0 (_ BitVec 32)) (v_prenex_12 (_ BitVec 32))) (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32))) (bvsge main_~j~0 v_prenex_12) (bvsge (_ bv1 32) v_prenex_12) (not (bvsge (_ bv2 32) v_prenex_12)) (not (bvsge v_arrayElimCell_21 v_prenex_12)))))} is VALID [2018-11-23 10:30:39,259 INFO L273 TraceCheckUtils]: 7: Hoare triple {5971#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 2bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 2bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {6332#(or (= (bvmul (_ bv8 32) main_~i~0) (_ bv0 32)) (= (_ bv4294967288 32) (bvmul (_ bv8 32) main_~i~0)) (forall ((v_arrayElimCell_21 (_ BitVec 32)) (main_~j~0 (_ BitVec 32)) (v_prenex_12 (_ BitVec 32))) (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv8 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32))) (bvsge main_~j~0 v_prenex_12) (bvsge (_ bv1 32) v_prenex_12) (not (bvsge (_ bv2 32) v_prenex_12)) (not (bvsge v_arrayElimCell_21 v_prenex_12)))))} is VALID [2018-11-23 10:30:39,260 INFO L273 TraceCheckUtils]: 6: Hoare triple {5971#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~DEFAULTVALUE~0 := 1bv32;~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {5971#true} is VALID [2018-11-23 10:30:39,260 INFO L273 TraceCheckUtils]: 5: Hoare triple {5971#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {5971#true} is VALID [2018-11-23 10:30:39,260 INFO L256 TraceCheckUtils]: 4: Hoare triple {5971#true} call #t~ret8 := main(); {5971#true} is VALID [2018-11-23 10:30:39,260 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {5971#true} {5971#true} #83#return; {5971#true} is VALID [2018-11-23 10:30:39,260 INFO L273 TraceCheckUtils]: 2: Hoare triple {5971#true} assume true; {5971#true} is VALID [2018-11-23 10:30:39,260 INFO L273 TraceCheckUtils]: 1: Hoare triple {5971#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {5971#true} is VALID [2018-11-23 10:30:39,261 INFO L256 TraceCheckUtils]: 0: Hoare triple {5971#true} call ULTIMATE.init(); {5971#true} is VALID [2018-11-23 10:30:39,274 INFO L134 CoverageAnalysis]: Checked inductivity of 94 backedges. 20 proven. 68 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-23 10:30:39,276 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:30:39,276 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 18] total 35 [2018-11-23 10:30:39,276 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 61 [2018-11-23 10:30:39,277 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:30:39,277 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 35 states. [2018-11-23 10:30:45,440 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 102 edges. 100 inductive. 0 not inductive. 2 times theorem prover too weak to decide inductivity. [2018-11-23 10:30:45,440 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-11-23 10:30:45,441 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-11-23 10:30:45,441 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=238, Invalid=952, Unknown=0, NotChecked=0, Total=1190 [2018-11-23 10:30:45,442 INFO L87 Difference]: Start difference. First operand 103 states and 116 transitions. Second operand 35 states. [2018-11-23 10:30:47,201 WARN L180 SmtUtils]: Spent 238.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 45 [2018-11-23 10:30:50,426 WARN L180 SmtUtils]: Spent 348.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 53 [2018-11-23 10:30:52,197 WARN L180 SmtUtils]: Spent 489.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 40 [2018-11-23 10:30:53,186 WARN L180 SmtUtils]: Spent 344.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 36 [2018-11-23 10:30:54,219 WARN L180 SmtUtils]: Spent 493.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 45 [2018-11-23 10:30:55,327 WARN L180 SmtUtils]: Spent 336.00 ms on a formula simplification. DAG size of input: 73 DAG size of output: 35 [2018-11-23 10:30:56,614 WARN L180 SmtUtils]: Spent 278.00 ms on a formula simplification. DAG size of input: 85 DAG size of output: 39 [2018-11-23 10:30:57,909 WARN L180 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 39 [2018-11-23 10:31:02,142 WARN L180 SmtUtils]: Spent 1.25 s on a formula simplification. DAG size of input: 99 DAG size of output: 82 [2018-11-23 10:31:05,263 WARN L180 SmtUtils]: Spent 202.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 50 [2018-11-23 10:31:06,005 WARN L180 SmtUtils]: Spent 214.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 60 [2018-11-23 10:31:09,223 WARN L180 SmtUtils]: Spent 204.00 ms on a formula simplification that was a NOOP. DAG size: 78 [2018-11-23 10:31:13,386 WARN L180 SmtUtils]: Spent 577.00 ms on a formula simplification. DAG size of input: 92 DAG size of output: 64 [2018-11-23 10:31:16,824 WARN L180 SmtUtils]: Spent 164.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 38 [2018-11-23 10:31:18,288 WARN L180 SmtUtils]: Spent 353.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 51 [2018-11-23 10:31:21,239 WARN L180 SmtUtils]: Spent 494.00 ms on a formula simplification. DAG size of input: 76 DAG size of output: 48 [2018-11-23 10:31:24,995 WARN L180 SmtUtils]: Spent 945.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 67 [2018-11-23 10:31:25,914 WARN L180 SmtUtils]: Spent 230.00 ms on a formula simplification that was a NOOP. DAG size: 55 [2018-11-23 10:31:29,797 WARN L180 SmtUtils]: Spent 155.00 ms on a formula simplification that was a NOOP. DAG size: 56