java -ea -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc ../../../trunk/examples/toolchains/AutomizerCInline_WitnessPrinter.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf -i ../../../trunk/examples/svcomp/array-tiling/nr3_true-unreach-call.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-61f4311 [2018-11-23 10:28:44,685 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 10:28:44,687 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 10:28:44,701 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 10:28:44,701 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 10:28:44,702 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 10:28:44,703 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 10:28:44,706 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 10:28:44,708 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 10:28:44,708 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 10:28:44,710 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 10:28:44,710 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 10:28:44,711 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 10:28:44,712 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 10:28:44,713 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 10:28:44,714 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 10:28:44,715 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 10:28:44,717 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 10:28:44,719 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 10:28:44,721 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 10:28:44,722 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 10:28:44,724 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 10:28:44,726 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 10:28:44,727 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 10:28:44,727 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 10:28:44,728 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 10:28:44,729 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 10:28:44,730 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 10:28:44,731 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 10:28:44,732 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 10:28:44,732 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 10:28:44,733 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 10:28:44,733 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 10:28:44,733 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 10:28:44,734 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 10:28:44,735 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 10:28:44,735 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf [2018-11-23 10:28:44,767 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 10:28:44,767 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 10:28:44,768 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 10:28:44,768 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 10:28:44,772 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 10:28:44,772 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 10:28:44,772 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 10:28:44,772 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 10:28:44,773 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 10:28:44,773 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 10:28:44,773 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 10:28:44,773 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 10:28:44,773 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 10:28:44,775 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 10:28:44,775 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-23 10:28:44,775 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-23 10:28:44,775 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 10:28:44,776 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 10:28:44,776 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 10:28:44,776 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 10:28:44,776 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 10:28:44,776 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 10:28:44,778 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 10:28:44,778 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 10:28:44,778 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 10:28:44,779 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 10:28:44,779 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 10:28:44,779 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 10:28:44,779 INFO L133 SettingsManager]: * Trace refinement strategy=WOLF [2018-11-23 10:28:44,780 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 10:28:44,780 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-11-23 10:28:44,780 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-11-23 10:28:44,780 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-23 10:28:44,840 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 10:28:44,854 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 10:28:44,858 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 10:28:44,860 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 10:28:44,861 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 10:28:44,862 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-tiling/nr3_true-unreach-call.i [2018-11-23 10:28:44,926 INFO L221 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/e022d078e/9e2317eba95b4473b467430a4788f5e7/FLAG10aa70242 [2018-11-23 10:28:45,422 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 10:28:45,422 INFO L161 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-tiling/nr3_true-unreach-call.i [2018-11-23 10:28:45,429 INFO L355 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/e022d078e/9e2317eba95b4473b467430a4788f5e7/FLAG10aa70242 [2018-11-23 10:28:45,733 INFO L363 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/e022d078e/9e2317eba95b4473b467430a4788f5e7 [2018-11-23 10:28:45,747 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 10:28:45,749 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 10:28:45,750 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 10:28:45,750 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 10:28:45,754 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 10:28:45,756 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 10:28:45" (1/1) ... [2018-11-23 10:28:45,760 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@570efbb1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:45, skipping insertion in model container [2018-11-23 10:28:45,760 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 10:28:45" (1/1) ... [2018-11-23 10:28:45,771 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 10:28:45,800 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 10:28:46,039 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 10:28:46,050 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 10:28:46,082 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 10:28:46,113 INFO L195 MainTranslator]: Completed translation [2018-11-23 10:28:46,114 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:46 WrapperNode [2018-11-23 10:28:46,114 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 10:28:46,115 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 10:28:46,115 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 10:28:46,115 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 10:28:46,124 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:46" (1/1) ... [2018-11-23 10:28:46,134 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:46" (1/1) ... [2018-11-23 10:28:46,142 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 10:28:46,142 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 10:28:46,142 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 10:28:46,143 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 10:28:46,151 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:46" (1/1) ... [2018-11-23 10:28:46,151 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:46" (1/1) ... [2018-11-23 10:28:46,154 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:46" (1/1) ... [2018-11-23 10:28:46,154 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:46" (1/1) ... [2018-11-23 10:28:46,169 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:46" (1/1) ... [2018-11-23 10:28:46,177 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:46" (1/1) ... [2018-11-23 10:28:46,179 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:46" (1/1) ... [2018-11-23 10:28:46,182 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 10:28:46,183 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 10:28:46,183 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 10:28:46,183 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 10:28:46,184 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:46" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 10:28:46,318 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-23 10:28:46,318 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-23 10:28:46,318 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-23 10:28:46,318 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE4 [2018-11-23 10:28:46,318 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 10:28:46,318 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 10:28:46,318 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-23 10:28:46,319 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-23 10:28:46,319 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-11-23 10:28:46,319 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-11-23 10:28:46,319 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE4 [2018-11-23 10:28:46,319 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-23 10:28:47,062 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 10:28:47,062 INFO L280 CfgBuilder]: Removed 3 assue(true) statements. [2018-11-23 10:28:47,062 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 10:28:47 BoogieIcfgContainer [2018-11-23 10:28:47,063 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 10:28:47,065 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 10:28:47,065 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 10:28:47,069 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 10:28:47,070 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 10:28:45" (1/3) ... [2018-11-23 10:28:47,071 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5059f032 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 10:28:47, skipping insertion in model container [2018-11-23 10:28:47,071 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:46" (2/3) ... [2018-11-23 10:28:47,072 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5059f032 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 10:28:47, skipping insertion in model container [2018-11-23 10:28:47,072 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 10:28:47" (3/3) ... [2018-11-23 10:28:47,074 INFO L112 eAbstractionObserver]: Analyzing ICFG nr3_true-unreach-call.i [2018-11-23 10:28:47,082 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 10:28:47,091 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-23 10:28:47,109 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-23 10:28:47,144 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 10:28:47,144 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 10:28:47,145 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 10:28:47,145 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 10:28:47,146 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 10:28:47,146 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 10:28:47,146 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 10:28:47,146 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 10:28:47,146 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 10:28:47,171 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states. [2018-11-23 10:28:47,178 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-11-23 10:28:47,179 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:47,180 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:47,182 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:47,188 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:47,189 INFO L82 PathProgramCache]: Analyzing trace with hash 1453831941, now seen corresponding path program 1 times [2018-11-23 10:28:47,193 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:47,194 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:47,214 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:28:47,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:47,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:47,327 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:47,701 INFO L256 TraceCheckUtils]: 0: Hoare triple {34#true} call ULTIMATE.init(); {34#true} is VALID [2018-11-23 10:28:47,705 INFO L273 TraceCheckUtils]: 1: Hoare triple {34#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {34#true} is VALID [2018-11-23 10:28:47,706 INFO L273 TraceCheckUtils]: 2: Hoare triple {34#true} assume true; {34#true} is VALID [2018-11-23 10:28:47,706 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {34#true} {34#true} #83#return; {34#true} is VALID [2018-11-23 10:28:47,706 INFO L256 TraceCheckUtils]: 4: Hoare triple {34#true} call #t~ret8 := main(); {34#true} is VALID [2018-11-23 10:28:47,707 INFO L273 TraceCheckUtils]: 5: Hoare triple {34#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {34#true} is VALID [2018-11-23 10:28:47,707 INFO L273 TraceCheckUtils]: 6: Hoare triple {34#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {34#true} is VALID [2018-11-23 10:28:47,707 INFO L273 TraceCheckUtils]: 7: Hoare triple {34#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {34#true} is VALID [2018-11-23 10:28:47,708 INFO L273 TraceCheckUtils]: 8: Hoare triple {34#true} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {34#true} is VALID [2018-11-23 10:28:47,708 INFO L273 TraceCheckUtils]: 9: Hoare triple {34#true} ~i~0 := 0bv32; {34#true} is VALID [2018-11-23 10:28:47,708 INFO L273 TraceCheckUtils]: 10: Hoare triple {34#true} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {34#true} is VALID [2018-11-23 10:28:47,722 INFO L273 TraceCheckUtils]: 11: Hoare triple {34#true} assume #t~short7; {72#|main_#t~short7|} is VALID [2018-11-23 10:28:47,736 INFO L256 TraceCheckUtils]: 12: Hoare triple {72#|main_#t~short7|} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {76#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:47,751 INFO L273 TraceCheckUtils]: 13: Hoare triple {76#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {80#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:47,761 INFO L273 TraceCheckUtils]: 14: Hoare triple {80#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 == ~cond; {35#false} is VALID [2018-11-23 10:28:47,761 INFO L273 TraceCheckUtils]: 15: Hoare triple {35#false} assume !false; {35#false} is VALID [2018-11-23 10:28:47,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:47,766 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:28:47,771 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:28:47,772 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 10:28:47,777 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 16 [2018-11-23 10:28:47,780 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:28:47,783 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states. [2018-11-23 10:28:47,864 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 16 edges. 16 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:47,864 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 10:28:47,873 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 10:28:47,873 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 10:28:47,876 INFO L87 Difference]: Start difference. First operand 31 states. Second operand 5 states. [2018-11-23 10:28:48,837 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:48,837 INFO L93 Difference]: Finished difference Result 60 states and 81 transitions. [2018-11-23 10:28:48,838 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 10:28:48,838 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 16 [2018-11-23 10:28:48,838 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:28:48,839 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-23 10:28:48,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 81 transitions. [2018-11-23 10:28:48,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-23 10:28:48,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 81 transitions. [2018-11-23 10:28:48,859 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states and 81 transitions. [2018-11-23 10:28:49,550 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 81 edges. 81 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:49,566 INFO L225 Difference]: With dead ends: 60 [2018-11-23 10:28:49,566 INFO L226 Difference]: Without dead ends: 31 [2018-11-23 10:28:49,570 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 10:28:49,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2018-11-23 10:28:49,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 30. [2018-11-23 10:28:49,761 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:28:49,762 INFO L82 GeneralOperation]: Start isEquivalent. First operand 31 states. Second operand 30 states. [2018-11-23 10:28:49,763 INFO L74 IsIncluded]: Start isIncluded. First operand 31 states. Second operand 30 states. [2018-11-23 10:28:49,763 INFO L87 Difference]: Start difference. First operand 31 states. Second operand 30 states. [2018-11-23 10:28:49,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:49,768 INFO L93 Difference]: Finished difference Result 31 states and 35 transitions. [2018-11-23 10:28:49,769 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 35 transitions. [2018-11-23 10:28:49,769 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:49,770 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:49,770 INFO L74 IsIncluded]: Start isIncluded. First operand 30 states. Second operand 31 states. [2018-11-23 10:28:49,770 INFO L87 Difference]: Start difference. First operand 30 states. Second operand 31 states. [2018-11-23 10:28:49,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:49,780 INFO L93 Difference]: Finished difference Result 31 states and 35 transitions. [2018-11-23 10:28:49,781 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 35 transitions. [2018-11-23 10:28:49,782 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:49,782 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:49,782 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:28:49,782 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:28:49,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-11-23 10:28:49,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 34 transitions. [2018-11-23 10:28:49,790 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 34 transitions. Word has length 16 [2018-11-23 10:28:49,791 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:28:49,791 INFO L480 AbstractCegarLoop]: Abstraction has 30 states and 34 transitions. [2018-11-23 10:28:49,791 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 10:28:49,791 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 34 transitions. [2018-11-23 10:28:49,792 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-11-23 10:28:49,792 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:49,793 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:49,794 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:49,794 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:49,794 INFO L82 PathProgramCache]: Analyzing trace with hash 1455678983, now seen corresponding path program 1 times [2018-11-23 10:28:49,795 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:49,795 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:49,823 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:28:50,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:50,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:50,099 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:50,389 WARN L180 SmtUtils]: Spent 182.00 ms on a formula simplification that was a NOOP. DAG size: 12 [2018-11-23 10:28:50,427 INFO L256 TraceCheckUtils]: 0: Hoare triple {267#true} call ULTIMATE.init(); {267#true} is VALID [2018-11-23 10:28:50,427 INFO L273 TraceCheckUtils]: 1: Hoare triple {267#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {267#true} is VALID [2018-11-23 10:28:50,428 INFO L273 TraceCheckUtils]: 2: Hoare triple {267#true} assume true; {267#true} is VALID [2018-11-23 10:28:50,428 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {267#true} {267#true} #83#return; {267#true} is VALID [2018-11-23 10:28:50,429 INFO L256 TraceCheckUtils]: 4: Hoare triple {267#true} call #t~ret8 := main(); {267#true} is VALID [2018-11-23 10:28:50,429 INFO L273 TraceCheckUtils]: 5: Hoare triple {267#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {267#true} is VALID [2018-11-23 10:28:50,448 INFO L273 TraceCheckUtils]: 6: Hoare triple {267#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {290#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} is VALID [2018-11-23 10:28:50,450 INFO L273 TraceCheckUtils]: 7: Hoare triple {290#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {294#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv3 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:50,470 INFO L273 TraceCheckUtils]: 8: Hoare triple {294#(and (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvsrem ~CELLCOUNT~0 (_ bv3 32)) (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {268#false} is VALID [2018-11-23 10:28:50,471 INFO L273 TraceCheckUtils]: 9: Hoare triple {268#false} ~i~0 := 0bv32; {268#false} is VALID [2018-11-23 10:28:50,471 INFO L273 TraceCheckUtils]: 10: Hoare triple {268#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {268#false} is VALID [2018-11-23 10:28:50,471 INFO L273 TraceCheckUtils]: 11: Hoare triple {268#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {268#false} is VALID [2018-11-23 10:28:50,472 INFO L256 TraceCheckUtils]: 12: Hoare triple {268#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {268#false} is VALID [2018-11-23 10:28:50,472 INFO L273 TraceCheckUtils]: 13: Hoare triple {268#false} ~cond := #in~cond; {268#false} is VALID [2018-11-23 10:28:50,472 INFO L273 TraceCheckUtils]: 14: Hoare triple {268#false} assume 0bv32 == ~cond; {268#false} is VALID [2018-11-23 10:28:50,473 INFO L273 TraceCheckUtils]: 15: Hoare triple {268#false} assume !false; {268#false} is VALID [2018-11-23 10:28:50,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:50,475 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:28:50,478 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:28:50,479 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 10:28:50,482 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2018-11-23 10:28:50,482 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:28:50,482 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states. [2018-11-23 10:28:50,542 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 16 edges. 16 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:50,543 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 10:28:50,543 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 10:28:50,543 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 10:28:50,544 INFO L87 Difference]: Start difference. First operand 30 states and 34 transitions. Second operand 4 states. [2018-11-23 10:28:51,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:51,782 INFO L93 Difference]: Finished difference Result 52 states and 60 transitions. [2018-11-23 10:28:51,782 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 10:28:51,782 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2018-11-23 10:28:51,783 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:28:51,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-23 10:28:51,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 50 transitions. [2018-11-23 10:28:51,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-23 10:28:51,791 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 50 transitions. [2018-11-23 10:28:51,791 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states and 50 transitions. [2018-11-23 10:28:52,117 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 50 edges. 50 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:52,119 INFO L225 Difference]: With dead ends: 52 [2018-11-23 10:28:52,120 INFO L226 Difference]: Without dead ends: 35 [2018-11-23 10:28:52,121 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 13 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 10:28:52,121 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states. [2018-11-23 10:28:52,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 31. [2018-11-23 10:28:52,145 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:28:52,146 INFO L82 GeneralOperation]: Start isEquivalent. First operand 35 states. Second operand 31 states. [2018-11-23 10:28:52,146 INFO L74 IsIncluded]: Start isIncluded. First operand 35 states. Second operand 31 states. [2018-11-23 10:28:52,146 INFO L87 Difference]: Start difference. First operand 35 states. Second operand 31 states. [2018-11-23 10:28:52,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:52,150 INFO L93 Difference]: Finished difference Result 35 states and 41 transitions. [2018-11-23 10:28:52,151 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 41 transitions. [2018-11-23 10:28:52,151 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:52,151 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:52,152 INFO L74 IsIncluded]: Start isIncluded. First operand 31 states. Second operand 35 states. [2018-11-23 10:28:52,152 INFO L87 Difference]: Start difference. First operand 31 states. Second operand 35 states. [2018-11-23 10:28:52,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:52,155 INFO L93 Difference]: Finished difference Result 35 states and 41 transitions. [2018-11-23 10:28:52,156 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 41 transitions. [2018-11-23 10:28:52,156 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:52,156 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:52,157 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:28:52,157 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:28:52,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2018-11-23 10:28:52,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 35 transitions. [2018-11-23 10:28:52,160 INFO L78 Accepts]: Start accepts. Automaton has 31 states and 35 transitions. Word has length 16 [2018-11-23 10:28:52,160 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:28:52,160 INFO L480 AbstractCegarLoop]: Abstraction has 31 states and 35 transitions. [2018-11-23 10:28:52,160 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 10:28:52,160 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 35 transitions. [2018-11-23 10:28:52,161 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-11-23 10:28:52,161 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:52,162 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:52,162 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:52,162 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:52,163 INFO L82 PathProgramCache]: Analyzing trace with hash -2089835012, now seen corresponding path program 1 times [2018-11-23 10:28:52,163 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:52,163 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:52,180 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:28:52,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:52,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:52,331 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:52,414 INFO L256 TraceCheckUtils]: 0: Hoare triple {501#true} call ULTIMATE.init(); {501#true} is VALID [2018-11-23 10:28:52,415 INFO L273 TraceCheckUtils]: 1: Hoare triple {501#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {501#true} is VALID [2018-11-23 10:28:52,415 INFO L273 TraceCheckUtils]: 2: Hoare triple {501#true} assume true; {501#true} is VALID [2018-11-23 10:28:52,415 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {501#true} {501#true} #83#return; {501#true} is VALID [2018-11-23 10:28:52,415 INFO L256 TraceCheckUtils]: 4: Hoare triple {501#true} call #t~ret8 := main(); {501#true} is VALID [2018-11-23 10:28:52,416 INFO L273 TraceCheckUtils]: 5: Hoare triple {501#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {501#true} is VALID [2018-11-23 10:28:52,416 INFO L273 TraceCheckUtils]: 6: Hoare triple {501#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {501#true} is VALID [2018-11-23 10:28:52,416 INFO L273 TraceCheckUtils]: 7: Hoare triple {501#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {501#true} is VALID [2018-11-23 10:28:52,421 INFO L273 TraceCheckUtils]: 8: Hoare triple {501#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32));~j~0 := 3bv32; {530#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:52,422 INFO L273 TraceCheckUtils]: 9: Hoare triple {530#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} assume !~bvsge32(~j~0, 1bv32); {502#false} is VALID [2018-11-23 10:28:52,422 INFO L273 TraceCheckUtils]: 10: Hoare triple {502#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {502#false} is VALID [2018-11-23 10:28:52,422 INFO L273 TraceCheckUtils]: 11: Hoare triple {502#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {502#false} is VALID [2018-11-23 10:28:52,423 INFO L273 TraceCheckUtils]: 12: Hoare triple {502#false} ~i~0 := 0bv32; {502#false} is VALID [2018-11-23 10:28:52,423 INFO L273 TraceCheckUtils]: 13: Hoare triple {502#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {502#false} is VALID [2018-11-23 10:28:52,423 INFO L273 TraceCheckUtils]: 14: Hoare triple {502#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {502#false} is VALID [2018-11-23 10:28:52,424 INFO L256 TraceCheckUtils]: 15: Hoare triple {502#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {502#false} is VALID [2018-11-23 10:28:52,424 INFO L273 TraceCheckUtils]: 16: Hoare triple {502#false} ~cond := #in~cond; {502#false} is VALID [2018-11-23 10:28:52,424 INFO L273 TraceCheckUtils]: 17: Hoare triple {502#false} assume 0bv32 == ~cond; {502#false} is VALID [2018-11-23 10:28:52,424 INFO L273 TraceCheckUtils]: 18: Hoare triple {502#false} assume !false; {502#false} is VALID [2018-11-23 10:28:52,426 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:52,426 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:28:52,429 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:28:52,429 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 10:28:52,430 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 19 [2018-11-23 10:28:52,430 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:28:52,431 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2018-11-23 10:28:52,503 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 19 edges. 19 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:52,503 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 10:28:52,503 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 10:28:52,504 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 10:28:52,504 INFO L87 Difference]: Start difference. First operand 31 states and 35 transitions. Second operand 3 states. [2018-11-23 10:28:52,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:52,786 INFO L93 Difference]: Finished difference Result 56 states and 66 transitions. [2018-11-23 10:28:52,786 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 10:28:52,786 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 19 [2018-11-23 10:28:52,786 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:28:52,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 10:28:52,789 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 55 transitions. [2018-11-23 10:28:52,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 10:28:52,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 55 transitions. [2018-11-23 10:28:52,793 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states and 55 transitions. [2018-11-23 10:28:53,006 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 55 edges. 55 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:53,009 INFO L225 Difference]: With dead ends: 56 [2018-11-23 10:28:53,009 INFO L226 Difference]: Without dead ends: 34 [2018-11-23 10:28:53,010 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 17 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 10:28:53,010 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-11-23 10:28:53,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 32. [2018-11-23 10:28:53,036 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:28:53,037 INFO L82 GeneralOperation]: Start isEquivalent. First operand 34 states. Second operand 32 states. [2018-11-23 10:28:53,037 INFO L74 IsIncluded]: Start isIncluded. First operand 34 states. Second operand 32 states. [2018-11-23 10:28:53,037 INFO L87 Difference]: Start difference. First operand 34 states. Second operand 32 states. [2018-11-23 10:28:53,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:53,041 INFO L93 Difference]: Finished difference Result 34 states and 39 transitions. [2018-11-23 10:28:53,041 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 39 transitions. [2018-11-23 10:28:53,042 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:53,042 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:53,042 INFO L74 IsIncluded]: Start isIncluded. First operand 32 states. Second operand 34 states. [2018-11-23 10:28:53,043 INFO L87 Difference]: Start difference. First operand 32 states. Second operand 34 states. [2018-11-23 10:28:53,045 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:53,045 INFO L93 Difference]: Finished difference Result 34 states and 39 transitions. [2018-11-23 10:28:53,046 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 39 transitions. [2018-11-23 10:28:53,046 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:53,046 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:53,047 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:28:53,047 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:28:53,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32 states. [2018-11-23 10:28:53,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 36 transitions. [2018-11-23 10:28:53,050 INFO L78 Accepts]: Start accepts. Automaton has 32 states and 36 transitions. Word has length 19 [2018-11-23 10:28:53,050 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:28:53,050 INFO L480 AbstractCegarLoop]: Abstraction has 32 states and 36 transitions. [2018-11-23 10:28:53,050 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 10:28:53,050 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 36 transitions. [2018-11-23 10:28:53,051 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-11-23 10:28:53,051 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:53,052 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:53,052 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:53,052 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:53,052 INFO L82 PathProgramCache]: Analyzing trace with hash 1382648830, now seen corresponding path program 1 times [2018-11-23 10:28:53,053 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:53,053 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:53,092 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:28:53,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:53,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:53,220 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:53,283 INFO L256 TraceCheckUtils]: 0: Hoare triple {749#true} call ULTIMATE.init(); {749#true} is VALID [2018-11-23 10:28:53,283 INFO L273 TraceCheckUtils]: 1: Hoare triple {749#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {749#true} is VALID [2018-11-23 10:28:53,284 INFO L273 TraceCheckUtils]: 2: Hoare triple {749#true} assume true; {749#true} is VALID [2018-11-23 10:28:53,284 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {749#true} {749#true} #83#return; {749#true} is VALID [2018-11-23 10:28:53,285 INFO L256 TraceCheckUtils]: 4: Hoare triple {749#true} call #t~ret8 := main(); {749#true} is VALID [2018-11-23 10:28:53,285 INFO L273 TraceCheckUtils]: 5: Hoare triple {749#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {749#true} is VALID [2018-11-23 10:28:53,286 INFO L273 TraceCheckUtils]: 6: Hoare triple {749#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {772#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:28:53,286 INFO L273 TraceCheckUtils]: 7: Hoare triple {772#(= (_ bv2 32) main_~MINVAL~0)} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {772#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:28:53,287 INFO L273 TraceCheckUtils]: 8: Hoare triple {772#(= (_ bv2 32) main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32));~j~0 := 3bv32; {779#(and (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:53,291 INFO L273 TraceCheckUtils]: 9: Hoare triple {779#(and (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {779#(and (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:53,292 INFO L273 TraceCheckUtils]: 10: Hoare triple {779#(and (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {750#false} is VALID [2018-11-23 10:28:53,292 INFO L273 TraceCheckUtils]: 11: Hoare triple {750#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {750#false} is VALID [2018-11-23 10:28:53,293 INFO L273 TraceCheckUtils]: 12: Hoare triple {750#false} assume !~bvsge32(~j~0, 1bv32); {750#false} is VALID [2018-11-23 10:28:53,293 INFO L273 TraceCheckUtils]: 13: Hoare triple {750#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {750#false} is VALID [2018-11-23 10:28:53,294 INFO L273 TraceCheckUtils]: 14: Hoare triple {750#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {750#false} is VALID [2018-11-23 10:28:53,294 INFO L273 TraceCheckUtils]: 15: Hoare triple {750#false} ~i~0 := 0bv32; {750#false} is VALID [2018-11-23 10:28:53,295 INFO L273 TraceCheckUtils]: 16: Hoare triple {750#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {750#false} is VALID [2018-11-23 10:28:53,295 INFO L273 TraceCheckUtils]: 17: Hoare triple {750#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {750#false} is VALID [2018-11-23 10:28:53,295 INFO L256 TraceCheckUtils]: 18: Hoare triple {750#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {750#false} is VALID [2018-11-23 10:28:53,296 INFO L273 TraceCheckUtils]: 19: Hoare triple {750#false} ~cond := #in~cond; {750#false} is VALID [2018-11-23 10:28:53,296 INFO L273 TraceCheckUtils]: 20: Hoare triple {750#false} assume 0bv32 == ~cond; {750#false} is VALID [2018-11-23 10:28:53,296 INFO L273 TraceCheckUtils]: 21: Hoare triple {750#false} assume !false; {750#false} is VALID [2018-11-23 10:28:53,297 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:53,298 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:28:53,300 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:28:53,300 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 10:28:53,300 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 22 [2018-11-23 10:28:53,301 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:28:53,302 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states. [2018-11-23 10:28:53,383 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 22 edges. 22 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:53,383 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 10:28:53,383 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 10:28:53,383 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 10:28:53,384 INFO L87 Difference]: Start difference. First operand 32 states and 36 transitions. Second operand 4 states. [2018-11-23 10:28:53,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:53,841 INFO L93 Difference]: Finished difference Result 57 states and 66 transitions. [2018-11-23 10:28:53,841 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 10:28:53,841 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 22 [2018-11-23 10:28:53,841 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:28:53,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-23 10:28:53,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 54 transitions. [2018-11-23 10:28:53,844 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-23 10:28:53,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 54 transitions. [2018-11-23 10:28:53,847 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states and 54 transitions. [2018-11-23 10:28:53,998 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 54 edges. 54 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:53,999 INFO L225 Difference]: With dead ends: 57 [2018-11-23 10:28:54,000 INFO L226 Difference]: Without dead ends: 34 [2018-11-23 10:28:54,000 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 19 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 10:28:54,001 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-11-23 10:28:54,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 33. [2018-11-23 10:28:54,027 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:28:54,028 INFO L82 GeneralOperation]: Start isEquivalent. First operand 34 states. Second operand 33 states. [2018-11-23 10:28:54,028 INFO L74 IsIncluded]: Start isIncluded. First operand 34 states. Second operand 33 states. [2018-11-23 10:28:54,028 INFO L87 Difference]: Start difference. First operand 34 states. Second operand 33 states. [2018-11-23 10:28:54,029 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:54,030 INFO L93 Difference]: Finished difference Result 34 states and 38 transitions. [2018-11-23 10:28:54,030 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 38 transitions. [2018-11-23 10:28:54,030 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:54,031 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:54,031 INFO L74 IsIncluded]: Start isIncluded. First operand 33 states. Second operand 34 states. [2018-11-23 10:28:54,031 INFO L87 Difference]: Start difference. First operand 33 states. Second operand 34 states. [2018-11-23 10:28:54,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:54,033 INFO L93 Difference]: Finished difference Result 34 states and 38 transitions. [2018-11-23 10:28:54,033 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 38 transitions. [2018-11-23 10:28:54,034 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:54,034 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:54,034 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:28:54,034 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:28:54,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33 states. [2018-11-23 10:28:54,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 37 transitions. [2018-11-23 10:28:54,037 INFO L78 Accepts]: Start accepts. Automaton has 33 states and 37 transitions. Word has length 22 [2018-11-23 10:28:54,037 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:28:54,037 INFO L480 AbstractCegarLoop]: Abstraction has 33 states and 37 transitions. [2018-11-23 10:28:54,037 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 10:28:54,037 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 37 transitions. [2018-11-23 10:28:54,038 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-11-23 10:28:54,038 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:54,038 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:54,039 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:54,039 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:54,039 INFO L82 PathProgramCache]: Analyzing trace with hash 1124483392, now seen corresponding path program 1 times [2018-11-23 10:28:54,039 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:54,040 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:54,065 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:28:54,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:54,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:54,180 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:54,226 INFO L256 TraceCheckUtils]: 0: Hoare triple {1010#true} call ULTIMATE.init(); {1010#true} is VALID [2018-11-23 10:28:54,227 INFO L273 TraceCheckUtils]: 1: Hoare triple {1010#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1010#true} is VALID [2018-11-23 10:28:54,227 INFO L273 TraceCheckUtils]: 2: Hoare triple {1010#true} assume true; {1010#true} is VALID [2018-11-23 10:28:54,228 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1010#true} {1010#true} #83#return; {1010#true} is VALID [2018-11-23 10:28:54,228 INFO L256 TraceCheckUtils]: 4: Hoare triple {1010#true} call #t~ret8 := main(); {1010#true} is VALID [2018-11-23 10:28:54,229 INFO L273 TraceCheckUtils]: 5: Hoare triple {1010#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1010#true} is VALID [2018-11-23 10:28:54,229 INFO L273 TraceCheckUtils]: 6: Hoare triple {1010#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1010#true} is VALID [2018-11-23 10:28:54,229 INFO L273 TraceCheckUtils]: 7: Hoare triple {1010#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1010#true} is VALID [2018-11-23 10:28:54,230 INFO L273 TraceCheckUtils]: 8: Hoare triple {1010#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32));~j~0 := 3bv32; {1039#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:54,231 INFO L273 TraceCheckUtils]: 9: Hoare triple {1039#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {1039#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:54,231 INFO L273 TraceCheckUtils]: 10: Hoare triple {1039#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {1039#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:54,234 INFO L273 TraceCheckUtils]: 11: Hoare triple {1039#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1049#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:54,234 INFO L273 TraceCheckUtils]: 12: Hoare triple {1049#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} assume !~bvsge32(~j~0, 1bv32); {1011#false} is VALID [2018-11-23 10:28:54,235 INFO L273 TraceCheckUtils]: 13: Hoare triple {1011#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1011#false} is VALID [2018-11-23 10:28:54,235 INFO L273 TraceCheckUtils]: 14: Hoare triple {1011#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {1011#false} is VALID [2018-11-23 10:28:54,235 INFO L273 TraceCheckUtils]: 15: Hoare triple {1011#false} ~i~0 := 0bv32; {1011#false} is VALID [2018-11-23 10:28:54,235 INFO L273 TraceCheckUtils]: 16: Hoare triple {1011#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1011#false} is VALID [2018-11-23 10:28:54,236 INFO L273 TraceCheckUtils]: 17: Hoare triple {1011#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1011#false} is VALID [2018-11-23 10:28:54,236 INFO L256 TraceCheckUtils]: 18: Hoare triple {1011#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1011#false} is VALID [2018-11-23 10:28:54,236 INFO L273 TraceCheckUtils]: 19: Hoare triple {1011#false} ~cond := #in~cond; {1011#false} is VALID [2018-11-23 10:28:54,236 INFO L273 TraceCheckUtils]: 20: Hoare triple {1011#false} assume 0bv32 == ~cond; {1011#false} is VALID [2018-11-23 10:28:54,237 INFO L273 TraceCheckUtils]: 21: Hoare triple {1011#false} assume !false; {1011#false} is VALID [2018-11-23 10:28:54,238 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:54,238 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:28:54,309 INFO L273 TraceCheckUtils]: 21: Hoare triple {1011#false} assume !false; {1011#false} is VALID [2018-11-23 10:28:54,310 INFO L273 TraceCheckUtils]: 20: Hoare triple {1011#false} assume 0bv32 == ~cond; {1011#false} is VALID [2018-11-23 10:28:54,310 INFO L273 TraceCheckUtils]: 19: Hoare triple {1011#false} ~cond := #in~cond; {1011#false} is VALID [2018-11-23 10:28:54,310 INFO L256 TraceCheckUtils]: 18: Hoare triple {1011#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1011#false} is VALID [2018-11-23 10:28:54,311 INFO L273 TraceCheckUtils]: 17: Hoare triple {1011#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1011#false} is VALID [2018-11-23 10:28:54,311 INFO L273 TraceCheckUtils]: 16: Hoare triple {1011#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1011#false} is VALID [2018-11-23 10:28:54,311 INFO L273 TraceCheckUtils]: 15: Hoare triple {1011#false} ~i~0 := 0bv32; {1011#false} is VALID [2018-11-23 10:28:54,312 INFO L273 TraceCheckUtils]: 14: Hoare triple {1011#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {1011#false} is VALID [2018-11-23 10:28:54,312 INFO L273 TraceCheckUtils]: 13: Hoare triple {1011#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1011#false} is VALID [2018-11-23 10:28:54,312 INFO L273 TraceCheckUtils]: 12: Hoare triple {1107#(bvsge main_~j~0 (_ bv1 32))} assume !~bvsge32(~j~0, 1bv32); {1011#false} is VALID [2018-11-23 10:28:54,314 INFO L273 TraceCheckUtils]: 11: Hoare triple {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1107#(bvsge main_~j~0 (_ bv1 32))} is VALID [2018-11-23 10:28:54,319 INFO L273 TraceCheckUtils]: 10: Hoare triple {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-23 10:28:54,319 INFO L273 TraceCheckUtils]: 9: Hoare triple {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} assume !!~bvsge32(~j~0, 1bv32); {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-23 10:28:54,321 INFO L273 TraceCheckUtils]: 8: Hoare triple {1010#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32));~j~0 := 3bv32; {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-23 10:28:54,321 INFO L273 TraceCheckUtils]: 7: Hoare triple {1010#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1010#true} is VALID [2018-11-23 10:28:54,321 INFO L273 TraceCheckUtils]: 6: Hoare triple {1010#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1010#true} is VALID [2018-11-23 10:28:54,322 INFO L273 TraceCheckUtils]: 5: Hoare triple {1010#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1010#true} is VALID [2018-11-23 10:28:54,322 INFO L256 TraceCheckUtils]: 4: Hoare triple {1010#true} call #t~ret8 := main(); {1010#true} is VALID [2018-11-23 10:28:54,322 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1010#true} {1010#true} #83#return; {1010#true} is VALID [2018-11-23 10:28:54,322 INFO L273 TraceCheckUtils]: 2: Hoare triple {1010#true} assume true; {1010#true} is VALID [2018-11-23 10:28:54,323 INFO L273 TraceCheckUtils]: 1: Hoare triple {1010#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1010#true} is VALID [2018-11-23 10:28:54,323 INFO L256 TraceCheckUtils]: 0: Hoare triple {1010#true} call ULTIMATE.init(); {1010#true} is VALID [2018-11-23 10:28:54,324 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:54,326 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:28:54,326 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 6 [2018-11-23 10:28:54,328 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 22 [2018-11-23 10:28:54,328 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:28:54,329 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 6 states. [2018-11-23 10:28:54,436 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 27 edges. 27 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:54,436 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 10:28:54,436 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 10:28:54,437 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-11-23 10:28:54,437 INFO L87 Difference]: Start difference. First operand 33 states and 37 transitions. Second operand 6 states. [2018-11-23 10:28:55,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:55,063 INFO L93 Difference]: Finished difference Result 62 states and 73 transitions. [2018-11-23 10:28:55,063 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 10:28:55,063 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 22 [2018-11-23 10:28:55,064 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:28:55,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6 states. [2018-11-23 10:28:55,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 60 transitions. [2018-11-23 10:28:55,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6 states. [2018-11-23 10:28:55,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 60 transitions. [2018-11-23 10:28:55,069 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states and 60 transitions. [2018-11-23 10:28:55,312 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 60 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:55,314 INFO L225 Difference]: With dead ends: 62 [2018-11-23 10:28:55,314 INFO L226 Difference]: Without dead ends: 38 [2018-11-23 10:28:55,315 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-11-23 10:28:55,315 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states. [2018-11-23 10:28:55,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 38. [2018-11-23 10:28:55,356 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:28:55,357 INFO L82 GeneralOperation]: Start isEquivalent. First operand 38 states. Second operand 38 states. [2018-11-23 10:28:55,357 INFO L74 IsIncluded]: Start isIncluded. First operand 38 states. Second operand 38 states. [2018-11-23 10:28:55,357 INFO L87 Difference]: Start difference. First operand 38 states. Second operand 38 states. [2018-11-23 10:28:55,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:55,359 INFO L93 Difference]: Finished difference Result 38 states and 43 transitions. [2018-11-23 10:28:55,359 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 43 transitions. [2018-11-23 10:28:55,360 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:55,360 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:55,360 INFO L74 IsIncluded]: Start isIncluded. First operand 38 states. Second operand 38 states. [2018-11-23 10:28:55,360 INFO L87 Difference]: Start difference. First operand 38 states. Second operand 38 states. [2018-11-23 10:28:55,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:55,362 INFO L93 Difference]: Finished difference Result 38 states and 43 transitions. [2018-11-23 10:28:55,363 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 43 transitions. [2018-11-23 10:28:55,363 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:55,364 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:55,364 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:28:55,364 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:28:55,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2018-11-23 10:28:55,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 43 transitions. [2018-11-23 10:28:55,366 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 43 transitions. Word has length 22 [2018-11-23 10:28:55,366 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:28:55,367 INFO L480 AbstractCegarLoop]: Abstraction has 38 states and 43 transitions. [2018-11-23 10:28:55,367 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 10:28:55,367 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 43 transitions. [2018-11-23 10:28:55,368 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-11-23 10:28:55,368 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:55,368 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:55,369 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:55,369 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:55,369 INFO L82 PathProgramCache]: Analyzing trace with hash 125626112, now seen corresponding path program 1 times [2018-11-23 10:28:55,372 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:55,372 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:55,391 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:28:55,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:55,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:55,520 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:55,622 INFO L256 TraceCheckUtils]: 0: Hoare triple {1361#true} call ULTIMATE.init(); {1361#true} is VALID [2018-11-23 10:28:55,622 INFO L273 TraceCheckUtils]: 1: Hoare triple {1361#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1361#true} is VALID [2018-11-23 10:28:55,623 INFO L273 TraceCheckUtils]: 2: Hoare triple {1361#true} assume true; {1361#true} is VALID [2018-11-23 10:28:55,623 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1361#true} {1361#true} #83#return; {1361#true} is VALID [2018-11-23 10:28:55,623 INFO L256 TraceCheckUtils]: 4: Hoare triple {1361#true} call #t~ret8 := main(); {1361#true} is VALID [2018-11-23 10:28:55,624 INFO L273 TraceCheckUtils]: 5: Hoare triple {1361#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1361#true} is VALID [2018-11-23 10:28:55,640 INFO L273 TraceCheckUtils]: 6: Hoare triple {1361#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1384#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:28:55,642 INFO L273 TraceCheckUtils]: 7: Hoare triple {1384#(= (_ bv2 32) main_~MINVAL~0)} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1384#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:28:55,651 INFO L273 TraceCheckUtils]: 8: Hoare triple {1384#(= (_ bv2 32) main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32));~j~0 := 3bv32; {1391#(and (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:55,652 INFO L273 TraceCheckUtils]: 9: Hoare triple {1391#(and (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {1391#(and (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:55,653 INFO L273 TraceCheckUtils]: 10: Hoare triple {1391#(and (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {1391#(and (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:55,657 INFO L273 TraceCheckUtils]: 11: Hoare triple {1391#(and (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1401#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:55,658 INFO L273 TraceCheckUtils]: 12: Hoare triple {1401#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {1401#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:55,659 INFO L273 TraceCheckUtils]: 13: Hoare triple {1401#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {1362#false} is VALID [2018-11-23 10:28:55,659 INFO L273 TraceCheckUtils]: 14: Hoare triple {1362#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1362#false} is VALID [2018-11-23 10:28:55,659 INFO L273 TraceCheckUtils]: 15: Hoare triple {1362#false} assume !!~bvsge32(~j~0, 1bv32); {1362#false} is VALID [2018-11-23 10:28:55,659 INFO L273 TraceCheckUtils]: 16: Hoare triple {1362#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {1362#false} is VALID [2018-11-23 10:28:55,660 INFO L273 TraceCheckUtils]: 17: Hoare triple {1362#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1362#false} is VALID [2018-11-23 10:28:55,660 INFO L273 TraceCheckUtils]: 18: Hoare triple {1362#false} assume !~bvsge32(~j~0, 1bv32); {1362#false} is VALID [2018-11-23 10:28:55,660 INFO L273 TraceCheckUtils]: 19: Hoare triple {1362#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1362#false} is VALID [2018-11-23 10:28:55,660 INFO L273 TraceCheckUtils]: 20: Hoare triple {1362#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {1362#false} is VALID [2018-11-23 10:28:55,660 INFO L273 TraceCheckUtils]: 21: Hoare triple {1362#false} ~i~0 := 0bv32; {1362#false} is VALID [2018-11-23 10:28:55,661 INFO L273 TraceCheckUtils]: 22: Hoare triple {1362#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1362#false} is VALID [2018-11-23 10:28:55,661 INFO L273 TraceCheckUtils]: 23: Hoare triple {1362#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1362#false} is VALID [2018-11-23 10:28:55,661 INFO L256 TraceCheckUtils]: 24: Hoare triple {1362#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1362#false} is VALID [2018-11-23 10:28:55,661 INFO L273 TraceCheckUtils]: 25: Hoare triple {1362#false} ~cond := #in~cond; {1362#false} is VALID [2018-11-23 10:28:55,662 INFO L273 TraceCheckUtils]: 26: Hoare triple {1362#false} assume 0bv32 == ~cond; {1362#false} is VALID [2018-11-23 10:28:55,662 INFO L273 TraceCheckUtils]: 27: Hoare triple {1362#false} assume !false; {1362#false} is VALID [2018-11-23 10:28:55,664 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 9 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-11-23 10:28:55,664 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:28:55,774 INFO L273 TraceCheckUtils]: 27: Hoare triple {1362#false} assume !false; {1362#false} is VALID [2018-11-23 10:28:55,774 INFO L273 TraceCheckUtils]: 26: Hoare triple {1362#false} assume 0bv32 == ~cond; {1362#false} is VALID [2018-11-23 10:28:55,774 INFO L273 TraceCheckUtils]: 25: Hoare triple {1362#false} ~cond := #in~cond; {1362#false} is VALID [2018-11-23 10:28:55,774 INFO L256 TraceCheckUtils]: 24: Hoare triple {1362#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1362#false} is VALID [2018-11-23 10:28:55,775 INFO L273 TraceCheckUtils]: 23: Hoare triple {1362#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1362#false} is VALID [2018-11-23 10:28:55,775 INFO L273 TraceCheckUtils]: 22: Hoare triple {1362#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1362#false} is VALID [2018-11-23 10:28:55,775 INFO L273 TraceCheckUtils]: 21: Hoare triple {1362#false} ~i~0 := 0bv32; {1362#false} is VALID [2018-11-23 10:28:55,776 INFO L273 TraceCheckUtils]: 20: Hoare triple {1362#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {1362#false} is VALID [2018-11-23 10:28:55,776 INFO L273 TraceCheckUtils]: 19: Hoare triple {1362#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1362#false} is VALID [2018-11-23 10:28:55,777 INFO L273 TraceCheckUtils]: 18: Hoare triple {1362#false} assume !~bvsge32(~j~0, 1bv32); {1362#false} is VALID [2018-11-23 10:28:55,777 INFO L273 TraceCheckUtils]: 17: Hoare triple {1362#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1362#false} is VALID [2018-11-23 10:28:55,777 INFO L273 TraceCheckUtils]: 16: Hoare triple {1362#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {1362#false} is VALID [2018-11-23 10:28:55,777 INFO L273 TraceCheckUtils]: 15: Hoare triple {1362#false} assume !!~bvsge32(~j~0, 1bv32); {1362#false} is VALID [2018-11-23 10:28:55,777 INFO L273 TraceCheckUtils]: 14: Hoare triple {1362#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1362#false} is VALID [2018-11-23 10:28:55,778 INFO L273 TraceCheckUtils]: 13: Hoare triple {1492#(bvsge main_~j~0 main_~MINVAL~0)} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {1362#false} is VALID [2018-11-23 10:28:55,778 INFO L273 TraceCheckUtils]: 12: Hoare triple {1492#(bvsge main_~j~0 main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {1492#(bvsge main_~j~0 main_~MINVAL~0)} is VALID [2018-11-23 10:28:55,780 INFO L273 TraceCheckUtils]: 11: Hoare triple {1499#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1492#(bvsge main_~j~0 main_~MINVAL~0)} is VALID [2018-11-23 10:28:55,780 INFO L273 TraceCheckUtils]: 10: Hoare triple {1499#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0)} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {1499#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0)} is VALID [2018-11-23 10:28:55,781 INFO L273 TraceCheckUtils]: 9: Hoare triple {1499#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {1499#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0)} is VALID [2018-11-23 10:28:55,781 INFO L273 TraceCheckUtils]: 8: Hoare triple {1509#(bvsge (_ bv2 32) main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32));~j~0 := 3bv32; {1499#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0)} is VALID [2018-11-23 10:28:55,782 INFO L273 TraceCheckUtils]: 7: Hoare triple {1509#(bvsge (_ bv2 32) main_~MINVAL~0)} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1509#(bvsge (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:28:55,783 INFO L273 TraceCheckUtils]: 6: Hoare triple {1361#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1509#(bvsge (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:28:55,783 INFO L273 TraceCheckUtils]: 5: Hoare triple {1361#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1361#true} is VALID [2018-11-23 10:28:55,783 INFO L256 TraceCheckUtils]: 4: Hoare triple {1361#true} call #t~ret8 := main(); {1361#true} is VALID [2018-11-23 10:28:55,784 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1361#true} {1361#true} #83#return; {1361#true} is VALID [2018-11-23 10:28:55,784 INFO L273 TraceCheckUtils]: 2: Hoare triple {1361#true} assume true; {1361#true} is VALID [2018-11-23 10:28:55,785 INFO L273 TraceCheckUtils]: 1: Hoare triple {1361#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1361#true} is VALID [2018-11-23 10:28:55,785 INFO L256 TraceCheckUtils]: 0: Hoare triple {1361#true} call ULTIMATE.init(); {1361#true} is VALID [2018-11-23 10:28:55,787 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 9 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-11-23 10:28:55,789 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:28:55,789 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 8 [2018-11-23 10:28:55,789 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 28 [2018-11-23 10:28:55,790 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:28:55,790 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 8 states. [2018-11-23 10:28:55,939 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 35 edges. 35 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:55,939 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 10:28:55,939 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 10:28:55,940 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-11-23 10:28:55,940 INFO L87 Difference]: Start difference. First operand 38 states and 43 transitions. Second operand 8 states. [2018-11-23 10:28:56,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:56,562 INFO L93 Difference]: Finished difference Result 68 states and 78 transitions. [2018-11-23 10:28:56,562 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 10:28:56,563 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 28 [2018-11-23 10:28:56,563 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:28:56,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8 states. [2018-11-23 10:28:56,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 58 transitions. [2018-11-23 10:28:56,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8 states. [2018-11-23 10:28:56,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 58 transitions. [2018-11-23 10:28:56,568 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 6 states and 58 transitions. [2018-11-23 10:28:56,735 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 58 edges. 58 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:56,736 INFO L225 Difference]: With dead ends: 68 [2018-11-23 10:28:56,736 INFO L226 Difference]: Without dead ends: 39 [2018-11-23 10:28:56,737 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2018-11-23 10:28:56,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states. [2018-11-23 10:28:56,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 38. [2018-11-23 10:28:56,778 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:28:56,778 INFO L82 GeneralOperation]: Start isEquivalent. First operand 39 states. Second operand 38 states. [2018-11-23 10:28:56,778 INFO L74 IsIncluded]: Start isIncluded. First operand 39 states. Second operand 38 states. [2018-11-23 10:28:56,778 INFO L87 Difference]: Start difference. First operand 39 states. Second operand 38 states. [2018-11-23 10:28:56,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:56,781 INFO L93 Difference]: Finished difference Result 39 states and 43 transitions. [2018-11-23 10:28:56,781 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 43 transitions. [2018-11-23 10:28:56,782 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:56,782 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:56,782 INFO L74 IsIncluded]: Start isIncluded. First operand 38 states. Second operand 39 states. [2018-11-23 10:28:56,782 INFO L87 Difference]: Start difference. First operand 38 states. Second operand 39 states. [2018-11-23 10:28:56,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:56,785 INFO L93 Difference]: Finished difference Result 39 states and 43 transitions. [2018-11-23 10:28:56,785 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 43 transitions. [2018-11-23 10:28:56,785 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:56,786 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:56,786 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:28:56,786 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:28:56,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2018-11-23 10:28:56,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 42 transitions. [2018-11-23 10:28:56,788 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 42 transitions. Word has length 28 [2018-11-23 10:28:56,788 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:28:56,789 INFO L480 AbstractCegarLoop]: Abstraction has 38 states and 42 transitions. [2018-11-23 10:28:56,789 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 10:28:56,789 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 42 transitions. [2018-11-23 10:28:56,790 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-11-23 10:28:56,790 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:56,790 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:56,790 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:56,791 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:56,791 INFO L82 PathProgramCache]: Analyzing trace with hash 1405489790, now seen corresponding path program 2 times [2018-11-23 10:28:56,791 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:56,791 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:56,822 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-23 10:28:57,145 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 10:28:57,145 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 10:28:57,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:57,201 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:57,359 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 16 [2018-11-23 10:28:57,367 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 15 [2018-11-23 10:28:57,370 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:28:57,374 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:57,397 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:57,398 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:36, output treesize:32 [2018-11-23 10:28:57,537 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 34 [2018-11-23 10:28:57,585 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,587 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,589 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 75 [2018-11-23 10:28:57,592 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:28:57,609 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:57,643 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:57,643 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:55, output treesize:51 [2018-11-23 10:28:57,877 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 25 [2018-11-23 10:28:57,892 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,894 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,897 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,900 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,903 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,906 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,909 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 80 [2018-11-23 10:28:57,930 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:28:57,956 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:57,975 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:57,975 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:38, output treesize:34 [2018-11-23 10:28:58,201 INFO L256 TraceCheckUtils]: 0: Hoare triple {1762#true} call ULTIMATE.init(); {1762#true} is VALID [2018-11-23 10:28:58,201 INFO L273 TraceCheckUtils]: 1: Hoare triple {1762#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1762#true} is VALID [2018-11-23 10:28:58,201 INFO L273 TraceCheckUtils]: 2: Hoare triple {1762#true} assume true; {1762#true} is VALID [2018-11-23 10:28:58,201 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1762#true} {1762#true} #83#return; {1762#true} is VALID [2018-11-23 10:28:58,202 INFO L256 TraceCheckUtils]: 4: Hoare triple {1762#true} call #t~ret8 := main(); {1762#true} is VALID [2018-11-23 10:28:58,202 INFO L273 TraceCheckUtils]: 5: Hoare triple {1762#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1762#true} is VALID [2018-11-23 10:28:58,203 INFO L273 TraceCheckUtils]: 6: Hoare triple {1762#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1785#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:58,204 INFO L273 TraceCheckUtils]: 7: Hoare triple {1785#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1789#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:58,204 INFO L273 TraceCheckUtils]: 8: Hoare triple {1789#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32));~j~0 := 3bv32; {1793#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:58,205 INFO L273 TraceCheckUtils]: 9: Hoare triple {1793#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {1793#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:58,209 INFO L273 TraceCheckUtils]: 10: Hoare triple {1793#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {1800#(and (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:58,214 INFO L273 TraceCheckUtils]: 11: Hoare triple {1800#(and (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1804#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:58,227 INFO L273 TraceCheckUtils]: 12: Hoare triple {1804#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {1804#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:58,232 INFO L273 TraceCheckUtils]: 13: Hoare triple {1804#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {1811#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:58,252 INFO L273 TraceCheckUtils]: 14: Hoare triple {1811#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1815#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:58,267 INFO L273 TraceCheckUtils]: 15: Hoare triple {1815#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {1815#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:58,282 INFO L273 TraceCheckUtils]: 16: Hoare triple {1815#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {1822#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:58,283 INFO L273 TraceCheckUtils]: 17: Hoare triple {1822#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1822#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:58,285 INFO L273 TraceCheckUtils]: 18: Hoare triple {1822#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsge32(~j~0, 1bv32); {1822#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:58,290 INFO L273 TraceCheckUtils]: 19: Hoare triple {1822#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1822#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:58,291 INFO L273 TraceCheckUtils]: 20: Hoare triple {1822#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {1822#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:58,292 INFO L273 TraceCheckUtils]: 21: Hoare triple {1822#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 0bv32; {1838#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967294 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:58,294 INFO L273 TraceCheckUtils]: 22: Hoare triple {1838#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967294 32)) (_ bv0 32)) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1842#|main_#t~short7|} is VALID [2018-11-23 10:28:58,295 INFO L273 TraceCheckUtils]: 23: Hoare triple {1842#|main_#t~short7|} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1763#false} is VALID [2018-11-23 10:28:58,295 INFO L256 TraceCheckUtils]: 24: Hoare triple {1763#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1763#false} is VALID [2018-11-23 10:28:58,295 INFO L273 TraceCheckUtils]: 25: Hoare triple {1763#false} ~cond := #in~cond; {1763#false} is VALID [2018-11-23 10:28:58,296 INFO L273 TraceCheckUtils]: 26: Hoare triple {1763#false} assume 0bv32 == ~cond; {1763#false} is VALID [2018-11-23 10:28:58,296 INFO L273 TraceCheckUtils]: 27: Hoare triple {1763#false} assume !false; {1763#false} is VALID [2018-11-23 10:28:58,303 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:58,303 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:28:58,796 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 44 [2018-11-23 10:28:58,808 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 48 [2018-11-23 10:28:58,823 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:58,823 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:58,826 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 87 [2018-11-23 10:28:59,076 WARN L180 SmtUtils]: Spent 208.00 ms on a formula simplification. DAG size of input: 40 DAG size of output: 36 [2018-11-23 10:28:59,181 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:59,190 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:59,241 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 2 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 38 treesize of output 66 [2018-11-23 10:28:59,262 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 3 xjuncts. [2018-11-23 10:28:59,300 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:59,301 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:59,303 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 40 [2018-11-23 10:28:59,305 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-11-23 10:28:59,507 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 7 xjuncts. [2018-11-23 10:28:59,708 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 5 xjuncts. [2018-11-23 10:28:59,935 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 5 xjuncts. [2018-11-23 10:29:00,174 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 5 xjuncts. [2018-11-23 10:29:00,175 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 2 variables, input treesize:46, output treesize:147 [2018-11-23 10:29:00,191 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:29:00,192 WARN L384 uantifierElimination]: Input elimination task: ∀ [|#memory_int|, |main_~#volArray~0.base|]. (bvsge (select (let ((.cse0 (bvmul (_ bv12 32) main_~i~0))) (store (let ((.cse1 (bvadd main_~j~0 (_ bv4294967295 32)))) (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0) main_~j~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg .cse1)) .cse0) .cse1)) (bvadd |main_~#volArray~0.offset| .cse0 (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32))) |main_~#volArray~0.offset|) main_~MINVAL~0) [2018-11-23 10:29:00,192 WARN L385 uantifierElimination]: ElimStorePlain result: ∀ [v_prenex_1, v_arrayElimCell_5]. (let ((.cse4 (bvadd main_~j~0 (_ bv4294967295 32))) (.cse5 (bvmul (_ bv12 32) main_~i~0))) (let ((.cse1 (bvsge (_ bv0 32) main_~MINVAL~0)) (.cse2 (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse5) |main_~#volArray~0.offset|)) (.cse3 (= |main_~#volArray~0.offset| (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg .cse4)) .cse5))) (.cse0 (= (_ bv0 32) (bvadd .cse5 (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))))) (and (or (not .cse0) .cse1) (or .cse2 .cse3 .cse0 (bvsge v_prenex_1 main_~MINVAL~0)) (or .cse2 .cse3 (bvsge v_arrayElimCell_5 main_~MINVAL~0) .cse1) (or .cse2 (bvsge .cse4 main_~MINVAL~0) .cse0) (or .cse3 (bvsge main_~j~0 main_~MINVAL~0) .cse0)))) [2018-11-23 10:29:00,918 WARN L180 SmtUtils]: Spent 452.00 ms on a formula simplification. DAG size of input: 39 DAG size of output: 34 [2018-11-23 10:29:01,249 WARN L180 SmtUtils]: Spent 186.00 ms on a formula simplification. DAG size of input: 23 DAG size of output: 22 [2018-11-23 10:29:01,377 INFO L273 TraceCheckUtils]: 27: Hoare triple {1763#false} assume !false; {1763#false} is VALID [2018-11-23 10:29:01,377 INFO L273 TraceCheckUtils]: 26: Hoare triple {1763#false} assume 0bv32 == ~cond; {1763#false} is VALID [2018-11-23 10:29:01,377 INFO L273 TraceCheckUtils]: 25: Hoare triple {1763#false} ~cond := #in~cond; {1763#false} is VALID [2018-11-23 10:29:01,377 INFO L256 TraceCheckUtils]: 24: Hoare triple {1763#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1763#false} is VALID [2018-11-23 10:29:01,384 INFO L273 TraceCheckUtils]: 23: Hoare triple {1842#|main_#t~short7|} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1763#false} is VALID [2018-11-23 10:29:01,386 INFO L273 TraceCheckUtils]: 22: Hoare triple {1873#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1842#|main_#t~short7|} is VALID [2018-11-23 10:29:01,387 INFO L273 TraceCheckUtils]: 21: Hoare triple {1877#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} ~i~0 := 0bv32; {1873#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is VALID [2018-11-23 10:29:01,388 INFO L273 TraceCheckUtils]: 20: Hoare triple {1877#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {1877#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:01,389 INFO L273 TraceCheckUtils]: 19: Hoare triple {1877#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1877#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:01,389 INFO L273 TraceCheckUtils]: 18: Hoare triple {1877#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsge32(~j~0, 1bv32); {1877#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:01,391 INFO L273 TraceCheckUtils]: 17: Hoare triple {1877#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1877#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:01,638 INFO L273 TraceCheckUtils]: 16: Hoare triple {1893#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {1877#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:01,639 INFO L273 TraceCheckUtils]: 15: Hoare triple {1893#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {1893#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:01,749 INFO L273 TraceCheckUtils]: 14: Hoare triple {1900#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv12 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1893#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:01,864 INFO L273 TraceCheckUtils]: 13: Hoare triple {1904#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~j~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv12 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {1900#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv12 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:01,865 INFO L273 TraceCheckUtils]: 12: Hoare triple {1904#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~j~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv12 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {1904#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~j~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv12 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:03,308 INFO L273 TraceCheckUtils]: 11: Hoare triple {1911#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv12 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1904#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)) main_~j~0) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv12 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:03,502 INFO L273 TraceCheckUtils]: 10: Hoare triple {1915#(and (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv12 32) main_~i~0)) (_ bv0 32)) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv12 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv12 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv12 32) main_~i~0)))) (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv12 32) main_~i~0)) (_ bv0 32)) (forall ((v_prenex_1 (_ BitVec 32))) (bvsge v_prenex_1 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (bvmul (_ bv12 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv12 32) main_~i~0)))) (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv12 32) main_~i~0)) (_ bv0 32)) (bvsge (_ bv0 32) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv12 32) main_~i~0)))))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {1911#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv12 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:03,504 INFO L273 TraceCheckUtils]: 9: Hoare triple {1915#(and (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv12 32) main_~i~0)) (_ bv0 32)) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv12 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv12 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv12 32) main_~i~0)))) (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv12 32) main_~i~0)) (_ bv0 32)) (forall ((v_prenex_1 (_ BitVec 32))) (bvsge v_prenex_1 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (bvmul (_ bv12 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv12 32) main_~i~0)))) (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv12 32) main_~i~0)) (_ bv0 32)) (bvsge (_ bv0 32) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv12 32) main_~i~0)))))} assume !!~bvsge32(~j~0, 1bv32); {1915#(and (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv12 32) main_~i~0)) (_ bv0 32)) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv12 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv12 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv12 32) main_~i~0)))) (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv12 32) main_~i~0)) (_ bv0 32)) (forall ((v_prenex_1 (_ BitVec 32))) (bvsge v_prenex_1 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (bvmul (_ bv12 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv12 32) main_~i~0)))) (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv12 32) main_~i~0)) (_ bv0 32)) (bvsge (_ bv0 32) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv12 32) main_~i~0)))))} is VALID [2018-11-23 10:29:03,525 INFO L273 TraceCheckUtils]: 8: Hoare triple {1922#(and (bvsge (_ bv3 32) main_~MINVAL~0) (or (forall ((v_prenex_1 (_ BitVec 32))) (bvsge v_prenex_1 main_~MINVAL~0)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv8 32) (bvmul (_ bv12 32) main_~i~0))) (or (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (bvsge (_ bv0 32) main_~MINVAL~0) (= (_ bv8 32) (bvmul (_ bv12 32) main_~i~0))) (or (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (bvsge (_ bv2 32) main_~MINVAL~0)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32));~j~0 := 3bv32; {1915#(and (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv12 32) main_~i~0)) (_ bv0 32)) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv12 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv12 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv12 32) main_~i~0)))) (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv12 32) main_~i~0)) (_ bv0 32)) (forall ((v_prenex_1 (_ BitVec 32))) (bvsge v_prenex_1 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (bvmul (_ bv12 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv12 32) main_~i~0)))) (or (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv12 32) main_~i~0)) (_ bv0 32)) (bvsge (_ bv0 32) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv12 32) main_~i~0)))))} is VALID [2018-11-23 10:29:03,526 INFO L273 TraceCheckUtils]: 7: Hoare triple {1926#(bvsge (_ bv3 32) main_~MINVAL~0)} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1922#(and (bvsge (_ bv3 32) main_~MINVAL~0) (or (forall ((v_prenex_1 (_ BitVec 32))) (bvsge v_prenex_1 main_~MINVAL~0)) (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv4 32) (bvmul (_ bv12 32) main_~i~0)) (= (_ bv8 32) (bvmul (_ bv12 32) main_~i~0))) (or (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (bvsge (_ bv0 32) main_~MINVAL~0) (= (_ bv8 32) (bvmul (_ bv12 32) main_~i~0))) (or (= (_ bv12 32) (bvmul (_ bv12 32) main_~i~0)) (bvsge (_ bv2 32) main_~MINVAL~0)))} is VALID [2018-11-23 10:29:03,526 INFO L273 TraceCheckUtils]: 6: Hoare triple {1762#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1926#(bvsge (_ bv3 32) main_~MINVAL~0)} is VALID [2018-11-23 10:29:03,527 INFO L273 TraceCheckUtils]: 5: Hoare triple {1762#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1762#true} is VALID [2018-11-23 10:29:03,527 INFO L256 TraceCheckUtils]: 4: Hoare triple {1762#true} call #t~ret8 := main(); {1762#true} is VALID [2018-11-23 10:29:03,527 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1762#true} {1762#true} #83#return; {1762#true} is VALID [2018-11-23 10:29:03,527 INFO L273 TraceCheckUtils]: 2: Hoare triple {1762#true} assume true; {1762#true} is VALID [2018-11-23 10:29:03,527 INFO L273 TraceCheckUtils]: 1: Hoare triple {1762#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1762#true} is VALID [2018-11-23 10:29:03,528 INFO L256 TraceCheckUtils]: 0: Hoare triple {1762#true} call ULTIMATE.init(); {1762#true} is VALID [2018-11-23 10:29:03,533 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:29:03,541 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:29:03,542 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 21 [2018-11-23 10:29:03,542 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 28 [2018-11-23 10:29:03,542 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:29:03,543 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 21 states. [2018-11-23 10:29:04,496 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 45 edges. 45 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:29:04,496 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 10:29:04,497 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 10:29:04,497 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=98, Invalid=322, Unknown=0, NotChecked=0, Total=420 [2018-11-23 10:29:04,497 INFO L87 Difference]: Start difference. First operand 38 states and 42 transitions. Second operand 21 states. [2018-11-23 10:29:07,057 WARN L180 SmtUtils]: Spent 170.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 52 [2018-11-23 10:29:07,948 WARN L180 SmtUtils]: Spent 137.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 41 [2018-11-23 10:29:08,469 WARN L180 SmtUtils]: Spent 161.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 45 [2018-11-23 10:29:09,800 WARN L180 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 36 [2018-11-23 10:29:14,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:29:14,835 INFO L93 Difference]: Finished difference Result 156 states and 197 transitions. [2018-11-23 10:29:14,835 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-11-23 10:29:14,835 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 28 [2018-11-23 10:29:14,836 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:29:14,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2018-11-23 10:29:14,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 168 transitions. [2018-11-23 10:29:14,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2018-11-23 10:29:14,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 168 transitions. [2018-11-23 10:29:14,846 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 30 states and 168 transitions. [2018-11-23 10:29:17,576 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 168 edges. 167 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2018-11-23 10:29:17,582 INFO L225 Difference]: With dead ends: 156 [2018-11-23 10:29:17,582 INFO L226 Difference]: Without dead ends: 127 [2018-11-23 10:29:17,585 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 74 GetRequests, 36 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 377 ImplicationChecksByTransitivity, 4.1s TimeCoverageRelationStatistics Valid=381, Invalid=1179, Unknown=0, NotChecked=0, Total=1560 [2018-11-23 10:29:17,585 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2018-11-23 10:29:17,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 78. [2018-11-23 10:29:17,838 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:29:17,838 INFO L82 GeneralOperation]: Start isEquivalent. First operand 127 states. Second operand 78 states. [2018-11-23 10:29:17,839 INFO L74 IsIncluded]: Start isIncluded. First operand 127 states. Second operand 78 states. [2018-11-23 10:29:17,839 INFO L87 Difference]: Start difference. First operand 127 states. Second operand 78 states. [2018-11-23 10:29:17,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:29:17,846 INFO L93 Difference]: Finished difference Result 127 states and 160 transitions. [2018-11-23 10:29:17,846 INFO L276 IsEmpty]: Start isEmpty. Operand 127 states and 160 transitions. [2018-11-23 10:29:17,846 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:29:17,847 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:29:17,847 INFO L74 IsIncluded]: Start isIncluded. First operand 78 states. Second operand 127 states. [2018-11-23 10:29:17,847 INFO L87 Difference]: Start difference. First operand 78 states. Second operand 127 states. [2018-11-23 10:29:17,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:29:17,853 INFO L93 Difference]: Finished difference Result 127 states and 160 transitions. [2018-11-23 10:29:17,853 INFO L276 IsEmpty]: Start isEmpty. Operand 127 states and 160 transitions. [2018-11-23 10:29:17,853 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:29:17,854 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:29:17,854 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:29:17,854 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:29:17,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-11-23 10:29:17,857 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 93 transitions. [2018-11-23 10:29:17,857 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 93 transitions. Word has length 28 [2018-11-23 10:29:17,857 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:29:17,857 INFO L480 AbstractCegarLoop]: Abstraction has 78 states and 93 transitions. [2018-11-23 10:29:17,857 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 10:29:17,857 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 93 transitions. [2018-11-23 10:29:17,858 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-11-23 10:29:17,858 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:29:17,859 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:29:17,859 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:29:17,859 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:29:17,859 INFO L82 PathProgramCache]: Analyzing trace with hash 756126263, now seen corresponding path program 1 times [2018-11-23 10:29:17,860 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:29:17,860 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:29:17,884 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 10:29:17,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:29:18,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:29:18,024 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:29:18,105 INFO L256 TraceCheckUtils]: 0: Hoare triple {2561#true} call ULTIMATE.init(); {2561#true} is VALID [2018-11-23 10:29:18,106 INFO L273 TraceCheckUtils]: 1: Hoare triple {2561#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {2561#true} is VALID [2018-11-23 10:29:18,106 INFO L273 TraceCheckUtils]: 2: Hoare triple {2561#true} assume true; {2561#true} is VALID [2018-11-23 10:29:18,106 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2561#true} {2561#true} #83#return; {2561#true} is VALID [2018-11-23 10:29:18,107 INFO L256 TraceCheckUtils]: 4: Hoare triple {2561#true} call #t~ret8 := main(); {2561#true} is VALID [2018-11-23 10:29:18,107 INFO L273 TraceCheckUtils]: 5: Hoare triple {2561#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {2561#true} is VALID [2018-11-23 10:29:18,108 INFO L273 TraceCheckUtils]: 6: Hoare triple {2561#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {2561#true} is VALID [2018-11-23 10:29:18,108 INFO L273 TraceCheckUtils]: 7: Hoare triple {2561#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {2561#true} is VALID [2018-11-23 10:29:18,123 INFO L273 TraceCheckUtils]: 8: Hoare triple {2561#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32));~j~0 := 3bv32; {2590#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:18,132 INFO L273 TraceCheckUtils]: 9: Hoare triple {2590#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {2590#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:18,145 INFO L273 TraceCheckUtils]: 10: Hoare triple {2590#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {2590#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:18,156 INFO L273 TraceCheckUtils]: 11: Hoare triple {2590#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2600#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:18,156 INFO L273 TraceCheckUtils]: 12: Hoare triple {2600#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {2600#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:18,158 INFO L273 TraceCheckUtils]: 13: Hoare triple {2600#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {2600#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:18,158 INFO L273 TraceCheckUtils]: 14: Hoare triple {2600#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2610#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:18,160 INFO L273 TraceCheckUtils]: 15: Hoare triple {2610#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {2610#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:18,160 INFO L273 TraceCheckUtils]: 16: Hoare triple {2610#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {2610#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:18,162 INFO L273 TraceCheckUtils]: 17: Hoare triple {2610#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2620#(= main_~j~0 (_ bv0 32))} is VALID [2018-11-23 10:29:18,163 INFO L273 TraceCheckUtils]: 18: Hoare triple {2620#(= main_~j~0 (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {2562#false} is VALID [2018-11-23 10:29:18,163 INFO L273 TraceCheckUtils]: 19: Hoare triple {2562#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {2562#false} is VALID [2018-11-23 10:29:18,163 INFO L273 TraceCheckUtils]: 20: Hoare triple {2562#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2562#false} is VALID [2018-11-23 10:29:18,164 INFO L273 TraceCheckUtils]: 21: Hoare triple {2562#false} assume !~bvsge32(~j~0, 1bv32); {2562#false} is VALID [2018-11-23 10:29:18,164 INFO L273 TraceCheckUtils]: 22: Hoare triple {2562#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {2562#false} is VALID [2018-11-23 10:29:18,164 INFO L273 TraceCheckUtils]: 23: Hoare triple {2562#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {2562#false} is VALID [2018-11-23 10:29:18,165 INFO L273 TraceCheckUtils]: 24: Hoare triple {2562#false} ~i~0 := 0bv32; {2562#false} is VALID [2018-11-23 10:29:18,165 INFO L273 TraceCheckUtils]: 25: Hoare triple {2562#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {2562#false} is VALID [2018-11-23 10:29:18,166 INFO L273 TraceCheckUtils]: 26: Hoare triple {2562#false} assume #t~short7; {2562#false} is VALID [2018-11-23 10:29:18,166 INFO L256 TraceCheckUtils]: 27: Hoare triple {2562#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {2562#false} is VALID [2018-11-23 10:29:18,167 INFO L273 TraceCheckUtils]: 28: Hoare triple {2562#false} ~cond := #in~cond; {2562#false} is VALID [2018-11-23 10:29:18,167 INFO L273 TraceCheckUtils]: 29: Hoare triple {2562#false} assume !(0bv32 == ~cond); {2562#false} is VALID [2018-11-23 10:29:18,167 INFO L273 TraceCheckUtils]: 30: Hoare triple {2562#false} assume true; {2562#false} is VALID [2018-11-23 10:29:18,168 INFO L268 TraceCheckUtils]: 31: Hoare quadruple {2562#false} {2562#false} #87#return; {2562#false} is VALID [2018-11-23 10:29:18,168 INFO L273 TraceCheckUtils]: 32: Hoare triple {2562#false} havoc #t~mem5;havoc #t~short7;havoc #t~mem6; {2562#false} is VALID [2018-11-23 10:29:18,168 INFO L273 TraceCheckUtils]: 33: Hoare triple {2562#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {2562#false} is VALID [2018-11-23 10:29:18,168 INFO L273 TraceCheckUtils]: 34: Hoare triple {2562#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {2562#false} is VALID [2018-11-23 10:29:18,169 INFO L273 TraceCheckUtils]: 35: Hoare triple {2562#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {2562#false} is VALID [2018-11-23 10:29:18,169 INFO L256 TraceCheckUtils]: 36: Hoare triple {2562#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {2562#false} is VALID [2018-11-23 10:29:18,169 INFO L273 TraceCheckUtils]: 37: Hoare triple {2562#false} ~cond := #in~cond; {2562#false} is VALID [2018-11-23 10:29:18,169 INFO L273 TraceCheckUtils]: 38: Hoare triple {2562#false} assume 0bv32 == ~cond; {2562#false} is VALID [2018-11-23 10:29:18,169 INFO L273 TraceCheckUtils]: 39: Hoare triple {2562#false} assume !false; {2562#false} is VALID [2018-11-23 10:29:18,172 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 11 proven. 12 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-23 10:29:18,172 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:29:18,388 INFO L273 TraceCheckUtils]: 39: Hoare triple {2562#false} assume !false; {2562#false} is VALID [2018-11-23 10:29:18,388 INFO L273 TraceCheckUtils]: 38: Hoare triple {2562#false} assume 0bv32 == ~cond; {2562#false} is VALID [2018-11-23 10:29:18,388 INFO L273 TraceCheckUtils]: 37: Hoare triple {2562#false} ~cond := #in~cond; {2562#false} is VALID [2018-11-23 10:29:18,389 INFO L256 TraceCheckUtils]: 36: Hoare triple {2562#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {2562#false} is VALID [2018-11-23 10:29:18,389 INFO L273 TraceCheckUtils]: 35: Hoare triple {2562#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {2562#false} is VALID [2018-11-23 10:29:18,389 INFO L273 TraceCheckUtils]: 34: Hoare triple {2562#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {2562#false} is VALID [2018-11-23 10:29:18,390 INFO L273 TraceCheckUtils]: 33: Hoare triple {2562#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {2562#false} is VALID [2018-11-23 10:29:18,390 INFO L273 TraceCheckUtils]: 32: Hoare triple {2562#false} havoc #t~mem5;havoc #t~short7;havoc #t~mem6; {2562#false} is VALID [2018-11-23 10:29:18,391 INFO L268 TraceCheckUtils]: 31: Hoare quadruple {2561#true} {2562#false} #87#return; {2562#false} is VALID [2018-11-23 10:29:18,391 INFO L273 TraceCheckUtils]: 30: Hoare triple {2561#true} assume true; {2561#true} is VALID [2018-11-23 10:29:18,391 INFO L273 TraceCheckUtils]: 29: Hoare triple {2561#true} assume !(0bv32 == ~cond); {2561#true} is VALID [2018-11-23 10:29:18,391 INFO L273 TraceCheckUtils]: 28: Hoare triple {2561#true} ~cond := #in~cond; {2561#true} is VALID [2018-11-23 10:29:18,391 INFO L256 TraceCheckUtils]: 27: Hoare triple {2562#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {2561#true} is VALID [2018-11-23 10:29:18,392 INFO L273 TraceCheckUtils]: 26: Hoare triple {2562#false} assume #t~short7; {2562#false} is VALID [2018-11-23 10:29:18,392 INFO L273 TraceCheckUtils]: 25: Hoare triple {2562#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {2562#false} is VALID [2018-11-23 10:29:18,392 INFO L273 TraceCheckUtils]: 24: Hoare triple {2562#false} ~i~0 := 0bv32; {2562#false} is VALID [2018-11-23 10:29:18,392 INFO L273 TraceCheckUtils]: 23: Hoare triple {2562#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {2562#false} is VALID [2018-11-23 10:29:18,393 INFO L273 TraceCheckUtils]: 22: Hoare triple {2562#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {2562#false} is VALID [2018-11-23 10:29:18,393 INFO L273 TraceCheckUtils]: 21: Hoare triple {2562#false} assume !~bvsge32(~j~0, 1bv32); {2562#false} is VALID [2018-11-23 10:29:18,393 INFO L273 TraceCheckUtils]: 20: Hoare triple {2562#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2562#false} is VALID [2018-11-23 10:29:18,393 INFO L273 TraceCheckUtils]: 19: Hoare triple {2562#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {2562#false} is VALID [2018-11-23 10:29:18,398 INFO L273 TraceCheckUtils]: 18: Hoare triple {2750#(not (bvsge main_~j~0 (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {2562#false} is VALID [2018-11-23 10:29:18,399 INFO L273 TraceCheckUtils]: 17: Hoare triple {2754#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2750#(not (bvsge main_~j~0 (_ bv1 32)))} is VALID [2018-11-23 10:29:18,399 INFO L273 TraceCheckUtils]: 16: Hoare triple {2754#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {2754#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:18,400 INFO L273 TraceCheckUtils]: 15: Hoare triple {2754#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {2754#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:18,405 INFO L273 TraceCheckUtils]: 14: Hoare triple {2764#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2754#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:18,405 INFO L273 TraceCheckUtils]: 13: Hoare triple {2764#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {2764#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:18,406 INFO L273 TraceCheckUtils]: 12: Hoare triple {2764#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {2764#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:18,410 INFO L273 TraceCheckUtils]: 11: Hoare triple {2774#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2764#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:18,411 INFO L273 TraceCheckUtils]: 10: Hoare triple {2774#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {2774#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:18,411 INFO L273 TraceCheckUtils]: 9: Hoare triple {2774#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {2774#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:18,411 INFO L273 TraceCheckUtils]: 8: Hoare triple {2561#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32));~j~0 := 3bv32; {2774#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:18,412 INFO L273 TraceCheckUtils]: 7: Hoare triple {2561#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {2561#true} is VALID [2018-11-23 10:29:18,412 INFO L273 TraceCheckUtils]: 6: Hoare triple {2561#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {2561#true} is VALID [2018-11-23 10:29:18,412 INFO L273 TraceCheckUtils]: 5: Hoare triple {2561#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {2561#true} is VALID [2018-11-23 10:29:18,412 INFO L256 TraceCheckUtils]: 4: Hoare triple {2561#true} call #t~ret8 := main(); {2561#true} is VALID [2018-11-23 10:29:18,412 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2561#true} {2561#true} #83#return; {2561#true} is VALID [2018-11-23 10:29:18,413 INFO L273 TraceCheckUtils]: 2: Hoare triple {2561#true} assume true; {2561#true} is VALID [2018-11-23 10:29:18,413 INFO L273 TraceCheckUtils]: 1: Hoare triple {2561#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {2561#true} is VALID [2018-11-23 10:29:18,413 INFO L256 TraceCheckUtils]: 0: Hoare triple {2561#true} call ULTIMATE.init(); {2561#true} is VALID [2018-11-23 10:29:18,416 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 13 proven. 12 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-11-23 10:29:18,419 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:29:18,419 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 10 [2018-11-23 10:29:18,421 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 40 [2018-11-23 10:29:18,424 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:29:18,424 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 10 states. [2018-11-23 10:29:18,620 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 53 edges. 53 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:29:18,620 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-23 10:29:18,620 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-23 10:29:18,620 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=63, Unknown=0, NotChecked=0, Total=90 [2018-11-23 10:29:18,621 INFO L87 Difference]: Start difference. First operand 78 states and 93 transitions. Second operand 10 states. [2018-11-23 10:29:19,827 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:29:19,828 INFO L93 Difference]: Finished difference Result 122 states and 144 transitions. [2018-11-23 10:29:19,828 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 10:29:19,828 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 40 [2018-11-23 10:29:19,828 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:29:19,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10 states. [2018-11-23 10:29:19,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 58 transitions. [2018-11-23 10:29:19,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10 states. [2018-11-23 10:29:19,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 58 transitions. [2018-11-23 10:29:19,832 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 6 states and 58 transitions. [2018-11-23 10:29:20,022 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 58 edges. 58 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:29:20,023 INFO L225 Difference]: With dead ends: 122 [2018-11-23 10:29:20,023 INFO L226 Difference]: Without dead ends: 71 [2018-11-23 10:29:20,025 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 79 GetRequests, 71 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=27, Invalid=63, Unknown=0, NotChecked=0, Total=90 [2018-11-23 10:29:20,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states. [2018-11-23 10:29:20,308 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 71. [2018-11-23 10:29:20,308 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:29:20,308 INFO L82 GeneralOperation]: Start isEquivalent. First operand 71 states. Second operand 71 states. [2018-11-23 10:29:20,309 INFO L74 IsIncluded]: Start isIncluded. First operand 71 states. Second operand 71 states. [2018-11-23 10:29:20,309 INFO L87 Difference]: Start difference. First operand 71 states. Second operand 71 states. [2018-11-23 10:29:20,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:29:20,313 INFO L93 Difference]: Finished difference Result 71 states and 78 transitions. [2018-11-23 10:29:20,313 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 78 transitions. [2018-11-23 10:29:20,313 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:29:20,313 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:29:20,313 INFO L74 IsIncluded]: Start isIncluded. First operand 71 states. Second operand 71 states. [2018-11-23 10:29:20,314 INFO L87 Difference]: Start difference. First operand 71 states. Second operand 71 states. [2018-11-23 10:29:20,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:29:20,316 INFO L93 Difference]: Finished difference Result 71 states and 78 transitions. [2018-11-23 10:29:20,316 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 78 transitions. [2018-11-23 10:29:20,317 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:29:20,317 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:29:20,317 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:29:20,317 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:29:20,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71 states. [2018-11-23 10:29:20,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 78 transitions. [2018-11-23 10:29:20,320 INFO L78 Accepts]: Start accepts. Automaton has 71 states and 78 transitions. Word has length 40 [2018-11-23 10:29:20,320 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:29:20,320 INFO L480 AbstractCegarLoop]: Abstraction has 71 states and 78 transitions. [2018-11-23 10:29:20,320 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-23 10:29:20,320 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 78 transitions. [2018-11-23 10:29:20,321 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-11-23 10:29:20,321 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:29:20,321 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 4, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:29:20,322 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:29:20,322 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:29:20,322 INFO L82 PathProgramCache]: Analyzing trace with hash 1104036981, now seen corresponding path program 3 times [2018-11-23 10:29:20,322 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:29:20,323 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:29:20,347 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2018-11-23 10:29:21,796 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2018-11-23 10:29:21,796 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 10:29:21,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:29:21,878 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:29:22,027 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 16 [2018-11-23 10:29:22,037 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 15 [2018-11-23 10:29:22,041 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:22,045 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:22,070 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:22,070 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:36, output treesize:32 [2018-11-23 10:29:22,229 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 34 [2018-11-23 10:29:22,277 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:22,279 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:22,280 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 75 [2018-11-23 10:29:22,282 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:22,295 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:22,335 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:22,335 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:55, output treesize:51 [2018-11-23 10:29:22,559 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 36 [2018-11-23 10:29:22,607 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:22,629 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:22,651 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:22,674 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:22,700 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:22,721 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:22,721 INFO L303 Elim1Store]: Index analysis took 157 ms [2018-11-23 10:29:22,722 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 129 [2018-11-23 10:29:22,727 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:22,748 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:22,772 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:22,772 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:54, output treesize:50 [2018-11-23 10:29:23,006 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 49 [2018-11-23 10:29:23,024 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:23,028 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:23,058 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:23,069 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:23,075 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:23,083 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:23,255 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 6 case distinctions, treesize of input 49 treesize of output 145 [2018-11-23 10:29:23,264 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 8 xjuncts. [2018-11-23 10:29:23,399 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 4 xjuncts. [2018-11-23 10:29:23,565 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 4 xjuncts. [2018-11-23 10:29:23,565 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:67, output treesize:257 [2018-11-23 10:29:23,601 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:29:23,602 WARN L384 uantifierElimination]: Input elimination task: ∃ [|v_#memory_int_26|]. (let ((.cse0 (select |v_#memory_int_26| |main_~#volArray~0.base|)) (.cse1 (bvmul (_ bv12 32) main_~i~0))) (and (= (select .cse0 (bvadd |main_~#volArray~0.offset| .cse1 (_ bv4294967272 32))) (_ bv3 32)) (= (_ bv0 32) (bvadd (select .cse0 (bvadd |main_~#volArray~0.offset| .cse1 (_ bv4294967276 32))) (_ bv4294967294 32))) (= (store |v_#memory_int_26| |main_~#volArray~0.base| (store .cse0 (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse1) main_~j~0)) |#memory_int|) (= (select .cse0 (bvadd |main_~#volArray~0.offset| .cse1 (_ bv4294967280 32))) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0))) [2018-11-23 10:29:23,602 WARN L385 uantifierElimination]: ElimStorePlain result: ∃ []. (let ((.cse12 (bvmul (_ bv12 32) main_~i~0))) (let ((.cse7 (bvadd |main_~#volArray~0.offset| .cse12 (_ bv4294967272 32))) (.cse9 (bvadd |main_~#volArray~0.offset| .cse12 (_ bv4294967280 32))) (.cse8 (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse12)) (.cse11 (select |#memory_int| |main_~#volArray~0.base|)) (.cse10 (bvadd |main_~#volArray~0.offset| .cse12 (_ bv4294967276 32)))) (let ((.cse1 (= (_ bv2 32) (select .cse11 .cse10))) (.cse0 (= main_~j~0 (select .cse11 .cse8))) (.cse2 (= (select .cse11 .cse9) (_ bv0 32))) (.cse3 (= (select .cse11 .cse7) (_ bv3 32))) (.cse4 (= |main_~#volArray~0.offset| (_ bv0 32))) (.cse5 (= (_ bv2 32) main_~i~0)) (.cse6 (= (_ bv2 32) main_~MINVAL~0))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6) (and .cse0 .cse1 .cse2 .cse4 (= .cse7 .cse8) .cse5 .cse6) (and .cse0 .cse1 .cse3 .cse4 (= .cse8 .cse9) .cse5 .cse6) (and .cse0 .cse2 .cse3 (= .cse10 .cse8) .cse4 .cse5 .cse6))))) [2018-11-23 10:29:23,863 WARN L180 SmtUtils]: Spent 198.00 ms on a formula simplification that was a NOOP. DAG size: 44 [2018-11-23 10:29:24,234 WARN L180 SmtUtils]: Spent 232.00 ms on a formula simplification that was a NOOP. DAG size: 52 [2018-11-23 10:29:24,599 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 86 treesize of output 75 [2018-11-23 10:29:24,649 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:24,652 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:24,654 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:24,663 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:24,665 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:24,669 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:24,674 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:24,677 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:24,689 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:24,700 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:24,704 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:24,708 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:24,727 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:24,730 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:24,755 INFO L303 Elim1Store]: Index analysis took 117 ms [2018-11-23 10:29:24,834 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 14 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 66 treesize of output 313 [2018-11-23 10:29:24,845 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-23 10:29:25,169 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-23 10:29:27,531 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 84 treesize of output 75 [2018-11-23 10:29:27,580 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:27,581 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:27,583 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:27,585 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:27,587 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:27,589 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:27,592 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:27,594 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:27,599 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:27,601 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:27,603 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:27,605 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 11 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 276 [2018-11-23 10:29:27,610 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:27,716 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:28,824 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:28,828 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 82 treesize of output 87 [2018-11-23 10:29:28,868 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:28,875 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:28,878 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:28,880 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:28,883 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:28,884 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:28,890 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:28,895 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:28,901 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:28,903 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:28,904 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:28,906 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 9 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 68 treesize of output 247 [2018-11-23 10:29:28,913 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:29,001 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:29,719 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:29,721 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 84 treesize of output 89 [2018-11-23 10:29:29,838 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:29,840 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:29,842 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:29,848 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:29,854 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:29,854 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:29,860 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:29,862 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:29,864 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:29,870 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:29,875 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:29,877 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 9 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 70 treesize of output 249 [2018-11-23 10:29:29,882 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:29,979 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:30,311 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-2 vars, End of recursive call: and 5 xjuncts. [2018-11-23 10:29:30,311 INFO L202 ElimStorePlain]: Needed 9 recursive calls to eliminate 4 variables, input treesize:337, output treesize:391 [2018-11-23 10:29:32,339 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:29:32,340 WARN L384 uantifierElimination]: Input elimination task: ∃ [v_prenex_3, |v_#memory_int_27|, v_prenex_2, v_prenex_4]. (let ((.cse3 (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32))))) (.cse13 (bvmul (_ bv12 32) main_~i~0))) (let ((.cse7 (bvadd |main_~#volArray~0.offset| .cse13 (_ bv4294967272 32))) (.cse10 (bvadd |main_~#volArray~0.offset| .cse13 (_ bv4294967280 32))) (.cse5 (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse13)) (.cse2 (bvadd .cse3 |main_~#volArray~0.offset| .cse13)) (.cse4 (= |main_~#volArray~0.offset| (_ bv0 32))) (.cse1 (bvadd |main_~#volArray~0.offset| .cse13 (_ bv4294967276 32))) (.cse6 (= (_ bv2 32) main_~i~0)) (.cse8 (= (_ bv2 32) main_~MINVAL~0))) (or (let ((.cse0 (select v_prenex_3 |main_~#volArray~0.base|))) (and (= (select .cse0 .cse1) (_ bv2 32)) (= main_~j~0 (bvadd (select .cse0 .cse2) (_ bv4294967295 32))) (= (bvadd .cse3 (_ bv16 32)) (_ bv0 32)) .cse4 (= (store v_prenex_3 |main_~#volArray~0.base| (store .cse0 .cse5 main_~j~0)) |#memory_int|) .cse6 (= (_ bv0 32) (bvadd (select .cse0 .cse7) (_ bv4294967293 32))) .cse8)) (let ((.cse9 (select |v_#memory_int_27| |main_~#volArray~0.base|))) (and (= main_~j~0 (bvadd (select .cse9 .cse2) (_ bv4294967295 32))) (= (store |v_#memory_int_27| |main_~#volArray~0.base| (store .cse9 .cse5 main_~j~0)) |#memory_int|) (= (bvadd .cse3 (_ bv20 32)) (_ bv0 32)) (= (_ bv0 32) (bvadd (select .cse9 .cse7) (_ bv4294967293 32))) .cse4 .cse6 (= (select .cse9 .cse10) (_ bv0 32)) .cse8)) (let ((.cse11 (select v_prenex_2 |main_~#volArray~0.base|))) (and (= main_~j~0 (bvadd (select .cse11 .cse2) (_ bv4294967295 32))) (= (_ bv0 32) (bvadd (select .cse11 .cse7) (_ bv4294967293 32))) (= (select .cse11 .cse1) (_ bv2 32)) (= (select .cse11 .cse10) (_ bv0 32)) .cse4 (= (store v_prenex_2 |main_~#volArray~0.base| (store .cse11 .cse5 main_~j~0)) |#memory_int|) .cse6 .cse8)) (let ((.cse12 (select v_prenex_4 |main_~#volArray~0.base|))) (and (= (select .cse12 .cse10) (_ bv0 32)) (= (store v_prenex_4 |main_~#volArray~0.base| (store .cse12 .cse5 main_~j~0)) |#memory_int|) (= main_~j~0 (bvadd (select .cse12 .cse2) (_ bv4294967295 32))) .cse4 (= (select .cse12 .cse1) (_ bv2 32)) .cse6 (= (bvadd .cse3 (_ bv24 32)) (_ bv0 32)) .cse8))))) [2018-11-23 10:29:32,340 WARN L385 uantifierElimination]: ElimStorePlain result: ∃ []. (let ((.cse15 (bvmul (_ bv12 32) main_~i~0))) (let ((.cse14 (select |#memory_int| |main_~#volArray~0.base|)) (.cse4 (bvadd |main_~#volArray~0.offset| .cse15 (_ bv4294967272 32)))) (let ((.cse11 (bvadd |main_~#volArray~0.offset| .cse15 (_ bv4294967280 32))) (.cse12 (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32))))) (.cse5 (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse15)) (.cse9 (select .cse14 .cse4)) (.cse13 (bvadd |main_~#volArray~0.offset| .cse15 (_ bv4294967276 32)))) (let ((.cse2 (= (_ bv2 32) (select .cse14 .cse13))) (.cse10 (= (_ bv0 32) (bvadd .cse9 (_ bv4294967293 32)))) (.cse0 (= main_~j~0 (select .cse14 .cse5))) (.cse1 (= main_~j~0 (bvadd (select .cse14 (bvadd .cse12 |main_~#volArray~0.offset| .cse15)) (_ bv4294967295 32)))) (.cse3 (= (select .cse14 .cse11) (_ bv0 32))) (.cse6 (= |main_~#volArray~0.offset| (_ bv0 32))) (.cse7 (= (_ bv2 32) main_~i~0)) (.cse8 (= (_ bv2 32) main_~MINVAL~0))) (or (and .cse0 .cse1 .cse2 .cse3 (= .cse4 .cse5) .cse6 .cse7 .cse8) (and .cse0 .cse1 .cse2 .cse3 (= .cse9 (_ bv3 32)) .cse6 .cse7 .cse8) (and .cse0 .cse1 .cse10 .cse6 (= .cse5 .cse11) .cse7 .cse8) (and .cse0 .cse1 .cse2 .cse10 (= (bvadd .cse12 (_ bv16 32)) (_ bv0 32)) .cse6 .cse7 .cse8) (and .cse0 .cse1 .cse3 (= .cse13 .cse5) .cse6 .cse7 .cse8)))))) [2018-11-23 10:29:33,058 WARN L180 SmtUtils]: Spent 586.00 ms on a formula simplification that was a NOOP. DAG size: 56 [2018-11-23 10:29:33,672 WARN L180 SmtUtils]: Spent 435.00 ms on a formula simplification that was a NOOP. DAG size: 62 [2018-11-23 10:29:34,276 WARN L180 SmtUtils]: Spent 413.00 ms on a formula simplification that was a NOOP. DAG size: 64 [2018-11-23 10:29:34,636 WARN L307 Elim1Store]: Array PQE input equivalent to false [2018-11-23 10:29:34,636 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:35,193 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 81 treesize of output 68 [2018-11-23 10:29:35,242 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:35,246 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:35,250 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:35,254 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:35,257 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:35,262 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:35,264 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:35,268 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:35,271 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:35,276 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:35,279 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:35,283 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:35,288 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:35,297 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:35,301 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:35,302 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:35,305 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:35,309 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:35,313 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:35,314 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:35,322 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:35,325 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 18 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 68 treesize of output 381 [2018-11-23 10:29:35,335 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:35,443 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:35,811 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 5 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 10:29:35,811 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 6 variables, input treesize:451, output treesize:102 [2018-11-23 10:29:37,826 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:29:37,827 WARN L384 uantifierElimination]: Input elimination task: ∃ [v_prenex_5, main_~j~0, |v_#memory_int_28|, v_prenex_8, v_prenex_6, v_prenex_7]. (let ((.cse1 (bvadd main_~j~0 (_ bv2 32))) (.cse13 (bvadd main_~j~0 (_ bv1 32)))) (let ((.cse10 (bvmul (_ bv4 32) (bvneg .cse13))) (.cse14 (bvmul (_ bv4 32) (bvneg .cse1)))) (let ((.cse0 (bvsge main_~j~0 (_ bv1 32))) (.cse3 (bvadd .cse14 |main_~#volArray~0.offset| (_ bv24 32))) (.cse8 (bvadd .cse10 |main_~#volArray~0.offset| (_ bv24 32))) (.cse4 (bvadd |main_~#volArray~0.offset| (_ bv8 32))) (.cse5 (not (bvsge main_~j~0 main_~MINVAL~0))) (.cse6 (= |main_~#volArray~0.offset| (_ bv0 32))) (.cse9 (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv24 32))) (.cse7 (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (.cse11 (= (_ bv2 32) main_~MINVAL~0))) (or (let ((.cse2 (select v_prenex_5 |main_~#volArray~0.base|))) (and .cse0 (= .cse1 (select .cse2 .cse3)) (= (_ bv0 32) (select .cse2 .cse4)) .cse5 .cse6 (= (bvadd (select .cse2 .cse7) (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd (select .cse2 .cse8) (_ bv4294967295 32)) main_~j~0) (= |#memory_int| (store v_prenex_5 |main_~#volArray~0.base| (store .cse2 .cse9 (_ bv0 32)))) (= (bvadd .cse10 (_ bv24 32)) (_ bv0 32)) .cse11)) (let ((.cse12 (select |v_#memory_int_28| |main_~#volArray~0.base|))) (and .cse0 (= (store |v_#memory_int_28| |main_~#volArray~0.base| (store .cse12 .cse9 (_ bv0 32))) |#memory_int|) (= .cse13 (select .cse12 .cse8)) .cse5 (= (bvadd (select .cse12 |main_~#volArray~0.offset|) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select .cse12 .cse7) (_ bv4294967294 32)) (_ bv0 32)) .cse6 (= .cse1 (select .cse12 .cse3)) .cse11 (= (_ bv4294967280 32) .cse14))) (let ((.cse15 (select v_prenex_8 |main_~#volArray~0.base|))) (and .cse0 (= .cse1 (select .cse15 .cse3)) (= (bvadd (select .cse15 .cse8) (_ bv4294967295 32)) main_~j~0) (= (bvadd (select .cse15 |main_~#volArray~0.offset|) (_ bv4294967293 32)) (_ bv0 32)) .cse5 (= (store v_prenex_8 |main_~#volArray~0.base| (store .cse15 .cse9 (_ bv0 32))) |#memory_int|) (= (bvadd .cse10 (_ bv16 32)) (_ bv0 32)) .cse6 .cse11)) (let ((.cse16 (select v_prenex_6 |main_~#volArray~0.base|))) (and .cse0 (= .cse1 (select .cse16 .cse3)) (= .cse13 (select .cse16 .cse8)) (= (store v_prenex_6 |main_~#volArray~0.base| (store .cse16 .cse9 (_ bv0 32))) |#memory_int|) .cse5 (= (bvadd .cse10 (_ bv20 32)) (_ bv0 32)) (= (_ bv0 32) (select .cse16 .cse4)) .cse6 .cse11)) (let ((.cse17 (select v_prenex_7 |main_~#volArray~0.base|))) (and .cse0 (= .cse1 (select .cse17 .cse3)) (= (bvadd (select .cse17 |main_~#volArray~0.offset|) (_ bv4294967293 32)) (_ bv0 32)) (= .cse13 (select .cse17 .cse8)) (= (select .cse17 .cse4) (_ bv0 32)) .cse5 .cse6 (= |#memory_int| (store v_prenex_7 |main_~#volArray~0.base| (store .cse17 .cse9 (_ bv0 32)))) (= (bvadd (select .cse17 .cse7) (_ bv4294967294 32)) (_ bv0 32)) .cse11)))))) [2018-11-23 10:29:37,827 WARN L385 uantifierElimination]: ElimStorePlain result: ∃ [main_~j~0]. (let ((.cse0 (select |#memory_int| |main_~#volArray~0.base|)) (.cse3 (bvadd main_~j~0 (_ bv1 32)))) (let ((.cse1 (select .cse0 (bvadd (bvmul (_ bv4 32) (bvneg .cse3)) |main_~#volArray~0.offset| (_ bv24 32)))) (.cse2 (select .cse0 |main_~#volArray~0.offset|))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select .cse0 (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv24 32)))) (= (_ bv0 32) (select .cse0 (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (not (bvsge main_~j~0 main_~MINVAL~0)) (= .cse1 (select .cse0 (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (select .cse0 (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (_ bv24 32))) .cse2) (= .cse1 .cse3) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv0 32) (bvadd .cse2 (_ bv4294967293 32))) (= (_ bv2 32) main_~MINVAL~0)))) [2018-11-23 10:29:39,603 INFO L256 TraceCheckUtils]: 0: Hoare triple {3219#true} call ULTIMATE.init(); {3219#true} is VALID [2018-11-23 10:29:39,603 INFO L273 TraceCheckUtils]: 1: Hoare triple {3219#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {3219#true} is VALID [2018-11-23 10:29:39,603 INFO L273 TraceCheckUtils]: 2: Hoare triple {3219#true} assume true; {3219#true} is VALID [2018-11-23 10:29:39,604 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {3219#true} {3219#true} #83#return; {3219#true} is VALID [2018-11-23 10:29:39,604 INFO L256 TraceCheckUtils]: 4: Hoare triple {3219#true} call #t~ret8 := main(); {3219#true} is VALID [2018-11-23 10:29:39,604 INFO L273 TraceCheckUtils]: 5: Hoare triple {3219#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {3219#true} is VALID [2018-11-23 10:29:39,604 INFO L273 TraceCheckUtils]: 6: Hoare triple {3219#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {3242#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:39,605 INFO L273 TraceCheckUtils]: 7: Hoare triple {3242#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 3bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 3bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {3246#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:39,605 INFO L273 TraceCheckUtils]: 8: Hoare triple {3246#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32));~j~0 := 3bv32; {3250#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:39,606 INFO L273 TraceCheckUtils]: 9: Hoare triple {3250#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {3250#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:39,608 INFO L273 TraceCheckUtils]: 10: Hoare triple {3250#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {3257#(and (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:39,615 INFO L273 TraceCheckUtils]: 11: Hoare triple {3257#(and (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3261#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:39,616 INFO L273 TraceCheckUtils]: 12: Hoare triple {3261#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {3261#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:39,621 INFO L273 TraceCheckUtils]: 13: Hoare triple {3261#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {3268#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:39,628 INFO L273 TraceCheckUtils]: 14: Hoare triple {3268#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3272#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:39,629 INFO L273 TraceCheckUtils]: 15: Hoare triple {3272#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {3272#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:39,637 INFO L273 TraceCheckUtils]: 16: Hoare triple {3272#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {3279#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:39,638 INFO L273 TraceCheckUtils]: 17: Hoare triple {3279#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3279#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:39,638 INFO L273 TraceCheckUtils]: 18: Hoare triple {3279#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~j~0, 1bv32); {3279#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:39,640 INFO L273 TraceCheckUtils]: 19: Hoare triple {3279#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967284 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3289#(and (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:39,641 INFO L273 TraceCheckUtils]: 20: Hoare triple {3289#(and (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32));~j~0 := 3bv32; {3289#(and (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:39,642 INFO L273 TraceCheckUtils]: 21: Hoare triple {3289#(and (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {3289#(and (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:39,656 INFO L273 TraceCheckUtils]: 22: Hoare triple {3289#(and (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {3299#(or (and (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (_ bv4294967272 32) (bvmul (_ bv4 32) (bvneg main_~j~0))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv4294967276 32) (bvmul (_ bv4 32) (bvneg main_~j~0))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)))} is VALID [2018-11-23 10:29:41,664 INFO L273 TraceCheckUtils]: 23: Hoare triple {3299#(or (and (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (_ bv4294967272 32) (bvmul (_ bv4 32) (bvneg main_~j~0))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv4294967276 32) (bvmul (_ bv4 32) (bvneg main_~j~0))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3303#(or (and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv20 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv24 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0)) (and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv16 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)))} is UNKNOWN [2018-11-23 10:29:41,665 INFO L273 TraceCheckUtils]: 24: Hoare triple {3303#(or (and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv20 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv24 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0)) (and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv16 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)))} assume !!~bvsge32(~j~0, 1bv32); {3303#(or (and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv20 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv24 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0)) (and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv16 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)))} is VALID [2018-11-23 10:29:41,734 INFO L273 TraceCheckUtils]: 25: Hoare triple {3303#(or (and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv20 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv24 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0)) (and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv16 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {3310#(or (and (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32)))) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv16 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (_ bv4294967276 32) (bvmul (_ bv4 32) (bvneg main_~j~0))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (_ bv4294967272 32) (bvmul (_ bv4 32) (bvneg main_~j~0))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32)))) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)))} is VALID [2018-11-23 10:29:43,740 INFO L273 TraceCheckUtils]: 26: Hoare triple {3310#(or (and (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32)))) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv16 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (_ bv4294967276 32) (bvmul (_ bv4 32) (bvneg main_~j~0))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (_ bv4294967272 32) (bvmul (_ bv4 32) (bvneg main_~j~0))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32)))) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3314#(or (and (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (_ bv4294967280 32) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))))) (and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv24 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32)))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv16 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))))) (and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv20 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))))) (and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))))))} is UNKNOWN [2018-11-23 10:29:43,744 INFO L273 TraceCheckUtils]: 27: Hoare triple {3314#(or (and (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (_ bv4294967280 32) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))))) (and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv24 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32)))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv16 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))))) (and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv20 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))))) (and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))))))} assume !!~bvsge32(~j~0, 1bv32); {3318#(and (bvsge main_~j~0 (_ bv1 32)) (or (and (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (_ bv4294967280 32) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))))) (and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv24 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32)))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv16 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))))) (and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv20 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))))) (and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))))))} is VALID [2018-11-23 10:29:43,763 INFO L273 TraceCheckUtils]: 28: Hoare triple {3318#(and (bvsge main_~j~0 (_ bv1 32)) (or (and (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))) (= (_ bv4294967280 32) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))))) (and (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv24 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))))) (and (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32)))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv16 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))))) (and (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) (_ bv20 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))))) (and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967276 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0) (_ bv4294967280 32))) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0))) (_ bv4294967295 32)) main_~j~0) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv12 32) main_~i~0)))))))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(3bv32, ~i~0), ~j~0))), 4bv32); {3322#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv24 32)))) (not (bvsge main_~j~0 main_~MINVAL~0)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967295 32)) main_~j~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:43,770 INFO L273 TraceCheckUtils]: 29: Hoare triple {3322#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv24 32)))) (not (bvsge main_~j~0 main_~MINVAL~0)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967295 32)) main_~j~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3322#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv24 32)))) (not (bvsge main_~j~0 main_~MINVAL~0)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967295 32)) main_~j~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:43,777 INFO L273 TraceCheckUtils]: 30: Hoare triple {3322#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv24 32)))) (not (bvsge main_~j~0 main_~MINVAL~0)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967295 32)) main_~j~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsge32(~j~0, 1bv32); {3322#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv24 32)))) (not (bvsge main_~j~0 main_~MINVAL~0)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967295 32)) main_~j~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:43,787 INFO L273 TraceCheckUtils]: 31: Hoare triple {3322#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv24 32)))) (not (bvsge main_~j~0 main_~MINVAL~0)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967295 32)) main_~j~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3322#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv24 32)))) (not (bvsge main_~j~0 main_~MINVAL~0)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967295 32)) main_~j~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:43,810 INFO L273 TraceCheckUtils]: 32: Hoare triple {3322#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv24 32)))) (not (bvsge main_~j~0 main_~MINVAL~0)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967295 32)) main_~j~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 3bv32)); {3322#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv24 32)))) (not (bvsge main_~j~0 main_~MINVAL~0)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967295 32)) main_~j~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:43,817 INFO L273 TraceCheckUtils]: 33: Hoare triple {3322#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv24 32)))) (not (bvsge main_~j~0 main_~MINVAL~0)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967295 32)) main_~j~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 0bv32; {3338#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv24 32)))) (not (bvsge main_~j~0 main_~MINVAL~0)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967295 32)) main_~j~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:43,824 INFO L273 TraceCheckUtils]: 34: Hoare triple {3338#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv24 32)))) (not (bvsge main_~j~0 main_~MINVAL~0)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967295 32)) main_~j~0) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (_ bv24 32))) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {3342#|main_#t~short7|} is VALID [2018-11-23 10:29:43,824 INFO L273 TraceCheckUtils]: 35: Hoare triple {3342#|main_#t~short7|} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {3220#false} is VALID [2018-11-23 10:29:43,825 INFO L256 TraceCheckUtils]: 36: Hoare triple {3220#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {3220#false} is VALID [2018-11-23 10:29:43,825 INFO L273 TraceCheckUtils]: 37: Hoare triple {3220#false} ~cond := #in~cond; {3220#false} is VALID [2018-11-23 10:29:43,825 INFO L273 TraceCheckUtils]: 38: Hoare triple {3220#false} assume 0bv32 == ~cond; {3220#false} is VALID [2018-11-23 10:29:43,825 INFO L273 TraceCheckUtils]: 39: Hoare triple {3220#false} assume !false; {3220#false} is VALID [2018-11-23 10:29:43,838 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 0 proven. 62 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:29:43,839 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:29:49,680 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 88 treesize of output 86 [2018-11-23 10:29:49,699 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 86 treesize of output 90 [2018-11-23 10:29:49,717 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:49,718 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:49,721 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 129 [2018-11-23 10:29:49,811 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:49,811 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:49,831 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 4 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 108 treesize of output 176 [2018-11-23 10:29:49,894 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:49,909 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:49,947 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:08,225 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 5 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 6 case distinctions, treesize of input 111 treesize of output 355 [2018-11-23 10:30:08,225 WARN L138 XnfTransformerHelper]: expecting exponential blowup for input size 6 [2018-11-23 10:30:08,369 WARN L307 Elim1Store]: Array PQE input equivalent to true [2018-11-23 10:30:08,370 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-11-23 10:31:07,021 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,028 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:31:07,030 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,031 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,032 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,034 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,036 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,037 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,039 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,039 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,040 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,042 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,057 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 11 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 122 treesize of output 349 [2018-11-23 10:31:07,574 WARN L180 SmtUtils]: Spent 443.00 ms on a formula simplification. DAG size of input: 74 DAG size of output: 59 [2018-11-23 10:31:07,609 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,610 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,612 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,614 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,616 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,617 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,618 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,619 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,620 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,621 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,630 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,634 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 11 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 81 treesize of output 172 [2018-11-23 10:31:07,638 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 1 xjuncts. [2018-11-23 10:31:07,671 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,702 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,704 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,715 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,717 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,740 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,741 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,750 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,751 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,759 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,779 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:07,782 INFO L303 Elim1Store]: Index analysis took 130 ms [2018-11-23 10:31:07,953 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 11 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 4 case distinctions, treesize of input 72 treesize of output 235 [2018-11-23 10:31:08,009 INFO L267 ElimStorePlain]: Start of recursive call 10: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 6 xjuncts. [2018-11-23 10:31:09,254 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 6 xjuncts. [2018-11-23 10:31:25,201 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:25,202 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:25,204 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:25,205 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:25,206 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:25,209 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:25,211 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:25,213 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:25,214 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:25,215 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:25,216 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:25,217 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:25,217 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:25,219 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:25,220 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:25,222 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:25,227 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 16 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 115 treesize of output 463 [2018-11-23 10:31:25,950 WARN L180 SmtUtils]: Spent 575.00 ms on a formula simplification. DAG size of input: 83 DAG size of output: 65 [2018-11-23 10:31:26,025 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:26,051 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:26,053 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:26,069 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:26,070 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:26,141 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:26,142 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:26,151 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:26,159 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:26,180 INFO L303 Elim1Store]: Index analysis took 172 ms [2018-11-23 10:31:26,354 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 16 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 5 case distinctions, treesize of input 172 treesize of output 346 [2018-11-23 10:31:26,386 INFO L267 ElimStorePlain]: Start of recursive call 12: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 6 xjuncts. [2018-11-23 10:31:26,445 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:26,445 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:26,447 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:26,447 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:26,449 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:26,450 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:26,451 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:26,452 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:26,453 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:26,458 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 16 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 181 treesize of output 267 [2018-11-23 10:31:26,461 INFO L267 ElimStorePlain]: Start of recursive call 13: End of recursive call: and 1 xjuncts. [2018-11-23 10:31:28,269 INFO L267 ElimStorePlain]: Start of recursive call 11: 1 dim-1 vars, End of recursive call: and 4 xjuncts. [2018-11-23 10:31:44,684 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:44,685 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:44,685 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:44,685 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:44,686 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:44,686 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:44,824 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:44,824 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:44,825 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:44,865 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:44,872 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:44,880 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:44,895 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:45,082 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:45,086 INFO L303 Elim1Store]: Index analysis took 426 ms [2018-11-23 10:31:51,186 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 14 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 163 treesize of output 444 [2018-11-23 10:32:17,855 WARN L180 SmtUtils]: Spent 26.52 s on a formula simplification. DAG size of input: 138 DAG size of output: 97 [2018-11-23 10:32:17,936 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:17,937 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:17,937 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:18,117 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:18,118 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:18,123 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:18,124 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:18,124 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:18,125 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:18,349 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:18,358 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:18,368 INFO L303 Elim1Store]: Index analysis took 451 ms [2018-11-23 10:32:18,370 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 15 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 195 treesize of output 315 [2018-11-23 10:32:18,374 INFO L267 ElimStorePlain]: Start of recursive call 15: End of recursive call: and 1 xjuncts. [2018-11-23 10:32:18,553 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:18,591 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:18,604 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:18,923 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:18,932 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:19,039 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:19,039 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:19,040 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:19,041 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:19,233 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:19,267 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:19,279 INFO L303 Elim1Store]: Index analysis took 761 ms [2018-11-23 10:32:19,442 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 15 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 5 case distinctions, treesize of input 196 treesize of output 406 [2018-11-23 10:32:19,503 INFO L267 ElimStorePlain]: Start of recursive call 16: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 14 xjuncts. [2018-11-23 10:32:19,564 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:19,577 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:19,578 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:19,776 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:19,776 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:19,827 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:19,827 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:19,828 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:19,828 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:20,023 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:20,058 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:32:20,069 INFO L303 Elim1Store]: Index analysis took 522 ms [2018-11-23 10:32:20,229 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 15 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 5 case distinctions, treesize of input 186 treesize of output 396 [2018-11-23 10:32:20,361 INFO L267 ElimStorePlain]: Start of recursive call 17: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 15 xjuncts.