java -ea -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc ../../../trunk/examples/toolchains/AutomizerCInline_WitnessPrinter.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf -i ../../../trunk/examples/svcomp/array-tiling/nr4_true-unreach-call.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-61f4311 [2018-11-23 10:28:46,737 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 10:28:46,739 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 10:28:46,751 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 10:28:46,752 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 10:28:46,753 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 10:28:46,754 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 10:28:46,756 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 10:28:46,758 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 10:28:46,759 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 10:28:46,760 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 10:28:46,760 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 10:28:46,761 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 10:28:46,762 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 10:28:46,763 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 10:28:46,764 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 10:28:46,765 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 10:28:46,766 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 10:28:46,768 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 10:28:46,770 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 10:28:46,771 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 10:28:46,772 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 10:28:46,775 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 10:28:46,775 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 10:28:46,775 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 10:28:46,776 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 10:28:46,781 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 10:28:46,782 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 10:28:46,782 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 10:28:46,783 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 10:28:46,784 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 10:28:46,785 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 10:28:46,785 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 10:28:46,786 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 10:28:46,788 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 10:28:46,790 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 10:28:46,791 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Bitvector.epf [2018-11-23 10:28:46,823 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 10:28:46,823 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 10:28:46,825 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 10:28:46,826 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 10:28:46,826 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 10:28:46,826 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 10:28:46,829 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 10:28:46,830 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 10:28:46,830 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 10:28:46,830 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 10:28:46,830 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 10:28:46,830 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 10:28:46,831 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 10:28:46,831 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 10:28:46,831 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-23 10:28:46,831 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-23 10:28:46,831 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 10:28:46,833 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 10:28:46,833 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 10:28:46,833 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 10:28:46,834 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 10:28:46,834 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 10:28:46,834 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 10:28:46,834 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 10:28:46,834 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 10:28:46,835 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 10:28:46,835 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 10:28:46,835 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 10:28:46,835 INFO L133 SettingsManager]: * Trace refinement strategy=WOLF [2018-11-23 10:28:46,836 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 10:28:46,836 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-11-23 10:28:46,836 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-11-23 10:28:46,836 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-23 10:28:46,880 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 10:28:46,894 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 10:28:46,899 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 10:28:46,901 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 10:28:46,901 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 10:28:46,902 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-tiling/nr4_true-unreach-call.i [2018-11-23 10:28:46,972 INFO L221 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c2e9ffd72/a4381a4484f04d108ed3b7a8263dbd09/FLAGaddbab107 [2018-11-23 10:28:47,435 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 10:28:47,436 INFO L161 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-tiling/nr4_true-unreach-call.i [2018-11-23 10:28:47,444 INFO L355 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c2e9ffd72/a4381a4484f04d108ed3b7a8263dbd09/FLAGaddbab107 [2018-11-23 10:28:47,797 INFO L363 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c2e9ffd72/a4381a4484f04d108ed3b7a8263dbd09 [2018-11-23 10:28:47,807 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 10:28:47,808 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 10:28:47,810 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 10:28:47,812 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 10:28:47,816 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 10:28:47,818 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 10:28:47" (1/1) ... [2018-11-23 10:28:47,821 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@50669a04 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:47, skipping insertion in model container [2018-11-23 10:28:47,821 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 10:28:47" (1/1) ... [2018-11-23 10:28:47,832 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 10:28:47,858 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 10:28:48,104 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 10:28:48,111 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 10:28:48,145 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 10:28:48,170 INFO L195 MainTranslator]: Completed translation [2018-11-23 10:28:48,171 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48 WrapperNode [2018-11-23 10:28:48,171 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 10:28:48,172 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 10:28:48,172 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 10:28:48,172 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 10:28:48,183 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48" (1/1) ... [2018-11-23 10:28:48,193 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48" (1/1) ... [2018-11-23 10:28:48,202 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 10:28:48,202 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 10:28:48,202 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 10:28:48,203 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 10:28:48,212 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48" (1/1) ... [2018-11-23 10:28:48,213 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48" (1/1) ... [2018-11-23 10:28:48,215 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48" (1/1) ... [2018-11-23 10:28:48,215 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48" (1/1) ... [2018-11-23 10:28:48,229 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48" (1/1) ... [2018-11-23 10:28:48,236 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48" (1/1) ... [2018-11-23 10:28:48,238 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48" (1/1) ... [2018-11-23 10:28:48,241 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 10:28:48,241 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 10:28:48,242 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 10:28:48,242 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 10:28:48,243 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 10:28:48,368 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-23 10:28:48,368 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-23 10:28:48,368 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-23 10:28:48,368 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE4 [2018-11-23 10:28:48,368 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 10:28:48,368 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 10:28:48,369 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-23 10:28:48,369 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-23 10:28:48,369 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-11-23 10:28:48,369 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-11-23 10:28:48,369 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE4 [2018-11-23 10:28:48,369 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-23 10:28:49,011 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 10:28:49,012 INFO L280 CfgBuilder]: Removed 3 assue(true) statements. [2018-11-23 10:28:49,012 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 10:28:49 BoogieIcfgContainer [2018-11-23 10:28:49,012 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 10:28:49,014 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 10:28:49,014 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 10:28:49,017 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 10:28:49,018 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 10:28:47" (1/3) ... [2018-11-23 10:28:49,019 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@35e0ac32 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 10:28:49, skipping insertion in model container [2018-11-23 10:28:49,019 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 10:28:48" (2/3) ... [2018-11-23 10:28:49,019 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@35e0ac32 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 10:28:49, skipping insertion in model container [2018-11-23 10:28:49,019 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 10:28:49" (3/3) ... [2018-11-23 10:28:49,021 INFO L112 eAbstractionObserver]: Analyzing ICFG nr4_true-unreach-call.i [2018-11-23 10:28:49,030 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 10:28:49,038 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-23 10:28:49,057 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-23 10:28:49,093 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 10:28:49,094 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 10:28:49,094 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 10:28:49,094 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 10:28:49,094 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 10:28:49,095 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 10:28:49,095 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 10:28:49,095 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 10:28:49,095 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 10:28:49,114 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states. [2018-11-23 10:28:49,121 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-11-23 10:28:49,121 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:49,122 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:49,125 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:49,131 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:49,131 INFO L82 PathProgramCache]: Analyzing trace with hash 1453831941, now seen corresponding path program 1 times [2018-11-23 10:28:49,136 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:49,137 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:49,154 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:28:49,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:49,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:49,227 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:49,673 INFO L256 TraceCheckUtils]: 0: Hoare triple {34#true} call ULTIMATE.init(); {34#true} is VALID [2018-11-23 10:28:49,676 INFO L273 TraceCheckUtils]: 1: Hoare triple {34#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {34#true} is VALID [2018-11-23 10:28:49,677 INFO L273 TraceCheckUtils]: 2: Hoare triple {34#true} assume true; {34#true} is VALID [2018-11-23 10:28:49,677 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {34#true} {34#true} #83#return; {34#true} is VALID [2018-11-23 10:28:49,677 INFO L256 TraceCheckUtils]: 4: Hoare triple {34#true} call #t~ret8 := main(); {34#true} is VALID [2018-11-23 10:28:49,678 INFO L273 TraceCheckUtils]: 5: Hoare triple {34#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {34#true} is VALID [2018-11-23 10:28:49,678 INFO L273 TraceCheckUtils]: 6: Hoare triple {34#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {34#true} is VALID [2018-11-23 10:28:49,678 INFO L273 TraceCheckUtils]: 7: Hoare triple {34#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {34#true} is VALID [2018-11-23 10:28:49,679 INFO L273 TraceCheckUtils]: 8: Hoare triple {34#true} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {34#true} is VALID [2018-11-23 10:28:49,679 INFO L273 TraceCheckUtils]: 9: Hoare triple {34#true} ~i~0 := 0bv32; {34#true} is VALID [2018-11-23 10:28:49,679 INFO L273 TraceCheckUtils]: 10: Hoare triple {34#true} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {34#true} is VALID [2018-11-23 10:28:49,682 INFO L273 TraceCheckUtils]: 11: Hoare triple {34#true} assume #t~short7; {72#|main_#t~short7|} is VALID [2018-11-23 10:28:49,691 INFO L256 TraceCheckUtils]: 12: Hoare triple {72#|main_#t~short7|} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {76#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:49,704 INFO L273 TraceCheckUtils]: 13: Hoare triple {76#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {80#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:49,717 INFO L273 TraceCheckUtils]: 14: Hoare triple {80#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 == ~cond; {35#false} is VALID [2018-11-23 10:28:49,718 INFO L273 TraceCheckUtils]: 15: Hoare triple {35#false} assume !false; {35#false} is VALID [2018-11-23 10:28:49,722 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:49,722 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:28:49,726 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:28:49,726 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 10:28:49,732 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 16 [2018-11-23 10:28:49,735 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:28:49,739 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states. [2018-11-23 10:28:49,824 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 16 edges. 16 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:49,825 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 10:28:49,832 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 10:28:49,833 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 10:28:49,835 INFO L87 Difference]: Start difference. First operand 31 states. Second operand 5 states. [2018-11-23 10:28:50,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:50,611 INFO L93 Difference]: Finished difference Result 60 states and 81 transitions. [2018-11-23 10:28:50,612 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 10:28:50,612 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 16 [2018-11-23 10:28:50,612 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:28:50,613 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-23 10:28:50,625 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 81 transitions. [2018-11-23 10:28:50,626 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-23 10:28:50,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 81 transitions. [2018-11-23 10:28:50,632 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states and 81 transitions. [2018-11-23 10:28:51,147 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 81 edges. 81 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:51,160 INFO L225 Difference]: With dead ends: 60 [2018-11-23 10:28:51,160 INFO L226 Difference]: Without dead ends: 31 [2018-11-23 10:28:51,164 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 10:28:51,179 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2018-11-23 10:28:51,217 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 30. [2018-11-23 10:28:51,217 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:28:51,218 INFO L82 GeneralOperation]: Start isEquivalent. First operand 31 states. Second operand 30 states. [2018-11-23 10:28:51,218 INFO L74 IsIncluded]: Start isIncluded. First operand 31 states. Second operand 30 states. [2018-11-23 10:28:51,219 INFO L87 Difference]: Start difference. First operand 31 states. Second operand 30 states. [2018-11-23 10:28:51,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:51,223 INFO L93 Difference]: Finished difference Result 31 states and 35 transitions. [2018-11-23 10:28:51,224 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 35 transitions. [2018-11-23 10:28:51,224 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:51,225 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:51,225 INFO L74 IsIncluded]: Start isIncluded. First operand 30 states. Second operand 31 states. [2018-11-23 10:28:51,225 INFO L87 Difference]: Start difference. First operand 30 states. Second operand 31 states. [2018-11-23 10:28:51,229 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:51,230 INFO L93 Difference]: Finished difference Result 31 states and 35 transitions. [2018-11-23 10:28:51,230 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 35 transitions. [2018-11-23 10:28:51,231 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:51,231 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:51,231 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:28:51,231 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:28:51,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-11-23 10:28:51,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 34 transitions. [2018-11-23 10:28:51,237 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 34 transitions. Word has length 16 [2018-11-23 10:28:51,237 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:28:51,237 INFO L480 AbstractCegarLoop]: Abstraction has 30 states and 34 transitions. [2018-11-23 10:28:51,238 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 10:28:51,238 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 34 transitions. [2018-11-23 10:28:51,239 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-11-23 10:28:51,239 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:51,239 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:51,240 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:51,240 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:51,240 INFO L82 PathProgramCache]: Analyzing trace with hash 1455678983, now seen corresponding path program 1 times [2018-11-23 10:28:51,241 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:51,241 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:51,274 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:28:51,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:51,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:51,352 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:51,480 INFO L256 TraceCheckUtils]: 0: Hoare triple {267#true} call ULTIMATE.init(); {267#true} is VALID [2018-11-23 10:28:51,481 INFO L273 TraceCheckUtils]: 1: Hoare triple {267#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {267#true} is VALID [2018-11-23 10:28:51,482 INFO L273 TraceCheckUtils]: 2: Hoare triple {267#true} assume true; {267#true} is VALID [2018-11-23 10:28:51,482 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {267#true} {267#true} #83#return; {267#true} is VALID [2018-11-23 10:28:51,483 INFO L256 TraceCheckUtils]: 4: Hoare triple {267#true} call #t~ret8 := main(); {267#true} is VALID [2018-11-23 10:28:51,483 INFO L273 TraceCheckUtils]: 5: Hoare triple {267#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {267#true} is VALID [2018-11-23 10:28:51,484 INFO L273 TraceCheckUtils]: 6: Hoare triple {267#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {290#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} is VALID [2018-11-23 10:28:51,485 INFO L273 TraceCheckUtils]: 7: Hoare triple {290#(bvsgt ~CELLCOUNT~0 (_ bv1 32))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {294#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:51,501 INFO L273 TraceCheckUtils]: 8: Hoare triple {294#(and (= (_ bv0 32) (bvsrem ~CELLCOUNT~0 (_ bv4 32))) (bvsgt ~CELLCOUNT~0 (_ bv1 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {268#false} is VALID [2018-11-23 10:28:51,501 INFO L273 TraceCheckUtils]: 9: Hoare triple {268#false} ~i~0 := 0bv32; {268#false} is VALID [2018-11-23 10:28:51,502 INFO L273 TraceCheckUtils]: 10: Hoare triple {268#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {268#false} is VALID [2018-11-23 10:28:51,502 INFO L273 TraceCheckUtils]: 11: Hoare triple {268#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {268#false} is VALID [2018-11-23 10:28:51,502 INFO L256 TraceCheckUtils]: 12: Hoare triple {268#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {268#false} is VALID [2018-11-23 10:28:51,502 INFO L273 TraceCheckUtils]: 13: Hoare triple {268#false} ~cond := #in~cond; {268#false} is VALID [2018-11-23 10:28:51,503 INFO L273 TraceCheckUtils]: 14: Hoare triple {268#false} assume 0bv32 == ~cond; {268#false} is VALID [2018-11-23 10:28:51,503 INFO L273 TraceCheckUtils]: 15: Hoare triple {268#false} assume !false; {268#false} is VALID [2018-11-23 10:28:51,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:51,504 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:28:51,509 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:28:51,509 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 10:28:51,511 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2018-11-23 10:28:51,511 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:28:51,512 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states. [2018-11-23 10:28:51,555 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 16 edges. 16 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:51,555 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 10:28:51,555 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 10:28:51,556 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 10:28:51,556 INFO L87 Difference]: Start difference. First operand 30 states and 34 transitions. Second operand 4 states. [2018-11-23 10:28:51,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:51,965 INFO L93 Difference]: Finished difference Result 52 states and 60 transitions. [2018-11-23 10:28:51,965 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 10:28:51,966 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2018-11-23 10:28:51,966 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:28:51,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-23 10:28:51,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 50 transitions. [2018-11-23 10:28:51,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-23 10:28:51,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 50 transitions. [2018-11-23 10:28:51,973 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states and 50 transitions. [2018-11-23 10:28:52,163 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 50 edges. 50 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:52,165 INFO L225 Difference]: With dead ends: 52 [2018-11-23 10:28:52,165 INFO L226 Difference]: Without dead ends: 35 [2018-11-23 10:28:52,166 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 13 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 10:28:52,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states. [2018-11-23 10:28:52,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 31. [2018-11-23 10:28:52,199 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:28:52,199 INFO L82 GeneralOperation]: Start isEquivalent. First operand 35 states. Second operand 31 states. [2018-11-23 10:28:52,199 INFO L74 IsIncluded]: Start isIncluded. First operand 35 states. Second operand 31 states. [2018-11-23 10:28:52,199 INFO L87 Difference]: Start difference. First operand 35 states. Second operand 31 states. [2018-11-23 10:28:52,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:52,205 INFO L93 Difference]: Finished difference Result 35 states and 41 transitions. [2018-11-23 10:28:52,205 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 41 transitions. [2018-11-23 10:28:52,206 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:52,206 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:52,206 INFO L74 IsIncluded]: Start isIncluded. First operand 31 states. Second operand 35 states. [2018-11-23 10:28:52,206 INFO L87 Difference]: Start difference. First operand 31 states. Second operand 35 states. [2018-11-23 10:28:52,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:52,210 INFO L93 Difference]: Finished difference Result 35 states and 41 transitions. [2018-11-23 10:28:52,210 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 41 transitions. [2018-11-23 10:28:52,211 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:52,211 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:52,211 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:28:52,211 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:28:52,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2018-11-23 10:28:52,214 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 35 transitions. [2018-11-23 10:28:52,214 INFO L78 Accepts]: Start accepts. Automaton has 31 states and 35 transitions. Word has length 16 [2018-11-23 10:28:52,214 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:28:52,214 INFO L480 AbstractCegarLoop]: Abstraction has 31 states and 35 transitions. [2018-11-23 10:28:52,214 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 10:28:52,214 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 35 transitions. [2018-11-23 10:28:52,215 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-11-23 10:28:52,215 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:52,215 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:52,216 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:52,216 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:52,216 INFO L82 PathProgramCache]: Analyzing trace with hash -2089835012, now seen corresponding path program 1 times [2018-11-23 10:28:52,217 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:52,217 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:52,234 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:28:52,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:52,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:52,285 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:52,371 INFO L256 TraceCheckUtils]: 0: Hoare triple {501#true} call ULTIMATE.init(); {501#true} is VALID [2018-11-23 10:28:52,372 INFO L273 TraceCheckUtils]: 1: Hoare triple {501#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {501#true} is VALID [2018-11-23 10:28:52,373 INFO L273 TraceCheckUtils]: 2: Hoare triple {501#true} assume true; {501#true} is VALID [2018-11-23 10:28:52,373 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {501#true} {501#true} #83#return; {501#true} is VALID [2018-11-23 10:28:52,373 INFO L256 TraceCheckUtils]: 4: Hoare triple {501#true} call #t~ret8 := main(); {501#true} is VALID [2018-11-23 10:28:52,374 INFO L273 TraceCheckUtils]: 5: Hoare triple {501#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {501#true} is VALID [2018-11-23 10:28:52,374 INFO L273 TraceCheckUtils]: 6: Hoare triple {501#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {501#true} is VALID [2018-11-23 10:28:52,374 INFO L273 TraceCheckUtils]: 7: Hoare triple {501#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {501#true} is VALID [2018-11-23 10:28:52,376 INFO L273 TraceCheckUtils]: 8: Hoare triple {501#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32));~j~0 := 4bv32; {530#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:52,376 INFO L273 TraceCheckUtils]: 9: Hoare triple {530#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} assume !~bvsge32(~j~0, 1bv32); {502#false} is VALID [2018-11-23 10:28:52,377 INFO L273 TraceCheckUtils]: 10: Hoare triple {502#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {502#false} is VALID [2018-11-23 10:28:52,377 INFO L273 TraceCheckUtils]: 11: Hoare triple {502#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {502#false} is VALID [2018-11-23 10:28:52,378 INFO L273 TraceCheckUtils]: 12: Hoare triple {502#false} ~i~0 := 0bv32; {502#false} is VALID [2018-11-23 10:28:52,378 INFO L273 TraceCheckUtils]: 13: Hoare triple {502#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {502#false} is VALID [2018-11-23 10:28:52,379 INFO L273 TraceCheckUtils]: 14: Hoare triple {502#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {502#false} is VALID [2018-11-23 10:28:52,379 INFO L256 TraceCheckUtils]: 15: Hoare triple {502#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {502#false} is VALID [2018-11-23 10:28:52,380 INFO L273 TraceCheckUtils]: 16: Hoare triple {502#false} ~cond := #in~cond; {502#false} is VALID [2018-11-23 10:28:52,380 INFO L273 TraceCheckUtils]: 17: Hoare triple {502#false} assume 0bv32 == ~cond; {502#false} is VALID [2018-11-23 10:28:52,380 INFO L273 TraceCheckUtils]: 18: Hoare triple {502#false} assume !false; {502#false} is VALID [2018-11-23 10:28:52,381 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:52,382 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 10:28:52,385 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:28:52,385 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 10:28:52,386 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 19 [2018-11-23 10:28:52,386 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:28:52,386 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states. [2018-11-23 10:28:52,436 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 19 edges. 19 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:52,436 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 10:28:52,436 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 10:28:52,437 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 10:28:52,437 INFO L87 Difference]: Start difference. First operand 31 states and 35 transitions. Second operand 3 states. [2018-11-23 10:28:52,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:52,664 INFO L93 Difference]: Finished difference Result 56 states and 66 transitions. [2018-11-23 10:28:52,664 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 10:28:52,664 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 19 [2018-11-23 10:28:52,665 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:28:52,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 10:28:52,668 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 55 transitions. [2018-11-23 10:28:52,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2018-11-23 10:28:52,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 55 transitions. [2018-11-23 10:28:52,671 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 3 states and 55 transitions. [2018-11-23 10:28:52,850 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 55 edges. 55 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:52,853 INFO L225 Difference]: With dead ends: 56 [2018-11-23 10:28:52,854 INFO L226 Difference]: Without dead ends: 34 [2018-11-23 10:28:52,854 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 17 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 10:28:52,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-11-23 10:28:52,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 32. [2018-11-23 10:28:52,880 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:28:52,880 INFO L82 GeneralOperation]: Start isEquivalent. First operand 34 states. Second operand 32 states. [2018-11-23 10:28:52,881 INFO L74 IsIncluded]: Start isIncluded. First operand 34 states. Second operand 32 states. [2018-11-23 10:28:52,881 INFO L87 Difference]: Start difference. First operand 34 states. Second operand 32 states. [2018-11-23 10:28:52,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:52,884 INFO L93 Difference]: Finished difference Result 34 states and 39 transitions. [2018-11-23 10:28:52,884 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 39 transitions. [2018-11-23 10:28:52,884 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:52,885 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:52,885 INFO L74 IsIncluded]: Start isIncluded. First operand 32 states. Second operand 34 states. [2018-11-23 10:28:52,885 INFO L87 Difference]: Start difference. First operand 32 states. Second operand 34 states. [2018-11-23 10:28:52,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:52,888 INFO L93 Difference]: Finished difference Result 34 states and 39 transitions. [2018-11-23 10:28:52,888 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 39 transitions. [2018-11-23 10:28:52,889 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:52,889 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:52,889 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:28:52,889 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:28:52,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32 states. [2018-11-23 10:28:52,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 36 transitions. [2018-11-23 10:28:52,892 INFO L78 Accepts]: Start accepts. Automaton has 32 states and 36 transitions. Word has length 19 [2018-11-23 10:28:52,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:28:52,892 INFO L480 AbstractCegarLoop]: Abstraction has 32 states and 36 transitions. [2018-11-23 10:28:52,892 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 10:28:52,892 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 36 transitions. [2018-11-23 10:28:52,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-11-23 10:28:52,893 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:52,893 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:52,894 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:52,894 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:52,894 INFO L82 PathProgramCache]: Analyzing trace with hash 1382648830, now seen corresponding path program 1 times [2018-11-23 10:28:52,895 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:52,895 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:52,922 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:28:52,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:52,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:52,997 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:53,071 INFO L256 TraceCheckUtils]: 0: Hoare triple {749#true} call ULTIMATE.init(); {749#true} is VALID [2018-11-23 10:28:53,072 INFO L273 TraceCheckUtils]: 1: Hoare triple {749#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {749#true} is VALID [2018-11-23 10:28:53,072 INFO L273 TraceCheckUtils]: 2: Hoare triple {749#true} assume true; {749#true} is VALID [2018-11-23 10:28:53,072 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {749#true} {749#true} #83#return; {749#true} is VALID [2018-11-23 10:28:53,073 INFO L256 TraceCheckUtils]: 4: Hoare triple {749#true} call #t~ret8 := main(); {749#true} is VALID [2018-11-23 10:28:53,073 INFO L273 TraceCheckUtils]: 5: Hoare triple {749#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {749#true} is VALID [2018-11-23 10:28:53,095 INFO L273 TraceCheckUtils]: 6: Hoare triple {749#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {772#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:28:53,111 INFO L273 TraceCheckUtils]: 7: Hoare triple {772#(= (_ bv2 32) main_~MINVAL~0)} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {772#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:28:53,120 INFO L273 TraceCheckUtils]: 8: Hoare triple {772#(= (_ bv2 32) main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32));~j~0 := 4bv32; {779#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:53,135 INFO L273 TraceCheckUtils]: 9: Hoare triple {779#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {779#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:53,144 INFO L273 TraceCheckUtils]: 10: Hoare triple {779#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {750#false} is VALID [2018-11-23 10:28:53,145 INFO L273 TraceCheckUtils]: 11: Hoare triple {750#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {750#false} is VALID [2018-11-23 10:28:53,145 INFO L273 TraceCheckUtils]: 12: Hoare triple {750#false} assume !~bvsge32(~j~0, 1bv32); {750#false} is VALID [2018-11-23 10:28:53,146 INFO L273 TraceCheckUtils]: 13: Hoare triple {750#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {750#false} is VALID [2018-11-23 10:28:53,146 INFO L273 TraceCheckUtils]: 14: Hoare triple {750#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {750#false} is VALID [2018-11-23 10:28:53,146 INFO L273 TraceCheckUtils]: 15: Hoare triple {750#false} ~i~0 := 0bv32; {750#false} is VALID [2018-11-23 10:28:53,147 INFO L273 TraceCheckUtils]: 16: Hoare triple {750#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {750#false} is VALID [2018-11-23 10:28:53,147 INFO L273 TraceCheckUtils]: 17: Hoare triple {750#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {750#false} is VALID [2018-11-23 10:28:53,147 INFO L256 TraceCheckUtils]: 18: Hoare triple {750#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {750#false} is VALID [2018-11-23 10:28:53,148 INFO L273 TraceCheckUtils]: 19: Hoare triple {750#false} ~cond := #in~cond; {750#false} is VALID [2018-11-23 10:28:53,148 INFO L273 TraceCheckUtils]: 20: Hoare triple {750#false} assume 0bv32 == ~cond; {750#false} is VALID [2018-11-23 10:28:53,148 INFO L273 TraceCheckUtils]: 21: Hoare triple {750#false} assume !false; {750#false} is VALID [2018-11-23 10:28:53,150 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:53,150 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (5)] Exception during sending of exit command (exit): Broken pipe [2018-11-23 10:28:53,156 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 10:28:53,157 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 10:28:53,157 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 22 [2018-11-23 10:28:53,157 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:28:53,158 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states. [2018-11-23 10:28:53,296 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 22 edges. 22 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:53,296 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 10:28:53,297 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 10:28:53,297 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 10:28:53,297 INFO L87 Difference]: Start difference. First operand 32 states and 36 transitions. Second operand 4 states. [2018-11-23 10:28:53,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:53,561 INFO L93 Difference]: Finished difference Result 57 states and 66 transitions. [2018-11-23 10:28:53,561 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 10:28:53,562 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 22 [2018-11-23 10:28:53,562 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:28:53,562 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-23 10:28:53,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 54 transitions. [2018-11-23 10:28:53,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-23 10:28:53,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 54 transitions. [2018-11-23 10:28:53,567 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states and 54 transitions. [2018-11-23 10:28:53,718 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 54 edges. 54 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:53,720 INFO L225 Difference]: With dead ends: 57 [2018-11-23 10:28:53,720 INFO L226 Difference]: Without dead ends: 34 [2018-11-23 10:28:53,721 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 19 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 10:28:53,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-11-23 10:28:53,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 33. [2018-11-23 10:28:53,752 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:28:53,752 INFO L82 GeneralOperation]: Start isEquivalent. First operand 34 states. Second operand 33 states. [2018-11-23 10:28:53,753 INFO L74 IsIncluded]: Start isIncluded. First operand 34 states. Second operand 33 states. [2018-11-23 10:28:53,753 INFO L87 Difference]: Start difference. First operand 34 states. Second operand 33 states. [2018-11-23 10:28:53,754 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:53,755 INFO L93 Difference]: Finished difference Result 34 states and 38 transitions. [2018-11-23 10:28:53,755 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 38 transitions. [2018-11-23 10:28:53,755 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:53,756 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:53,756 INFO L74 IsIncluded]: Start isIncluded. First operand 33 states. Second operand 34 states. [2018-11-23 10:28:53,756 INFO L87 Difference]: Start difference. First operand 33 states. Second operand 34 states. [2018-11-23 10:28:53,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:53,758 INFO L93 Difference]: Finished difference Result 34 states and 38 transitions. [2018-11-23 10:28:53,759 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 38 transitions. [2018-11-23 10:28:53,759 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:53,759 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:53,760 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:28:53,760 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:28:53,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33 states. [2018-11-23 10:28:53,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 37 transitions. [2018-11-23 10:28:53,762 INFO L78 Accepts]: Start accepts. Automaton has 33 states and 37 transitions. Word has length 22 [2018-11-23 10:28:53,763 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:28:53,763 INFO L480 AbstractCegarLoop]: Abstraction has 33 states and 37 transitions. [2018-11-23 10:28:53,763 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 10:28:53,763 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 37 transitions. [2018-11-23 10:28:53,764 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-11-23 10:28:53,764 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:53,764 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:53,764 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:53,765 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:53,765 INFO L82 PathProgramCache]: Analyzing trace with hash 1124483392, now seen corresponding path program 1 times [2018-11-23 10:28:53,765 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:53,765 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:53,794 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:28:53,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:53,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:53,856 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:53,906 INFO L256 TraceCheckUtils]: 0: Hoare triple {1010#true} call ULTIMATE.init(); {1010#true} is VALID [2018-11-23 10:28:53,907 INFO L273 TraceCheckUtils]: 1: Hoare triple {1010#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1010#true} is VALID [2018-11-23 10:28:53,907 INFO L273 TraceCheckUtils]: 2: Hoare triple {1010#true} assume true; {1010#true} is VALID [2018-11-23 10:28:53,908 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1010#true} {1010#true} #83#return; {1010#true} is VALID [2018-11-23 10:28:53,908 INFO L256 TraceCheckUtils]: 4: Hoare triple {1010#true} call #t~ret8 := main(); {1010#true} is VALID [2018-11-23 10:28:53,908 INFO L273 TraceCheckUtils]: 5: Hoare triple {1010#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1010#true} is VALID [2018-11-23 10:28:53,909 INFO L273 TraceCheckUtils]: 6: Hoare triple {1010#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1010#true} is VALID [2018-11-23 10:28:53,909 INFO L273 TraceCheckUtils]: 7: Hoare triple {1010#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1010#true} is VALID [2018-11-23 10:28:53,910 INFO L273 TraceCheckUtils]: 8: Hoare triple {1010#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32));~j~0 := 4bv32; {1039#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:53,910 INFO L273 TraceCheckUtils]: 9: Hoare triple {1039#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {1039#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:53,911 INFO L273 TraceCheckUtils]: 10: Hoare triple {1039#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {1039#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:53,911 INFO L273 TraceCheckUtils]: 11: Hoare triple {1039#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1049#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 10:28:53,914 INFO L273 TraceCheckUtils]: 12: Hoare triple {1049#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} assume !~bvsge32(~j~0, 1bv32); {1011#false} is VALID [2018-11-23 10:28:53,914 INFO L273 TraceCheckUtils]: 13: Hoare triple {1011#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1011#false} is VALID [2018-11-23 10:28:53,915 INFO L273 TraceCheckUtils]: 14: Hoare triple {1011#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1011#false} is VALID [2018-11-23 10:28:53,915 INFO L273 TraceCheckUtils]: 15: Hoare triple {1011#false} ~i~0 := 0bv32; {1011#false} is VALID [2018-11-23 10:28:53,915 INFO L273 TraceCheckUtils]: 16: Hoare triple {1011#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1011#false} is VALID [2018-11-23 10:28:53,916 INFO L273 TraceCheckUtils]: 17: Hoare triple {1011#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1011#false} is VALID [2018-11-23 10:28:53,916 INFO L256 TraceCheckUtils]: 18: Hoare triple {1011#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1011#false} is VALID [2018-11-23 10:28:53,916 INFO L273 TraceCheckUtils]: 19: Hoare triple {1011#false} ~cond := #in~cond; {1011#false} is VALID [2018-11-23 10:28:53,916 INFO L273 TraceCheckUtils]: 20: Hoare triple {1011#false} assume 0bv32 == ~cond; {1011#false} is VALID [2018-11-23 10:28:53,917 INFO L273 TraceCheckUtils]: 21: Hoare triple {1011#false} assume !false; {1011#false} is VALID [2018-11-23 10:28:53,918 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:53,918 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:28:54,007 INFO L273 TraceCheckUtils]: 21: Hoare triple {1011#false} assume !false; {1011#false} is VALID [2018-11-23 10:28:54,007 INFO L273 TraceCheckUtils]: 20: Hoare triple {1011#false} assume 0bv32 == ~cond; {1011#false} is VALID [2018-11-23 10:28:54,007 INFO L273 TraceCheckUtils]: 19: Hoare triple {1011#false} ~cond := #in~cond; {1011#false} is VALID [2018-11-23 10:28:54,008 INFO L256 TraceCheckUtils]: 18: Hoare triple {1011#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1011#false} is VALID [2018-11-23 10:28:54,008 INFO L273 TraceCheckUtils]: 17: Hoare triple {1011#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1011#false} is VALID [2018-11-23 10:28:54,008 INFO L273 TraceCheckUtils]: 16: Hoare triple {1011#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1011#false} is VALID [2018-11-23 10:28:54,008 INFO L273 TraceCheckUtils]: 15: Hoare triple {1011#false} ~i~0 := 0bv32; {1011#false} is VALID [2018-11-23 10:28:54,009 INFO L273 TraceCheckUtils]: 14: Hoare triple {1011#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1011#false} is VALID [2018-11-23 10:28:54,009 INFO L273 TraceCheckUtils]: 13: Hoare triple {1011#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1011#false} is VALID [2018-11-23 10:28:54,010 INFO L273 TraceCheckUtils]: 12: Hoare triple {1107#(bvsge main_~j~0 (_ bv1 32))} assume !~bvsge32(~j~0, 1bv32); {1011#false} is VALID [2018-11-23 10:28:54,011 INFO L273 TraceCheckUtils]: 11: Hoare triple {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1107#(bvsge main_~j~0 (_ bv1 32))} is VALID [2018-11-23 10:28:54,017 INFO L273 TraceCheckUtils]: 10: Hoare triple {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-23 10:28:54,018 INFO L273 TraceCheckUtils]: 9: Hoare triple {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} assume !!~bvsge32(~j~0, 1bv32); {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-23 10:28:54,019 INFO L273 TraceCheckUtils]: 8: Hoare triple {1010#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32));~j~0 := 4bv32; {1111#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32))} is VALID [2018-11-23 10:28:54,019 INFO L273 TraceCheckUtils]: 7: Hoare triple {1010#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1010#true} is VALID [2018-11-23 10:28:54,019 INFO L273 TraceCheckUtils]: 6: Hoare triple {1010#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1010#true} is VALID [2018-11-23 10:28:54,020 INFO L273 TraceCheckUtils]: 5: Hoare triple {1010#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1010#true} is VALID [2018-11-23 10:28:54,020 INFO L256 TraceCheckUtils]: 4: Hoare triple {1010#true} call #t~ret8 := main(); {1010#true} is VALID [2018-11-23 10:28:54,020 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1010#true} {1010#true} #83#return; {1010#true} is VALID [2018-11-23 10:28:54,020 INFO L273 TraceCheckUtils]: 2: Hoare triple {1010#true} assume true; {1010#true} is VALID [2018-11-23 10:28:54,021 INFO L273 TraceCheckUtils]: 1: Hoare triple {1010#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1010#true} is VALID [2018-11-23 10:28:54,021 INFO L256 TraceCheckUtils]: 0: Hoare triple {1010#true} call ULTIMATE.init(); {1010#true} is VALID [2018-11-23 10:28:54,022 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:54,024 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:28:54,024 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 6 [2018-11-23 10:28:54,025 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 22 [2018-11-23 10:28:54,025 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:28:54,026 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 6 states. [2018-11-23 10:28:54,115 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 27 edges. 27 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:54,115 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 10:28:54,115 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 10:28:54,115 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-11-23 10:28:54,116 INFO L87 Difference]: Start difference. First operand 33 states and 37 transitions. Second operand 6 states. [2018-11-23 10:28:54,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:54,681 INFO L93 Difference]: Finished difference Result 65 states and 78 transitions. [2018-11-23 10:28:54,681 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 10:28:54,681 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 22 [2018-11-23 10:28:54,681 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:28:54,681 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6 states. [2018-11-23 10:28:54,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 65 transitions. [2018-11-23 10:28:54,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6 states. [2018-11-23 10:28:54,686 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 65 transitions. [2018-11-23 10:28:54,686 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 6 states and 65 transitions. [2018-11-23 10:28:54,907 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 65 edges. 65 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:54,909 INFO L225 Difference]: With dead ends: 65 [2018-11-23 10:28:54,909 INFO L226 Difference]: Without dead ends: 41 [2018-11-23 10:28:54,910 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=23, Unknown=0, NotChecked=0, Total=42 [2018-11-23 10:28:54,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2018-11-23 10:28:54,954 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 41. [2018-11-23 10:28:54,954 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:28:54,954 INFO L82 GeneralOperation]: Start isEquivalent. First operand 41 states. Second operand 41 states. [2018-11-23 10:28:54,955 INFO L74 IsIncluded]: Start isIncluded. First operand 41 states. Second operand 41 states. [2018-11-23 10:28:54,955 INFO L87 Difference]: Start difference. First operand 41 states. Second operand 41 states. [2018-11-23 10:28:54,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:54,957 INFO L93 Difference]: Finished difference Result 41 states and 47 transitions. [2018-11-23 10:28:54,957 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 47 transitions. [2018-11-23 10:28:54,958 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:54,958 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:54,958 INFO L74 IsIncluded]: Start isIncluded. First operand 41 states. Second operand 41 states. [2018-11-23 10:28:54,958 INFO L87 Difference]: Start difference. First operand 41 states. Second operand 41 states. [2018-11-23 10:28:54,960 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:54,960 INFO L93 Difference]: Finished difference Result 41 states and 47 transitions. [2018-11-23 10:28:54,961 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 47 transitions. [2018-11-23 10:28:54,962 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:54,962 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:54,962 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:28:54,962 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:28:54,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2018-11-23 10:28:54,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 47 transitions. [2018-11-23 10:28:54,965 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 47 transitions. Word has length 22 [2018-11-23 10:28:54,965 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:28:54,965 INFO L480 AbstractCegarLoop]: Abstraction has 41 states and 47 transitions. [2018-11-23 10:28:54,965 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 10:28:54,965 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 47 transitions. [2018-11-23 10:28:54,966 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-11-23 10:28:54,967 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:54,967 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:54,967 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:54,967 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:54,968 INFO L82 PathProgramCache]: Analyzing trace with hash 1422556282, now seen corresponding path program 1 times [2018-11-23 10:28:54,968 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:54,968 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:54,987 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 10:28:55,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:55,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:55,058 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:55,152 INFO L256 TraceCheckUtils]: 0: Hoare triple {1377#true} call ULTIMATE.init(); {1377#true} is VALID [2018-11-23 10:28:55,152 INFO L273 TraceCheckUtils]: 1: Hoare triple {1377#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1377#true} is VALID [2018-11-23 10:28:55,152 INFO L273 TraceCheckUtils]: 2: Hoare triple {1377#true} assume true; {1377#true} is VALID [2018-11-23 10:28:55,153 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1377#true} {1377#true} #83#return; {1377#true} is VALID [2018-11-23 10:28:55,153 INFO L256 TraceCheckUtils]: 4: Hoare triple {1377#true} call #t~ret8 := main(); {1377#true} is VALID [2018-11-23 10:28:55,153 INFO L273 TraceCheckUtils]: 5: Hoare triple {1377#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1377#true} is VALID [2018-11-23 10:28:55,169 INFO L273 TraceCheckUtils]: 6: Hoare triple {1377#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1400#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:28:55,174 INFO L273 TraceCheckUtils]: 7: Hoare triple {1400#(= (_ bv2 32) main_~MINVAL~0)} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1400#(= (_ bv2 32) main_~MINVAL~0)} is VALID [2018-11-23 10:28:55,175 INFO L273 TraceCheckUtils]: 8: Hoare triple {1400#(= (_ bv2 32) main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32));~j~0 := 4bv32; {1407#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:55,176 INFO L273 TraceCheckUtils]: 9: Hoare triple {1407#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {1407#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:55,182 INFO L273 TraceCheckUtils]: 10: Hoare triple {1407#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {1407#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:55,185 INFO L273 TraceCheckUtils]: 11: Hoare triple {1407#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1417#(and (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:55,186 INFO L273 TraceCheckUtils]: 12: Hoare triple {1417#(and (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {1417#(and (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:55,187 INFO L273 TraceCheckUtils]: 13: Hoare triple {1417#(and (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {1378#false} is VALID [2018-11-23 10:28:55,187 INFO L273 TraceCheckUtils]: 14: Hoare triple {1378#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1378#false} is VALID [2018-11-23 10:28:55,187 INFO L273 TraceCheckUtils]: 15: Hoare triple {1378#false} assume !!~bvsge32(~j~0, 1bv32); {1378#false} is VALID [2018-11-23 10:28:55,187 INFO L273 TraceCheckUtils]: 16: Hoare triple {1378#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {1378#false} is VALID [2018-11-23 10:28:55,187 INFO L273 TraceCheckUtils]: 17: Hoare triple {1378#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1378#false} is VALID [2018-11-23 10:28:55,188 INFO L273 TraceCheckUtils]: 18: Hoare triple {1378#false} assume !!~bvsge32(~j~0, 1bv32); {1378#false} is VALID [2018-11-23 10:28:55,188 INFO L273 TraceCheckUtils]: 19: Hoare triple {1378#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {1378#false} is VALID [2018-11-23 10:28:55,188 INFO L273 TraceCheckUtils]: 20: Hoare triple {1378#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1378#false} is VALID [2018-11-23 10:28:55,188 INFO L273 TraceCheckUtils]: 21: Hoare triple {1378#false} assume !~bvsge32(~j~0, 1bv32); {1378#false} is VALID [2018-11-23 10:28:55,188 INFO L273 TraceCheckUtils]: 22: Hoare triple {1378#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1378#false} is VALID [2018-11-23 10:28:55,189 INFO L273 TraceCheckUtils]: 23: Hoare triple {1378#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1378#false} is VALID [2018-11-23 10:28:55,189 INFO L273 TraceCheckUtils]: 24: Hoare triple {1378#false} ~i~0 := 0bv32; {1378#false} is VALID [2018-11-23 10:28:55,189 INFO L273 TraceCheckUtils]: 25: Hoare triple {1378#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1378#false} is VALID [2018-11-23 10:28:55,189 INFO L273 TraceCheckUtils]: 26: Hoare triple {1378#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1378#false} is VALID [2018-11-23 10:28:55,190 INFO L256 TraceCheckUtils]: 27: Hoare triple {1378#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1378#false} is VALID [2018-11-23 10:28:55,190 INFO L273 TraceCheckUtils]: 28: Hoare triple {1378#false} ~cond := #in~cond; {1378#false} is VALID [2018-11-23 10:28:55,190 INFO L273 TraceCheckUtils]: 29: Hoare triple {1378#false} assume 0bv32 == ~cond; {1378#false} is VALID [2018-11-23 10:28:55,190 INFO L273 TraceCheckUtils]: 30: Hoare triple {1378#false} assume !false; {1378#false} is VALID [2018-11-23 10:28:55,192 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 14 proven. 2 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-11-23 10:28:55,193 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:28:55,343 INFO L273 TraceCheckUtils]: 30: Hoare triple {1378#false} assume !false; {1378#false} is VALID [2018-11-23 10:28:55,344 INFO L273 TraceCheckUtils]: 29: Hoare triple {1378#false} assume 0bv32 == ~cond; {1378#false} is VALID [2018-11-23 10:28:55,344 INFO L273 TraceCheckUtils]: 28: Hoare triple {1378#false} ~cond := #in~cond; {1378#false} is VALID [2018-11-23 10:28:55,344 INFO L256 TraceCheckUtils]: 27: Hoare triple {1378#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1378#false} is VALID [2018-11-23 10:28:55,345 INFO L273 TraceCheckUtils]: 26: Hoare triple {1378#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1378#false} is VALID [2018-11-23 10:28:55,345 INFO L273 TraceCheckUtils]: 25: Hoare triple {1378#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1378#false} is VALID [2018-11-23 10:28:55,346 INFO L273 TraceCheckUtils]: 24: Hoare triple {1378#false} ~i~0 := 0bv32; {1378#false} is VALID [2018-11-23 10:28:55,346 INFO L273 TraceCheckUtils]: 23: Hoare triple {1378#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1378#false} is VALID [2018-11-23 10:28:55,346 INFO L273 TraceCheckUtils]: 22: Hoare triple {1378#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1378#false} is VALID [2018-11-23 10:28:55,346 INFO L273 TraceCheckUtils]: 21: Hoare triple {1378#false} assume !~bvsge32(~j~0, 1bv32); {1378#false} is VALID [2018-11-23 10:28:55,346 INFO L273 TraceCheckUtils]: 20: Hoare triple {1378#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1378#false} is VALID [2018-11-23 10:28:55,347 INFO L273 TraceCheckUtils]: 19: Hoare triple {1378#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {1378#false} is VALID [2018-11-23 10:28:55,347 INFO L273 TraceCheckUtils]: 18: Hoare triple {1378#false} assume !!~bvsge32(~j~0, 1bv32); {1378#false} is VALID [2018-11-23 10:28:55,347 INFO L273 TraceCheckUtils]: 17: Hoare triple {1378#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1378#false} is VALID [2018-11-23 10:28:55,347 INFO L273 TraceCheckUtils]: 16: Hoare triple {1378#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {1378#false} is VALID [2018-11-23 10:28:55,348 INFO L273 TraceCheckUtils]: 15: Hoare triple {1378#false} assume !!~bvsge32(~j~0, 1bv32); {1378#false} is VALID [2018-11-23 10:28:55,348 INFO L273 TraceCheckUtils]: 14: Hoare triple {1378#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1378#false} is VALID [2018-11-23 10:28:55,348 INFO L273 TraceCheckUtils]: 13: Hoare triple {1526#(bvsge main_~j~0 main_~MINVAL~0)} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {1378#false} is VALID [2018-11-23 10:28:55,349 INFO L273 TraceCheckUtils]: 12: Hoare triple {1526#(bvsge main_~j~0 main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {1526#(bvsge main_~j~0 main_~MINVAL~0)} is VALID [2018-11-23 10:28:55,350 INFO L273 TraceCheckUtils]: 11: Hoare triple {1533#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1526#(bvsge main_~j~0 main_~MINVAL~0)} is VALID [2018-11-23 10:28:55,351 INFO L273 TraceCheckUtils]: 10: Hoare triple {1533#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0)} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {1533#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0)} is VALID [2018-11-23 10:28:55,351 INFO L273 TraceCheckUtils]: 9: Hoare triple {1533#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {1533#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0)} is VALID [2018-11-23 10:28:55,352 INFO L273 TraceCheckUtils]: 8: Hoare triple {1543#(bvsge (_ bv3 32) main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32));~j~0 := 4bv32; {1533#(bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0)} is VALID [2018-11-23 10:28:55,352 INFO L273 TraceCheckUtils]: 7: Hoare triple {1543#(bvsge (_ bv3 32) main_~MINVAL~0)} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1543#(bvsge (_ bv3 32) main_~MINVAL~0)} is VALID [2018-11-23 10:28:55,353 INFO L273 TraceCheckUtils]: 6: Hoare triple {1377#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1543#(bvsge (_ bv3 32) main_~MINVAL~0)} is VALID [2018-11-23 10:28:55,353 INFO L273 TraceCheckUtils]: 5: Hoare triple {1377#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1377#true} is VALID [2018-11-23 10:28:55,354 INFO L256 TraceCheckUtils]: 4: Hoare triple {1377#true} call #t~ret8 := main(); {1377#true} is VALID [2018-11-23 10:28:55,354 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1377#true} {1377#true} #83#return; {1377#true} is VALID [2018-11-23 10:28:55,354 INFO L273 TraceCheckUtils]: 2: Hoare triple {1377#true} assume true; {1377#true} is VALID [2018-11-23 10:28:55,355 INFO L273 TraceCheckUtils]: 1: Hoare triple {1377#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1377#true} is VALID [2018-11-23 10:28:55,355 INFO L256 TraceCheckUtils]: 0: Hoare triple {1377#true} call ULTIMATE.init(); {1377#true} is VALID [2018-11-23 10:28:55,357 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 14 proven. 2 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-11-23 10:28:55,359 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:28:55,359 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 8 [2018-11-23 10:28:55,360 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 31 [2018-11-23 10:28:55,360 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:28:55,360 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 8 states. [2018-11-23 10:28:55,454 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 35 edges. 35 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:55,454 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 10:28:55,454 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 10:28:55,454 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-23 10:28:55,455 INFO L87 Difference]: Start difference. First operand 41 states and 47 transitions. Second operand 8 states. [2018-11-23 10:28:55,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:55,963 INFO L93 Difference]: Finished difference Result 74 states and 86 transitions. [2018-11-23 10:28:55,963 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 10:28:55,964 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 31 [2018-11-23 10:28:55,964 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:28:55,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8 states. [2018-11-23 10:28:55,966 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 61 transitions. [2018-11-23 10:28:55,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8 states. [2018-11-23 10:28:55,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 61 transitions. [2018-11-23 10:28:55,969 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 6 states and 61 transitions. [2018-11-23 10:28:56,165 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 61 edges. 61 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:28:56,166 INFO L225 Difference]: With dead ends: 74 [2018-11-23 10:28:56,167 INFO L226 Difference]: Without dead ends: 42 [2018-11-23 10:28:56,167 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 62 GetRequests, 55 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=43, Unknown=0, NotChecked=0, Total=72 [2018-11-23 10:28:56,168 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states. [2018-11-23 10:28:56,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 41. [2018-11-23 10:28:56,227 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:28:56,227 INFO L82 GeneralOperation]: Start isEquivalent. First operand 42 states. Second operand 41 states. [2018-11-23 10:28:56,227 INFO L74 IsIncluded]: Start isIncluded. First operand 42 states. Second operand 41 states. [2018-11-23 10:28:56,227 INFO L87 Difference]: Start difference. First operand 42 states. Second operand 41 states. [2018-11-23 10:28:56,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:56,230 INFO L93 Difference]: Finished difference Result 42 states and 46 transitions. [2018-11-23 10:28:56,231 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 46 transitions. [2018-11-23 10:28:56,231 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:56,231 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:56,232 INFO L74 IsIncluded]: Start isIncluded. First operand 41 states. Second operand 42 states. [2018-11-23 10:28:56,232 INFO L87 Difference]: Start difference. First operand 41 states. Second operand 42 states. [2018-11-23 10:28:56,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:28:56,234 INFO L93 Difference]: Finished difference Result 42 states and 46 transitions. [2018-11-23 10:28:56,234 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 46 transitions. [2018-11-23 10:28:56,235 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:28:56,235 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:28:56,235 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:28:56,235 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:28:56,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2018-11-23 10:28:56,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 45 transitions. [2018-11-23 10:28:56,238 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 45 transitions. Word has length 31 [2018-11-23 10:28:56,238 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:28:56,238 INFO L480 AbstractCegarLoop]: Abstraction has 41 states and 45 transitions. [2018-11-23 10:28:56,238 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 10:28:56,238 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 45 transitions. [2018-11-23 10:28:56,239 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-11-23 10:28:56,239 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:28:56,239 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:28:56,240 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:28:56,240 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:28:56,240 INFO L82 PathProgramCache]: Analyzing trace with hash 401597370, now seen corresponding path program 2 times [2018-11-23 10:28:56,240 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:28:56,241 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:28:56,266 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-23 10:28:56,398 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 10:28:56,398 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 10:28:56,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:28:56,432 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:28:56,593 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 16 [2018-11-23 10:28:56,600 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 15 [2018-11-23 10:28:56,602 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:28:56,607 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:56,629 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:56,629 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:36, output treesize:32 [2018-11-23 10:28:56,775 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 34 [2018-11-23 10:28:56,817 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:56,819 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:56,820 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 75 [2018-11-23 10:28:56,830 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:28:56,844 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:56,882 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:56,883 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:55, output treesize:51 [2018-11-23 10:28:57,136 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 51 [2018-11-23 10:28:57,220 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,222 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,224 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,226 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,228 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,230 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,231 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 190 [2018-11-23 10:28:57,239 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:28:57,289 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:57,340 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:57,341 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:74, output treesize:70 [2018-11-23 10:28:57,731 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 32 [2018-11-23 10:28:57,748 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,750 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,752 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,755 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,757 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,760 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,762 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,764 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,767 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,769 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,773 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,775 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:28:57,777 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 151 [2018-11-23 10:28:57,782 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:28:57,828 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:57,850 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:28:57,851 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:47, output treesize:43 [2018-11-23 10:28:58,107 INFO L256 TraceCheckUtils]: 0: Hoare triple {1814#true} call ULTIMATE.init(); {1814#true} is VALID [2018-11-23 10:28:58,108 INFO L273 TraceCheckUtils]: 1: Hoare triple {1814#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1814#true} is VALID [2018-11-23 10:28:58,108 INFO L273 TraceCheckUtils]: 2: Hoare triple {1814#true} assume true; {1814#true} is VALID [2018-11-23 10:28:58,108 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1814#true} {1814#true} #83#return; {1814#true} is VALID [2018-11-23 10:28:58,108 INFO L256 TraceCheckUtils]: 4: Hoare triple {1814#true} call #t~ret8 := main(); {1814#true} is VALID [2018-11-23 10:28:58,109 INFO L273 TraceCheckUtils]: 5: Hoare triple {1814#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1814#true} is VALID [2018-11-23 10:28:58,110 INFO L273 TraceCheckUtils]: 6: Hoare triple {1814#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {1837#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:58,111 INFO L273 TraceCheckUtils]: 7: Hoare triple {1837#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1841#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:58,112 INFO L273 TraceCheckUtils]: 8: Hoare triple {1841#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32));~j~0 := 4bv32; {1845#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:58,112 INFO L273 TraceCheckUtils]: 9: Hoare triple {1845#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {1845#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:58,114 INFO L273 TraceCheckUtils]: 10: Hoare triple {1845#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {1852#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:58,119 INFO L273 TraceCheckUtils]: 11: Hoare triple {1852#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1856#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:58,120 INFO L273 TraceCheckUtils]: 12: Hoare triple {1856#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {1856#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:58,125 INFO L273 TraceCheckUtils]: 13: Hoare triple {1856#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {1863#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:58,127 INFO L273 TraceCheckUtils]: 14: Hoare triple {1863#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1867#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:58,129 INFO L273 TraceCheckUtils]: 15: Hoare triple {1867#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {1867#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:58,134 INFO L273 TraceCheckUtils]: 16: Hoare triple {1867#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {1874#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:58,142 INFO L273 TraceCheckUtils]: 17: Hoare triple {1874#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1878#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0))) (_ bv4294967293 32)) main_~j~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:58,146 INFO L273 TraceCheckUtils]: 18: Hoare triple {1878#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0))) (_ bv4294967293 32)) main_~j~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {1878#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0))) (_ bv4294967293 32)) main_~j~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:28:58,153 INFO L273 TraceCheckUtils]: 19: Hoare triple {1878#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0))) (_ bv4294967293 32)) main_~j~0) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {1885#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:58,155 INFO L273 TraceCheckUtils]: 20: Hoare triple {1885#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1885#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:58,155 INFO L273 TraceCheckUtils]: 21: Hoare triple {1885#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsge32(~j~0, 1bv32); {1885#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:58,156 INFO L273 TraceCheckUtils]: 22: Hoare triple {1885#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1885#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:58,157 INFO L273 TraceCheckUtils]: 23: Hoare triple {1885#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1885#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:58,173 INFO L273 TraceCheckUtils]: 24: Hoare triple {1885#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 0bv32; {1901#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:28:58,176 INFO L273 TraceCheckUtils]: 25: Hoare triple {1901#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|)) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1905#|main_#t~short7|} is VALID [2018-11-23 10:28:58,176 INFO L273 TraceCheckUtils]: 26: Hoare triple {1905#|main_#t~short7|} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1815#false} is VALID [2018-11-23 10:28:58,177 INFO L256 TraceCheckUtils]: 27: Hoare triple {1815#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1815#false} is VALID [2018-11-23 10:28:58,177 INFO L273 TraceCheckUtils]: 28: Hoare triple {1815#false} ~cond := #in~cond; {1815#false} is VALID [2018-11-23 10:28:58,177 INFO L273 TraceCheckUtils]: 29: Hoare triple {1815#false} assume 0bv32 == ~cond; {1815#false} is VALID [2018-11-23 10:28:58,177 INFO L273 TraceCheckUtils]: 30: Hoare triple {1815#false} assume !false; {1815#false} is VALID [2018-11-23 10:28:58,185 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:28:58,185 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:28:58,965 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 61 treesize of output 59 [2018-11-23 10:28:59,006 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 59 treesize of output 63 [2018-11-23 10:28:59,044 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:59,046 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:59,048 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 63 treesize of output 102 [2018-11-23 10:28:59,093 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:59,095 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:59,096 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:59,097 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:59,099 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 81 treesize of output 181 [2018-11-23 10:28:59,411 WARN L180 SmtUtils]: Spent 214.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 46 [2018-11-23 10:28:59,463 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:59,477 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:59,481 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:59,490 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:59,495 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:59,501 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:59,563 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 3 case distinctions, treesize of input 56 treesize of output 142 [2018-11-23 10:28:59,578 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 4 xjuncts. [2018-11-23 10:28:59,620 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:59,620 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:59,621 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:59,625 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:59,626 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:59,626 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:28:59,628 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 64 treesize of output 96 [2018-11-23 10:28:59,632 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-11-23 10:28:59,976 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 9 xjuncts. [2018-11-23 10:29:00,258 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 6 xjuncts. [2018-11-23 10:29:00,457 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 6 xjuncts. [2018-11-23 10:29:00,661 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 6 xjuncts. [2018-11-23 10:29:01,011 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 6 xjuncts. [2018-11-23 10:29:01,011 INFO L202 ElimStorePlain]: Needed 7 recursive calls to eliminate 2 variables, input treesize:61, output treesize:202 [2018-11-23 10:29:01,047 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:29:01,048 WARN L384 uantifierElimination]: Input elimination task: ∀ [|#memory_int|, |main_~#volArray~0.base|]. (bvsge (select (let ((.cse0 (bvmul (_ bv16 32) main_~i~0))) (store (let ((.cse2 (bvadd main_~j~0 (_ bv4294967294 32)))) (store (let ((.cse1 (bvadd main_~j~0 (_ bv4294967295 32)))) (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg .cse1)) |main_~#volArray~0.offset| .cse0) .cse1)) (bvadd |main_~#volArray~0.offset| .cse0 (bvmul (_ bv4 32) (bvneg .cse2))) .cse2)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) .cse0) (_ bv0 32))) |main_~#volArray~0.offset|) main_~MINVAL~0) [2018-11-23 10:29:01,048 WARN L385 uantifierElimination]: ElimStorePlain result: ∀ [v_prenex_1, v_arrayElimCell_6]. (let ((.cse2 (bvadd main_~j~0 (_ bv4294967294 32))) (.cse4 (bvadd main_~j~0 (_ bv4294967295 32))) (.cse7 (bvmul (_ bv16 32) main_~i~0))) (let ((.cse0 (= |main_~#volArray~0.offset| (bvadd (bvmul (_ bv4 32) (bvneg .cse4)) |main_~#volArray~0.offset| .cse7))) (.cse5 (= |main_~#volArray~0.offset| (bvadd |main_~#volArray~0.offset| .cse7 (bvmul (_ bv4 32) (bvneg .cse2))))) (.cse1 (= |main_~#volArray~0.offset| (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse7))) (.cse3 (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) .cse7))) (.cse6 (bvsge (_ bv0 32) main_~MINVAL~0))) (and (or .cse0 .cse1 (bvsge .cse2 main_~MINVAL~0) .cse3) (or (bvsge .cse4 main_~MINVAL~0) .cse1 .cse3) (or .cse0 .cse5 .cse1 (bvsge v_prenex_1 main_~MINVAL~0) .cse6) (or (bvsge main_~j~0 main_~MINVAL~0) .cse3) (or .cse0 (bvsge v_arrayElimCell_6 main_~MINVAL~0) .cse5 .cse1 .cse3) (or (not .cse3) .cse6)))) [2018-11-23 10:29:01,795 WARN L180 SmtUtils]: Spent 490.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 43 [2018-11-23 10:29:02,243 INFO L273 TraceCheckUtils]: 30: Hoare triple {1815#false} assume !false; {1815#false} is VALID [2018-11-23 10:29:02,243 INFO L273 TraceCheckUtils]: 29: Hoare triple {1815#false} assume 0bv32 == ~cond; {1815#false} is VALID [2018-11-23 10:29:02,243 INFO L273 TraceCheckUtils]: 28: Hoare triple {1815#false} ~cond := #in~cond; {1815#false} is VALID [2018-11-23 10:29:02,244 INFO L256 TraceCheckUtils]: 27: Hoare triple {1815#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {1815#false} is VALID [2018-11-23 10:29:02,244 INFO L273 TraceCheckUtils]: 26: Hoare triple {1905#|main_#t~short7|} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {1815#false} is VALID [2018-11-23 10:29:02,246 INFO L273 TraceCheckUtils]: 25: Hoare triple {1936#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {1905#|main_#t~short7|} is VALID [2018-11-23 10:29:02,247 INFO L273 TraceCheckUtils]: 24: Hoare triple {1940#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} ~i~0 := 0bv32; {1936#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is VALID [2018-11-23 10:29:02,247 INFO L273 TraceCheckUtils]: 23: Hoare triple {1940#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {1940#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:02,247 INFO L273 TraceCheckUtils]: 22: Hoare triple {1940#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {1940#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:02,248 INFO L273 TraceCheckUtils]: 21: Hoare triple {1940#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsge32(~j~0, 1bv32); {1940#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:02,248 INFO L273 TraceCheckUtils]: 20: Hoare triple {1940#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1940#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:02,391 INFO L273 TraceCheckUtils]: 19: Hoare triple {1956#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {1940#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:02,393 INFO L273 TraceCheckUtils]: 18: Hoare triple {1956#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {1956#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:02,417 INFO L273 TraceCheckUtils]: 17: Hoare triple {1963#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1956#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:02,533 INFO L273 TraceCheckUtils]: 16: Hoare triple {1967#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {1963#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:02,534 INFO L273 TraceCheckUtils]: 15: Hoare triple {1967#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {1967#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:02,654 INFO L273 TraceCheckUtils]: 14: Hoare triple {1974#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1967#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:02,816 INFO L273 TraceCheckUtils]: 13: Hoare triple {1978#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {1974#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:02,817 INFO L273 TraceCheckUtils]: 12: Hoare triple {1978#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {1978#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:03,286 INFO L273 TraceCheckUtils]: 11: Hoare triple {1985#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {1978#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:03,493 INFO L273 TraceCheckUtils]: 10: Hoare triple {1989#(and (or (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0))) (forall ((v_arrayElimCell_6 (_ BitVec 32))) (bvsge v_arrayElimCell_6 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (not (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (bvsge (_ bv0 32) main_~MINVAL~0)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {1985#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) |main_~#volArray~0.offset|) main_~MINVAL~0)} is VALID [2018-11-23 10:29:03,495 INFO L273 TraceCheckUtils]: 9: Hoare triple {1989#(and (or (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0))) (forall ((v_arrayElimCell_6 (_ BitVec 32))) (bvsge v_arrayElimCell_6 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (not (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (bvsge (_ bv0 32) main_~MINVAL~0)))} assume !!~bvsge32(~j~0, 1bv32); {1989#(and (or (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0))) (forall ((v_arrayElimCell_6 (_ BitVec 32))) (bvsge v_arrayElimCell_6 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (not (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (bvsge (_ bv0 32) main_~MINVAL~0)))} is VALID [2018-11-23 10:29:03,516 INFO L273 TraceCheckUtils]: 8: Hoare triple {1996#(and (or (forall ((v_arrayElimCell_6 (_ BitVec 32))) (bvsge v_arrayElimCell_6 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (bvsge (_ bv4 32) main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32));~j~0 := 4bv32; {1989#(and (or (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0))) (forall ((v_arrayElimCell_6 (_ BitVec 32))) (bvsge v_arrayElimCell_6 main_~MINVAL~0)) (= (_ bv0 32) (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (not (= (_ bv0 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (bvsge (_ bv0 32) main_~MINVAL~0)))} is VALID [2018-11-23 10:29:03,518 INFO L273 TraceCheckUtils]: 7: Hoare triple {2000#(bvsge (_ bv4 32) main_~MINVAL~0)} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {1996#(and (or (forall ((v_arrayElimCell_6 (_ BitVec 32))) (bvsge v_arrayElimCell_6 main_~MINVAL~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))) (bvsge (_ bv4 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:03,519 INFO L273 TraceCheckUtils]: 6: Hoare triple {1814#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {2000#(bvsge (_ bv4 32) main_~MINVAL~0)} is VALID [2018-11-23 10:29:03,519 INFO L273 TraceCheckUtils]: 5: Hoare triple {1814#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {1814#true} is VALID [2018-11-23 10:29:03,519 INFO L256 TraceCheckUtils]: 4: Hoare triple {1814#true} call #t~ret8 := main(); {1814#true} is VALID [2018-11-23 10:29:03,519 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {1814#true} {1814#true} #83#return; {1814#true} is VALID [2018-11-23 10:29:03,520 INFO L273 TraceCheckUtils]: 2: Hoare triple {1814#true} assume true; {1814#true} is VALID [2018-11-23 10:29:03,520 INFO L273 TraceCheckUtils]: 1: Hoare triple {1814#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {1814#true} is VALID [2018-11-23 10:29:03,520 INFO L256 TraceCheckUtils]: 0: Hoare triple {1814#true} call ULTIMATE.init(); {1814#true} is VALID [2018-11-23 10:29:03,526 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:29:03,534 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:29:03,534 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 25 [2018-11-23 10:29:03,534 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 31 [2018-11-23 10:29:03,535 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:29:03,535 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 25 states. [2018-11-23 10:29:04,484 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 51 edges. 51 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:29:04,484 INFO L459 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-11-23 10:29:04,484 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-11-23 10:29:04,485 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=140, Invalid=460, Unknown=0, NotChecked=0, Total=600 [2018-11-23 10:29:04,485 INFO L87 Difference]: Start difference. First operand 41 states and 45 transitions. Second operand 25 states. [2018-11-23 10:29:06,588 WARN L180 SmtUtils]: Spent 126.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 46 [2018-11-23 10:29:07,146 WARN L180 SmtUtils]: Spent 253.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 65 [2018-11-23 10:29:08,497 WARN L180 SmtUtils]: Spent 171.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 51 [2018-11-23 10:29:09,230 WARN L180 SmtUtils]: Spent 212.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 55 [2018-11-23 10:29:10,611 WARN L180 SmtUtils]: Spent 294.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 64 [2018-11-23 10:29:10,999 WARN L180 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 41 [2018-11-23 10:29:11,315 WARN L180 SmtUtils]: Spent 162.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 45 [2018-11-23 10:29:12,367 WARN L180 SmtUtils]: Spent 207.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 50 [2018-11-23 10:29:13,407 WARN L180 SmtUtils]: Spent 182.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 43 [2018-11-23 10:29:14,000 WARN L180 SmtUtils]: Spent 177.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 46 [2018-11-23 10:29:14,542 WARN L180 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 35 [2018-11-23 10:29:16,026 WARN L180 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 39 DAG size of output: 33 [2018-11-23 10:29:16,486 WARN L180 SmtUtils]: Spent 148.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 39 [2018-11-23 10:29:22,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:29:22,882 INFO L93 Difference]: Finished difference Result 197 states and 248 transitions. [2018-11-23 10:29:22,882 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-11-23 10:29:22,882 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 31 [2018-11-23 10:29:22,882 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:29:22,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2018-11-23 10:29:22,890 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 220 transitions. [2018-11-23 10:29:22,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2018-11-23 10:29:22,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 220 transitions. [2018-11-23 10:29:22,897 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 45 states and 220 transitions. [2018-11-23 10:29:28,251 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 220 edges. 218 inductive. 0 not inductive. 2 times theorem prover too weak to decide inductivity. [2018-11-23 10:29:28,255 INFO L225 Difference]: With dead ends: 197 [2018-11-23 10:29:28,255 INFO L226 Difference]: Without dead ends: 165 [2018-11-23 10:29:28,257 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 38 SyntacticMatches, 0 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 928 ImplicationChecksByTransitivity, 8.7s TimeCoverageRelationStatistics Valid=736, Invalid=2456, Unknown=0, NotChecked=0, Total=3192 [2018-11-23 10:29:28,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165 states. [2018-11-23 10:29:28,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165 to 95. [2018-11-23 10:29:28,500 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:29:28,500 INFO L82 GeneralOperation]: Start isEquivalent. First operand 165 states. Second operand 95 states. [2018-11-23 10:29:28,500 INFO L74 IsIncluded]: Start isIncluded. First operand 165 states. Second operand 95 states. [2018-11-23 10:29:28,500 INFO L87 Difference]: Start difference. First operand 165 states. Second operand 95 states. [2018-11-23 10:29:28,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:29:28,509 INFO L93 Difference]: Finished difference Result 165 states and 207 transitions. [2018-11-23 10:29:28,509 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 207 transitions. [2018-11-23 10:29:28,510 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:29:28,510 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:29:28,510 INFO L74 IsIncluded]: Start isIncluded. First operand 95 states. Second operand 165 states. [2018-11-23 10:29:28,511 INFO L87 Difference]: Start difference. First operand 95 states. Second operand 165 states. [2018-11-23 10:29:28,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:29:28,518 INFO L93 Difference]: Finished difference Result 165 states and 207 transitions. [2018-11-23 10:29:28,518 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 207 transitions. [2018-11-23 10:29:28,518 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:29:28,519 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:29:28,519 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:29:28,519 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:29:28,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 95 states. [2018-11-23 10:29:28,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 113 transitions. [2018-11-23 10:29:28,523 INFO L78 Accepts]: Start accepts. Automaton has 95 states and 113 transitions. Word has length 31 [2018-11-23 10:29:28,523 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:29:28,523 INFO L480 AbstractCegarLoop]: Abstraction has 95 states and 113 transitions. [2018-11-23 10:29:28,523 INFO L481 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-11-23 10:29:28,524 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 113 transitions. [2018-11-23 10:29:28,524 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-11-23 10:29:28,525 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:29:28,525 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:29:28,525 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:29:28,525 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:29:28,525 INFO L82 PathProgramCache]: Analyzing trace with hash -624989837, now seen corresponding path program 1 times [2018-11-23 10:29:28,526 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:29:28,526 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:29:28,551 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 10:29:28,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:29:28,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:29:28,630 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:29:28,770 INFO L256 TraceCheckUtils]: 0: Hoare triple {2813#true} call ULTIMATE.init(); {2813#true} is VALID [2018-11-23 10:29:28,770 INFO L273 TraceCheckUtils]: 1: Hoare triple {2813#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {2813#true} is VALID [2018-11-23 10:29:28,771 INFO L273 TraceCheckUtils]: 2: Hoare triple {2813#true} assume true; {2813#true} is VALID [2018-11-23 10:29:28,771 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2813#true} {2813#true} #83#return; {2813#true} is VALID [2018-11-23 10:29:28,771 INFO L256 TraceCheckUtils]: 4: Hoare triple {2813#true} call #t~ret8 := main(); {2813#true} is VALID [2018-11-23 10:29:28,771 INFO L273 TraceCheckUtils]: 5: Hoare triple {2813#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {2813#true} is VALID [2018-11-23 10:29:28,771 INFO L273 TraceCheckUtils]: 6: Hoare triple {2813#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {2813#true} is VALID [2018-11-23 10:29:28,772 INFO L273 TraceCheckUtils]: 7: Hoare triple {2813#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {2813#true} is VALID [2018-11-23 10:29:28,772 INFO L273 TraceCheckUtils]: 8: Hoare triple {2813#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32));~j~0 := 4bv32; {2842#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:28,772 INFO L273 TraceCheckUtils]: 9: Hoare triple {2842#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {2842#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:28,774 INFO L273 TraceCheckUtils]: 10: Hoare triple {2842#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {2842#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:28,775 INFO L273 TraceCheckUtils]: 11: Hoare triple {2842#(= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2852#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:28,779 INFO L273 TraceCheckUtils]: 12: Hoare triple {2852#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {2852#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:28,787 INFO L273 TraceCheckUtils]: 13: Hoare triple {2852#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {2852#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:28,791 INFO L273 TraceCheckUtils]: 14: Hoare triple {2852#(= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2862#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:28,793 INFO L273 TraceCheckUtils]: 15: Hoare triple {2862#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {2862#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:28,793 INFO L273 TraceCheckUtils]: 16: Hoare triple {2862#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {2862#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:28,794 INFO L273 TraceCheckUtils]: 17: Hoare triple {2862#(= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2872#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:28,794 INFO L273 TraceCheckUtils]: 18: Hoare triple {2872#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {2872#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:28,794 INFO L273 TraceCheckUtils]: 19: Hoare triple {2872#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {2872#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:29:28,803 INFO L273 TraceCheckUtils]: 20: Hoare triple {2872#(= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2882#(= main_~j~0 (_ bv0 32))} is VALID [2018-11-23 10:29:28,817 INFO L273 TraceCheckUtils]: 21: Hoare triple {2882#(= main_~j~0 (_ bv0 32))} assume !!~bvsge32(~j~0, 1bv32); {2814#false} is VALID [2018-11-23 10:29:28,817 INFO L273 TraceCheckUtils]: 22: Hoare triple {2814#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {2814#false} is VALID [2018-11-23 10:29:28,817 INFO L273 TraceCheckUtils]: 23: Hoare triple {2814#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2814#false} is VALID [2018-11-23 10:29:28,818 INFO L273 TraceCheckUtils]: 24: Hoare triple {2814#false} assume !~bvsge32(~j~0, 1bv32); {2814#false} is VALID [2018-11-23 10:29:28,818 INFO L273 TraceCheckUtils]: 25: Hoare triple {2814#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {2814#false} is VALID [2018-11-23 10:29:28,818 INFO L273 TraceCheckUtils]: 26: Hoare triple {2814#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {2814#false} is VALID [2018-11-23 10:29:28,818 INFO L273 TraceCheckUtils]: 27: Hoare triple {2814#false} ~i~0 := 0bv32; {2814#false} is VALID [2018-11-23 10:29:28,818 INFO L273 TraceCheckUtils]: 28: Hoare triple {2814#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {2814#false} is VALID [2018-11-23 10:29:28,819 INFO L273 TraceCheckUtils]: 29: Hoare triple {2814#false} assume #t~short7; {2814#false} is VALID [2018-11-23 10:29:28,819 INFO L256 TraceCheckUtils]: 30: Hoare triple {2814#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {2814#false} is VALID [2018-11-23 10:29:28,819 INFO L273 TraceCheckUtils]: 31: Hoare triple {2814#false} ~cond := #in~cond; {2814#false} is VALID [2018-11-23 10:29:28,819 INFO L273 TraceCheckUtils]: 32: Hoare triple {2814#false} assume !(0bv32 == ~cond); {2814#false} is VALID [2018-11-23 10:29:28,820 INFO L273 TraceCheckUtils]: 33: Hoare triple {2814#false} assume true; {2814#false} is VALID [2018-11-23 10:29:28,820 INFO L268 TraceCheckUtils]: 34: Hoare quadruple {2814#false} {2814#false} #87#return; {2814#false} is VALID [2018-11-23 10:29:28,820 INFO L273 TraceCheckUtils]: 35: Hoare triple {2814#false} havoc #t~short7;havoc #t~mem5;havoc #t~mem6; {2814#false} is VALID [2018-11-23 10:29:28,820 INFO L273 TraceCheckUtils]: 36: Hoare triple {2814#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {2814#false} is VALID [2018-11-23 10:29:28,820 INFO L273 TraceCheckUtils]: 37: Hoare triple {2814#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {2814#false} is VALID [2018-11-23 10:29:28,821 INFO L273 TraceCheckUtils]: 38: Hoare triple {2814#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {2814#false} is VALID [2018-11-23 10:29:28,821 INFO L256 TraceCheckUtils]: 39: Hoare triple {2814#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {2814#false} is VALID [2018-11-23 10:29:28,821 INFO L273 TraceCheckUtils]: 40: Hoare triple {2814#false} ~cond := #in~cond; {2814#false} is VALID [2018-11-23 10:29:28,821 INFO L273 TraceCheckUtils]: 41: Hoare triple {2814#false} assume 0bv32 == ~cond; {2814#false} is VALID [2018-11-23 10:29:28,821 INFO L273 TraceCheckUtils]: 42: Hoare triple {2814#false} assume !false; {2814#false} is VALID [2018-11-23 10:29:28,823 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 14 proven. 22 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-23 10:29:28,823 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:29:29,112 INFO L273 TraceCheckUtils]: 42: Hoare triple {2814#false} assume !false; {2814#false} is VALID [2018-11-23 10:29:29,113 INFO L273 TraceCheckUtils]: 41: Hoare triple {2814#false} assume 0bv32 == ~cond; {2814#false} is VALID [2018-11-23 10:29:29,113 INFO L273 TraceCheckUtils]: 40: Hoare triple {2814#false} ~cond := #in~cond; {2814#false} is VALID [2018-11-23 10:29:29,113 INFO L256 TraceCheckUtils]: 39: Hoare triple {2814#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {2814#false} is VALID [2018-11-23 10:29:29,114 INFO L273 TraceCheckUtils]: 38: Hoare triple {2814#false} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {2814#false} is VALID [2018-11-23 10:29:29,114 INFO L273 TraceCheckUtils]: 37: Hoare triple {2814#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {2814#false} is VALID [2018-11-23 10:29:29,114 INFO L273 TraceCheckUtils]: 36: Hoare triple {2814#false} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {2814#false} is VALID [2018-11-23 10:29:29,114 INFO L273 TraceCheckUtils]: 35: Hoare triple {2814#false} havoc #t~short7;havoc #t~mem5;havoc #t~mem6; {2814#false} is VALID [2018-11-23 10:29:29,115 INFO L268 TraceCheckUtils]: 34: Hoare quadruple {2813#true} {2814#false} #87#return; {2814#false} is VALID [2018-11-23 10:29:29,115 INFO L273 TraceCheckUtils]: 33: Hoare triple {2813#true} assume true; {2813#true} is VALID [2018-11-23 10:29:29,115 INFO L273 TraceCheckUtils]: 32: Hoare triple {2813#true} assume !(0bv32 == ~cond); {2813#true} is VALID [2018-11-23 10:29:29,115 INFO L273 TraceCheckUtils]: 31: Hoare triple {2813#true} ~cond := #in~cond; {2813#true} is VALID [2018-11-23 10:29:29,115 INFO L256 TraceCheckUtils]: 30: Hoare triple {2814#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {2813#true} is VALID [2018-11-23 10:29:29,115 INFO L273 TraceCheckUtils]: 29: Hoare triple {2814#false} assume #t~short7; {2814#false} is VALID [2018-11-23 10:29:29,116 INFO L273 TraceCheckUtils]: 28: Hoare triple {2814#false} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {2814#false} is VALID [2018-11-23 10:29:29,116 INFO L273 TraceCheckUtils]: 27: Hoare triple {2814#false} ~i~0 := 0bv32; {2814#false} is VALID [2018-11-23 10:29:29,116 INFO L273 TraceCheckUtils]: 26: Hoare triple {2814#false} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {2814#false} is VALID [2018-11-23 10:29:29,116 INFO L273 TraceCheckUtils]: 25: Hoare triple {2814#false} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {2814#false} is VALID [2018-11-23 10:29:29,116 INFO L273 TraceCheckUtils]: 24: Hoare triple {2814#false} assume !~bvsge32(~j~0, 1bv32); {2814#false} is VALID [2018-11-23 10:29:29,116 INFO L273 TraceCheckUtils]: 23: Hoare triple {2814#false} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {2814#false} is VALID [2018-11-23 10:29:29,116 INFO L273 TraceCheckUtils]: 22: Hoare triple {2814#false} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {2814#false} is VALID [2018-11-23 10:29:29,118 INFO L273 TraceCheckUtils]: 21: Hoare triple {3012#(not (bvsge main_~j~0 (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {2814#false} is VALID [2018-11-23 10:29:29,119 INFO L273 TraceCheckUtils]: 20: Hoare triple {3016#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3012#(not (bvsge main_~j~0 (_ bv1 32)))} is VALID [2018-11-23 10:29:29,120 INFO L273 TraceCheckUtils]: 19: Hoare triple {3016#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {3016#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:29,120 INFO L273 TraceCheckUtils]: 18: Hoare triple {3016#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {3016#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:29,124 INFO L273 TraceCheckUtils]: 17: Hoare triple {3026#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3016#(not (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:29,125 INFO L273 TraceCheckUtils]: 16: Hoare triple {3026#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {3026#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:29,125 INFO L273 TraceCheckUtils]: 15: Hoare triple {3026#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {3026#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:29,129 INFO L273 TraceCheckUtils]: 14: Hoare triple {3036#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3026#(not (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:29,130 INFO L273 TraceCheckUtils]: 13: Hoare triple {3036#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {3036#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:29,138 INFO L273 TraceCheckUtils]: 12: Hoare triple {3036#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {3036#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:29,142 INFO L273 TraceCheckUtils]: 11: Hoare triple {3046#(not (bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3036#(not (bvsge (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:29,143 INFO L273 TraceCheckUtils]: 10: Hoare triple {3046#(not (bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {3046#(not (bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:29,143 INFO L273 TraceCheckUtils]: 9: Hoare triple {3046#(not (bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32)))} assume !!~bvsge32(~j~0, 1bv32); {3046#(not (bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:29,144 INFO L273 TraceCheckUtils]: 8: Hoare triple {2813#true} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32));~j~0 := 4bv32; {3046#(not (bvsge (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv1 32)))} is VALID [2018-11-23 10:29:29,144 INFO L273 TraceCheckUtils]: 7: Hoare triple {2813#true} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {2813#true} is VALID [2018-11-23 10:29:29,144 INFO L273 TraceCheckUtils]: 6: Hoare triple {2813#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {2813#true} is VALID [2018-11-23 10:29:29,144 INFO L273 TraceCheckUtils]: 5: Hoare triple {2813#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {2813#true} is VALID [2018-11-23 10:29:29,144 INFO L256 TraceCheckUtils]: 4: Hoare triple {2813#true} call #t~ret8 := main(); {2813#true} is VALID [2018-11-23 10:29:29,145 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {2813#true} {2813#true} #83#return; {2813#true} is VALID [2018-11-23 10:29:29,145 INFO L273 TraceCheckUtils]: 2: Hoare triple {2813#true} assume true; {2813#true} is VALID [2018-11-23 10:29:29,145 INFO L273 TraceCheckUtils]: 1: Hoare triple {2813#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {2813#true} is VALID [2018-11-23 10:29:29,145 INFO L256 TraceCheckUtils]: 0: Hoare triple {2813#true} call ULTIMATE.init(); {2813#true} is VALID [2018-11-23 10:29:29,146 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 16 proven. 22 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-11-23 10:29:29,149 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:29:29,149 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 12 [2018-11-23 10:29:29,150 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 43 [2018-11-23 10:29:29,150 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:29:29,151 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 12 states. [2018-11-23 10:29:29,277 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 59 edges. 59 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:29:29,278 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-23 10:29:29,278 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-23 10:29:29,278 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2018-11-23 10:29:29,278 INFO L87 Difference]: Start difference. First operand 95 states and 113 transitions. Second operand 12 states. [2018-11-23 10:29:30,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:29:30,833 INFO L93 Difference]: Finished difference Result 129 states and 151 transitions. [2018-11-23 10:29:30,833 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 10:29:30,833 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 43 [2018-11-23 10:29:30,833 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:29:30,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2018-11-23 10:29:30,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 61 transitions. [2018-11-23 10:29:30,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2018-11-23 10:29:30,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 61 transitions. [2018-11-23 10:29:30,837 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 7 states and 61 transitions. [2018-11-23 10:29:31,020 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 61 edges. 61 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:29:31,022 INFO L225 Difference]: With dead ends: 129 [2018-11-23 10:29:31,022 INFO L226 Difference]: Without dead ends: 69 [2018-11-23 10:29:31,023 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 75 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2018-11-23 10:29:31,024 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2018-11-23 10:29:31,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 69. [2018-11-23 10:29:31,155 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:29:31,155 INFO L82 GeneralOperation]: Start isEquivalent. First operand 69 states. Second operand 69 states. [2018-11-23 10:29:31,155 INFO L74 IsIncluded]: Start isIncluded. First operand 69 states. Second operand 69 states. [2018-11-23 10:29:31,155 INFO L87 Difference]: Start difference. First operand 69 states. Second operand 69 states. [2018-11-23 10:29:31,158 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:29:31,159 INFO L93 Difference]: Finished difference Result 69 states and 75 transitions. [2018-11-23 10:29:31,159 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 75 transitions. [2018-11-23 10:29:31,159 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:29:31,159 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:29:31,159 INFO L74 IsIncluded]: Start isIncluded. First operand 69 states. Second operand 69 states. [2018-11-23 10:29:31,160 INFO L87 Difference]: Start difference. First operand 69 states. Second operand 69 states. [2018-11-23 10:29:31,162 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:29:31,163 INFO L93 Difference]: Finished difference Result 69 states and 75 transitions. [2018-11-23 10:29:31,163 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 75 transitions. [2018-11-23 10:29:31,163 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:29:31,163 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:29:31,163 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:29:31,163 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:29:31,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2018-11-23 10:29:31,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 75 transitions. [2018-11-23 10:29:31,166 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 75 transitions. Word has length 43 [2018-11-23 10:29:31,166 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:29:31,167 INFO L480 AbstractCegarLoop]: Abstraction has 69 states and 75 transitions. [2018-11-23 10:29:31,167 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-23 10:29:31,167 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 75 transitions. [2018-11-23 10:29:31,168 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-11-23 10:29:31,168 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:29:31,168 INFO L402 BasicCegarLoop]: trace histogram [8, 8, 6, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:29:31,169 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:29:31,169 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:29:31,169 INFO L82 PathProgramCache]: Analyzing trace with hash 253315372, now seen corresponding path program 2 times [2018-11-23 10:29:31,169 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:29:31,169 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:29:31,193 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-23 10:29:31,464 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 10:29:31,464 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 10:29:31,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:29:31,563 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:29:31,687 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 16 [2018-11-23 10:29:31,696 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 15 [2018-11-23 10:29:31,698 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:31,702 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:31,723 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:31,723 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:36, output treesize:32 [2018-11-23 10:29:31,888 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 34 [2018-11-23 10:29:31,924 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:31,929 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:31,930 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 75 [2018-11-23 10:29:31,934 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:31,949 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:31,982 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:31,982 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:55, output treesize:51 [2018-11-23 10:29:32,300 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 34 [2018-11-23 10:29:32,352 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:32,354 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:32,356 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:32,358 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:32,360 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:32,361 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:32,363 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 127 [2018-11-23 10:29:32,366 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:32,389 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:32,413 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:32,413 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:52, output treesize:48 [2018-11-23 10:29:32,668 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 60 treesize of output 51 [2018-11-23 10:29:32,693 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:32,695 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:32,697 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:32,699 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:32,701 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:32,703 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:32,705 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:32,707 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:32,709 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:32,711 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:32,715 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:32,717 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:32,718 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 254 [2018-11-23 10:29:32,721 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:32,768 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:32,812 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:32,812 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:74, output treesize:70 [2018-11-23 10:29:33,060 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 79 treesize of output 68 [2018-11-23 10:29:33,166 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,168 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,171 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,174 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,176 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,179 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,182 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,184 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,186 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,189 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,191 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,194 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,196 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,199 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,210 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,212 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,214 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 16 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 68 treesize of output 394 [2018-11-23 10:29:33,224 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:33,290 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:33,343 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:33,343 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:93, output treesize:89 [2018-11-23 10:29:33,693 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 98 treesize of output 85 [2018-11-23 10:29:33,763 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,765 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,766 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,768 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,769 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,771 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,772 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,774 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,776 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,777 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,786 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,787 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,788 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,789 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,791 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,792 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:33,793 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,795 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,797 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,798 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,800 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,802 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:33,804 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 21 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 85 treesize of output 542 [2018-11-23 10:29:33,828 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:33,913 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:33,981 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:33,982 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:112, output treesize:120 [2018-11-23 10:29:34,500 WARN L180 SmtUtils]: Spent 191.00 ms on a formula simplification that was a NOOP. DAG size: 55 [2018-11-23 10:29:34,564 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 78 treesize of output 61 [2018-11-23 10:29:34,581 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,583 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,584 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,586 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,587 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,589 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,590 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,592 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,594 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,595 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,598 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,599 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,600 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,602 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,603 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,605 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,606 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,608 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,609 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,611 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,612 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,614 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,616 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,618 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,620 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,622 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,624 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:34,626 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 27 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 61 treesize of output 338 [2018-11-23 10:29:34,637 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:34,753 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:34,797 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:29:34,797 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:84, output treesize:80 [2018-11-23 10:29:35,659 INFO L256 TraceCheckUtils]: 0: Hoare triple {3493#true} call ULTIMATE.init(); {3493#true} is VALID [2018-11-23 10:29:35,659 INFO L273 TraceCheckUtils]: 1: Hoare triple {3493#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {3493#true} is VALID [2018-11-23 10:29:35,659 INFO L273 TraceCheckUtils]: 2: Hoare triple {3493#true} assume true; {3493#true} is VALID [2018-11-23 10:29:35,660 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {3493#true} {3493#true} #83#return; {3493#true} is VALID [2018-11-23 10:29:35,660 INFO L256 TraceCheckUtils]: 4: Hoare triple {3493#true} call #t~ret8 := main(); {3493#true} is VALID [2018-11-23 10:29:35,660 INFO L273 TraceCheckUtils]: 5: Hoare triple {3493#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {3493#true} is VALID [2018-11-23 10:29:35,676 INFO L273 TraceCheckUtils]: 6: Hoare triple {3493#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {3516#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:35,677 INFO L273 TraceCheckUtils]: 7: Hoare triple {3516#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {3520#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:35,678 INFO L273 TraceCheckUtils]: 8: Hoare triple {3520#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32));~j~0 := 4bv32; {3524#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:35,679 INFO L273 TraceCheckUtils]: 9: Hoare triple {3524#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {3524#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:35,679 INFO L273 TraceCheckUtils]: 10: Hoare triple {3524#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {3524#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:35,680 INFO L273 TraceCheckUtils]: 11: Hoare triple {3524#(and (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3534#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:35,681 INFO L273 TraceCheckUtils]: 12: Hoare triple {3534#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {3534#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:35,685 INFO L273 TraceCheckUtils]: 13: Hoare triple {3534#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {3541#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:35,689 INFO L273 TraceCheckUtils]: 14: Hoare triple {3541#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3545#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:35,691 INFO L273 TraceCheckUtils]: 15: Hoare triple {3545#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {3545#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:35,695 INFO L273 TraceCheckUtils]: 16: Hoare triple {3545#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {3552#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:35,702 INFO L273 TraceCheckUtils]: 17: Hoare triple {3552#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3556#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:35,705 INFO L273 TraceCheckUtils]: 18: Hoare triple {3556#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {3556#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:35,711 INFO L273 TraceCheckUtils]: 19: Hoare triple {3556#(and (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {3563#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:35,713 INFO L273 TraceCheckUtils]: 20: Hoare triple {3563#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3563#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:35,714 INFO L273 TraceCheckUtils]: 21: Hoare triple {3563#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~j~0, 1bv32); {3563#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:35,715 INFO L273 TraceCheckUtils]: 22: Hoare triple {3563#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv3 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)))) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3573#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:35,734 INFO L273 TraceCheckUtils]: 23: Hoare triple {3573#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32));~j~0 := 4bv32; {3577#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:35,736 INFO L273 TraceCheckUtils]: 24: Hoare triple {3577#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {3577#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:35,740 INFO L273 TraceCheckUtils]: 25: Hoare triple {3577#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {3584#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:35,746 INFO L273 TraceCheckUtils]: 26: Hoare triple {3584#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967292 32)) (_ bv0 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv2 32) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3588#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:35,748 INFO L273 TraceCheckUtils]: 27: Hoare triple {3588#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {3588#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:35,756 INFO L273 TraceCheckUtils]: 28: Hoare triple {3588#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {3595#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:35,764 INFO L273 TraceCheckUtils]: 29: Hoare triple {3595#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (_ bv2 32) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3599#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:35,767 INFO L273 TraceCheckUtils]: 30: Hoare triple {3599#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {3599#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:35,774 INFO L273 TraceCheckUtils]: 31: Hoare triple {3599#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {3606#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:35,785 INFO L273 TraceCheckUtils]: 32: Hoare triple {3606#(and (= (bvadd main_~j~0 (_ bv4294967294 32)) (_ bv0 32)) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= main_~j~0 (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3610#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0))) (_ bv4294967293 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:35,790 INFO L273 TraceCheckUtils]: 33: Hoare triple {3610#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0))) (_ bv4294967293 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvsge32(~j~0, 1bv32); {3610#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0))) (_ bv4294967293 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:35,799 INFO L273 TraceCheckUtils]: 34: Hoare triple {3610#(and (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967272 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (bvadd main_~j~0 (_ bv1 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv1 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967268 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~j~0 (_ bv4294967295 32)) (_ bv0 32)) (= (_ bv2 32) main_~i~0) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv3 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0))) (_ bv4294967293 32)) main_~j~0) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967276 32)))) (= (bvadd main_~j~0 (_ bv2 32)) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv2 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)))) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {3617#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:35,801 INFO L273 TraceCheckUtils]: 35: Hoare triple {3617#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3617#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:35,802 INFO L273 TraceCheckUtils]: 36: Hoare triple {3617#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsge32(~j~0, 1bv32); {3617#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:35,804 INFO L273 TraceCheckUtils]: 37: Hoare triple {3617#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3617#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:35,818 INFO L273 TraceCheckUtils]: 38: Hoare triple {3617#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3617#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:35,820 INFO L273 TraceCheckUtils]: 39: Hoare triple {3617#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} ~i~0 := 0bv32; {3633#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:35,822 INFO L273 TraceCheckUtils]: 40: Hoare triple {3633#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {3633#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:35,824 INFO L273 TraceCheckUtils]: 41: Hoare triple {3633#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume #t~short7; {3633#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:35,828 INFO L256 TraceCheckUtils]: 42: Hoare triple {3633#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {3643#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv16 32)) (_ bv4294967292 32)) (_ bv0 32)) (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv28 32)) (_ bv0 32)) (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv20 32)) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv20 32))) (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv24 32)) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32)))))} is VALID [2018-11-23 10:29:35,829 INFO L273 TraceCheckUtils]: 43: Hoare triple {3643#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv16 32)) (_ bv4294967292 32)) (_ bv0 32)) (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv28 32)) (_ bv0 32)) (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv20 32)) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv20 32))) (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv24 32)) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32)))))} ~cond := #in~cond; {3643#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv16 32)) (_ bv4294967292 32)) (_ bv0 32)) (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv28 32)) (_ bv0 32)) (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv20 32)) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv20 32))) (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv24 32)) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32)))))} is VALID [2018-11-23 10:29:35,829 INFO L273 TraceCheckUtils]: 44: Hoare triple {3643#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv16 32)) (_ bv4294967292 32)) (_ bv0 32)) (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv28 32)) (_ bv0 32)) (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv20 32)) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv20 32))) (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv24 32)) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32)))))} assume !(0bv32 == ~cond); {3643#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv16 32)) (_ bv4294967292 32)) (_ bv0 32)) (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv28 32)) (_ bv0 32)) (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv20 32)) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv20 32))) (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv24 32)) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32)))))} is VALID [2018-11-23 10:29:35,830 INFO L273 TraceCheckUtils]: 45: Hoare triple {3643#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv16 32)) (_ bv4294967292 32)) (_ bv0 32)) (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv28 32)) (_ bv0 32)) (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv20 32)) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv20 32))) (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv24 32)) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32)))))} assume true; {3643#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv16 32)) (_ bv4294967292 32)) (_ bv0 32)) (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv28 32)) (_ bv0 32)) (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv20 32)) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv20 32))) (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv24 32)) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32)))))} is VALID [2018-11-23 10:29:35,831 INFO L268 TraceCheckUtils]: 46: Hoare quadruple {3643#(exists ((|v_main_~#volArray~0.base_BEFORE_CALL_1| (_ BitVec 32))) (and (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv16 32)) (_ bv4294967292 32)) (_ bv0 32)) (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv28 32)) (_ bv0 32)) (= (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv20 32)) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv4 32))) (= (_ bv3 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv20 32))) (= (bvadd (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv24 32)) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv12 32))) (= (_ bv2 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_1|) (_ bv8 32)))))} {3633#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #87#return; {3633#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:35,832 INFO L273 TraceCheckUtils]: 47: Hoare triple {3633#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} havoc #t~short7;havoc #t~mem5;havoc #t~mem6; {3633#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:29:35,834 INFO L273 TraceCheckUtils]: 48: Hoare triple {3633#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= main_~i~0 (_ bv0 32)) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3662#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:29:35,838 INFO L273 TraceCheckUtils]: 49: Hoare triple {3662#(and (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv28 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (_ bv4294967293 32)) (_ bv0 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (= (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv20 32))) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32)))) (= (_ bv2 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv8 32)))) (= (bvadd (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv24 32))) (_ bv4294967294 32)) (_ bv0 32)) (= (_ bv4 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {3666#|main_#t~short7|} is VALID [2018-11-23 10:29:35,839 INFO L273 TraceCheckUtils]: 50: Hoare triple {3666#|main_#t~short7|} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {3494#false} is VALID [2018-11-23 10:29:35,839 INFO L256 TraceCheckUtils]: 51: Hoare triple {3494#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {3494#false} is VALID [2018-11-23 10:29:35,840 INFO L273 TraceCheckUtils]: 52: Hoare triple {3494#false} ~cond := #in~cond; {3494#false} is VALID [2018-11-23 10:29:35,840 INFO L273 TraceCheckUtils]: 53: Hoare triple {3494#false} assume 0bv32 == ~cond; {3494#false} is VALID [2018-11-23 10:29:35,840 INFO L273 TraceCheckUtils]: 54: Hoare triple {3494#false} assume !false; {3494#false} is VALID [2018-11-23 10:29:35,864 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 3 proven. 107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:29:35,864 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:29:38,139 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 79 treesize of output 77 [2018-11-23 10:29:38,158 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 77 treesize of output 81 [2018-11-23 10:29:38,178 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:38,181 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:38,183 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 81 treesize of output 120 [2018-11-23 10:29:38,253 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:38,254 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:38,266 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 4 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 99 treesize of output 167 [2018-11-23 10:29:38,380 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:38,380 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:38,410 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:38,545 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 5 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 6 case distinctions, treesize of input 102 treesize of output 215 [2018-11-23 10:29:38,575 WARN L307 Elim1Store]: Array PQE input equivalent to true [2018-11-23 10:29:38,576 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-11-23 10:29:39,061 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:39,061 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:39,062 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:39,062 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:39,062 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:39,063 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:39,063 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:39,064 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:39,065 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:39,066 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:39,067 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:39,067 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:39,070 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 92 treesize of output 296 [2018-11-23 10:29:39,117 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:39,118 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:39,118 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:39,118 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:39,119 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:39,119 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:39,120 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:39,127 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 19 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 179 treesize of output 374 [2018-11-23 10:29:44,525 WARN L180 SmtUtils]: Spent 5.34 s on a formula simplification. DAG size of input: 76 DAG size of output: 50 [2018-11-23 10:29:44,628 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:44,628 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:44,629 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:44,629 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:44,629 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:44,630 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,113 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,115 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,116 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,121 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,121 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,125 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,126 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,126 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,143 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,144 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,145 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,147 INFO L303 Elim1Store]: Index analysis took 526 ms [2018-11-23 10:29:45,165 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 23 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 127 treesize of output 250 [2018-11-23 10:29:45,172 INFO L267 ElimStorePlain]: Start of recursive call 10: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-23 10:29:45,353 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-23 10:29:45,396 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-23 10:29:45,704 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,704 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,705 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,705 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,706 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,709 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:45,709 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,710 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,710 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,711 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,711 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,712 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,715 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 9 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 92 treesize of output 266 [2018-11-23 10:29:45,774 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,777 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:45,777 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,778 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,780 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:45,782 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 11 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 139 treesize of output 182 [2018-11-23 10:29:46,020 WARN L180 SmtUtils]: Spent 180.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 37 [2018-11-23 10:29:46,034 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,034 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,053 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,053 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,054 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,063 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,064 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,064 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,081 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 8 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 50 treesize of output 105 [2018-11-23 10:29:46,092 INFO L267 ElimStorePlain]: Start of recursive call 13: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-23 10:29:46,167 INFO L267 ElimStorePlain]: Start of recursive call 12: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-23 10:29:46,231 INFO L267 ElimStorePlain]: Start of recursive call 11: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-23 10:29:46,795 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,796 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,796 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,797 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,799 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:29:46,800 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,800 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,801 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,801 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,802 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,802 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,805 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 9 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 229 [2018-11-23 10:29:46,831 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,832 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,832 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,833 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,833 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,834 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:46,836 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 14 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 127 treesize of output 266 [2018-11-23 10:29:57,454 WARN L180 SmtUtils]: Spent 10.56 s on a formula simplification. DAG size of input: 62 DAG size of output: 43 [2018-11-23 10:29:57,474 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:57,478 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:57,478 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:57,480 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:57,489 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:57,494 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:57,494 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:57,500 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:57,501 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:57,502 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:57,515 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:29:57,532 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 15 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 95 treesize of output 166 [2018-11-23 10:29:57,542 INFO L267 ElimStorePlain]: Start of recursive call 16: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-23 10:29:57,714 INFO L267 ElimStorePlain]: Start of recursive call 15: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-23 10:29:57,777 INFO L267 ElimStorePlain]: Start of recursive call 14: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-23 10:30:00,092 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv16 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0) (bvadd |main_~#volArray~0.offset| .cse0 (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))) [2018-11-23 10:30:00,097 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:00,098 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:02,117 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv16 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0 (_ bv4 32)) (bvadd |main_~#volArray~0.offset| .cse0 (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))) [2018-11-23 10:30:04,146 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| .cse0) (bvadd |main_~#volArray~0.offset| .cse0))) [2018-11-23 10:30:06,169 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv16 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0))) [2018-11-23 10:30:06,195 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:06,195 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:08,209 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| .cse0) (bvadd |main_~#volArray~0.offset| .cse0 (_ bv4 32)))) [2018-11-23 10:30:08,223 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:10,248 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv16 32) main_~i~0))) (= (select v_prenex_4 (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| .cse0)) (select v_prenex_4 (bvadd |main_~#volArray~0.offset| .cse0 (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))))) [2018-11-23 10:30:12,266 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv16 32) main_~i~0))) (= (select v_prenex_4 (bvadd |main_~#volArray~0.offset| .cse0 (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))) (select v_prenex_4 (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0)))) [2018-11-23 10:30:12,272 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:12,284 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:12,285 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:12,293 INFO L303 Elim1Store]: Index analysis took 14240 ms [2018-11-23 10:30:18,583 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 8 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 8 case distinctions, treesize of input 90 treesize of output 245 [2018-11-23 10:30:18,640 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:18,641 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:18,641 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:18,642 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:18,642 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:18,642 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:18,643 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:18,646 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 10:30:18,647 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:18,647 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:18,647 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:18,648 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:18,649 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:18,649 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:18,650 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:18,668 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:18,670 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 16 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 230 treesize of output 419 [2018-11-23 10:30:18,965 WARN L180 SmtUtils]: Spent 234.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 44 [2018-11-23 10:30:18,982 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:18,982 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:18,989 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:18,990 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:18,991 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:18,991 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:18,992 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:18,993 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:18,993 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:19,011 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:19,011 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:19,012 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:19,012 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:19,013 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:19,013 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:19,031 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 15 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 63 treesize of output 163 [2018-11-23 10:30:19,038 INFO L267 ElimStorePlain]: Start of recursive call 19: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-23 10:30:19,152 INFO L267 ElimStorePlain]: Start of recursive call 18: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-23 10:30:23,449 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:23,449 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:23,451 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:25,469 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv16 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0))) [2018-11-23 10:30:25,473 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:25,474 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:25,474 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:25,475 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:27,483 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv16 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0 (_ bv8 32)) (bvadd |main_~#volArray~0.offset| .cse0 (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))) [2018-11-23 10:30:29,502 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| .cse0) (bvadd |main_~#volArray~0.offset| .cse0 (_ bv4 32)))) [2018-11-23 10:30:31,520 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv16 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0 (_ bv4 32)) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0))) [2018-11-23 10:30:31,524 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:31,525 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:33,537 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| .cse0) (bvadd |main_~#volArray~0.offset| .cse0 (_ bv8 32)))) [2018-11-23 10:30:33,553 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:33,556 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:33,565 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:33,565 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:33,567 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:35,585 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv16 32) main_~i~0))) (= (select v_prenex_9 (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0)) (select v_prenex_9 (bvadd |main_~#volArray~0.offset| .cse0 (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))))) [2018-11-23 10:30:35,594 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:35,603 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:35,604 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:35,611 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:35,612 INFO L303 Elim1Store]: Index analysis took 12175 ms [2018-11-23 10:30:37,996 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 18 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 9 case distinctions, treesize of input 127 treesize of output 335 [2018-11-23 10:30:46,765 WARN L180 SmtUtils]: Spent 8.68 s on a formula simplification. DAG size of input: 110 DAG size of output: 83 [2018-11-23 10:30:46,791 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:46,791 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:48,812 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv16 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0 (_ bv8 32)) (bvadd |main_~#volArray~0.offset| .cse0 (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))) [2018-11-23 10:30:48,822 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:50,839 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| .cse0) (bvadd |main_~#volArray~0.offset| .cse0 (_ bv8 32)))) [2018-11-23 10:30:52,866 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv16 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0 (_ bv8 32)) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0))) [2018-11-23 10:30:52,877 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:52,945 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:52,945 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:52,946 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:54,963 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv16 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0))) [2018-11-23 10:30:54,971 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:54,972 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:54,972 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:56,981 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| .cse0) (bvadd |main_~#volArray~0.offset| .cse0 (_ bv4 32)))) [2018-11-23 10:30:59,003 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv16 32) main_~i~0))) (= (bvadd |main_~#volArray~0.offset| .cse0 (_ bv4 32)) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0))) [2018-11-23 10:30:59,017 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:59,024 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:59,025 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:59,026 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:59,031 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:59,056 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:59,056 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:59,067 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:30:59,068 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:01,081 WARN L670 Elim1Store]: solver failed to check if following equality is implied: (let ((.cse0 (bvmul (_ bv16 32) main_~i~0))) (= (select v_arrayElimArr_16 (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0)) (select v_arrayElimArr_16 (bvadd |main_~#volArray~0.offset| .cse0 (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))))) [2018-11-23 10:31:01,097 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:01,099 INFO L303 Elim1Store]: Index analysis took 14320 ms [2018-11-23 10:31:01,186 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 7 select indices, 7 select index equivalence classes, 20 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 8 case distinctions, treesize of input 110 treesize of output 331 [2018-11-23 10:31:01,222 INFO L267 ElimStorePlain]: Start of recursive call 21: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 8 xjuncts. [2018-11-23 10:31:02,325 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,326 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,327 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,327 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,327 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,329 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,329 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,365 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,366 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,367 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,367 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,368 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,368 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,369 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,373 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,374 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,374 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,375 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,388 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,389 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,389 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,390 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,390 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,391 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 10:31:02,404 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 24 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 87 treesize of output 261 [2018-11-23 10:31:02,414 INFO L267 ElimStorePlain]: Start of recursive call 22: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-23 10:31:02,948 INFO L267 ElimStorePlain]: Start of recursive call 20: 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 6 xjuncts. [2018-11-23 10:31:03,560 INFO L267 ElimStorePlain]: Start of recursive call 17: 2 dim-1 vars, End of recursive call: 3 dim-0 vars, and 8 xjuncts. [2018-11-23 10:31:05,248 INFO L267 ElimStorePlain]: Start of recursive call 6: 8 dim-1 vars, End of recursive call: 6 dim-0 vars, and 12 xjuncts. [2018-11-23 10:31:05,861 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: 6 dim-0 vars, and 12 xjuncts. [2018-11-23 10:31:06,421 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: 6 dim-0 vars, and 12 xjuncts. [2018-11-23 10:31:06,965 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: 6 dim-0 vars, and 12 xjuncts. [2018-11-23 10:31:07,520 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 6 dim-0 vars, and 12 xjuncts. [2018-11-23 10:31:08,100 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 6 dim-0 vars, and 12 xjuncts. [2018-11-23 10:31:08,101 INFO L202 ElimStorePlain]: Needed 22 recursive calls to eliminate 2 variables, input treesize:79, output treesize:733 [2018-11-23 10:31:08,125 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:31:08,126 WARN L384 uantifierElimination]: Input elimination task: ∀ [|#memory_int|, |main_~#volArray~0.base|]. (bvsge (select (let ((.cse0 (bvmul (_ bv16 32) main_~i~0))) (store (store (store (store (store (let ((.cse1 (bvadd main_~j~0 (_ bv4294967295 32)))) (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| .cse0) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg .cse1)) |main_~#volArray~0.offset| .cse0) .cse1)) (bvadd |main_~#volArray~0.offset| .cse0 (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| .cse0) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| .cse0 (_ bv4 32)) (_ bv3 32)) (bvadd |main_~#volArray~0.offset| .cse0 (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| .cse0 (_ bv12 32)) (_ bv0 32))) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0) [2018-11-23 10:31:08,126 WARN L385 uantifierElimination]: ElimStorePlain result: ∀ [v_arrayElimCell_19, v_arrayElimCell_15, v_arrayElimCell_20, v_arrayElimCell_17, v_arrayElimCell_16, v_arrayElimCell_18]. (let ((.cse15 (bvadd main_~j~0 (_ bv4294967295 32)))) (let ((.cse21 (bvmul (_ bv4 32) (bvneg .cse15))) (.cse11 (bvmul (_ bv4 32) (bvneg main_~j~0))) (.cse22 (bvmul (_ bv16 32) main_~i~0))) (let ((.cse17 (bvadd |main_~#volArray~0.offset| .cse22 (_ bv8 32))) (.cse13 (bvadd |main_~#volArray~0.offset| .cse22 (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))) (.cse18 (bvadd .cse11 |main_~#volArray~0.offset| .cse22)) (.cse16 (bvadd |main_~#volArray~0.offset| .cse22)) (.cse19 (bvadd |main_~#volArray~0.offset| (_ bv4 32))) (.cse20 (bvadd .cse21 |main_~#volArray~0.offset| .cse22)) (.cse12 (bvadd |main_~#volArray~0.offset| .cse22 (_ bv4 32)))) (let ((.cse10 (not (= .cse20 .cse12))) (.cse0 (bvsge (_ bv3 32) main_~MINVAL~0)) (.cse14 (not (= (bvadd .cse21 (_ bv4294967288 32)) (_ bv0 32)))) (.cse1 (= .cse19 .cse20)) (.cse3 (= .cse20 .cse16)) (.cse4 (= .cse12 .cse18)) (.cse5 (= .cse17 .cse13)) (.cse6 (= .cse19 .cse12)) (.cse7 (= .cse19 .cse13)) (.cse2 (= .cse19 .cse18)) (.cse8 (= .cse17 .cse18)) (.cse9 (= .cse16 .cse13))) (and (or .cse0 .cse1 .cse2) (or .cse3 .cse4 (bvsge v_arrayElimCell_19 main_~MINVAL~0) .cse5 .cse6 .cse1 .cse7 .cse2 .cse8 .cse9) (or (bvsge v_arrayElimCell_15 main_~MINVAL~0) (not .cse9) .cse6) (or .cse0 .cse10) (or (bvsge v_arrayElimCell_20 main_~MINVAL~0) .cse6 (not (= (_ bv8 32) .cse11))) (or .cse7 (bvsge v_arrayElimCell_17 main_~MINVAL~0) (not (= .cse12 .cse13))) (or (bvsge v_arrayElimCell_16 main_~MINVAL~0) .cse1 .cse10) (or .cse0 .cse14) (or .cse6 .cse14 (bvsge v_arrayElimCell_18 main_~MINVAL~0)) (or .cse3 (bvsge main_~j~0 main_~MINVAL~0) .cse4 .cse5 .cse6 .cse7 .cse8 .cse9) (or .cse3 .cse4 .cse5 .cse6 .cse1 (bvsge (_ bv0 32) main_~MINVAL~0) .cse2 .cse8 .cse9) (or .cse3 .cse4 .cse5 .cse6 (bvsge .cse15 main_~MINVAL~0) .cse7 .cse2 .cse8 .cse9)))))) [2018-11-23 10:31:09,792 WARN L180 SmtUtils]: Spent 1.21 s on a formula simplification. DAG size of input: 78 DAG size of output: 48 [2018-11-23 10:31:10,421 WARN L180 SmtUtils]: Spent 264.00 ms on a formula simplification that was a NOOP. DAG size: 48 [2018-11-23 10:31:10,889 INFO L273 TraceCheckUtils]: 54: Hoare triple {3494#false} assume !false; {3494#false} is VALID [2018-11-23 10:31:10,890 INFO L273 TraceCheckUtils]: 53: Hoare triple {3494#false} assume 0bv32 == ~cond; {3494#false} is VALID [2018-11-23 10:31:10,890 INFO L273 TraceCheckUtils]: 52: Hoare triple {3494#false} ~cond := #in~cond; {3494#false} is VALID [2018-11-23 10:31:10,890 INFO L256 TraceCheckUtils]: 51: Hoare triple {3494#false} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {3494#false} is VALID [2018-11-23 10:31:10,892 INFO L273 TraceCheckUtils]: 50: Hoare triple {3666#|main_#t~short7|} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {3494#false} is VALID [2018-11-23 10:31:10,894 INFO L273 TraceCheckUtils]: 49: Hoare triple {3697#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {3666#|main_#t~short7|} is VALID [2018-11-23 10:31:12,932 INFO L273 TraceCheckUtils]: 48: Hoare triple {3701#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {3697#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))) main_~MINVAL~0)} is UNKNOWN [2018-11-23 10:31:12,933 INFO L273 TraceCheckUtils]: 47: Hoare triple {3701#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} havoc #t~short7;havoc #t~mem5;havoc #t~mem6; {3701#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:12,934 INFO L268 TraceCheckUtils]: 46: Hoare quadruple {3493#true} {3701#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} #87#return; {3701#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:12,934 INFO L273 TraceCheckUtils]: 45: Hoare triple {3493#true} assume true; {3493#true} is VALID [2018-11-23 10:31:12,934 INFO L273 TraceCheckUtils]: 44: Hoare triple {3493#true} assume !(0bv32 == ~cond); {3493#true} is VALID [2018-11-23 10:31:12,934 INFO L273 TraceCheckUtils]: 43: Hoare triple {3493#true} ~cond := #in~cond; {3493#true} is VALID [2018-11-23 10:31:12,934 INFO L256 TraceCheckUtils]: 42: Hoare triple {3701#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {3493#true} is VALID [2018-11-23 10:31:12,935 INFO L273 TraceCheckUtils]: 41: Hoare triple {3701#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} assume #t~short7; {3701#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:12,935 INFO L273 TraceCheckUtils]: 40: Hoare triple {3701#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {3701#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:12,936 INFO L273 TraceCheckUtils]: 39: Hoare triple {3729#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} ~i~0 := 0bv32; {3701#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:12,936 INFO L273 TraceCheckUtils]: 38: Hoare triple {3729#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {3729#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:12,936 INFO L273 TraceCheckUtils]: 37: Hoare triple {3729#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3729#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:12,937 INFO L273 TraceCheckUtils]: 36: Hoare triple {3729#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume !~bvsge32(~j~0, 1bv32); {3729#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:12,938 INFO L273 TraceCheckUtils]: 35: Hoare triple {3729#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3729#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:13,258 INFO L273 TraceCheckUtils]: 34: Hoare triple {3745#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {3729#(bvsge (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:13,258 INFO L273 TraceCheckUtils]: 33: Hoare triple {3745#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {3745#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:13,283 INFO L273 TraceCheckUtils]: 32: Hoare triple {3752#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3745#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:13,536 INFO L273 TraceCheckUtils]: 31: Hoare triple {3756#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {3752#(bvsge (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:13,536 INFO L273 TraceCheckUtils]: 30: Hoare triple {3756#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {3756#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:13,597 INFO L273 TraceCheckUtils]: 29: Hoare triple {3763#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3756#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:13,861 INFO L273 TraceCheckUtils]: 28: Hoare triple {3767#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {3763#(bvsge (select (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:13,861 INFO L273 TraceCheckUtils]: 27: Hoare triple {3767#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {3767#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:14,092 INFO L273 TraceCheckUtils]: 26: Hoare triple {3774#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3767#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:14,422 INFO L273 TraceCheckUtils]: 25: Hoare triple {3778#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {3774#(bvsge (select (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:14,423 INFO L273 TraceCheckUtils]: 24: Hoare triple {3778#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {3778#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:14,424 INFO L273 TraceCheckUtils]: 23: Hoare triple {3785#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv3 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32));~j~0 := 4bv32; {3778#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (bvadd main_~j~0 (_ bv4294967294 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:14,437 INFO L273 TraceCheckUtils]: 22: Hoare triple {3789#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4 32)) (_ bv3 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {3785#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv3 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967288 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4294967292 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:14,438 INFO L273 TraceCheckUtils]: 21: Hoare triple {3789#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4 32)) (_ bv3 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume !~bvsge32(~j~0, 1bv32); {3789#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4 32)) (_ bv3 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:14,442 INFO L273 TraceCheckUtils]: 20: Hoare triple {3789#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4 32)) (_ bv3 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3789#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4 32)) (_ bv3 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:14,882 INFO L273 TraceCheckUtils]: 19: Hoare triple {3799#(bvsge (select (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4 32)) (_ bv3 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {3789#(bvsge (select (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4 32)) (_ bv3 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:14,883 INFO L273 TraceCheckUtils]: 18: Hoare triple {3799#(bvsge (select (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4 32)) (_ bv3 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {3799#(bvsge (select (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4 32)) (_ bv3 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:14,916 INFO L273 TraceCheckUtils]: 17: Hoare triple {3806#(bvsge (select (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4 32)) (_ bv3 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3799#(bvsge (select (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4 32)) (_ bv3 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:15,114 INFO L273 TraceCheckUtils]: 16: Hoare triple {3810#(bvsge (select (store (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4 32)) (_ bv3 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {3806#(bvsge (select (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4 32)) (_ bv3 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:15,114 INFO L273 TraceCheckUtils]: 15: Hoare triple {3810#(bvsge (select (store (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4 32)) (_ bv3 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} assume !!~bvsge32(~j~0, 1bv32); {3810#(bvsge (select (store (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4 32)) (_ bv3 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:15,485 INFO L273 TraceCheckUtils]: 14: Hoare triple {3817#(bvsge (select (store (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4 32)) (_ bv3 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3810#(bvsge (select (store (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) main_~j~0) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4 32)) (_ bv3 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:15,778 INFO L273 TraceCheckUtils]: 13: Hoare triple {3821#(and (or (bvsge (_ bv3 32) main_~MINVAL~0) (not (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (_ bv4294967292 32)) (_ bv0 32)))) (or (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (bvsge (_ bv0 32) main_~MINVAL~0) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0)))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv4 32) (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))) (or (bvsge (_ bv3 32) main_~MINVAL~0) (not (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (_ bv4294967288 32)) (_ bv0 32)))) (or (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0)))) (or (forall ((v_arrayElimCell_19 (_ BitVec 32))) (bvsge v_arrayElimCell_19 main_~MINVAL~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv4 32) (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {3817#(bvsge (select (store (store (store (store (store (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (bvadd main_~j~0 (_ bv4294967295 32))) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv4 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv4 32)) (_ bv3 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv8 32)) (_ bv2 32)) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0) (_ bv12 32)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv4 32))) main_~MINVAL~0)} is VALID [2018-11-23 10:31:15,780 INFO L273 TraceCheckUtils]: 12: Hoare triple {3821#(and (or (bvsge (_ bv3 32) main_~MINVAL~0) (not (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (_ bv4294967292 32)) (_ bv0 32)))) (or (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (bvsge (_ bv0 32) main_~MINVAL~0) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0)))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv4 32) (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))) (or (bvsge (_ bv3 32) main_~MINVAL~0) (not (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (_ bv4294967288 32)) (_ bv0 32)))) (or (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0)))) (or (forall ((v_arrayElimCell_19 (_ BitVec 32))) (bvsge v_arrayElimCell_19 main_~MINVAL~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv4 32) (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))))} assume !!~bvsge32(~j~0, 1bv32); {3821#(and (or (bvsge (_ bv3 32) main_~MINVAL~0) (not (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (_ bv4294967292 32)) (_ bv0 32)))) (or (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (bvsge (_ bv0 32) main_~MINVAL~0) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0)))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv4 32) (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))) (or (bvsge (_ bv3 32) main_~MINVAL~0) (not (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (_ bv4294967288 32)) (_ bv0 32)))) (or (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0)))) (or (forall ((v_arrayElimCell_19 (_ BitVec 32))) (bvsge v_arrayElimCell_19 main_~MINVAL~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv4 32) (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))))} is VALID [2018-11-23 10:31:16,022 INFO L273 TraceCheckUtils]: 11: Hoare triple {3828#(and (or (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) main_~MINVAL~0) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (forall ((v_arrayElimCell_19 (_ BitVec 32))) (bvsge v_arrayElimCell_19 main_~MINVAL~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))) (_ bv4294967292 32)) (_ bv0 32))) (or (bvsge (_ bv3 32) main_~MINVAL~0) (not (= (_ bv8 32) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))) (or (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (bvsge (_ bv0 32) main_~MINVAL~0)) (or (not (= (_ bv4 32) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))) (bvsge (_ bv3 32) main_~MINVAL~0)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {3821#(and (or (bvsge (_ bv3 32) main_~MINVAL~0) (not (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (_ bv4294967292 32)) (_ bv0 32)))) (or (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (bvsge (_ bv0 32) main_~MINVAL~0) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0)))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv4 32) (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))) (or (bvsge (_ bv3 32) main_~MINVAL~0) (not (= (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (_ bv4294967288 32)) (_ bv0 32)))) (or (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0)))) (or (forall ((v_arrayElimCell_19 (_ BitVec 32))) (bvsge v_arrayElimCell_19 main_~MINVAL~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0))) (= (_ bv4 32) (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))))} is VALID [2018-11-23 10:31:16,023 INFO L273 TraceCheckUtils]: 10: Hoare triple {3828#(and (or (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) main_~MINVAL~0) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (forall ((v_arrayElimCell_19 (_ BitVec 32))) (bvsge v_arrayElimCell_19 main_~MINVAL~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))) (_ bv4294967292 32)) (_ bv0 32))) (or (bvsge (_ bv3 32) main_~MINVAL~0) (not (= (_ bv8 32) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))) (or (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (bvsge (_ bv0 32) main_~MINVAL~0)) (or (not (= (_ bv4 32) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))) (bvsge (_ bv3 32) main_~MINVAL~0)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {3828#(and (or (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) main_~MINVAL~0) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (forall ((v_arrayElimCell_19 (_ BitVec 32))) (bvsge v_arrayElimCell_19 main_~MINVAL~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))) (_ bv4294967292 32)) (_ bv0 32))) (or (bvsge (_ bv3 32) main_~MINVAL~0) (not (= (_ bv8 32) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))) (or (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (bvsge (_ bv0 32) main_~MINVAL~0)) (or (not (= (_ bv4 32) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))) (bvsge (_ bv3 32) main_~MINVAL~0)))} is VALID [2018-11-23 10:31:16,024 INFO L273 TraceCheckUtils]: 9: Hoare triple {3828#(and (or (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) main_~MINVAL~0) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (forall ((v_arrayElimCell_19 (_ BitVec 32))) (bvsge v_arrayElimCell_19 main_~MINVAL~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))) (_ bv4294967292 32)) (_ bv0 32))) (or (bvsge (_ bv3 32) main_~MINVAL~0) (not (= (_ bv8 32) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))) (or (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (bvsge (_ bv0 32) main_~MINVAL~0)) (or (not (= (_ bv4 32) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))) (bvsge (_ bv3 32) main_~MINVAL~0)))} assume !!~bvsge32(~j~0, 1bv32); {3828#(and (or (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) main_~MINVAL~0) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (forall ((v_arrayElimCell_19 (_ BitVec 32))) (bvsge v_arrayElimCell_19 main_~MINVAL~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))) (_ bv4294967292 32)) (_ bv0 32))) (or (bvsge (_ bv3 32) main_~MINVAL~0) (not (= (_ bv8 32) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))) (or (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (bvsge (_ bv0 32) main_~MINVAL~0)) (or (not (= (_ bv4 32) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))) (bvsge (_ bv3 32) main_~MINVAL~0)))} is VALID [2018-11-23 10:31:16,048 INFO L273 TraceCheckUtils]: 8: Hoare triple {3838#(and (bvsge (_ bv3 32) main_~MINVAL~0) (or (forall ((v_arrayElimCell_19 (_ BitVec 32))) (bvsge v_arrayElimCell_19 main_~MINVAL~0)) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32));~j~0 := 4bv32; {3828#(and (or (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (bvsge (bvadd main_~j~0 (_ bv4294967294 32)) main_~MINVAL~0) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (forall ((v_arrayElimCell_19 (_ BitVec 32))) (bvsge v_arrayElimCell_19 main_~MINVAL~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (bvsge (bvadd main_~j~0 (_ bv4294967295 32)) main_~MINVAL~0) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967293 32)))) (bvmul (_ bv16 32) main_~i~0)))) (or (bvsge (_ bv3 32) main_~MINVAL~0) (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))) (_ bv4294967292 32)) (_ bv0 32))) (or (bvsge (_ bv3 32) main_~MINVAL~0) (not (= (_ bv8 32) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32))))))) (or (= (_ bv4 32) (bvadd (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967295 32)))) (bvmul (_ bv16 32) main_~i~0))) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))) (_ bv4294967292 32)) (_ bv0 32)) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (bvsge (_ bv0 32) main_~MINVAL~0)) (or (not (= (_ bv4 32) (bvmul (_ bv4 32) (bvneg (bvadd main_~j~0 (_ bv4294967294 32)))))) (bvsge (_ bv3 32) main_~MINVAL~0)))} is VALID [2018-11-23 10:31:16,049 INFO L273 TraceCheckUtils]: 7: Hoare triple {3842#(bvsge (_ bv3 32) main_~MINVAL~0)} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {3838#(and (bvsge (_ bv3 32) main_~MINVAL~0) (or (forall ((v_arrayElimCell_19 (_ BitVec 32))) (bvsge v_arrayElimCell_19 main_~MINVAL~0)) (= (_ bv0 32) (bvmul (_ bv16 32) main_~i~0)) (= (bvadd (bvmul (_ bv16 32) main_~i~0) (_ bv4294967280 32)) (_ bv0 32))))} is VALID [2018-11-23 10:31:16,049 INFO L273 TraceCheckUtils]: 6: Hoare triple {3493#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {3842#(bvsge (_ bv3 32) main_~MINVAL~0)} is VALID [2018-11-23 10:31:16,049 INFO L273 TraceCheckUtils]: 5: Hoare triple {3493#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {3493#true} is VALID [2018-11-23 10:31:16,050 INFO L256 TraceCheckUtils]: 4: Hoare triple {3493#true} call #t~ret8 := main(); {3493#true} is VALID [2018-11-23 10:31:16,050 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {3493#true} {3493#true} #83#return; {3493#true} is VALID [2018-11-23 10:31:16,050 INFO L273 TraceCheckUtils]: 2: Hoare triple {3493#true} assume true; {3493#true} is VALID [2018-11-23 10:31:16,050 INFO L273 TraceCheckUtils]: 1: Hoare triple {3493#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {3493#true} is VALID [2018-11-23 10:31:16,050 INFO L256 TraceCheckUtils]: 0: Hoare triple {3493#true} call ULTIMATE.init(); {3493#true} is VALID [2018-11-23 10:31:16,066 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 3 proven. 107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 10:31:16,069 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:31:16,069 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 23] total 44 [2018-11-23 10:31:16,070 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 55 [2018-11-23 10:31:16,070 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:31:16,070 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 44 states. [2018-11-23 10:31:21,013 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 99 edges. 98 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2018-11-23 10:31:21,013 INFO L459 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-11-23 10:31:21,014 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-11-23 10:31:21,014 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=369, Invalid=1523, Unknown=0, NotChecked=0, Total=1892 [2018-11-23 10:31:21,014 INFO L87 Difference]: Start difference. First operand 69 states and 75 transitions. Second operand 44 states. [2018-11-23 10:31:24,833 WARN L180 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 37 [2018-11-23 10:31:25,575 WARN L180 SmtUtils]: Spent 269.00 ms on a formula simplification. DAG size of input: 106 DAG size of output: 80 [2018-11-23 10:31:29,257 WARN L180 SmtUtils]: Spent 375.00 ms on a formula simplification. DAG size of input: 142 DAG size of output: 35 [2018-11-23 10:31:30,652 WARN L180 SmtUtils]: Spent 415.00 ms on a formula simplification. DAG size of input: 143 DAG size of output: 36 [2018-11-23 10:31:33,893 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 26 [2018-11-23 10:31:34,827 WARN L180 SmtUtils]: Spent 115.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 27 [2018-11-23 10:31:35,563 WARN L180 SmtUtils]: Spent 220.00 ms on a formula simplification. DAG size of input: 83 DAG size of output: 60 [2018-11-23 10:31:36,823 WARN L180 SmtUtils]: Spent 445.00 ms on a formula simplification. DAG size of input: 131 DAG size of output: 94 [2018-11-23 10:31:40,660 WARN L180 SmtUtils]: Spent 388.00 ms on a formula simplification. DAG size of input: 102 DAG size of output: 78 [2018-11-23 10:31:43,147 WARN L180 SmtUtils]: Spent 284.00 ms on a formula simplification. DAG size of input: 99 DAG size of output: 51 [2018-11-23 10:31:44,554 WARN L180 SmtUtils]: Spent 248.00 ms on a formula simplification. DAG size of input: 95 DAG size of output: 41 [2018-11-23 10:31:47,055 WARN L180 SmtUtils]: Spent 196.00 ms on a formula simplification. DAG size of input: 85 DAG size of output: 35 [2018-11-23 10:31:48,799 WARN L180 SmtUtils]: Spent 146.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 26 [2018-11-23 10:31:56,589 WARN L180 SmtUtils]: Spent 268.00 ms on a formula simplification. DAG size of input: 95 DAG size of output: 47 [2018-11-23 10:31:57,985 WARN L180 SmtUtils]: Spent 279.00 ms on a formula simplification. DAG size of input: 91 DAG size of output: 66 [2018-11-23 10:31:58,918 WARN L180 SmtUtils]: Spent 165.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 31 [2018-11-23 10:32:01,277 WARN L180 SmtUtils]: Spent 112.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 48 [2018-11-23 10:32:01,767 WARN L180 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 49 [2018-11-23 10:32:06,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:32:06,911 INFO L93 Difference]: Finished difference Result 188 states and 214 transitions. [2018-11-23 10:32:06,911 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-11-23 10:32:06,911 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 55 [2018-11-23 10:32:06,911 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 10:32:06,912 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2018-11-23 10:32:06,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 178 transitions. [2018-11-23 10:32:06,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2018-11-23 10:32:06,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 178 transitions. [2018-11-23 10:32:06,927 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 51 states and 178 transitions. [2018-11-23 10:32:21,905 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 178 edges. 171 inductive. 0 not inductive. 7 times theorem prover too weak to decide inductivity. [2018-11-23 10:32:21,908 INFO L225 Difference]: With dead ends: 188 [2018-11-23 10:32:21,908 INFO L226 Difference]: Without dead ends: 154 [2018-11-23 10:32:21,910 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 138 GetRequests, 66 SyntacticMatches, 1 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1663 ImplicationChecksByTransitivity, 17.4s TimeCoverageRelationStatistics Valid=964, Invalid=4292, Unknown=0, NotChecked=0, Total=5256 [2018-11-23 10:32:21,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154 states. [2018-11-23 10:32:22,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154 to 122. [2018-11-23 10:32:22,265 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2018-11-23 10:32:22,265 INFO L82 GeneralOperation]: Start isEquivalent. First operand 154 states. Second operand 122 states. [2018-11-23 10:32:22,265 INFO L74 IsIncluded]: Start isIncluded. First operand 154 states. Second operand 122 states. [2018-11-23 10:32:22,265 INFO L87 Difference]: Start difference. First operand 154 states. Second operand 122 states. [2018-11-23 10:32:22,271 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:32:22,271 INFO L93 Difference]: Finished difference Result 154 states and 172 transitions. [2018-11-23 10:32:22,272 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 172 transitions. [2018-11-23 10:32:22,272 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:32:22,272 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:32:22,273 INFO L74 IsIncluded]: Start isIncluded. First operand 122 states. Second operand 154 states. [2018-11-23 10:32:22,273 INFO L87 Difference]: Start difference. First operand 122 states. Second operand 154 states. [2018-11-23 10:32:22,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 10:32:22,279 INFO L93 Difference]: Finished difference Result 154 states and 172 transitions. [2018-11-23 10:32:22,279 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 172 transitions. [2018-11-23 10:32:22,280 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 10:32:22,280 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2018-11-23 10:32:22,280 INFO L88 GeneralOperation]: Finished isEquivalent. [2018-11-23 10:32:22,280 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2018-11-23 10:32:22,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 122 states. [2018-11-23 10:32:22,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 137 transitions. [2018-11-23 10:32:22,285 INFO L78 Accepts]: Start accepts. Automaton has 122 states and 137 transitions. Word has length 55 [2018-11-23 10:32:22,285 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 10:32:22,285 INFO L480 AbstractCegarLoop]: Abstraction has 122 states and 137 transitions. [2018-11-23 10:32:22,286 INFO L481 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-11-23 10:32:22,286 INFO L276 IsEmpty]: Start isEmpty. Operand 122 states and 137 transitions. [2018-11-23 10:32:22,287 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-11-23 10:32:22,287 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 10:32:22,287 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 10:32:22,287 INFO L423 AbstractCegarLoop]: === Iteration 10 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 10:32:22,287 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 10:32:22,287 INFO L82 PathProgramCache]: Analyzing trace with hash 651610521, now seen corresponding path program 3 times [2018-11-23 10:32:22,288 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 10:32:22,288 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 10:32:22,309 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2018-11-23 10:32:22,588 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-11-23 10:32:22,588 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 10:32:22,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 10:32:22,629 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 10:32:22,738 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 14 [2018-11-23 10:32:22,748 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 13 [2018-11-23 10:32:22,750 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:32:22,759 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:32:22,788 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 10:32:22,788 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:28, output treesize:24 [2018-11-23 10:32:22,810 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:32:22,810 WARN L384 uantifierElimination]: Input elimination task: ∃ [|v_#memory_int_42|, main_~j~0]. (and (bvsge main_~j~0 (_ bv1 32)) (= (store |v_#memory_int_42| |main_~#volArray~0.base| (store (select |v_#memory_int_42| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)) (_ bv0 32))) |#memory_int|) (= |main_~#volArray~0.offset| (_ bv0 32)) (not (bvsge main_~j~0 (_ bv2 32)))) [2018-11-23 10:32:22,811 WARN L385 uantifierElimination]: ElimStorePlain result: ∃ [main_~j~0]. (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (= |main_~#volArray~0.offset| (_ bv0 32)) (not (bvsge main_~j~0 (_ bv2 32)))) [2018-11-23 10:32:23,777 INFO L256 TraceCheckUtils]: 0: Hoare triple {4660#true} call ULTIMATE.init(); {4660#true} is VALID [2018-11-23 10:32:23,777 INFO L273 TraceCheckUtils]: 1: Hoare triple {4660#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {4660#true} is VALID [2018-11-23 10:32:23,777 INFO L273 TraceCheckUtils]: 2: Hoare triple {4660#true} assume true; {4660#true} is VALID [2018-11-23 10:32:23,777 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {4660#true} {4660#true} #83#return; {4660#true} is VALID [2018-11-23 10:32:23,777 INFO L256 TraceCheckUtils]: 4: Hoare triple {4660#true} call #t~ret8 := main(); {4660#true} is VALID [2018-11-23 10:32:23,778 INFO L273 TraceCheckUtils]: 5: Hoare triple {4660#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {4660#true} is VALID [2018-11-23 10:32:23,778 INFO L273 TraceCheckUtils]: 6: Hoare triple {4660#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {4683#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} is VALID [2018-11-23 10:32:23,779 INFO L273 TraceCheckUtils]: 7: Hoare triple {4683#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {4687#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:23,779 INFO L273 TraceCheckUtils]: 8: Hoare triple {4687#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32));~j~0 := 4bv32; {4687#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:23,780 INFO L273 TraceCheckUtils]: 9: Hoare triple {4687#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {4687#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:23,791 INFO L273 TraceCheckUtils]: 10: Hoare triple {4687#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {4687#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:23,792 INFO L273 TraceCheckUtils]: 11: Hoare triple {4687#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4687#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:23,793 INFO L273 TraceCheckUtils]: 12: Hoare triple {4687#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {4687#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:23,793 INFO L273 TraceCheckUtils]: 13: Hoare triple {4687#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {4687#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:23,794 INFO L273 TraceCheckUtils]: 14: Hoare triple {4687#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4687#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:23,794 INFO L273 TraceCheckUtils]: 15: Hoare triple {4687#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {4687#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:23,795 INFO L273 TraceCheckUtils]: 16: Hoare triple {4687#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {4687#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:23,795 INFO L273 TraceCheckUtils]: 17: Hoare triple {4687#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4687#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:23,796 INFO L273 TraceCheckUtils]: 18: Hoare triple {4687#(and (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvsge32(~j~0, 1bv32); {4721#(and (bvsge main_~j~0 (_ bv1 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:23,802 INFO L273 TraceCheckUtils]: 19: Hoare triple {4721#(and (bvsge main_~j~0 (_ bv1 32)) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~MINVAL~0) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {4725#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:32:23,803 INFO L273 TraceCheckUtils]: 20: Hoare triple {4725#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4725#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:32:23,804 INFO L273 TraceCheckUtils]: 21: Hoare triple {4725#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !~bvsge32(~j~0, 1bv32); {4725#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:32:23,804 INFO L273 TraceCheckUtils]: 22: Hoare triple {4725#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {4725#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:32:23,805 INFO L273 TraceCheckUtils]: 23: Hoare triple {4725#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {4725#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:32:23,806 INFO L273 TraceCheckUtils]: 24: Hoare triple {4725#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} ~i~0 := 0bv32; {4741#(and (= main_~i~0 (_ bv0 32)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:32:23,807 INFO L273 TraceCheckUtils]: 25: Hoare triple {4741#(and (= main_~i~0 (_ bv0 32)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {4741#(and (= main_~i~0 (_ bv0 32)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:32:23,808 INFO L273 TraceCheckUtils]: 26: Hoare triple {4741#(and (= main_~i~0 (_ bv0 32)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume #t~short7; {4741#(and (= main_~i~0 (_ bv0 32)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:32:23,816 INFO L256 TraceCheckUtils]: 27: Hoare triple {4741#(and (= main_~i~0 (_ bv0 32)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} is VALID [2018-11-23 10:32:23,817 INFO L273 TraceCheckUtils]: 28: Hoare triple {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} ~cond := #in~cond; {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} is VALID [2018-11-23 10:32:23,817 INFO L273 TraceCheckUtils]: 29: Hoare triple {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} assume !(0bv32 == ~cond); {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} is VALID [2018-11-23 10:32:23,817 INFO L273 TraceCheckUtils]: 30: Hoare triple {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} assume true; {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} is VALID [2018-11-23 10:32:23,818 INFO L268 TraceCheckUtils]: 31: Hoare quadruple {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} {4741#(and (= main_~i~0 (_ bv0 32)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} #87#return; {4741#(and (= main_~i~0 (_ bv0 32)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:32:23,819 INFO L273 TraceCheckUtils]: 32: Hoare triple {4741#(and (= main_~i~0 (_ bv0 32)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} havoc #t~short7;havoc #t~mem5;havoc #t~mem6; {4741#(and (= main_~i~0 (_ bv0 32)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:32:23,823 INFO L273 TraceCheckUtils]: 33: Hoare triple {4741#(and (= main_~i~0 (_ bv0 32)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {4770#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:23,824 INFO L273 TraceCheckUtils]: 34: Hoare triple {4770#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {4770#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:23,825 INFO L273 TraceCheckUtils]: 35: Hoare triple {4770#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} assume #t~short7; {4770#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:23,829 INFO L256 TraceCheckUtils]: 36: Hoare triple {4770#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} is VALID [2018-11-23 10:32:23,830 INFO L273 TraceCheckUtils]: 37: Hoare triple {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} ~cond := #in~cond; {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} is VALID [2018-11-23 10:32:23,830 INFO L273 TraceCheckUtils]: 38: Hoare triple {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} assume !(0bv32 == ~cond); {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} is VALID [2018-11-23 10:32:23,831 INFO L273 TraceCheckUtils]: 39: Hoare triple {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} assume true; {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} is VALID [2018-11-23 10:32:23,831 INFO L268 TraceCheckUtils]: 40: Hoare quadruple {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} {4770#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #87#return; {4770#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:23,832 INFO L273 TraceCheckUtils]: 41: Hoare triple {4770#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} havoc #t~short7;havoc #t~mem5;havoc #t~mem6; {4770#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:23,836 INFO L273 TraceCheckUtils]: 42: Hoare triple {4770#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (bvadd main_~i~0 (_ bv4294967295 32)) (_ bv0 32)))} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {4798#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:32:23,837 INFO L273 TraceCheckUtils]: 43: Hoare triple {4798#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {4798#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:32:23,837 INFO L273 TraceCheckUtils]: 44: Hoare triple {4798#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} assume #t~short7; {4798#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:32:23,841 INFO L256 TraceCheckUtils]: 45: Hoare triple {4798#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} is VALID [2018-11-23 10:32:23,842 INFO L273 TraceCheckUtils]: 46: Hoare triple {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} ~cond := #in~cond; {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} is VALID [2018-11-23 10:32:23,842 INFO L273 TraceCheckUtils]: 47: Hoare triple {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} assume !(0bv32 == ~cond); {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} is VALID [2018-11-23 10:32:23,843 INFO L273 TraceCheckUtils]: 48: Hoare triple {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} assume true; {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} is VALID [2018-11-23 10:32:23,843 INFO L268 TraceCheckUtils]: 49: Hoare quadruple {4751#(exists ((main_~j~0 (_ BitVec 32)) (|v_main_~#volArray~0.base_BEFORE_CALL_3| (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |v_main_~#volArray~0.base_BEFORE_CALL_3|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32)))))} {4798#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} #87#return; {4798#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:32:23,844 INFO L273 TraceCheckUtils]: 50: Hoare triple {4798#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} havoc #t~short7;havoc #t~mem5;havoc #t~mem6; {4798#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} is VALID [2018-11-23 10:32:23,850 INFO L273 TraceCheckUtils]: 51: Hoare triple {4798#(and (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)) (= (_ bv2 32) main_~i~0))} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {4826#(and (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:32:23,854 INFO L273 TraceCheckUtils]: 52: Hoare triple {4826#(and (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {4826#(and (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} is VALID [2018-11-23 10:32:23,859 INFO L273 TraceCheckUtils]: 53: Hoare triple {4826#(and (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (exists ((main_~j~0 (_ BitVec 32))) (and (bvsge main_~j~0 (_ bv1 32)) (= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (_ bv16 32)))) (not (bvsge main_~j~0 (_ bv2 32))))) (= |main_~#volArray~0.offset| (_ bv0 32)))} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {4833#|main_#t~short7|} is VALID [2018-11-23 10:32:23,860 INFO L256 TraceCheckUtils]: 54: Hoare triple {4833#|main_#t~short7|} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {4837#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:32:23,860 INFO L273 TraceCheckUtils]: 55: Hoare triple {4837#(= (bvadd |__VERIFIER_assert_#in~cond| (_ bv4294967295 32)) (_ bv0 32))} ~cond := #in~cond; {4841#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} is VALID [2018-11-23 10:32:23,861 INFO L273 TraceCheckUtils]: 56: Hoare triple {4841#(= (bvadd __VERIFIER_assert_~cond (_ bv4294967295 32)) (_ bv0 32))} assume 0bv32 == ~cond; {4661#false} is VALID [2018-11-23 10:32:23,861 INFO L273 TraceCheckUtils]: 57: Hoare triple {4661#false} assume !false; {4661#false} is VALID [2018-11-23 10:32:23,875 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 3 proven. 38 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-11-23 10:32:23,876 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 10:32:24,366 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2018-11-23 10:32:24,445 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 3 [2018-11-23 10:32:24,447 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 10:32:24,455 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:32:24,478 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 10:32:24,478 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:24, output treesize:15 [2018-11-23 10:32:24,485 WARN L383 uantifierElimination]: Trying to double check SDD result, but SMT solver's response was UNKNOWN. [2018-11-23 10:32:24,485 WARN L384 uantifierElimination]: Input elimination task: ∀ [|#memory_int|, |main_~#volArray~0.base|]. (or (= (_ bv0 32) (select (store (select |#memory_int| |main_~#volArray~0.base|) (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) |main_~#volArray~0.offset| (bvmul (_ bv16 32) main_~i~0)) (_ bv0 32)) (bvadd |main_~#volArray~0.offset| (_ bv12 32)))) (bvsge main_~j~0 main_~MINVAL~0)) [2018-11-23 10:32:24,485 WARN L385 uantifierElimination]: ElimStorePlain result: ∀ []. (or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32))) [2018-11-23 10:32:24,946 INFO L273 TraceCheckUtils]: 57: Hoare triple {4661#false} assume !false; {4661#false} is VALID [2018-11-23 10:32:24,947 INFO L273 TraceCheckUtils]: 56: Hoare triple {4851#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} assume 0bv32 == ~cond; {4661#false} is VALID [2018-11-23 10:32:24,947 INFO L273 TraceCheckUtils]: 55: Hoare triple {4855#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} ~cond := #in~cond; {4851#(not (= (_ bv0 32) __VERIFIER_assert_~cond))} is VALID [2018-11-23 10:32:24,948 INFO L256 TraceCheckUtils]: 54: Hoare triple {4833#|main_#t~short7|} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {4855#(not (= |__VERIFIER_assert_#in~cond| (_ bv0 32)))} is VALID [2018-11-23 10:32:24,949 INFO L273 TraceCheckUtils]: 53: Hoare triple {4862#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume !#t~short7;call #t~mem6 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := 0bv32 == #t~mem6; {4833#|main_#t~short7|} is VALID [2018-11-23 10:32:24,949 INFO L273 TraceCheckUtils]: 52: Hoare triple {4862#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {4862#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-23 10:32:25,203 INFO L273 TraceCheckUtils]: 51: Hoare triple {4869#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {4862#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0))))} is VALID [2018-11-23 10:32:25,204 INFO L273 TraceCheckUtils]: 50: Hoare triple {4869#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} havoc #t~short7;havoc #t~mem5;havoc #t~mem6; {4869#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-23 10:32:25,205 INFO L268 TraceCheckUtils]: 49: Hoare quadruple {4660#true} {4869#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} #87#return; {4869#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-23 10:32:25,205 INFO L273 TraceCheckUtils]: 48: Hoare triple {4660#true} assume true; {4660#true} is VALID [2018-11-23 10:32:25,205 INFO L273 TraceCheckUtils]: 47: Hoare triple {4660#true} assume !(0bv32 == ~cond); {4660#true} is VALID [2018-11-23 10:32:25,205 INFO L273 TraceCheckUtils]: 46: Hoare triple {4660#true} ~cond := #in~cond; {4660#true} is VALID [2018-11-23 10:32:25,206 INFO L256 TraceCheckUtils]: 45: Hoare triple {4869#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {4660#true} is VALID [2018-11-23 10:32:25,206 INFO L273 TraceCheckUtils]: 44: Hoare triple {4869#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} assume #t~short7; {4869#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-23 10:32:25,206 INFO L273 TraceCheckUtils]: 43: Hoare triple {4869#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {4869#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-23 10:32:25,551 INFO L273 TraceCheckUtils]: 42: Hoare triple {4897#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {4869#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv4 32))))} is VALID [2018-11-23 10:32:25,551 INFO L273 TraceCheckUtils]: 41: Hoare triple {4897#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} havoc #t~short7;havoc #t~mem5;havoc #t~mem6; {4897#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} is VALID [2018-11-23 10:32:25,566 INFO L268 TraceCheckUtils]: 40: Hoare quadruple {4660#true} {4897#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} #87#return; {4897#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} is VALID [2018-11-23 10:32:25,566 INFO L273 TraceCheckUtils]: 39: Hoare triple {4660#true} assume true; {4660#true} is VALID [2018-11-23 10:32:25,566 INFO L273 TraceCheckUtils]: 38: Hoare triple {4660#true} assume !(0bv32 == ~cond); {4660#true} is VALID [2018-11-23 10:32:25,567 INFO L273 TraceCheckUtils]: 37: Hoare triple {4660#true} ~cond := #in~cond; {4660#true} is VALID [2018-11-23 10:32:25,567 INFO L256 TraceCheckUtils]: 36: Hoare triple {4897#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {4660#true} is VALID [2018-11-23 10:32:25,568 INFO L273 TraceCheckUtils]: 35: Hoare triple {4897#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} assume #t~short7; {4897#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} is VALID [2018-11-23 10:32:25,568 INFO L273 TraceCheckUtils]: 34: Hoare triple {4897#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {4897#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} is VALID [2018-11-23 10:32:25,894 INFO L273 TraceCheckUtils]: 33: Hoare triple {4925#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} #t~post4 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post4);havoc #t~post4; {4897#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv8 32))))} is VALID [2018-11-23 10:32:25,895 INFO L273 TraceCheckUtils]: 32: Hoare triple {4925#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} havoc #t~short7;havoc #t~mem5;havoc #t~mem6; {4925#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} is VALID [2018-11-23 10:32:25,896 INFO L268 TraceCheckUtils]: 31: Hoare quadruple {4660#true} {4925#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} #87#return; {4925#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} is VALID [2018-11-23 10:32:25,896 INFO L273 TraceCheckUtils]: 30: Hoare triple {4660#true} assume true; {4660#true} is VALID [2018-11-23 10:32:25,896 INFO L273 TraceCheckUtils]: 29: Hoare triple {4660#true} assume !(0bv32 == ~cond); {4660#true} is VALID [2018-11-23 10:32:25,896 INFO L273 TraceCheckUtils]: 28: Hoare triple {4660#true} ~cond := #in~cond; {4660#true} is VALID [2018-11-23 10:32:25,896 INFO L256 TraceCheckUtils]: 27: Hoare triple {4925#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} call __VERIFIER_assert((if #t~short7 then 1bv32 else 0bv32)); {4660#true} is VALID [2018-11-23 10:32:25,897 INFO L273 TraceCheckUtils]: 26: Hoare triple {4925#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} assume #t~short7; {4925#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} is VALID [2018-11-23 10:32:25,897 INFO L273 TraceCheckUtils]: 25: Hoare triple {4925#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} assume !!~bvslt32(~i~0, ~CELLCOUNT~0);call #t~mem5 := read~intINTTYPE4(~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~i~0)), 4bv32);#t~short7 := ~bvsge32(#t~mem5, ~MINVAL~0); {4925#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} is VALID [2018-11-23 10:32:25,897 INFO L273 TraceCheckUtils]: 24: Hoare triple {4953#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))))} ~i~0 := 0bv32; {4925#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (bvmul (_ bv4 32) main_~i~0) (_ bv12 32))))} is VALID [2018-11-23 10:32:25,898 INFO L273 TraceCheckUtils]: 23: Hoare triple {4953#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))))} assume !~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32)); {4953#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))))} is VALID [2018-11-23 10:32:25,898 INFO L273 TraceCheckUtils]: 22: Hoare triple {4953#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))))} #t~post2 := ~i~0;~i~0 := ~bvadd32(1bv32, #t~post2);havoc #t~post2; {4953#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))))} is VALID [2018-11-23 10:32:25,898 INFO L273 TraceCheckUtils]: 21: Hoare triple {4953#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))))} assume !~bvsge32(~j~0, 1bv32); {4953#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))))} is VALID [2018-11-23 10:32:25,899 INFO L273 TraceCheckUtils]: 20: Hoare triple {4953#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4953#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))))} is VALID [2018-11-23 10:32:26,071 INFO L273 TraceCheckUtils]: 19: Hoare triple {4969#(or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)))} assume !~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(0bv32, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {4953#(= (_ bv0 32) (select (select |#memory_int| |main_~#volArray~0.base|) (bvadd |main_~#volArray~0.offset| (_ bv12 32))))} is VALID [2018-11-23 10:32:26,074 INFO L273 TraceCheckUtils]: 18: Hoare triple {4973#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32)))))} assume !!~bvsge32(~j~0, 1bv32); {4969#(or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)))} is VALID [2018-11-23 10:32:26,075 INFO L273 TraceCheckUtils]: 17: Hoare triple {4973#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32)))))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4973#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32)))))} is VALID [2018-11-23 10:32:26,075 INFO L273 TraceCheckUtils]: 16: Hoare triple {4973#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32)))))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {4973#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32)))))} is VALID [2018-11-23 10:32:26,078 INFO L273 TraceCheckUtils]: 15: Hoare triple {4973#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32)))))} assume !!~bvsge32(~j~0, 1bv32); {4973#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32)))))} is VALID [2018-11-23 10:32:26,078 INFO L273 TraceCheckUtils]: 14: Hoare triple {4973#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32)))))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4973#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32)))))} is VALID [2018-11-23 10:32:26,080 INFO L273 TraceCheckUtils]: 13: Hoare triple {4973#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32)))))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {4973#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32)))))} is VALID [2018-11-23 10:32:26,080 INFO L273 TraceCheckUtils]: 12: Hoare triple {4973#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32)))))} assume !!~bvsge32(~j~0, 1bv32); {4973#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32)))))} is VALID [2018-11-23 10:32:26,082 INFO L273 TraceCheckUtils]: 11: Hoare triple {4973#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32)))))} #t~post3 := ~j~0;~j~0 := ~bvsub32(#t~post3, 1bv32);havoc #t~post3; {4973#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32)))))} is VALID [2018-11-23 10:32:26,082 INFO L273 TraceCheckUtils]: 10: Hoare triple {4973#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32)))))} assume ~bvsge32(~j~0, ~MINVAL~0);call write~intINTTYPE4(~j~0, ~#volArray~0.base, ~bvadd32(~#volArray~0.offset, ~bvmul32(4bv32, ~bvsub32(~bvmul32(4bv32, ~i~0), ~j~0))), 4bv32); {4973#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32)))))} is VALID [2018-11-23 10:32:26,084 INFO L273 TraceCheckUtils]: 9: Hoare triple {4973#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32)))))} assume !!~bvsge32(~j~0, 1bv32); {4973#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32)))))} is VALID [2018-11-23 10:32:26,084 INFO L273 TraceCheckUtils]: 8: Hoare triple {4973#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32)))))} assume !!~bvsle32(~i~0, ~bvsdiv32(~CELLCOUNT~0, 4bv32));~j~0 := 4bv32; {4973#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32)))))} is VALID [2018-11-23 10:32:26,087 INFO L273 TraceCheckUtils]: 7: Hoare triple {5007#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (not (bvsge main_~j~0 (_ bv1 32))) (= (_ bv4294967292 32) (bvmul (_ bv4 32) (bvneg main_~j~0)))))} assume !(0bv32 != ~bvsrem32(~CELLCOUNT~0, 4bv32));assume 0bv32 != (if 0bv32 == ~bvsrem32(~CELLCOUNT~0, 4bv32) then 1bv32 else 0bv32);~i~0 := 1bv32; {4973#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (= (bvadd (bvmul (_ bv4 32) (bvneg main_~j~0)) (bvmul (_ bv16 32) main_~i~0) (_ bv4294967284 32)) (_ bv0 32)) (not (bvsge main_~j~0 (_ bv1 32)))))} is VALID [2018-11-23 10:32:26,092 INFO L273 TraceCheckUtils]: 6: Hoare triple {4660#true} assume ~bvsgt32(~CELLCOUNT~0, 1bv32);~MINVAL~0 := 2bv32;havoc ~i~0;havoc ~j~0;call ~#volArray~0.base, ~#volArray~0.offset := #Ultimate.alloc(~bvmul32(4bv32, ~CELLCOUNT~0)); {5007#(forall ((main_~j~0 (_ BitVec 32))) (or (bvsge main_~j~0 main_~MINVAL~0) (not (bvsge main_~j~0 (_ bv1 32))) (= (_ bv4294967292 32) (bvmul (_ bv4 32) (bvneg main_~j~0)))))} is VALID [2018-11-23 10:32:26,092 INFO L273 TraceCheckUtils]: 5: Hoare triple {4660#true} ~CELLCOUNT~0 := #t~nondet1;havoc #t~nondet1; {4660#true} is VALID [2018-11-23 10:32:26,092 INFO L256 TraceCheckUtils]: 4: Hoare triple {4660#true} call #t~ret8 := main(); {4660#true} is VALID [2018-11-23 10:32:26,092 INFO L268 TraceCheckUtils]: 3: Hoare quadruple {4660#true} {4660#true} #83#return; {4660#true} is VALID [2018-11-23 10:32:26,093 INFO L273 TraceCheckUtils]: 2: Hoare triple {4660#true} assume true; {4660#true} is VALID [2018-11-23 10:32:26,093 INFO L273 TraceCheckUtils]: 1: Hoare triple {4660#true} #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];~CELLCOUNT~0 := 0bv32; {4660#true} is VALID [2018-11-23 10:32:26,093 INFO L256 TraceCheckUtils]: 0: Hoare triple {4660#true} call ULTIMATE.init(); {4660#true} is VALID [2018-11-23 10:32:26,100 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 6 proven. 35 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-11-23 10:32:26,102 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 10:32:26,103 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13] total 24 [2018-11-23 10:32:26,103 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 58 [2018-11-23 10:32:26,103 INFO L84 Accepts]: Finished accepts. word is accepted. [2018-11-23 10:32:26,104 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 24 states. [2018-11-23 10:32:27,661 INFO L119 InductivityCheck]: Floyd-Hoare automaton has 85 edges. 85 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2018-11-23 10:32:27,661 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-23 10:32:27,661 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-23 10:32:27,661 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=477, Unknown=0, NotChecked=0, Total=552 [2018-11-23 10:32:27,662 INFO L87 Difference]: Start difference. First operand 122 states and 137 transitions. Second operand 24 states.